1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Arizona core driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2012 Wolfson Microelectronics plc
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/err.h>
13*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
14*4882a593Smuzhiyun #include <linux/interrupt.h>
15*4882a593Smuzhiyun #include <linux/mfd/core.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/of.h>
18*4882a593Smuzhiyun #include <linux/of_device.h>
19*4882a593Smuzhiyun #include <linux/pm_runtime.h>
20*4882a593Smuzhiyun #include <linux/regmap.h>
21*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
22*4882a593Smuzhiyun #include <linux/regulator/machine.h>
23*4882a593Smuzhiyun #include <linux/slab.h>
24*4882a593Smuzhiyun #include <linux/ktime.h>
25*4882a593Smuzhiyun #include <linux/platform_device.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include <linux/mfd/arizona/core.h>
28*4882a593Smuzhiyun #include <linux/mfd/arizona/registers.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #include "arizona.h"
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun static const char * const wm5102_core_supplies[] = {
33*4882a593Smuzhiyun "AVDD",
34*4882a593Smuzhiyun "DBVDD1",
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
arizona_clk32k_enable(struct arizona * arizona)37*4882a593Smuzhiyun int arizona_clk32k_enable(struct arizona *arizona)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun int ret = 0;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun mutex_lock(&arizona->clk_lock);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun arizona->clk32k_ref++;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun if (arizona->clk32k_ref == 1) {
46*4882a593Smuzhiyun switch (arizona->pdata.clk32k_src) {
47*4882a593Smuzhiyun case ARIZONA_32KZ_MCLK1:
48*4882a593Smuzhiyun ret = pm_runtime_get_sync(arizona->dev);
49*4882a593Smuzhiyun if (ret != 0)
50*4882a593Smuzhiyun goto err_ref;
51*4882a593Smuzhiyun ret = clk_prepare_enable(arizona->mclk[ARIZONA_MCLK1]);
52*4882a593Smuzhiyun if (ret != 0) {
53*4882a593Smuzhiyun pm_runtime_put_sync(arizona->dev);
54*4882a593Smuzhiyun goto err_ref;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun break;
57*4882a593Smuzhiyun case ARIZONA_32KZ_MCLK2:
58*4882a593Smuzhiyun ret = clk_prepare_enable(arizona->mclk[ARIZONA_MCLK2]);
59*4882a593Smuzhiyun if (ret != 0)
60*4882a593Smuzhiyun goto err_ref;
61*4882a593Smuzhiyun break;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun ret = regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
65*4882a593Smuzhiyun ARIZONA_CLK_32K_ENA,
66*4882a593Smuzhiyun ARIZONA_CLK_32K_ENA);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun err_ref:
70*4882a593Smuzhiyun if (ret != 0)
71*4882a593Smuzhiyun arizona->clk32k_ref--;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun mutex_unlock(&arizona->clk_lock);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun return ret;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(arizona_clk32k_enable);
78*4882a593Smuzhiyun
arizona_clk32k_disable(struct arizona * arizona)79*4882a593Smuzhiyun int arizona_clk32k_disable(struct arizona *arizona)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun mutex_lock(&arizona->clk_lock);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun WARN_ON(arizona->clk32k_ref <= 0);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun arizona->clk32k_ref--;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun if (arizona->clk32k_ref == 0) {
88*4882a593Smuzhiyun regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
89*4882a593Smuzhiyun ARIZONA_CLK_32K_ENA, 0);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun switch (arizona->pdata.clk32k_src) {
92*4882a593Smuzhiyun case ARIZONA_32KZ_MCLK1:
93*4882a593Smuzhiyun pm_runtime_put_sync(arizona->dev);
94*4882a593Smuzhiyun clk_disable_unprepare(arizona->mclk[ARIZONA_MCLK1]);
95*4882a593Smuzhiyun break;
96*4882a593Smuzhiyun case ARIZONA_32KZ_MCLK2:
97*4882a593Smuzhiyun clk_disable_unprepare(arizona->mclk[ARIZONA_MCLK2]);
98*4882a593Smuzhiyun break;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun mutex_unlock(&arizona->clk_lock);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun return 0;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(arizona_clk32k_disable);
107*4882a593Smuzhiyun
arizona_clkgen_err(int irq,void * data)108*4882a593Smuzhiyun static irqreturn_t arizona_clkgen_err(int irq, void *data)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun struct arizona *arizona = data;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun dev_err(arizona->dev, "CLKGEN error\n");
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun return IRQ_HANDLED;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
arizona_underclocked(int irq,void * data)117*4882a593Smuzhiyun static irqreturn_t arizona_underclocked(int irq, void *data)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun struct arizona *arizona = data;
120*4882a593Smuzhiyun unsigned int val;
121*4882a593Smuzhiyun int ret;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_8,
124*4882a593Smuzhiyun &val);
125*4882a593Smuzhiyun if (ret != 0) {
126*4882a593Smuzhiyun dev_err(arizona->dev, "Failed to read underclock status: %d\n",
127*4882a593Smuzhiyun ret);
128*4882a593Smuzhiyun return IRQ_NONE;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun if (val & ARIZONA_AIF3_UNDERCLOCKED_STS)
132*4882a593Smuzhiyun dev_err(arizona->dev, "AIF3 underclocked\n");
133*4882a593Smuzhiyun if (val & ARIZONA_AIF2_UNDERCLOCKED_STS)
134*4882a593Smuzhiyun dev_err(arizona->dev, "AIF2 underclocked\n");
135*4882a593Smuzhiyun if (val & ARIZONA_AIF1_UNDERCLOCKED_STS)
136*4882a593Smuzhiyun dev_err(arizona->dev, "AIF1 underclocked\n");
137*4882a593Smuzhiyun if (val & ARIZONA_ISRC3_UNDERCLOCKED_STS)
138*4882a593Smuzhiyun dev_err(arizona->dev, "ISRC3 underclocked\n");
139*4882a593Smuzhiyun if (val & ARIZONA_ISRC2_UNDERCLOCKED_STS)
140*4882a593Smuzhiyun dev_err(arizona->dev, "ISRC2 underclocked\n");
141*4882a593Smuzhiyun if (val & ARIZONA_ISRC1_UNDERCLOCKED_STS)
142*4882a593Smuzhiyun dev_err(arizona->dev, "ISRC1 underclocked\n");
143*4882a593Smuzhiyun if (val & ARIZONA_FX_UNDERCLOCKED_STS)
144*4882a593Smuzhiyun dev_err(arizona->dev, "FX underclocked\n");
145*4882a593Smuzhiyun if (val & ARIZONA_ASRC_UNDERCLOCKED_STS)
146*4882a593Smuzhiyun dev_err(arizona->dev, "ASRC underclocked\n");
147*4882a593Smuzhiyun if (val & ARIZONA_DAC_UNDERCLOCKED_STS)
148*4882a593Smuzhiyun dev_err(arizona->dev, "DAC underclocked\n");
149*4882a593Smuzhiyun if (val & ARIZONA_ADC_UNDERCLOCKED_STS)
150*4882a593Smuzhiyun dev_err(arizona->dev, "ADC underclocked\n");
151*4882a593Smuzhiyun if (val & ARIZONA_MIXER_UNDERCLOCKED_STS)
152*4882a593Smuzhiyun dev_err(arizona->dev, "Mixer dropped sample\n");
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun return IRQ_HANDLED;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
arizona_overclocked(int irq,void * data)157*4882a593Smuzhiyun static irqreturn_t arizona_overclocked(int irq, void *data)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun struct arizona *arizona = data;
160*4882a593Smuzhiyun unsigned int val[3];
161*4882a593Smuzhiyun int ret;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun ret = regmap_bulk_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_6,
164*4882a593Smuzhiyun &val[0], 3);
165*4882a593Smuzhiyun if (ret != 0) {
166*4882a593Smuzhiyun dev_err(arizona->dev, "Failed to read overclock status: %d\n",
167*4882a593Smuzhiyun ret);
168*4882a593Smuzhiyun return IRQ_NONE;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun switch (arizona->type) {
172*4882a593Smuzhiyun case WM8998:
173*4882a593Smuzhiyun case WM1814:
174*4882a593Smuzhiyun /* Some bits are shifted on WM8998,
175*4882a593Smuzhiyun * rearrange to match the standard bit layout
176*4882a593Smuzhiyun */
177*4882a593Smuzhiyun val[0] = ((val[0] & 0x60e0) >> 1) |
178*4882a593Smuzhiyun ((val[0] & 0x1e00) >> 2) |
179*4882a593Smuzhiyun (val[0] & 0x000f);
180*4882a593Smuzhiyun break;
181*4882a593Smuzhiyun default:
182*4882a593Smuzhiyun break;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun if (val[0] & ARIZONA_PWM_OVERCLOCKED_STS)
186*4882a593Smuzhiyun dev_err(arizona->dev, "PWM overclocked\n");
187*4882a593Smuzhiyun if (val[0] & ARIZONA_FX_CORE_OVERCLOCKED_STS)
188*4882a593Smuzhiyun dev_err(arizona->dev, "FX core overclocked\n");
189*4882a593Smuzhiyun if (val[0] & ARIZONA_DAC_SYS_OVERCLOCKED_STS)
190*4882a593Smuzhiyun dev_err(arizona->dev, "DAC SYS overclocked\n");
191*4882a593Smuzhiyun if (val[0] & ARIZONA_DAC_WARP_OVERCLOCKED_STS)
192*4882a593Smuzhiyun dev_err(arizona->dev, "DAC WARP overclocked\n");
193*4882a593Smuzhiyun if (val[0] & ARIZONA_ADC_OVERCLOCKED_STS)
194*4882a593Smuzhiyun dev_err(arizona->dev, "ADC overclocked\n");
195*4882a593Smuzhiyun if (val[0] & ARIZONA_MIXER_OVERCLOCKED_STS)
196*4882a593Smuzhiyun dev_err(arizona->dev, "Mixer overclocked\n");
197*4882a593Smuzhiyun if (val[0] & ARIZONA_AIF3_SYNC_OVERCLOCKED_STS)
198*4882a593Smuzhiyun dev_err(arizona->dev, "AIF3 overclocked\n");
199*4882a593Smuzhiyun if (val[0] & ARIZONA_AIF2_SYNC_OVERCLOCKED_STS)
200*4882a593Smuzhiyun dev_err(arizona->dev, "AIF2 overclocked\n");
201*4882a593Smuzhiyun if (val[0] & ARIZONA_AIF1_SYNC_OVERCLOCKED_STS)
202*4882a593Smuzhiyun dev_err(arizona->dev, "AIF1 overclocked\n");
203*4882a593Smuzhiyun if (val[0] & ARIZONA_PAD_CTRL_OVERCLOCKED_STS)
204*4882a593Smuzhiyun dev_err(arizona->dev, "Pad control overclocked\n");
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun if (val[1] & ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS)
207*4882a593Smuzhiyun dev_err(arizona->dev, "Slimbus subsystem overclocked\n");
208*4882a593Smuzhiyun if (val[1] & ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS)
209*4882a593Smuzhiyun dev_err(arizona->dev, "Slimbus async overclocked\n");
210*4882a593Smuzhiyun if (val[1] & ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS)
211*4882a593Smuzhiyun dev_err(arizona->dev, "Slimbus sync overclocked\n");
212*4882a593Smuzhiyun if (val[1] & ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS)
213*4882a593Smuzhiyun dev_err(arizona->dev, "ASRC async system overclocked\n");
214*4882a593Smuzhiyun if (val[1] & ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS)
215*4882a593Smuzhiyun dev_err(arizona->dev, "ASRC async WARP overclocked\n");
216*4882a593Smuzhiyun if (val[1] & ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS)
217*4882a593Smuzhiyun dev_err(arizona->dev, "ASRC sync system overclocked\n");
218*4882a593Smuzhiyun if (val[1] & ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS)
219*4882a593Smuzhiyun dev_err(arizona->dev, "ASRC sync WARP overclocked\n");
220*4882a593Smuzhiyun if (val[1] & ARIZONA_ADSP2_1_OVERCLOCKED_STS)
221*4882a593Smuzhiyun dev_err(arizona->dev, "DSP1 overclocked\n");
222*4882a593Smuzhiyun if (val[1] & ARIZONA_ISRC3_OVERCLOCKED_STS)
223*4882a593Smuzhiyun dev_err(arizona->dev, "ISRC3 overclocked\n");
224*4882a593Smuzhiyun if (val[1] & ARIZONA_ISRC2_OVERCLOCKED_STS)
225*4882a593Smuzhiyun dev_err(arizona->dev, "ISRC2 overclocked\n");
226*4882a593Smuzhiyun if (val[1] & ARIZONA_ISRC1_OVERCLOCKED_STS)
227*4882a593Smuzhiyun dev_err(arizona->dev, "ISRC1 overclocked\n");
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun if (val[2] & ARIZONA_SPDIF_OVERCLOCKED_STS)
230*4882a593Smuzhiyun dev_err(arizona->dev, "SPDIF overclocked\n");
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun return IRQ_HANDLED;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun #define ARIZONA_REG_POLL_DELAY_US 7500
236*4882a593Smuzhiyun
arizona_poll_reg_delay(ktime_t timeout)237*4882a593Smuzhiyun static inline bool arizona_poll_reg_delay(ktime_t timeout)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun if (ktime_compare(ktime_get(), timeout) > 0)
240*4882a593Smuzhiyun return false;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun usleep_range(ARIZONA_REG_POLL_DELAY_US / 2, ARIZONA_REG_POLL_DELAY_US);
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun return true;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun
arizona_poll_reg(struct arizona * arizona,int timeout_ms,unsigned int reg,unsigned int mask,unsigned int target)247*4882a593Smuzhiyun static int arizona_poll_reg(struct arizona *arizona,
248*4882a593Smuzhiyun int timeout_ms, unsigned int reg,
249*4882a593Smuzhiyun unsigned int mask, unsigned int target)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun ktime_t timeout = ktime_add_us(ktime_get(), timeout_ms * USEC_PER_MSEC);
252*4882a593Smuzhiyun unsigned int val = 0;
253*4882a593Smuzhiyun int ret;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun do {
256*4882a593Smuzhiyun ret = regmap_read(arizona->regmap, reg, &val);
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun if ((val & mask) == target)
259*4882a593Smuzhiyun return 0;
260*4882a593Smuzhiyun } while (arizona_poll_reg_delay(timeout));
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun if (ret) {
263*4882a593Smuzhiyun dev_err(arizona->dev, "Failed polling reg 0x%x: %d\n",
264*4882a593Smuzhiyun reg, ret);
265*4882a593Smuzhiyun return ret;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun dev_err(arizona->dev, "Polling reg 0x%x timed out: %x\n", reg, val);
269*4882a593Smuzhiyun return -ETIMEDOUT;
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun
arizona_wait_for_boot(struct arizona * arizona)272*4882a593Smuzhiyun static int arizona_wait_for_boot(struct arizona *arizona)
273*4882a593Smuzhiyun {
274*4882a593Smuzhiyun int ret;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun /*
277*4882a593Smuzhiyun * We can't use an interrupt as we need to runtime resume to do so,
278*4882a593Smuzhiyun * we won't race with the interrupt handler as it'll be blocked on
279*4882a593Smuzhiyun * runtime resume.
280*4882a593Smuzhiyun */
281*4882a593Smuzhiyun ret = arizona_poll_reg(arizona, 30, ARIZONA_INTERRUPT_RAW_STATUS_5,
282*4882a593Smuzhiyun ARIZONA_BOOT_DONE_STS, ARIZONA_BOOT_DONE_STS);
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun if (!ret)
285*4882a593Smuzhiyun regmap_write(arizona->regmap, ARIZONA_INTERRUPT_STATUS_5,
286*4882a593Smuzhiyun ARIZONA_BOOT_DONE_STS);
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun pm_runtime_mark_last_busy(arizona->dev);
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun return ret;
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun
arizona_enable_reset(struct arizona * arizona)293*4882a593Smuzhiyun static inline void arizona_enable_reset(struct arizona *arizona)
294*4882a593Smuzhiyun {
295*4882a593Smuzhiyun if (arizona->pdata.reset)
296*4882a593Smuzhiyun gpiod_set_raw_value_cansleep(arizona->pdata.reset, 0);
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
arizona_disable_reset(struct arizona * arizona)299*4882a593Smuzhiyun static void arizona_disable_reset(struct arizona *arizona)
300*4882a593Smuzhiyun {
301*4882a593Smuzhiyun if (arizona->pdata.reset) {
302*4882a593Smuzhiyun switch (arizona->type) {
303*4882a593Smuzhiyun case WM5110:
304*4882a593Smuzhiyun case WM8280:
305*4882a593Smuzhiyun /* Meet requirements for minimum reset duration */
306*4882a593Smuzhiyun usleep_range(5000, 10000);
307*4882a593Smuzhiyun break;
308*4882a593Smuzhiyun default:
309*4882a593Smuzhiyun break;
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun gpiod_set_raw_value_cansleep(arizona->pdata.reset, 1);
313*4882a593Smuzhiyun usleep_range(1000, 5000);
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun struct arizona_sysclk_state {
318*4882a593Smuzhiyun unsigned int fll;
319*4882a593Smuzhiyun unsigned int sysclk;
320*4882a593Smuzhiyun };
321*4882a593Smuzhiyun
arizona_enable_freerun_sysclk(struct arizona * arizona,struct arizona_sysclk_state * state)322*4882a593Smuzhiyun static int arizona_enable_freerun_sysclk(struct arizona *arizona,
323*4882a593Smuzhiyun struct arizona_sysclk_state *state)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun int ret, err;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun /* Cache existing FLL and SYSCLK settings */
328*4882a593Smuzhiyun ret = regmap_read(arizona->regmap, ARIZONA_FLL1_CONTROL_1, &state->fll);
329*4882a593Smuzhiyun if (ret) {
330*4882a593Smuzhiyun dev_err(arizona->dev, "Failed to cache FLL settings: %d\n",
331*4882a593Smuzhiyun ret);
332*4882a593Smuzhiyun return ret;
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1,
335*4882a593Smuzhiyun &state->sysclk);
336*4882a593Smuzhiyun if (ret) {
337*4882a593Smuzhiyun dev_err(arizona->dev, "Failed to cache SYSCLK settings: %d\n",
338*4882a593Smuzhiyun ret);
339*4882a593Smuzhiyun return ret;
340*4882a593Smuzhiyun }
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun /* Start up SYSCLK using the FLL in free running mode */
343*4882a593Smuzhiyun ret = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1,
344*4882a593Smuzhiyun ARIZONA_FLL1_ENA | ARIZONA_FLL1_FREERUN);
345*4882a593Smuzhiyun if (ret) {
346*4882a593Smuzhiyun dev_err(arizona->dev,
347*4882a593Smuzhiyun "Failed to start FLL in freerunning mode: %d\n",
348*4882a593Smuzhiyun ret);
349*4882a593Smuzhiyun return ret;
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun ret = arizona_poll_reg(arizona, 180, ARIZONA_INTERRUPT_RAW_STATUS_5,
352*4882a593Smuzhiyun ARIZONA_FLL1_CLOCK_OK_STS,
353*4882a593Smuzhiyun ARIZONA_FLL1_CLOCK_OK_STS);
354*4882a593Smuzhiyun if (ret)
355*4882a593Smuzhiyun goto err_fll;
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun ret = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, 0x0144);
358*4882a593Smuzhiyun if (ret) {
359*4882a593Smuzhiyun dev_err(arizona->dev, "Failed to start SYSCLK: %d\n", ret);
360*4882a593Smuzhiyun goto err_fll;
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun return 0;
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun err_fll:
366*4882a593Smuzhiyun err = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1, state->fll);
367*4882a593Smuzhiyun if (err)
368*4882a593Smuzhiyun dev_err(arizona->dev,
369*4882a593Smuzhiyun "Failed to re-apply old FLL settings: %d\n", err);
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun return ret;
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun
arizona_disable_freerun_sysclk(struct arizona * arizona,struct arizona_sysclk_state * state)374*4882a593Smuzhiyun static int arizona_disable_freerun_sysclk(struct arizona *arizona,
375*4882a593Smuzhiyun struct arizona_sysclk_state *state)
376*4882a593Smuzhiyun {
377*4882a593Smuzhiyun int ret;
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun ret = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1,
380*4882a593Smuzhiyun state->sysclk);
381*4882a593Smuzhiyun if (ret) {
382*4882a593Smuzhiyun dev_err(arizona->dev,
383*4882a593Smuzhiyun "Failed to re-apply old SYSCLK settings: %d\n", ret);
384*4882a593Smuzhiyun return ret;
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun ret = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1, state->fll);
388*4882a593Smuzhiyun if (ret) {
389*4882a593Smuzhiyun dev_err(arizona->dev,
390*4882a593Smuzhiyun "Failed to re-apply old FLL settings: %d\n", ret);
391*4882a593Smuzhiyun return ret;
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun return 0;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun
wm5102_apply_hardware_patch(struct arizona * arizona)397*4882a593Smuzhiyun static int wm5102_apply_hardware_patch(struct arizona *arizona)
398*4882a593Smuzhiyun {
399*4882a593Smuzhiyun struct arizona_sysclk_state state;
400*4882a593Smuzhiyun int err, ret;
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun ret = arizona_enable_freerun_sysclk(arizona, &state);
403*4882a593Smuzhiyun if (ret)
404*4882a593Smuzhiyun return ret;
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun /* Start the write sequencer and wait for it to finish */
407*4882a593Smuzhiyun ret = regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
408*4882a593Smuzhiyun ARIZONA_WSEQ_ENA | ARIZONA_WSEQ_START | 160);
409*4882a593Smuzhiyun if (ret) {
410*4882a593Smuzhiyun dev_err(arizona->dev, "Failed to start write sequencer: %d\n",
411*4882a593Smuzhiyun ret);
412*4882a593Smuzhiyun goto err;
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun ret = arizona_poll_reg(arizona, 30, ARIZONA_WRITE_SEQUENCER_CTRL_1,
416*4882a593Smuzhiyun ARIZONA_WSEQ_BUSY, 0);
417*4882a593Smuzhiyun if (ret)
418*4882a593Smuzhiyun regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
419*4882a593Smuzhiyun ARIZONA_WSEQ_ABORT);
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun err:
422*4882a593Smuzhiyun err = arizona_disable_freerun_sysclk(arizona, &state);
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun return ret ?: err;
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun /*
428*4882a593Smuzhiyun * Register patch to some of the CODECs internal write sequences
429*4882a593Smuzhiyun * to ensure a clean exit from the low power sleep state.
430*4882a593Smuzhiyun */
431*4882a593Smuzhiyun static const struct reg_sequence wm5110_sleep_patch[] = {
432*4882a593Smuzhiyun { 0x337A, 0xC100 },
433*4882a593Smuzhiyun { 0x337B, 0x0041 },
434*4882a593Smuzhiyun { 0x3300, 0xA210 },
435*4882a593Smuzhiyun { 0x3301, 0x050C },
436*4882a593Smuzhiyun };
437*4882a593Smuzhiyun
wm5110_apply_sleep_patch(struct arizona * arizona)438*4882a593Smuzhiyun static int wm5110_apply_sleep_patch(struct arizona *arizona)
439*4882a593Smuzhiyun {
440*4882a593Smuzhiyun struct arizona_sysclk_state state;
441*4882a593Smuzhiyun int err, ret;
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun ret = arizona_enable_freerun_sysclk(arizona, &state);
444*4882a593Smuzhiyun if (ret)
445*4882a593Smuzhiyun return ret;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun ret = regmap_multi_reg_write_bypassed(arizona->regmap,
448*4882a593Smuzhiyun wm5110_sleep_patch,
449*4882a593Smuzhiyun ARRAY_SIZE(wm5110_sleep_patch));
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun err = arizona_disable_freerun_sysclk(arizona, &state);
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun return ret ?: err;
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun
wm5102_clear_write_sequencer(struct arizona * arizona)456*4882a593Smuzhiyun static int wm5102_clear_write_sequencer(struct arizona *arizona)
457*4882a593Smuzhiyun {
458*4882a593Smuzhiyun int ret;
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun ret = regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_3,
461*4882a593Smuzhiyun 0x0);
462*4882a593Smuzhiyun if (ret) {
463*4882a593Smuzhiyun dev_err(arizona->dev,
464*4882a593Smuzhiyun "Failed to clear write sequencer state: %d\n", ret);
465*4882a593Smuzhiyun return ret;
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun arizona_enable_reset(arizona);
469*4882a593Smuzhiyun regulator_disable(arizona->dcvdd);
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun msleep(20);
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun ret = regulator_enable(arizona->dcvdd);
474*4882a593Smuzhiyun if (ret) {
475*4882a593Smuzhiyun dev_err(arizona->dev, "Failed to re-enable DCVDD: %d\n", ret);
476*4882a593Smuzhiyun return ret;
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun arizona_disable_reset(arizona);
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun return 0;
481*4882a593Smuzhiyun }
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun #ifdef CONFIG_PM
arizona_isolate_dcvdd(struct arizona * arizona)484*4882a593Smuzhiyun static int arizona_isolate_dcvdd(struct arizona *arizona)
485*4882a593Smuzhiyun {
486*4882a593Smuzhiyun int ret;
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun ret = regmap_update_bits(arizona->regmap,
489*4882a593Smuzhiyun ARIZONA_ISOLATION_CONTROL,
490*4882a593Smuzhiyun ARIZONA_ISOLATE_DCVDD1,
491*4882a593Smuzhiyun ARIZONA_ISOLATE_DCVDD1);
492*4882a593Smuzhiyun if (ret != 0)
493*4882a593Smuzhiyun dev_err(arizona->dev, "Failed to isolate DCVDD: %d\n", ret);
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun return ret;
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun
arizona_connect_dcvdd(struct arizona * arizona)498*4882a593Smuzhiyun static int arizona_connect_dcvdd(struct arizona *arizona)
499*4882a593Smuzhiyun {
500*4882a593Smuzhiyun int ret;
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun ret = regmap_update_bits(arizona->regmap,
503*4882a593Smuzhiyun ARIZONA_ISOLATION_CONTROL,
504*4882a593Smuzhiyun ARIZONA_ISOLATE_DCVDD1, 0);
505*4882a593Smuzhiyun if (ret != 0)
506*4882a593Smuzhiyun dev_err(arizona->dev, "Failed to connect DCVDD: %d\n", ret);
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun return ret;
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun
arizona_is_jack_det_active(struct arizona * arizona)511*4882a593Smuzhiyun static int arizona_is_jack_det_active(struct arizona *arizona)
512*4882a593Smuzhiyun {
513*4882a593Smuzhiyun unsigned int val;
514*4882a593Smuzhiyun int ret;
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun ret = regmap_read(arizona->regmap, ARIZONA_JACK_DETECT_ANALOGUE, &val);
517*4882a593Smuzhiyun if (ret) {
518*4882a593Smuzhiyun dev_err(arizona->dev,
519*4882a593Smuzhiyun "Failed to check jack det status: %d\n", ret);
520*4882a593Smuzhiyun return ret;
521*4882a593Smuzhiyun } else if (val & ARIZONA_JD1_ENA) {
522*4882a593Smuzhiyun return 1;
523*4882a593Smuzhiyun } else {
524*4882a593Smuzhiyun return 0;
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun
arizona_runtime_resume(struct device * dev)528*4882a593Smuzhiyun static int arizona_runtime_resume(struct device *dev)
529*4882a593Smuzhiyun {
530*4882a593Smuzhiyun struct arizona *arizona = dev_get_drvdata(dev);
531*4882a593Smuzhiyun int ret;
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun dev_dbg(arizona->dev, "Leaving AoD mode\n");
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun if (arizona->has_fully_powered_off) {
536*4882a593Smuzhiyun dev_dbg(arizona->dev, "Re-enabling core supplies\n");
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun ret = regulator_bulk_enable(arizona->num_core_supplies,
539*4882a593Smuzhiyun arizona->core_supplies);
540*4882a593Smuzhiyun if (ret) {
541*4882a593Smuzhiyun dev_err(dev, "Failed to enable core supplies: %d\n",
542*4882a593Smuzhiyun ret);
543*4882a593Smuzhiyun return ret;
544*4882a593Smuzhiyun }
545*4882a593Smuzhiyun }
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun ret = regulator_enable(arizona->dcvdd);
548*4882a593Smuzhiyun if (ret != 0) {
549*4882a593Smuzhiyun dev_err(arizona->dev, "Failed to enable DCVDD: %d\n", ret);
550*4882a593Smuzhiyun if (arizona->has_fully_powered_off)
551*4882a593Smuzhiyun regulator_bulk_disable(arizona->num_core_supplies,
552*4882a593Smuzhiyun arizona->core_supplies);
553*4882a593Smuzhiyun return ret;
554*4882a593Smuzhiyun }
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun if (arizona->has_fully_powered_off) {
557*4882a593Smuzhiyun arizona_disable_reset(arizona);
558*4882a593Smuzhiyun enable_irq(arizona->irq);
559*4882a593Smuzhiyun arizona->has_fully_powered_off = false;
560*4882a593Smuzhiyun }
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun regcache_cache_only(arizona->regmap, false);
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun switch (arizona->type) {
565*4882a593Smuzhiyun case WM5102:
566*4882a593Smuzhiyun if (arizona->external_dcvdd) {
567*4882a593Smuzhiyun ret = arizona_connect_dcvdd(arizona);
568*4882a593Smuzhiyun if (ret != 0)
569*4882a593Smuzhiyun goto err;
570*4882a593Smuzhiyun }
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun ret = wm5102_patch(arizona);
573*4882a593Smuzhiyun if (ret != 0) {
574*4882a593Smuzhiyun dev_err(arizona->dev, "Failed to apply patch: %d\n",
575*4882a593Smuzhiyun ret);
576*4882a593Smuzhiyun goto err;
577*4882a593Smuzhiyun }
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun ret = wm5102_apply_hardware_patch(arizona);
580*4882a593Smuzhiyun if (ret) {
581*4882a593Smuzhiyun dev_err(arizona->dev,
582*4882a593Smuzhiyun "Failed to apply hardware patch: %d\n",
583*4882a593Smuzhiyun ret);
584*4882a593Smuzhiyun goto err;
585*4882a593Smuzhiyun }
586*4882a593Smuzhiyun break;
587*4882a593Smuzhiyun case WM5110:
588*4882a593Smuzhiyun case WM8280:
589*4882a593Smuzhiyun ret = arizona_wait_for_boot(arizona);
590*4882a593Smuzhiyun if (ret)
591*4882a593Smuzhiyun goto err;
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun if (arizona->external_dcvdd) {
594*4882a593Smuzhiyun ret = arizona_connect_dcvdd(arizona);
595*4882a593Smuzhiyun if (ret != 0)
596*4882a593Smuzhiyun goto err;
597*4882a593Smuzhiyun } else {
598*4882a593Smuzhiyun /*
599*4882a593Smuzhiyun * As this is only called for the internal regulator
600*4882a593Smuzhiyun * (where we know voltage ranges available) it is ok
601*4882a593Smuzhiyun * to request an exact range.
602*4882a593Smuzhiyun */
603*4882a593Smuzhiyun ret = regulator_set_voltage(arizona->dcvdd,
604*4882a593Smuzhiyun 1200000, 1200000);
605*4882a593Smuzhiyun if (ret < 0) {
606*4882a593Smuzhiyun dev_err(arizona->dev,
607*4882a593Smuzhiyun "Failed to set resume voltage: %d\n",
608*4882a593Smuzhiyun ret);
609*4882a593Smuzhiyun goto err;
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun }
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun ret = wm5110_apply_sleep_patch(arizona);
614*4882a593Smuzhiyun if (ret) {
615*4882a593Smuzhiyun dev_err(arizona->dev,
616*4882a593Smuzhiyun "Failed to re-apply sleep patch: %d\n",
617*4882a593Smuzhiyun ret);
618*4882a593Smuzhiyun goto err;
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun break;
621*4882a593Smuzhiyun case WM1831:
622*4882a593Smuzhiyun case CS47L24:
623*4882a593Smuzhiyun ret = arizona_wait_for_boot(arizona);
624*4882a593Smuzhiyun if (ret != 0)
625*4882a593Smuzhiyun goto err;
626*4882a593Smuzhiyun break;
627*4882a593Smuzhiyun default:
628*4882a593Smuzhiyun ret = arizona_wait_for_boot(arizona);
629*4882a593Smuzhiyun if (ret != 0)
630*4882a593Smuzhiyun goto err;
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun if (arizona->external_dcvdd) {
633*4882a593Smuzhiyun ret = arizona_connect_dcvdd(arizona);
634*4882a593Smuzhiyun if (ret != 0)
635*4882a593Smuzhiyun goto err;
636*4882a593Smuzhiyun }
637*4882a593Smuzhiyun break;
638*4882a593Smuzhiyun }
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun ret = regcache_sync(arizona->regmap);
641*4882a593Smuzhiyun if (ret != 0) {
642*4882a593Smuzhiyun dev_err(arizona->dev, "Failed to restore register cache\n");
643*4882a593Smuzhiyun goto err;
644*4882a593Smuzhiyun }
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun return 0;
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun err:
649*4882a593Smuzhiyun regcache_cache_only(arizona->regmap, true);
650*4882a593Smuzhiyun regulator_disable(arizona->dcvdd);
651*4882a593Smuzhiyun return ret;
652*4882a593Smuzhiyun }
653*4882a593Smuzhiyun
arizona_runtime_suspend(struct device * dev)654*4882a593Smuzhiyun static int arizona_runtime_suspend(struct device *dev)
655*4882a593Smuzhiyun {
656*4882a593Smuzhiyun struct arizona *arizona = dev_get_drvdata(dev);
657*4882a593Smuzhiyun int jd_active = 0;
658*4882a593Smuzhiyun int ret;
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun dev_dbg(arizona->dev, "Entering AoD mode\n");
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun switch (arizona->type) {
663*4882a593Smuzhiyun case WM5110:
664*4882a593Smuzhiyun case WM8280:
665*4882a593Smuzhiyun jd_active = arizona_is_jack_det_active(arizona);
666*4882a593Smuzhiyun if (jd_active < 0)
667*4882a593Smuzhiyun return jd_active;
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun if (arizona->external_dcvdd) {
670*4882a593Smuzhiyun ret = arizona_isolate_dcvdd(arizona);
671*4882a593Smuzhiyun if (ret != 0)
672*4882a593Smuzhiyun return ret;
673*4882a593Smuzhiyun } else {
674*4882a593Smuzhiyun /*
675*4882a593Smuzhiyun * As this is only called for the internal regulator
676*4882a593Smuzhiyun * (where we know voltage ranges available) it is ok
677*4882a593Smuzhiyun * to request an exact range.
678*4882a593Smuzhiyun */
679*4882a593Smuzhiyun ret = regulator_set_voltage(arizona->dcvdd,
680*4882a593Smuzhiyun 1175000, 1175000);
681*4882a593Smuzhiyun if (ret < 0) {
682*4882a593Smuzhiyun dev_err(arizona->dev,
683*4882a593Smuzhiyun "Failed to set suspend voltage: %d\n",
684*4882a593Smuzhiyun ret);
685*4882a593Smuzhiyun return ret;
686*4882a593Smuzhiyun }
687*4882a593Smuzhiyun }
688*4882a593Smuzhiyun break;
689*4882a593Smuzhiyun case WM5102:
690*4882a593Smuzhiyun jd_active = arizona_is_jack_det_active(arizona);
691*4882a593Smuzhiyun if (jd_active < 0)
692*4882a593Smuzhiyun return jd_active;
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun if (arizona->external_dcvdd) {
695*4882a593Smuzhiyun ret = arizona_isolate_dcvdd(arizona);
696*4882a593Smuzhiyun if (ret != 0)
697*4882a593Smuzhiyun return ret;
698*4882a593Smuzhiyun }
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun if (!jd_active) {
701*4882a593Smuzhiyun ret = regmap_write(arizona->regmap,
702*4882a593Smuzhiyun ARIZONA_WRITE_SEQUENCER_CTRL_3, 0x0);
703*4882a593Smuzhiyun if (ret) {
704*4882a593Smuzhiyun dev_err(arizona->dev,
705*4882a593Smuzhiyun "Failed to clear write sequencer: %d\n",
706*4882a593Smuzhiyun ret);
707*4882a593Smuzhiyun return ret;
708*4882a593Smuzhiyun }
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun break;
711*4882a593Smuzhiyun case WM1831:
712*4882a593Smuzhiyun case CS47L24:
713*4882a593Smuzhiyun break;
714*4882a593Smuzhiyun default:
715*4882a593Smuzhiyun jd_active = arizona_is_jack_det_active(arizona);
716*4882a593Smuzhiyun if (jd_active < 0)
717*4882a593Smuzhiyun return jd_active;
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun if (arizona->external_dcvdd) {
720*4882a593Smuzhiyun ret = arizona_isolate_dcvdd(arizona);
721*4882a593Smuzhiyun if (ret != 0)
722*4882a593Smuzhiyun return ret;
723*4882a593Smuzhiyun }
724*4882a593Smuzhiyun break;
725*4882a593Smuzhiyun }
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun regcache_cache_only(arizona->regmap, true);
728*4882a593Smuzhiyun regcache_mark_dirty(arizona->regmap);
729*4882a593Smuzhiyun regulator_disable(arizona->dcvdd);
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun /* Allow us to completely power down if no jack detection */
732*4882a593Smuzhiyun if (!jd_active) {
733*4882a593Smuzhiyun dev_dbg(arizona->dev, "Fully powering off\n");
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun arizona->has_fully_powered_off = true;
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun disable_irq_nosync(arizona->irq);
738*4882a593Smuzhiyun arizona_enable_reset(arizona);
739*4882a593Smuzhiyun regulator_bulk_disable(arizona->num_core_supplies,
740*4882a593Smuzhiyun arizona->core_supplies);
741*4882a593Smuzhiyun }
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun return 0;
744*4882a593Smuzhiyun }
745*4882a593Smuzhiyun #endif
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
arizona_suspend(struct device * dev)748*4882a593Smuzhiyun static int arizona_suspend(struct device *dev)
749*4882a593Smuzhiyun {
750*4882a593Smuzhiyun struct arizona *arizona = dev_get_drvdata(dev);
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun dev_dbg(arizona->dev, "Suspend, disabling IRQ\n");
753*4882a593Smuzhiyun disable_irq(arizona->irq);
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun return 0;
756*4882a593Smuzhiyun }
757*4882a593Smuzhiyun
arizona_suspend_noirq(struct device * dev)758*4882a593Smuzhiyun static int arizona_suspend_noirq(struct device *dev)
759*4882a593Smuzhiyun {
760*4882a593Smuzhiyun struct arizona *arizona = dev_get_drvdata(dev);
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun dev_dbg(arizona->dev, "Late suspend, reenabling IRQ\n");
763*4882a593Smuzhiyun enable_irq(arizona->irq);
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun return 0;
766*4882a593Smuzhiyun }
767*4882a593Smuzhiyun
arizona_resume_noirq(struct device * dev)768*4882a593Smuzhiyun static int arizona_resume_noirq(struct device *dev)
769*4882a593Smuzhiyun {
770*4882a593Smuzhiyun struct arizona *arizona = dev_get_drvdata(dev);
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun dev_dbg(arizona->dev, "Early resume, disabling IRQ\n");
773*4882a593Smuzhiyun disable_irq(arizona->irq);
774*4882a593Smuzhiyun
775*4882a593Smuzhiyun return 0;
776*4882a593Smuzhiyun }
777*4882a593Smuzhiyun
arizona_resume(struct device * dev)778*4882a593Smuzhiyun static int arizona_resume(struct device *dev)
779*4882a593Smuzhiyun {
780*4882a593Smuzhiyun struct arizona *arizona = dev_get_drvdata(dev);
781*4882a593Smuzhiyun
782*4882a593Smuzhiyun dev_dbg(arizona->dev, "Resume, reenabling IRQ\n");
783*4882a593Smuzhiyun enable_irq(arizona->irq);
784*4882a593Smuzhiyun
785*4882a593Smuzhiyun return 0;
786*4882a593Smuzhiyun }
787*4882a593Smuzhiyun #endif
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun const struct dev_pm_ops arizona_pm_ops = {
790*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(arizona_runtime_suspend,
791*4882a593Smuzhiyun arizona_runtime_resume,
792*4882a593Smuzhiyun NULL)
793*4882a593Smuzhiyun SET_SYSTEM_SLEEP_PM_OPS(arizona_suspend, arizona_resume)
794*4882a593Smuzhiyun SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(arizona_suspend_noirq,
795*4882a593Smuzhiyun arizona_resume_noirq)
796*4882a593Smuzhiyun };
797*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(arizona_pm_ops);
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun #ifdef CONFIG_OF
arizona_of_get_type(struct device * dev)800*4882a593Smuzhiyun unsigned long arizona_of_get_type(struct device *dev)
801*4882a593Smuzhiyun {
802*4882a593Smuzhiyun const struct of_device_id *id = of_match_device(arizona_of_match, dev);
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun if (id)
805*4882a593Smuzhiyun return (unsigned long)id->data;
806*4882a593Smuzhiyun else
807*4882a593Smuzhiyun return 0;
808*4882a593Smuzhiyun }
809*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(arizona_of_get_type);
810*4882a593Smuzhiyun
arizona_of_get_core_pdata(struct arizona * arizona)811*4882a593Smuzhiyun static int arizona_of_get_core_pdata(struct arizona *arizona)
812*4882a593Smuzhiyun {
813*4882a593Smuzhiyun struct arizona_pdata *pdata = &arizona->pdata;
814*4882a593Smuzhiyun int ret, i;
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun /* Handle old non-standard DT binding */
817*4882a593Smuzhiyun pdata->reset = devm_gpiod_get(arizona->dev, "wlf,reset", GPIOD_OUT_LOW);
818*4882a593Smuzhiyun if (IS_ERR(pdata->reset)) {
819*4882a593Smuzhiyun ret = PTR_ERR(pdata->reset);
820*4882a593Smuzhiyun
821*4882a593Smuzhiyun /*
822*4882a593Smuzhiyun * Reset missing will be caught when other binding is read
823*4882a593Smuzhiyun * but all other errors imply this binding is in use but has
824*4882a593Smuzhiyun * encountered a problem so should be handled.
825*4882a593Smuzhiyun */
826*4882a593Smuzhiyun if (ret == -EPROBE_DEFER)
827*4882a593Smuzhiyun return ret;
828*4882a593Smuzhiyun else if (ret != -ENOENT && ret != -ENOSYS)
829*4882a593Smuzhiyun dev_err(arizona->dev, "Reset GPIO malformed: %d\n",
830*4882a593Smuzhiyun ret);
831*4882a593Smuzhiyun
832*4882a593Smuzhiyun pdata->reset = NULL;
833*4882a593Smuzhiyun }
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun ret = of_property_read_u32_array(arizona->dev->of_node,
836*4882a593Smuzhiyun "wlf,gpio-defaults",
837*4882a593Smuzhiyun pdata->gpio_defaults,
838*4882a593Smuzhiyun ARRAY_SIZE(pdata->gpio_defaults));
839*4882a593Smuzhiyun if (ret >= 0) {
840*4882a593Smuzhiyun /*
841*4882a593Smuzhiyun * All values are literal except out of range values
842*4882a593Smuzhiyun * which are chip default, translate into platform
843*4882a593Smuzhiyun * data which uses 0 as chip default and out of range
844*4882a593Smuzhiyun * as zero.
845*4882a593Smuzhiyun */
846*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(pdata->gpio_defaults); i++) {
847*4882a593Smuzhiyun if (pdata->gpio_defaults[i] > 0xffff)
848*4882a593Smuzhiyun pdata->gpio_defaults[i] = 0;
849*4882a593Smuzhiyun else if (pdata->gpio_defaults[i] == 0)
850*4882a593Smuzhiyun pdata->gpio_defaults[i] = 0x10000;
851*4882a593Smuzhiyun }
852*4882a593Smuzhiyun } else {
853*4882a593Smuzhiyun dev_err(arizona->dev, "Failed to parse GPIO defaults: %d\n",
854*4882a593Smuzhiyun ret);
855*4882a593Smuzhiyun }
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun return 0;
858*4882a593Smuzhiyun }
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun const struct of_device_id arizona_of_match[] = {
861*4882a593Smuzhiyun { .compatible = "wlf,wm5102", .data = (void *)WM5102 },
862*4882a593Smuzhiyun { .compatible = "wlf,wm5110", .data = (void *)WM5110 },
863*4882a593Smuzhiyun { .compatible = "wlf,wm8280", .data = (void *)WM8280 },
864*4882a593Smuzhiyun { .compatible = "wlf,wm8997", .data = (void *)WM8997 },
865*4882a593Smuzhiyun { .compatible = "wlf,wm8998", .data = (void *)WM8998 },
866*4882a593Smuzhiyun { .compatible = "wlf,wm1814", .data = (void *)WM1814 },
867*4882a593Smuzhiyun { .compatible = "wlf,wm1831", .data = (void *)WM1831 },
868*4882a593Smuzhiyun { .compatible = "cirrus,cs47l24", .data = (void *)CS47L24 },
869*4882a593Smuzhiyun {},
870*4882a593Smuzhiyun };
871*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(arizona_of_match);
872*4882a593Smuzhiyun #else
arizona_of_get_core_pdata(struct arizona * arizona)873*4882a593Smuzhiyun static inline int arizona_of_get_core_pdata(struct arizona *arizona)
874*4882a593Smuzhiyun {
875*4882a593Smuzhiyun return 0;
876*4882a593Smuzhiyun }
877*4882a593Smuzhiyun #endif
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun static const struct mfd_cell early_devs[] = {
880*4882a593Smuzhiyun { .name = "arizona-ldo1" },
881*4882a593Smuzhiyun };
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun static const char * const wm5102_supplies[] = {
884*4882a593Smuzhiyun "MICVDD",
885*4882a593Smuzhiyun "DBVDD2",
886*4882a593Smuzhiyun "DBVDD3",
887*4882a593Smuzhiyun "CPVDD",
888*4882a593Smuzhiyun "SPKVDDL",
889*4882a593Smuzhiyun "SPKVDDR",
890*4882a593Smuzhiyun };
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun static const struct mfd_cell wm5102_devs[] = {
893*4882a593Smuzhiyun { .name = "arizona-micsupp" },
894*4882a593Smuzhiyun { .name = "arizona-gpio" },
895*4882a593Smuzhiyun {
896*4882a593Smuzhiyun .name = "arizona-extcon",
897*4882a593Smuzhiyun .parent_supplies = wm5102_supplies,
898*4882a593Smuzhiyun .num_parent_supplies = 1, /* We only need MICVDD */
899*4882a593Smuzhiyun },
900*4882a593Smuzhiyun { .name = "arizona-haptics" },
901*4882a593Smuzhiyun { .name = "arizona-pwm" },
902*4882a593Smuzhiyun {
903*4882a593Smuzhiyun .name = "wm5102-codec",
904*4882a593Smuzhiyun .parent_supplies = wm5102_supplies,
905*4882a593Smuzhiyun .num_parent_supplies = ARRAY_SIZE(wm5102_supplies),
906*4882a593Smuzhiyun },
907*4882a593Smuzhiyun };
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun static const struct mfd_cell wm5110_devs[] = {
910*4882a593Smuzhiyun { .name = "arizona-micsupp" },
911*4882a593Smuzhiyun { .name = "arizona-gpio" },
912*4882a593Smuzhiyun {
913*4882a593Smuzhiyun .name = "arizona-extcon",
914*4882a593Smuzhiyun .parent_supplies = wm5102_supplies,
915*4882a593Smuzhiyun .num_parent_supplies = 1, /* We only need MICVDD */
916*4882a593Smuzhiyun },
917*4882a593Smuzhiyun { .name = "arizona-haptics" },
918*4882a593Smuzhiyun { .name = "arizona-pwm" },
919*4882a593Smuzhiyun {
920*4882a593Smuzhiyun .name = "wm5110-codec",
921*4882a593Smuzhiyun .parent_supplies = wm5102_supplies,
922*4882a593Smuzhiyun .num_parent_supplies = ARRAY_SIZE(wm5102_supplies),
923*4882a593Smuzhiyun },
924*4882a593Smuzhiyun };
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun static const char * const cs47l24_supplies[] = {
927*4882a593Smuzhiyun "MICVDD",
928*4882a593Smuzhiyun "CPVDD",
929*4882a593Smuzhiyun "SPKVDD",
930*4882a593Smuzhiyun };
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun static const struct mfd_cell cs47l24_devs[] = {
933*4882a593Smuzhiyun { .name = "arizona-gpio" },
934*4882a593Smuzhiyun { .name = "arizona-haptics" },
935*4882a593Smuzhiyun { .name = "arizona-pwm" },
936*4882a593Smuzhiyun {
937*4882a593Smuzhiyun .name = "cs47l24-codec",
938*4882a593Smuzhiyun .parent_supplies = cs47l24_supplies,
939*4882a593Smuzhiyun .num_parent_supplies = ARRAY_SIZE(cs47l24_supplies),
940*4882a593Smuzhiyun },
941*4882a593Smuzhiyun };
942*4882a593Smuzhiyun
943*4882a593Smuzhiyun static const char * const wm8997_supplies[] = {
944*4882a593Smuzhiyun "MICVDD",
945*4882a593Smuzhiyun "DBVDD2",
946*4882a593Smuzhiyun "CPVDD",
947*4882a593Smuzhiyun "SPKVDD",
948*4882a593Smuzhiyun };
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun static const struct mfd_cell wm8997_devs[] = {
951*4882a593Smuzhiyun { .name = "arizona-micsupp" },
952*4882a593Smuzhiyun { .name = "arizona-gpio" },
953*4882a593Smuzhiyun {
954*4882a593Smuzhiyun .name = "arizona-extcon",
955*4882a593Smuzhiyun .parent_supplies = wm8997_supplies,
956*4882a593Smuzhiyun .num_parent_supplies = 1, /* We only need MICVDD */
957*4882a593Smuzhiyun },
958*4882a593Smuzhiyun { .name = "arizona-haptics" },
959*4882a593Smuzhiyun { .name = "arizona-pwm" },
960*4882a593Smuzhiyun {
961*4882a593Smuzhiyun .name = "wm8997-codec",
962*4882a593Smuzhiyun .parent_supplies = wm8997_supplies,
963*4882a593Smuzhiyun .num_parent_supplies = ARRAY_SIZE(wm8997_supplies),
964*4882a593Smuzhiyun },
965*4882a593Smuzhiyun };
966*4882a593Smuzhiyun
967*4882a593Smuzhiyun static const struct mfd_cell wm8998_devs[] = {
968*4882a593Smuzhiyun { .name = "arizona-micsupp" },
969*4882a593Smuzhiyun { .name = "arizona-gpio" },
970*4882a593Smuzhiyun {
971*4882a593Smuzhiyun .name = "arizona-extcon",
972*4882a593Smuzhiyun .parent_supplies = wm5102_supplies,
973*4882a593Smuzhiyun .num_parent_supplies = 1, /* We only need MICVDD */
974*4882a593Smuzhiyun },
975*4882a593Smuzhiyun { .name = "arizona-haptics" },
976*4882a593Smuzhiyun { .name = "arizona-pwm" },
977*4882a593Smuzhiyun {
978*4882a593Smuzhiyun .name = "wm8998-codec",
979*4882a593Smuzhiyun .parent_supplies = wm5102_supplies,
980*4882a593Smuzhiyun .num_parent_supplies = ARRAY_SIZE(wm5102_supplies),
981*4882a593Smuzhiyun },
982*4882a593Smuzhiyun };
983*4882a593Smuzhiyun
arizona_dev_init(struct arizona * arizona)984*4882a593Smuzhiyun int arizona_dev_init(struct arizona *arizona)
985*4882a593Smuzhiyun {
986*4882a593Smuzhiyun static const char * const mclk_name[] = { "mclk1", "mclk2" };
987*4882a593Smuzhiyun struct device *dev = arizona->dev;
988*4882a593Smuzhiyun const char *type_name = NULL;
989*4882a593Smuzhiyun unsigned int reg, val;
990*4882a593Smuzhiyun int (*apply_patch)(struct arizona *) = NULL;
991*4882a593Smuzhiyun const struct mfd_cell *subdevs = NULL;
992*4882a593Smuzhiyun int n_subdevs = 0, ret, i;
993*4882a593Smuzhiyun
994*4882a593Smuzhiyun dev_set_drvdata(arizona->dev, arizona);
995*4882a593Smuzhiyun mutex_init(&arizona->clk_lock);
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun if (dev_get_platdata(arizona->dev)) {
998*4882a593Smuzhiyun memcpy(&arizona->pdata, dev_get_platdata(arizona->dev),
999*4882a593Smuzhiyun sizeof(arizona->pdata));
1000*4882a593Smuzhiyun } else {
1001*4882a593Smuzhiyun ret = arizona_of_get_core_pdata(arizona);
1002*4882a593Smuzhiyun if (ret < 0)
1003*4882a593Smuzhiyun return ret;
1004*4882a593Smuzhiyun }
1005*4882a593Smuzhiyun
1006*4882a593Smuzhiyun BUILD_BUG_ON(ARRAY_SIZE(arizona->mclk) != ARRAY_SIZE(mclk_name));
1007*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(arizona->mclk); i++) {
1008*4882a593Smuzhiyun arizona->mclk[i] = devm_clk_get(arizona->dev, mclk_name[i]);
1009*4882a593Smuzhiyun if (IS_ERR(arizona->mclk[i])) {
1010*4882a593Smuzhiyun dev_info(arizona->dev, "Failed to get %s: %ld\n",
1011*4882a593Smuzhiyun mclk_name[i], PTR_ERR(arizona->mclk[i]));
1012*4882a593Smuzhiyun arizona->mclk[i] = NULL;
1013*4882a593Smuzhiyun }
1014*4882a593Smuzhiyun }
1015*4882a593Smuzhiyun
1016*4882a593Smuzhiyun regcache_cache_only(arizona->regmap, true);
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun switch (arizona->type) {
1019*4882a593Smuzhiyun case WM5102:
1020*4882a593Smuzhiyun case WM5110:
1021*4882a593Smuzhiyun case WM8280:
1022*4882a593Smuzhiyun case WM8997:
1023*4882a593Smuzhiyun case WM8998:
1024*4882a593Smuzhiyun case WM1814:
1025*4882a593Smuzhiyun case WM1831:
1026*4882a593Smuzhiyun case CS47L24:
1027*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++)
1028*4882a593Smuzhiyun arizona->core_supplies[i].supply
1029*4882a593Smuzhiyun = wm5102_core_supplies[i];
1030*4882a593Smuzhiyun arizona->num_core_supplies = ARRAY_SIZE(wm5102_core_supplies);
1031*4882a593Smuzhiyun break;
1032*4882a593Smuzhiyun default:
1033*4882a593Smuzhiyun dev_err(arizona->dev, "Unknown device type %d\n",
1034*4882a593Smuzhiyun arizona->type);
1035*4882a593Smuzhiyun return -ENODEV;
1036*4882a593Smuzhiyun }
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun /* Mark DCVDD as external, LDO1 driver will clear if internal */
1039*4882a593Smuzhiyun arizona->external_dcvdd = true;
1040*4882a593Smuzhiyun
1041*4882a593Smuzhiyun switch (arizona->type) {
1042*4882a593Smuzhiyun case WM1831:
1043*4882a593Smuzhiyun case CS47L24:
1044*4882a593Smuzhiyun break; /* No LDO1 regulator */
1045*4882a593Smuzhiyun default:
1046*4882a593Smuzhiyun ret = mfd_add_devices(arizona->dev, -1, early_devs,
1047*4882a593Smuzhiyun ARRAY_SIZE(early_devs), NULL, 0, NULL);
1048*4882a593Smuzhiyun if (ret != 0) {
1049*4882a593Smuzhiyun dev_err(dev, "Failed to add early children: %d\n", ret);
1050*4882a593Smuzhiyun return ret;
1051*4882a593Smuzhiyun }
1052*4882a593Smuzhiyun break;
1053*4882a593Smuzhiyun }
1054*4882a593Smuzhiyun
1055*4882a593Smuzhiyun ret = devm_regulator_bulk_get(dev, arizona->num_core_supplies,
1056*4882a593Smuzhiyun arizona->core_supplies);
1057*4882a593Smuzhiyun if (ret != 0) {
1058*4882a593Smuzhiyun dev_err(dev, "Failed to request core supplies: %d\n",
1059*4882a593Smuzhiyun ret);
1060*4882a593Smuzhiyun goto err_early;
1061*4882a593Smuzhiyun }
1062*4882a593Smuzhiyun
1063*4882a593Smuzhiyun /**
1064*4882a593Smuzhiyun * Don't use devres here because the only device we have to get
1065*4882a593Smuzhiyun * against is the MFD device and DCVDD will likely be supplied by
1066*4882a593Smuzhiyun * one of its children. Meaning that the regulator will be
1067*4882a593Smuzhiyun * destroyed by the time devres calls regulator put.
1068*4882a593Smuzhiyun */
1069*4882a593Smuzhiyun arizona->dcvdd = regulator_get(arizona->dev, "DCVDD");
1070*4882a593Smuzhiyun if (IS_ERR(arizona->dcvdd)) {
1071*4882a593Smuzhiyun ret = PTR_ERR(arizona->dcvdd);
1072*4882a593Smuzhiyun dev_err(dev, "Failed to request DCVDD: %d\n", ret);
1073*4882a593Smuzhiyun goto err_early;
1074*4882a593Smuzhiyun }
1075*4882a593Smuzhiyun
1076*4882a593Smuzhiyun if (!arizona->pdata.reset) {
1077*4882a593Smuzhiyun /* Start out with /RESET low to put the chip into reset */
1078*4882a593Smuzhiyun arizona->pdata.reset = devm_gpiod_get(arizona->dev, "reset",
1079*4882a593Smuzhiyun GPIOD_OUT_LOW);
1080*4882a593Smuzhiyun if (IS_ERR(arizona->pdata.reset)) {
1081*4882a593Smuzhiyun ret = PTR_ERR(arizona->pdata.reset);
1082*4882a593Smuzhiyun if (ret == -EPROBE_DEFER)
1083*4882a593Smuzhiyun goto err_dcvdd;
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun dev_err(arizona->dev,
1086*4882a593Smuzhiyun "Reset GPIO missing/malformed: %d\n", ret);
1087*4882a593Smuzhiyun
1088*4882a593Smuzhiyun arizona->pdata.reset = NULL;
1089*4882a593Smuzhiyun }
1090*4882a593Smuzhiyun }
1091*4882a593Smuzhiyun
1092*4882a593Smuzhiyun ret = regulator_bulk_enable(arizona->num_core_supplies,
1093*4882a593Smuzhiyun arizona->core_supplies);
1094*4882a593Smuzhiyun if (ret != 0) {
1095*4882a593Smuzhiyun dev_err(dev, "Failed to enable core supplies: %d\n",
1096*4882a593Smuzhiyun ret);
1097*4882a593Smuzhiyun goto err_dcvdd;
1098*4882a593Smuzhiyun }
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun ret = regulator_enable(arizona->dcvdd);
1101*4882a593Smuzhiyun if (ret != 0) {
1102*4882a593Smuzhiyun dev_err(dev, "Failed to enable DCVDD: %d\n", ret);
1103*4882a593Smuzhiyun goto err_enable;
1104*4882a593Smuzhiyun }
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun arizona_disable_reset(arizona);
1107*4882a593Smuzhiyun
1108*4882a593Smuzhiyun regcache_cache_only(arizona->regmap, false);
1109*4882a593Smuzhiyun
1110*4882a593Smuzhiyun /* Verify that this is a chip we know about */
1111*4882a593Smuzhiyun ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, ®);
1112*4882a593Smuzhiyun if (ret != 0) {
1113*4882a593Smuzhiyun dev_err(dev, "Failed to read ID register: %d\n", ret);
1114*4882a593Smuzhiyun goto err_reset;
1115*4882a593Smuzhiyun }
1116*4882a593Smuzhiyun
1117*4882a593Smuzhiyun switch (reg) {
1118*4882a593Smuzhiyun case 0x5102:
1119*4882a593Smuzhiyun case 0x5110:
1120*4882a593Smuzhiyun case 0x6349:
1121*4882a593Smuzhiyun case 0x6363:
1122*4882a593Smuzhiyun case 0x8997:
1123*4882a593Smuzhiyun break;
1124*4882a593Smuzhiyun default:
1125*4882a593Smuzhiyun dev_err(arizona->dev, "Unknown device ID: %x\n", reg);
1126*4882a593Smuzhiyun ret = -ENODEV;
1127*4882a593Smuzhiyun goto err_reset;
1128*4882a593Smuzhiyun }
1129*4882a593Smuzhiyun
1130*4882a593Smuzhiyun /* If we have a /RESET GPIO we'll already be reset */
1131*4882a593Smuzhiyun if (!arizona->pdata.reset) {
1132*4882a593Smuzhiyun ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0);
1133*4882a593Smuzhiyun if (ret != 0) {
1134*4882a593Smuzhiyun dev_err(dev, "Failed to reset device: %d\n", ret);
1135*4882a593Smuzhiyun goto err_reset;
1136*4882a593Smuzhiyun }
1137*4882a593Smuzhiyun
1138*4882a593Smuzhiyun usleep_range(1000, 5000);
1139*4882a593Smuzhiyun }
1140*4882a593Smuzhiyun
1141*4882a593Smuzhiyun /* Ensure device startup is complete */
1142*4882a593Smuzhiyun switch (arizona->type) {
1143*4882a593Smuzhiyun case WM5102:
1144*4882a593Smuzhiyun ret = regmap_read(arizona->regmap,
1145*4882a593Smuzhiyun ARIZONA_WRITE_SEQUENCER_CTRL_3, &val);
1146*4882a593Smuzhiyun if (ret) {
1147*4882a593Smuzhiyun dev_err(dev,
1148*4882a593Smuzhiyun "Failed to check write sequencer state: %d\n",
1149*4882a593Smuzhiyun ret);
1150*4882a593Smuzhiyun } else if (val & 0x01) {
1151*4882a593Smuzhiyun ret = wm5102_clear_write_sequencer(arizona);
1152*4882a593Smuzhiyun if (ret)
1153*4882a593Smuzhiyun return ret;
1154*4882a593Smuzhiyun }
1155*4882a593Smuzhiyun break;
1156*4882a593Smuzhiyun default:
1157*4882a593Smuzhiyun break;
1158*4882a593Smuzhiyun }
1159*4882a593Smuzhiyun
1160*4882a593Smuzhiyun ret = arizona_wait_for_boot(arizona);
1161*4882a593Smuzhiyun if (ret) {
1162*4882a593Smuzhiyun dev_err(arizona->dev, "Device failed initial boot: %d\n", ret);
1163*4882a593Smuzhiyun goto err_reset;
1164*4882a593Smuzhiyun }
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun /* Read the device ID information & do device specific stuff */
1167*4882a593Smuzhiyun ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, ®);
1168*4882a593Smuzhiyun if (ret != 0) {
1169*4882a593Smuzhiyun dev_err(dev, "Failed to read ID register: %d\n", ret);
1170*4882a593Smuzhiyun goto err_reset;
1171*4882a593Smuzhiyun }
1172*4882a593Smuzhiyun
1173*4882a593Smuzhiyun ret = regmap_read(arizona->regmap, ARIZONA_DEVICE_REVISION,
1174*4882a593Smuzhiyun &arizona->rev);
1175*4882a593Smuzhiyun if (ret != 0) {
1176*4882a593Smuzhiyun dev_err(dev, "Failed to read revision register: %d\n", ret);
1177*4882a593Smuzhiyun goto err_reset;
1178*4882a593Smuzhiyun }
1179*4882a593Smuzhiyun arizona->rev &= ARIZONA_DEVICE_REVISION_MASK;
1180*4882a593Smuzhiyun
1181*4882a593Smuzhiyun switch (reg) {
1182*4882a593Smuzhiyun case 0x5102:
1183*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_MFD_WM5102)) {
1184*4882a593Smuzhiyun type_name = "WM5102";
1185*4882a593Smuzhiyun if (arizona->type != WM5102) {
1186*4882a593Smuzhiyun dev_warn(arizona->dev,
1187*4882a593Smuzhiyun "WM5102 registered as %d\n",
1188*4882a593Smuzhiyun arizona->type);
1189*4882a593Smuzhiyun arizona->type = WM5102;
1190*4882a593Smuzhiyun }
1191*4882a593Smuzhiyun
1192*4882a593Smuzhiyun apply_patch = wm5102_patch;
1193*4882a593Smuzhiyun arizona->rev &= 0x7;
1194*4882a593Smuzhiyun subdevs = wm5102_devs;
1195*4882a593Smuzhiyun n_subdevs = ARRAY_SIZE(wm5102_devs);
1196*4882a593Smuzhiyun }
1197*4882a593Smuzhiyun break;
1198*4882a593Smuzhiyun case 0x5110:
1199*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_MFD_WM5110)) {
1200*4882a593Smuzhiyun switch (arizona->type) {
1201*4882a593Smuzhiyun case WM5110:
1202*4882a593Smuzhiyun type_name = "WM5110";
1203*4882a593Smuzhiyun break;
1204*4882a593Smuzhiyun case WM8280:
1205*4882a593Smuzhiyun type_name = "WM8280";
1206*4882a593Smuzhiyun break;
1207*4882a593Smuzhiyun default:
1208*4882a593Smuzhiyun type_name = "WM5110";
1209*4882a593Smuzhiyun dev_warn(arizona->dev,
1210*4882a593Smuzhiyun "WM5110 registered as %d\n",
1211*4882a593Smuzhiyun arizona->type);
1212*4882a593Smuzhiyun arizona->type = WM5110;
1213*4882a593Smuzhiyun break;
1214*4882a593Smuzhiyun }
1215*4882a593Smuzhiyun
1216*4882a593Smuzhiyun apply_patch = wm5110_patch;
1217*4882a593Smuzhiyun subdevs = wm5110_devs;
1218*4882a593Smuzhiyun n_subdevs = ARRAY_SIZE(wm5110_devs);
1219*4882a593Smuzhiyun }
1220*4882a593Smuzhiyun break;
1221*4882a593Smuzhiyun case 0x6363:
1222*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_MFD_CS47L24)) {
1223*4882a593Smuzhiyun switch (arizona->type) {
1224*4882a593Smuzhiyun case CS47L24:
1225*4882a593Smuzhiyun type_name = "CS47L24";
1226*4882a593Smuzhiyun break;
1227*4882a593Smuzhiyun
1228*4882a593Smuzhiyun case WM1831:
1229*4882a593Smuzhiyun type_name = "WM1831";
1230*4882a593Smuzhiyun break;
1231*4882a593Smuzhiyun
1232*4882a593Smuzhiyun default:
1233*4882a593Smuzhiyun dev_warn(arizona->dev,
1234*4882a593Smuzhiyun "CS47L24 registered as %d\n",
1235*4882a593Smuzhiyun arizona->type);
1236*4882a593Smuzhiyun arizona->type = CS47L24;
1237*4882a593Smuzhiyun break;
1238*4882a593Smuzhiyun }
1239*4882a593Smuzhiyun
1240*4882a593Smuzhiyun apply_patch = cs47l24_patch;
1241*4882a593Smuzhiyun subdevs = cs47l24_devs;
1242*4882a593Smuzhiyun n_subdevs = ARRAY_SIZE(cs47l24_devs);
1243*4882a593Smuzhiyun }
1244*4882a593Smuzhiyun break;
1245*4882a593Smuzhiyun case 0x8997:
1246*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_MFD_WM8997)) {
1247*4882a593Smuzhiyun type_name = "WM8997";
1248*4882a593Smuzhiyun if (arizona->type != WM8997) {
1249*4882a593Smuzhiyun dev_warn(arizona->dev,
1250*4882a593Smuzhiyun "WM8997 registered as %d\n",
1251*4882a593Smuzhiyun arizona->type);
1252*4882a593Smuzhiyun arizona->type = WM8997;
1253*4882a593Smuzhiyun }
1254*4882a593Smuzhiyun
1255*4882a593Smuzhiyun apply_patch = wm8997_patch;
1256*4882a593Smuzhiyun subdevs = wm8997_devs;
1257*4882a593Smuzhiyun n_subdevs = ARRAY_SIZE(wm8997_devs);
1258*4882a593Smuzhiyun }
1259*4882a593Smuzhiyun break;
1260*4882a593Smuzhiyun case 0x6349:
1261*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_MFD_WM8998)) {
1262*4882a593Smuzhiyun switch (arizona->type) {
1263*4882a593Smuzhiyun case WM8998:
1264*4882a593Smuzhiyun type_name = "WM8998";
1265*4882a593Smuzhiyun break;
1266*4882a593Smuzhiyun
1267*4882a593Smuzhiyun case WM1814:
1268*4882a593Smuzhiyun type_name = "WM1814";
1269*4882a593Smuzhiyun break;
1270*4882a593Smuzhiyun
1271*4882a593Smuzhiyun default:
1272*4882a593Smuzhiyun type_name = "WM8998";
1273*4882a593Smuzhiyun dev_warn(arizona->dev,
1274*4882a593Smuzhiyun "WM8998 registered as %d\n",
1275*4882a593Smuzhiyun arizona->type);
1276*4882a593Smuzhiyun arizona->type = WM8998;
1277*4882a593Smuzhiyun }
1278*4882a593Smuzhiyun
1279*4882a593Smuzhiyun apply_patch = wm8998_patch;
1280*4882a593Smuzhiyun subdevs = wm8998_devs;
1281*4882a593Smuzhiyun n_subdevs = ARRAY_SIZE(wm8998_devs);
1282*4882a593Smuzhiyun }
1283*4882a593Smuzhiyun break;
1284*4882a593Smuzhiyun default:
1285*4882a593Smuzhiyun dev_err(arizona->dev, "Unknown device ID %x\n", reg);
1286*4882a593Smuzhiyun ret = -ENODEV;
1287*4882a593Smuzhiyun goto err_reset;
1288*4882a593Smuzhiyun }
1289*4882a593Smuzhiyun
1290*4882a593Smuzhiyun if (!subdevs) {
1291*4882a593Smuzhiyun dev_err(arizona->dev,
1292*4882a593Smuzhiyun "No kernel support for device ID %x\n", reg);
1293*4882a593Smuzhiyun ret = -ENODEV;
1294*4882a593Smuzhiyun goto err_reset;
1295*4882a593Smuzhiyun }
1296*4882a593Smuzhiyun
1297*4882a593Smuzhiyun dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A');
1298*4882a593Smuzhiyun
1299*4882a593Smuzhiyun if (apply_patch) {
1300*4882a593Smuzhiyun ret = apply_patch(arizona);
1301*4882a593Smuzhiyun if (ret != 0) {
1302*4882a593Smuzhiyun dev_err(arizona->dev, "Failed to apply patch: %d\n",
1303*4882a593Smuzhiyun ret);
1304*4882a593Smuzhiyun goto err_reset;
1305*4882a593Smuzhiyun }
1306*4882a593Smuzhiyun
1307*4882a593Smuzhiyun switch (arizona->type) {
1308*4882a593Smuzhiyun case WM5102:
1309*4882a593Smuzhiyun ret = wm5102_apply_hardware_patch(arizona);
1310*4882a593Smuzhiyun if (ret) {
1311*4882a593Smuzhiyun dev_err(arizona->dev,
1312*4882a593Smuzhiyun "Failed to apply hardware patch: %d\n",
1313*4882a593Smuzhiyun ret);
1314*4882a593Smuzhiyun goto err_reset;
1315*4882a593Smuzhiyun }
1316*4882a593Smuzhiyun break;
1317*4882a593Smuzhiyun case WM5110:
1318*4882a593Smuzhiyun case WM8280:
1319*4882a593Smuzhiyun ret = wm5110_apply_sleep_patch(arizona);
1320*4882a593Smuzhiyun if (ret) {
1321*4882a593Smuzhiyun dev_err(arizona->dev,
1322*4882a593Smuzhiyun "Failed to apply sleep patch: %d\n",
1323*4882a593Smuzhiyun ret);
1324*4882a593Smuzhiyun goto err_reset;
1325*4882a593Smuzhiyun }
1326*4882a593Smuzhiyun break;
1327*4882a593Smuzhiyun default:
1328*4882a593Smuzhiyun break;
1329*4882a593Smuzhiyun }
1330*4882a593Smuzhiyun }
1331*4882a593Smuzhiyun
1332*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
1333*4882a593Smuzhiyun if (!arizona->pdata.gpio_defaults[i])
1334*4882a593Smuzhiyun continue;
1335*4882a593Smuzhiyun
1336*4882a593Smuzhiyun regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i,
1337*4882a593Smuzhiyun arizona->pdata.gpio_defaults[i]);
1338*4882a593Smuzhiyun }
1339*4882a593Smuzhiyun
1340*4882a593Smuzhiyun /* Chip default */
1341*4882a593Smuzhiyun if (!arizona->pdata.clk32k_src)
1342*4882a593Smuzhiyun arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2;
1343*4882a593Smuzhiyun
1344*4882a593Smuzhiyun switch (arizona->pdata.clk32k_src) {
1345*4882a593Smuzhiyun case ARIZONA_32KZ_MCLK1:
1346*4882a593Smuzhiyun case ARIZONA_32KZ_MCLK2:
1347*4882a593Smuzhiyun regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
1348*4882a593Smuzhiyun ARIZONA_CLK_32K_SRC_MASK,
1349*4882a593Smuzhiyun arizona->pdata.clk32k_src - 1);
1350*4882a593Smuzhiyun arizona_clk32k_enable(arizona);
1351*4882a593Smuzhiyun break;
1352*4882a593Smuzhiyun case ARIZONA_32KZ_NONE:
1353*4882a593Smuzhiyun regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
1354*4882a593Smuzhiyun ARIZONA_CLK_32K_SRC_MASK, 2);
1355*4882a593Smuzhiyun break;
1356*4882a593Smuzhiyun default:
1357*4882a593Smuzhiyun dev_err(arizona->dev, "Invalid 32kHz clock source: %d\n",
1358*4882a593Smuzhiyun arizona->pdata.clk32k_src);
1359*4882a593Smuzhiyun ret = -EINVAL;
1360*4882a593Smuzhiyun goto err_reset;
1361*4882a593Smuzhiyun }
1362*4882a593Smuzhiyun
1363*4882a593Smuzhiyun for (i = 0; i < ARIZONA_MAX_MICBIAS; i++) {
1364*4882a593Smuzhiyun if (!arizona->pdata.micbias[i].mV &&
1365*4882a593Smuzhiyun !arizona->pdata.micbias[i].bypass)
1366*4882a593Smuzhiyun continue;
1367*4882a593Smuzhiyun
1368*4882a593Smuzhiyun /* Apply default for bypass mode */
1369*4882a593Smuzhiyun if (!arizona->pdata.micbias[i].mV)
1370*4882a593Smuzhiyun arizona->pdata.micbias[i].mV = 2800;
1371*4882a593Smuzhiyun
1372*4882a593Smuzhiyun val = (arizona->pdata.micbias[i].mV - 1500) / 100;
1373*4882a593Smuzhiyun
1374*4882a593Smuzhiyun val <<= ARIZONA_MICB1_LVL_SHIFT;
1375*4882a593Smuzhiyun
1376*4882a593Smuzhiyun if (arizona->pdata.micbias[i].ext_cap)
1377*4882a593Smuzhiyun val |= ARIZONA_MICB1_EXT_CAP;
1378*4882a593Smuzhiyun
1379*4882a593Smuzhiyun if (arizona->pdata.micbias[i].discharge)
1380*4882a593Smuzhiyun val |= ARIZONA_MICB1_DISCH;
1381*4882a593Smuzhiyun
1382*4882a593Smuzhiyun if (arizona->pdata.micbias[i].soft_start)
1383*4882a593Smuzhiyun val |= ARIZONA_MICB1_RATE;
1384*4882a593Smuzhiyun
1385*4882a593Smuzhiyun if (arizona->pdata.micbias[i].bypass)
1386*4882a593Smuzhiyun val |= ARIZONA_MICB1_BYPASS;
1387*4882a593Smuzhiyun
1388*4882a593Smuzhiyun regmap_update_bits(arizona->regmap,
1389*4882a593Smuzhiyun ARIZONA_MIC_BIAS_CTRL_1 + i,
1390*4882a593Smuzhiyun ARIZONA_MICB1_LVL_MASK |
1391*4882a593Smuzhiyun ARIZONA_MICB1_EXT_CAP |
1392*4882a593Smuzhiyun ARIZONA_MICB1_DISCH |
1393*4882a593Smuzhiyun ARIZONA_MICB1_BYPASS |
1394*4882a593Smuzhiyun ARIZONA_MICB1_RATE, val);
1395*4882a593Smuzhiyun }
1396*4882a593Smuzhiyun
1397*4882a593Smuzhiyun pm_runtime_set_active(arizona->dev);
1398*4882a593Smuzhiyun pm_runtime_enable(arizona->dev);
1399*4882a593Smuzhiyun
1400*4882a593Smuzhiyun /* Set up for interrupts */
1401*4882a593Smuzhiyun ret = arizona_irq_init(arizona);
1402*4882a593Smuzhiyun if (ret != 0)
1403*4882a593Smuzhiyun goto err_pm;
1404*4882a593Smuzhiyun
1405*4882a593Smuzhiyun pm_runtime_set_autosuspend_delay(arizona->dev, 100);
1406*4882a593Smuzhiyun pm_runtime_use_autosuspend(arizona->dev);
1407*4882a593Smuzhiyun
1408*4882a593Smuzhiyun arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error",
1409*4882a593Smuzhiyun arizona_clkgen_err, arizona);
1410*4882a593Smuzhiyun arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked",
1411*4882a593Smuzhiyun arizona_overclocked, arizona);
1412*4882a593Smuzhiyun arizona_request_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, "Underclocked",
1413*4882a593Smuzhiyun arizona_underclocked, arizona);
1414*4882a593Smuzhiyun
1415*4882a593Smuzhiyun ret = mfd_add_devices(arizona->dev, PLATFORM_DEVID_NONE,
1416*4882a593Smuzhiyun subdevs, n_subdevs, NULL, 0, NULL);
1417*4882a593Smuzhiyun
1418*4882a593Smuzhiyun if (ret) {
1419*4882a593Smuzhiyun dev_err(arizona->dev, "Failed to add subdevices: %d\n", ret);
1420*4882a593Smuzhiyun goto err_irq;
1421*4882a593Smuzhiyun }
1422*4882a593Smuzhiyun
1423*4882a593Smuzhiyun return 0;
1424*4882a593Smuzhiyun
1425*4882a593Smuzhiyun err_irq:
1426*4882a593Smuzhiyun arizona_irq_exit(arizona);
1427*4882a593Smuzhiyun err_pm:
1428*4882a593Smuzhiyun pm_runtime_disable(arizona->dev);
1429*4882a593Smuzhiyun
1430*4882a593Smuzhiyun switch (arizona->pdata.clk32k_src) {
1431*4882a593Smuzhiyun case ARIZONA_32KZ_MCLK1:
1432*4882a593Smuzhiyun case ARIZONA_32KZ_MCLK2:
1433*4882a593Smuzhiyun arizona_clk32k_disable(arizona);
1434*4882a593Smuzhiyun break;
1435*4882a593Smuzhiyun default:
1436*4882a593Smuzhiyun break;
1437*4882a593Smuzhiyun }
1438*4882a593Smuzhiyun err_reset:
1439*4882a593Smuzhiyun arizona_enable_reset(arizona);
1440*4882a593Smuzhiyun regulator_disable(arizona->dcvdd);
1441*4882a593Smuzhiyun err_enable:
1442*4882a593Smuzhiyun regulator_bulk_disable(arizona->num_core_supplies,
1443*4882a593Smuzhiyun arizona->core_supplies);
1444*4882a593Smuzhiyun err_dcvdd:
1445*4882a593Smuzhiyun regulator_put(arizona->dcvdd);
1446*4882a593Smuzhiyun err_early:
1447*4882a593Smuzhiyun mfd_remove_devices(dev);
1448*4882a593Smuzhiyun return ret;
1449*4882a593Smuzhiyun }
1450*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(arizona_dev_init);
1451*4882a593Smuzhiyun
arizona_dev_exit(struct arizona * arizona)1452*4882a593Smuzhiyun int arizona_dev_exit(struct arizona *arizona)
1453*4882a593Smuzhiyun {
1454*4882a593Smuzhiyun disable_irq(arizona->irq);
1455*4882a593Smuzhiyun pm_runtime_disable(arizona->dev);
1456*4882a593Smuzhiyun
1457*4882a593Smuzhiyun regulator_disable(arizona->dcvdd);
1458*4882a593Smuzhiyun regulator_put(arizona->dcvdd);
1459*4882a593Smuzhiyun
1460*4882a593Smuzhiyun switch (arizona->pdata.clk32k_src) {
1461*4882a593Smuzhiyun case ARIZONA_32KZ_MCLK1:
1462*4882a593Smuzhiyun case ARIZONA_32KZ_MCLK2:
1463*4882a593Smuzhiyun arizona_clk32k_disable(arizona);
1464*4882a593Smuzhiyun break;
1465*4882a593Smuzhiyun default:
1466*4882a593Smuzhiyun break;
1467*4882a593Smuzhiyun }
1468*4882a593Smuzhiyun
1469*4882a593Smuzhiyun mfd_remove_devices(arizona->dev);
1470*4882a593Smuzhiyun arizona_free_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, arizona);
1471*4882a593Smuzhiyun arizona_free_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, arizona);
1472*4882a593Smuzhiyun arizona_free_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, arizona);
1473*4882a593Smuzhiyun arizona_irq_exit(arizona);
1474*4882a593Smuzhiyun arizona_enable_reset(arizona);
1475*4882a593Smuzhiyun
1476*4882a593Smuzhiyun regulator_bulk_disable(arizona->num_core_supplies,
1477*4882a593Smuzhiyun arizona->core_supplies);
1478*4882a593Smuzhiyun return 0;
1479*4882a593Smuzhiyun }
1480*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(arizona_dev_exit);
1481