1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Altera Arria10 DevKit System Resource MFD Driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Thor Thayer <tthayer@opensource.altera.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPI access for Altera Arria10 MAX5 System Resource Chip
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Adapted from DA9052
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/mfd/altera-a10sr.h>
15*4882a593Smuzhiyun #include <linux/mfd/core.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun #include <linux/of.h>
18*4882a593Smuzhiyun #include <linux/spi/spi.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun static const struct mfd_cell altr_a10sr_subdev_info[] = {
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun .name = "altr_a10sr_gpio",
23*4882a593Smuzhiyun .of_compatible = "altr,a10sr-gpio",
24*4882a593Smuzhiyun },
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun .name = "altr_a10sr_reset",
27*4882a593Smuzhiyun .of_compatible = "altr,a10sr-reset",
28*4882a593Smuzhiyun },
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
altr_a10sr_reg_readable(struct device * dev,unsigned int reg)31*4882a593Smuzhiyun static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun switch (reg) {
34*4882a593Smuzhiyun case ALTR_A10SR_VERSION_READ:
35*4882a593Smuzhiyun case ALTR_A10SR_LED_REG:
36*4882a593Smuzhiyun case ALTR_A10SR_PBDSW_REG:
37*4882a593Smuzhiyun case ALTR_A10SR_PBDSW_IRQ_REG:
38*4882a593Smuzhiyun case ALTR_A10SR_PWR_GOOD1_REG:
39*4882a593Smuzhiyun case ALTR_A10SR_PWR_GOOD2_REG:
40*4882a593Smuzhiyun case ALTR_A10SR_PWR_GOOD3_REG:
41*4882a593Smuzhiyun case ALTR_A10SR_FMCAB_REG:
42*4882a593Smuzhiyun case ALTR_A10SR_HPS_RST_REG:
43*4882a593Smuzhiyun case ALTR_A10SR_USB_QSPI_REG:
44*4882a593Smuzhiyun case ALTR_A10SR_SFPA_REG:
45*4882a593Smuzhiyun case ALTR_A10SR_SFPB_REG:
46*4882a593Smuzhiyun case ALTR_A10SR_I2C_M_REG:
47*4882a593Smuzhiyun case ALTR_A10SR_WARM_RST_REG:
48*4882a593Smuzhiyun case ALTR_A10SR_WR_KEY_REG:
49*4882a593Smuzhiyun case ALTR_A10SR_PMBUS_REG:
50*4882a593Smuzhiyun return true;
51*4882a593Smuzhiyun default:
52*4882a593Smuzhiyun return false;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
altr_a10sr_reg_writeable(struct device * dev,unsigned int reg)56*4882a593Smuzhiyun static bool altr_a10sr_reg_writeable(struct device *dev, unsigned int reg)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun switch (reg) {
59*4882a593Smuzhiyun case ALTR_A10SR_LED_REG:
60*4882a593Smuzhiyun case ALTR_A10SR_PBDSW_IRQ_REG:
61*4882a593Smuzhiyun case ALTR_A10SR_FMCAB_REG:
62*4882a593Smuzhiyun case ALTR_A10SR_HPS_RST_REG:
63*4882a593Smuzhiyun case ALTR_A10SR_USB_QSPI_REG:
64*4882a593Smuzhiyun case ALTR_A10SR_SFPA_REG:
65*4882a593Smuzhiyun case ALTR_A10SR_SFPB_REG:
66*4882a593Smuzhiyun case ALTR_A10SR_WARM_RST_REG:
67*4882a593Smuzhiyun case ALTR_A10SR_WR_KEY_REG:
68*4882a593Smuzhiyun case ALTR_A10SR_PMBUS_REG:
69*4882a593Smuzhiyun return true;
70*4882a593Smuzhiyun default:
71*4882a593Smuzhiyun return false;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
altr_a10sr_reg_volatile(struct device * dev,unsigned int reg)75*4882a593Smuzhiyun static bool altr_a10sr_reg_volatile(struct device *dev, unsigned int reg)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun switch (reg) {
78*4882a593Smuzhiyun case ALTR_A10SR_PBDSW_REG:
79*4882a593Smuzhiyun case ALTR_A10SR_PBDSW_IRQ_REG:
80*4882a593Smuzhiyun case ALTR_A10SR_PWR_GOOD1_REG:
81*4882a593Smuzhiyun case ALTR_A10SR_PWR_GOOD2_REG:
82*4882a593Smuzhiyun case ALTR_A10SR_PWR_GOOD3_REG:
83*4882a593Smuzhiyun case ALTR_A10SR_HPS_RST_REG:
84*4882a593Smuzhiyun case ALTR_A10SR_I2C_M_REG:
85*4882a593Smuzhiyun case ALTR_A10SR_WARM_RST_REG:
86*4882a593Smuzhiyun case ALTR_A10SR_WR_KEY_REG:
87*4882a593Smuzhiyun case ALTR_A10SR_PMBUS_REG:
88*4882a593Smuzhiyun return true;
89*4882a593Smuzhiyun default:
90*4882a593Smuzhiyun return false;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun static const struct regmap_config altr_a10sr_regmap_config = {
95*4882a593Smuzhiyun .reg_bits = 8,
96*4882a593Smuzhiyun .val_bits = 8,
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun .cache_type = REGCACHE_NONE,
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun .use_single_read = true,
101*4882a593Smuzhiyun .use_single_write = true,
102*4882a593Smuzhiyun .read_flag_mask = 1,
103*4882a593Smuzhiyun .write_flag_mask = 0,
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun .max_register = ALTR_A10SR_WR_KEY_REG,
106*4882a593Smuzhiyun .readable_reg = altr_a10sr_reg_readable,
107*4882a593Smuzhiyun .writeable_reg = altr_a10sr_reg_writeable,
108*4882a593Smuzhiyun .volatile_reg = altr_a10sr_reg_volatile,
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun
altr_a10sr_spi_probe(struct spi_device * spi)112*4882a593Smuzhiyun static int altr_a10sr_spi_probe(struct spi_device *spi)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun int ret;
115*4882a593Smuzhiyun struct altr_a10sr *a10sr;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun a10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr),
118*4882a593Smuzhiyun GFP_KERNEL);
119*4882a593Smuzhiyun if (!a10sr)
120*4882a593Smuzhiyun return -ENOMEM;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun spi->mode = SPI_MODE_3;
123*4882a593Smuzhiyun spi->bits_per_word = 8;
124*4882a593Smuzhiyun spi_setup(spi);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun a10sr->dev = &spi->dev;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun spi_set_drvdata(spi, a10sr);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun a10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config);
131*4882a593Smuzhiyun if (IS_ERR(a10sr->regmap)) {
132*4882a593Smuzhiyun ret = PTR_ERR(a10sr->regmap);
133*4882a593Smuzhiyun dev_err(&spi->dev, "Failed to allocate register map: %d\n",
134*4882a593Smuzhiyun ret);
135*4882a593Smuzhiyun return ret;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun ret = devm_mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO,
139*4882a593Smuzhiyun altr_a10sr_subdev_info,
140*4882a593Smuzhiyun ARRAY_SIZE(altr_a10sr_subdev_info),
141*4882a593Smuzhiyun NULL, 0, NULL);
142*4882a593Smuzhiyun if (ret)
143*4882a593Smuzhiyun dev_err(a10sr->dev, "Failed to register sub-devices: %d\n",
144*4882a593Smuzhiyun ret);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun return ret;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun static const struct of_device_id altr_a10sr_spi_of_match[] = {
150*4882a593Smuzhiyun { .compatible = "altr,a10sr" },
151*4882a593Smuzhiyun { },
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun static struct spi_driver altr_a10sr_spi_driver = {
155*4882a593Smuzhiyun .probe = altr_a10sr_spi_probe,
156*4882a593Smuzhiyun .driver = {
157*4882a593Smuzhiyun .name = "altr_a10sr",
158*4882a593Smuzhiyun .of_match_table = of_match_ptr(altr_a10sr_spi_of_match),
159*4882a593Smuzhiyun },
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun builtin_driver(altr_a10sr_spi_driver, spi_register_driver)
162