xref: /OK3568_Linux_fs/kernel/drivers/mfd/ab8500-debugfs.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) ST-Ericsson SA 2010
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun /*
8*4882a593Smuzhiyun  * AB8500 register access
9*4882a593Smuzhiyun  * ======================
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * read:
12*4882a593Smuzhiyun  * # echo BANK  >  <debugfs>/ab8500/register-bank
13*4882a593Smuzhiyun  * # echo ADDR  >  <debugfs>/ab8500/register-address
14*4882a593Smuzhiyun  * # cat <debugfs>/ab8500/register-value
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  * write:
17*4882a593Smuzhiyun  * # echo BANK  >  <debugfs>/ab8500/register-bank
18*4882a593Smuzhiyun  * # echo ADDR  >  <debugfs>/ab8500/register-address
19*4882a593Smuzhiyun  * # echo VALUE >  <debugfs>/ab8500/register-value
20*4882a593Smuzhiyun  *
21*4882a593Smuzhiyun  * read all registers from a bank:
22*4882a593Smuzhiyun  * # echo BANK  >  <debugfs>/ab8500/register-bank
23*4882a593Smuzhiyun  * # cat <debugfs>/ab8500/all-bank-register
24*4882a593Smuzhiyun  *
25*4882a593Smuzhiyun  * BANK   target AB8500 register bank
26*4882a593Smuzhiyun  * ADDR   target AB8500 register address
27*4882a593Smuzhiyun  * VALUE  decimal or 0x-prefixed hexadecimal
28*4882a593Smuzhiyun  *
29*4882a593Smuzhiyun  *
30*4882a593Smuzhiyun  * User Space notification on AB8500 IRQ
31*4882a593Smuzhiyun  * =====================================
32*4882a593Smuzhiyun  *
33*4882a593Smuzhiyun  * Allows user space entity to be notified when target AB8500 IRQ occurs.
34*4882a593Smuzhiyun  * When subscribed, a sysfs entry is created in ab8500.i2c platform device.
35*4882a593Smuzhiyun  * One can pool this file to get target IRQ occurence information.
36*4882a593Smuzhiyun  *
37*4882a593Smuzhiyun  * subscribe to an AB8500 IRQ:
38*4882a593Smuzhiyun  * # echo IRQ  >  <debugfs>/ab8500/irq-subscribe
39*4882a593Smuzhiyun  *
40*4882a593Smuzhiyun  * unsubscribe from an AB8500 IRQ:
41*4882a593Smuzhiyun  * # echo IRQ  >  <debugfs>/ab8500/irq-unsubscribe
42*4882a593Smuzhiyun  *
43*4882a593Smuzhiyun  *
44*4882a593Smuzhiyun  * AB8500 register formated read/write access
45*4882a593Smuzhiyun  * ==========================================
46*4882a593Smuzhiyun  *
47*4882a593Smuzhiyun  * Read:  read data, data>>SHIFT, data&=MASK, output data
48*4882a593Smuzhiyun  *        [0xABCDEF98] shift=12 mask=0xFFF => 0x00000CDE
49*4882a593Smuzhiyun  * Write: read data, data &= ~(MASK<<SHIFT), data |= (VALUE<<SHIFT), write data
50*4882a593Smuzhiyun  *        [0xABCDEF98] shift=12 mask=0xFFF value=0x123 => [0xAB123F98]
51*4882a593Smuzhiyun  *
52*4882a593Smuzhiyun  * Usage:
53*4882a593Smuzhiyun  * # echo "CMD [OPTIONS] BANK ADRESS [VALUE]" > $debugfs/ab8500/hwreg
54*4882a593Smuzhiyun  *
55*4882a593Smuzhiyun  * CMD      read      read access
56*4882a593Smuzhiyun  *          write     write access
57*4882a593Smuzhiyun  *
58*4882a593Smuzhiyun  * BANK     target reg bank
59*4882a593Smuzhiyun  * ADDRESS  target reg address
60*4882a593Smuzhiyun  * VALUE    (write) value to be updated
61*4882a593Smuzhiyun  *
62*4882a593Smuzhiyun  * OPTIONS
63*4882a593Smuzhiyun  *  -d|-dec            (read) output in decimal
64*4882a593Smuzhiyun  *  -h|-hexa           (read) output in 0x-hexa (default)
65*4882a593Smuzhiyun  *  -l|-w|-b           32bit (default), 16bit or 8bit reg access
66*4882a593Smuzhiyun  *  -m|-mask MASK      0x-hexa mask (default 0xFFFFFFFF)
67*4882a593Smuzhiyun  *  -s|-shift SHIFT    bit shift value (read:left, write:right)
68*4882a593Smuzhiyun  *  -o|-offset OFFSET  address offset to add to ADDRESS value
69*4882a593Smuzhiyun  *
70*4882a593Smuzhiyun  * Warning: bit shift operation is applied to bit-mask.
71*4882a593Smuzhiyun  * Warning: bit shift direction depends on read or right command.
72*4882a593Smuzhiyun  */
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #include <linux/seq_file.h>
75*4882a593Smuzhiyun #include <linux/uaccess.h>
76*4882a593Smuzhiyun #include <linux/fs.h>
77*4882a593Smuzhiyun #include <linux/init.h>
78*4882a593Smuzhiyun #include <linux/debugfs.h>
79*4882a593Smuzhiyun #include <linux/platform_device.h>
80*4882a593Smuzhiyun #include <linux/interrupt.h>
81*4882a593Smuzhiyun #include <linux/kobject.h>
82*4882a593Smuzhiyun #include <linux/slab.h>
83*4882a593Smuzhiyun #include <linux/irq.h>
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun #include <linux/mfd/abx500.h>
86*4882a593Smuzhiyun #include <linux/mfd/abx500/ab8500.h>
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS
89*4882a593Smuzhiyun #include <linux/string.h>
90*4882a593Smuzhiyun #include <linux/ctype.h>
91*4882a593Smuzhiyun #endif
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun static u32 debug_bank;
94*4882a593Smuzhiyun static u32 debug_address;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun static int irq_ab8500;
97*4882a593Smuzhiyun static int irq_first;
98*4882a593Smuzhiyun static int irq_last;
99*4882a593Smuzhiyun static u32 *irq_count;
100*4882a593Smuzhiyun static int num_irqs;
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun static struct device_attribute **dev_attr;
103*4882a593Smuzhiyun static char **event_name;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun /**
106*4882a593Smuzhiyun  * struct ab8500_reg_range
107*4882a593Smuzhiyun  * @first: the first address of the range
108*4882a593Smuzhiyun  * @last: the last address of the range
109*4882a593Smuzhiyun  * @perm: access permissions for the range
110*4882a593Smuzhiyun  */
111*4882a593Smuzhiyun struct ab8500_reg_range {
112*4882a593Smuzhiyun 	u8 first;
113*4882a593Smuzhiyun 	u8 last;
114*4882a593Smuzhiyun 	u8 perm;
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun /**
118*4882a593Smuzhiyun  * struct ab8500_prcmu_ranges
119*4882a593Smuzhiyun  * @num_ranges: the number of ranges in the list
120*4882a593Smuzhiyun  * @bankid: bank identifier
121*4882a593Smuzhiyun  * @range: the list of register ranges
122*4882a593Smuzhiyun  */
123*4882a593Smuzhiyun struct ab8500_prcmu_ranges {
124*4882a593Smuzhiyun 	u8 num_ranges;
125*4882a593Smuzhiyun 	u8 bankid;
126*4882a593Smuzhiyun 	const struct ab8500_reg_range *range;
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun /* hwreg- "mask" and "shift" entries ressources */
130*4882a593Smuzhiyun struct hwreg_cfg {
131*4882a593Smuzhiyun 	u32  bank;      /* target bank */
132*4882a593Smuzhiyun 	unsigned long addr;      /* target address */
133*4882a593Smuzhiyun 	uint fmt;       /* format */
134*4882a593Smuzhiyun 	unsigned long mask; /* read/write mask, applied before any bit shift */
135*4882a593Smuzhiyun 	long shift;     /* bit shift (read:right shift, write:left shift */
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun /* fmt bit #0: 0=hexa, 1=dec */
138*4882a593Smuzhiyun #define REG_FMT_DEC(c) ((c)->fmt & 0x1)
139*4882a593Smuzhiyun #define REG_FMT_HEX(c) (!REG_FMT_DEC(c))
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun static struct hwreg_cfg hwreg_cfg = {
142*4882a593Smuzhiyun 	.addr = 0,			/* default: invalid phys addr */
143*4882a593Smuzhiyun 	.fmt = 0,			/* default: 32bit access, hex output */
144*4882a593Smuzhiyun 	.mask = 0xFFFFFFFF,	/* default: no mask */
145*4882a593Smuzhiyun 	.shift = 0,			/* default: no bit shift */
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun #define AB8500_NAME_STRING "ab8500"
149*4882a593Smuzhiyun #define AB8500_NUM_BANKS AB8500_DEBUG_FIELD_LAST
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun #define AB8500_REV_REG 0x80
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun static struct ab8500_prcmu_ranges *debug_ranges;
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun static struct ab8500_prcmu_ranges ab8500_debug_ranges[AB8500_NUM_BANKS] = {
156*4882a593Smuzhiyun 	[AB8500_M_FSM_RANK] = {
157*4882a593Smuzhiyun 		.num_ranges = 0,
158*4882a593Smuzhiyun 		.range = NULL,
159*4882a593Smuzhiyun 	},
160*4882a593Smuzhiyun 	[AB8500_SYS_CTRL1_BLOCK] = {
161*4882a593Smuzhiyun 		.num_ranges = 3,
162*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
163*4882a593Smuzhiyun 			{
164*4882a593Smuzhiyun 				.first = 0x00,
165*4882a593Smuzhiyun 				.last = 0x02,
166*4882a593Smuzhiyun 			},
167*4882a593Smuzhiyun 			{
168*4882a593Smuzhiyun 				.first = 0x42,
169*4882a593Smuzhiyun 				.last = 0x42,
170*4882a593Smuzhiyun 			},
171*4882a593Smuzhiyun 			{
172*4882a593Smuzhiyun 				.first = 0x80,
173*4882a593Smuzhiyun 				.last = 0x81,
174*4882a593Smuzhiyun 			},
175*4882a593Smuzhiyun 		},
176*4882a593Smuzhiyun 	},
177*4882a593Smuzhiyun 	[AB8500_SYS_CTRL2_BLOCK] = {
178*4882a593Smuzhiyun 		.num_ranges = 4,
179*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
180*4882a593Smuzhiyun 			{
181*4882a593Smuzhiyun 				.first = 0x00,
182*4882a593Smuzhiyun 				.last = 0x0D,
183*4882a593Smuzhiyun 			},
184*4882a593Smuzhiyun 			{
185*4882a593Smuzhiyun 				.first = 0x0F,
186*4882a593Smuzhiyun 				.last = 0x17,
187*4882a593Smuzhiyun 			},
188*4882a593Smuzhiyun 			{
189*4882a593Smuzhiyun 				.first = 0x30,
190*4882a593Smuzhiyun 				.last = 0x30,
191*4882a593Smuzhiyun 			},
192*4882a593Smuzhiyun 			{
193*4882a593Smuzhiyun 				.first = 0x32,
194*4882a593Smuzhiyun 				.last = 0x33,
195*4882a593Smuzhiyun 			},
196*4882a593Smuzhiyun 		},
197*4882a593Smuzhiyun 	},
198*4882a593Smuzhiyun 	[AB8500_REGU_CTRL1] = {
199*4882a593Smuzhiyun 		.num_ranges = 3,
200*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
201*4882a593Smuzhiyun 			{
202*4882a593Smuzhiyun 				.first = 0x00,
203*4882a593Smuzhiyun 				.last = 0x00,
204*4882a593Smuzhiyun 			},
205*4882a593Smuzhiyun 			{
206*4882a593Smuzhiyun 				.first = 0x03,
207*4882a593Smuzhiyun 				.last = 0x10,
208*4882a593Smuzhiyun 			},
209*4882a593Smuzhiyun 			{
210*4882a593Smuzhiyun 				.first = 0x80,
211*4882a593Smuzhiyun 				.last = 0x84,
212*4882a593Smuzhiyun 			},
213*4882a593Smuzhiyun 		},
214*4882a593Smuzhiyun 	},
215*4882a593Smuzhiyun 	[AB8500_REGU_CTRL2] = {
216*4882a593Smuzhiyun 		.num_ranges = 5,
217*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
218*4882a593Smuzhiyun 			{
219*4882a593Smuzhiyun 				.first = 0x00,
220*4882a593Smuzhiyun 				.last = 0x15,
221*4882a593Smuzhiyun 			},
222*4882a593Smuzhiyun 			{
223*4882a593Smuzhiyun 				.first = 0x17,
224*4882a593Smuzhiyun 				.last = 0x19,
225*4882a593Smuzhiyun 			},
226*4882a593Smuzhiyun 			{
227*4882a593Smuzhiyun 				.first = 0x1B,
228*4882a593Smuzhiyun 				.last = 0x1D,
229*4882a593Smuzhiyun 			},
230*4882a593Smuzhiyun 			{
231*4882a593Smuzhiyun 				.first = 0x1F,
232*4882a593Smuzhiyun 				.last = 0x22,
233*4882a593Smuzhiyun 			},
234*4882a593Smuzhiyun 			{
235*4882a593Smuzhiyun 				.first = 0x40,
236*4882a593Smuzhiyun 				.last = 0x44,
237*4882a593Smuzhiyun 			},
238*4882a593Smuzhiyun 			/*
239*4882a593Smuzhiyun 			 * 0x80-0x8B are SIM registers and should
240*4882a593Smuzhiyun 			 * not be accessed from here
241*4882a593Smuzhiyun 			 */
242*4882a593Smuzhiyun 		},
243*4882a593Smuzhiyun 	},
244*4882a593Smuzhiyun 	[AB8500_USB] = {
245*4882a593Smuzhiyun 		.num_ranges = 2,
246*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
247*4882a593Smuzhiyun 			{
248*4882a593Smuzhiyun 				.first = 0x80,
249*4882a593Smuzhiyun 				.last = 0x83,
250*4882a593Smuzhiyun 			},
251*4882a593Smuzhiyun 			{
252*4882a593Smuzhiyun 				.first = 0x87,
253*4882a593Smuzhiyun 				.last = 0x8A,
254*4882a593Smuzhiyun 			},
255*4882a593Smuzhiyun 		},
256*4882a593Smuzhiyun 	},
257*4882a593Smuzhiyun 	[AB8500_TVOUT] = {
258*4882a593Smuzhiyun 		.num_ranges = 9,
259*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
260*4882a593Smuzhiyun 			{
261*4882a593Smuzhiyun 				.first = 0x00,
262*4882a593Smuzhiyun 				.last = 0x12,
263*4882a593Smuzhiyun 			},
264*4882a593Smuzhiyun 			{
265*4882a593Smuzhiyun 				.first = 0x15,
266*4882a593Smuzhiyun 				.last = 0x17,
267*4882a593Smuzhiyun 			},
268*4882a593Smuzhiyun 			{
269*4882a593Smuzhiyun 				.first = 0x19,
270*4882a593Smuzhiyun 				.last = 0x21,
271*4882a593Smuzhiyun 			},
272*4882a593Smuzhiyun 			{
273*4882a593Smuzhiyun 				.first = 0x27,
274*4882a593Smuzhiyun 				.last = 0x2C,
275*4882a593Smuzhiyun 			},
276*4882a593Smuzhiyun 			{
277*4882a593Smuzhiyun 				.first = 0x41,
278*4882a593Smuzhiyun 				.last = 0x41,
279*4882a593Smuzhiyun 			},
280*4882a593Smuzhiyun 			{
281*4882a593Smuzhiyun 				.first = 0x45,
282*4882a593Smuzhiyun 				.last = 0x5B,
283*4882a593Smuzhiyun 			},
284*4882a593Smuzhiyun 			{
285*4882a593Smuzhiyun 				.first = 0x5D,
286*4882a593Smuzhiyun 				.last = 0x5D,
287*4882a593Smuzhiyun 			},
288*4882a593Smuzhiyun 			{
289*4882a593Smuzhiyun 				.first = 0x69,
290*4882a593Smuzhiyun 				.last = 0x69,
291*4882a593Smuzhiyun 			},
292*4882a593Smuzhiyun 			{
293*4882a593Smuzhiyun 				.first = 0x80,
294*4882a593Smuzhiyun 				.last = 0x81,
295*4882a593Smuzhiyun 			},
296*4882a593Smuzhiyun 		},
297*4882a593Smuzhiyun 	},
298*4882a593Smuzhiyun 	[AB8500_DBI] = {
299*4882a593Smuzhiyun 		.num_ranges = 0,
300*4882a593Smuzhiyun 		.range = NULL,
301*4882a593Smuzhiyun 	},
302*4882a593Smuzhiyun 	[AB8500_ECI_AV_ACC] = {
303*4882a593Smuzhiyun 		.num_ranges = 1,
304*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
305*4882a593Smuzhiyun 			{
306*4882a593Smuzhiyun 				.first = 0x80,
307*4882a593Smuzhiyun 				.last = 0x82,
308*4882a593Smuzhiyun 			},
309*4882a593Smuzhiyun 		},
310*4882a593Smuzhiyun 	},
311*4882a593Smuzhiyun 	[AB8500_RESERVED] = {
312*4882a593Smuzhiyun 		.num_ranges = 0,
313*4882a593Smuzhiyun 		.range = NULL,
314*4882a593Smuzhiyun 	},
315*4882a593Smuzhiyun 	[AB8500_GPADC] = {
316*4882a593Smuzhiyun 		.num_ranges = 1,
317*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
318*4882a593Smuzhiyun 			{
319*4882a593Smuzhiyun 				.first = 0x00,
320*4882a593Smuzhiyun 				.last = 0x08,
321*4882a593Smuzhiyun 			},
322*4882a593Smuzhiyun 		},
323*4882a593Smuzhiyun 	},
324*4882a593Smuzhiyun 	[AB8500_CHARGER] = {
325*4882a593Smuzhiyun 		.num_ranges = 9,
326*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
327*4882a593Smuzhiyun 			{
328*4882a593Smuzhiyun 				.first = 0x00,
329*4882a593Smuzhiyun 				.last = 0x03,
330*4882a593Smuzhiyun 			},
331*4882a593Smuzhiyun 			{
332*4882a593Smuzhiyun 				.first = 0x05,
333*4882a593Smuzhiyun 				.last = 0x05,
334*4882a593Smuzhiyun 			},
335*4882a593Smuzhiyun 			{
336*4882a593Smuzhiyun 				.first = 0x40,
337*4882a593Smuzhiyun 				.last = 0x40,
338*4882a593Smuzhiyun 			},
339*4882a593Smuzhiyun 			{
340*4882a593Smuzhiyun 				.first = 0x42,
341*4882a593Smuzhiyun 				.last = 0x42,
342*4882a593Smuzhiyun 			},
343*4882a593Smuzhiyun 			{
344*4882a593Smuzhiyun 				.first = 0x44,
345*4882a593Smuzhiyun 				.last = 0x44,
346*4882a593Smuzhiyun 			},
347*4882a593Smuzhiyun 			{
348*4882a593Smuzhiyun 				.first = 0x50,
349*4882a593Smuzhiyun 				.last = 0x55,
350*4882a593Smuzhiyun 			},
351*4882a593Smuzhiyun 			{
352*4882a593Smuzhiyun 				.first = 0x80,
353*4882a593Smuzhiyun 				.last = 0x82,
354*4882a593Smuzhiyun 			},
355*4882a593Smuzhiyun 			{
356*4882a593Smuzhiyun 				.first = 0xC0,
357*4882a593Smuzhiyun 				.last = 0xC2,
358*4882a593Smuzhiyun 			},
359*4882a593Smuzhiyun 			{
360*4882a593Smuzhiyun 				.first = 0xf5,
361*4882a593Smuzhiyun 				.last = 0xf6,
362*4882a593Smuzhiyun 			},
363*4882a593Smuzhiyun 		},
364*4882a593Smuzhiyun 	},
365*4882a593Smuzhiyun 	[AB8500_GAS_GAUGE] = {
366*4882a593Smuzhiyun 		.num_ranges = 3,
367*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
368*4882a593Smuzhiyun 			{
369*4882a593Smuzhiyun 				.first = 0x00,
370*4882a593Smuzhiyun 				.last = 0x00,
371*4882a593Smuzhiyun 			},
372*4882a593Smuzhiyun 			{
373*4882a593Smuzhiyun 				.first = 0x07,
374*4882a593Smuzhiyun 				.last = 0x0A,
375*4882a593Smuzhiyun 			},
376*4882a593Smuzhiyun 			{
377*4882a593Smuzhiyun 				.first = 0x10,
378*4882a593Smuzhiyun 				.last = 0x14,
379*4882a593Smuzhiyun 			},
380*4882a593Smuzhiyun 		},
381*4882a593Smuzhiyun 	},
382*4882a593Smuzhiyun 	[AB8500_AUDIO] = {
383*4882a593Smuzhiyun 		.num_ranges = 1,
384*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
385*4882a593Smuzhiyun 			{
386*4882a593Smuzhiyun 				.first = 0x00,
387*4882a593Smuzhiyun 				.last = 0x6F,
388*4882a593Smuzhiyun 			},
389*4882a593Smuzhiyun 		},
390*4882a593Smuzhiyun 	},
391*4882a593Smuzhiyun 	[AB8500_INTERRUPT] = {
392*4882a593Smuzhiyun 		.num_ranges = 0,
393*4882a593Smuzhiyun 		.range = NULL,
394*4882a593Smuzhiyun 	},
395*4882a593Smuzhiyun 	[AB8500_RTC] = {
396*4882a593Smuzhiyun 		.num_ranges = 1,
397*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
398*4882a593Smuzhiyun 			{
399*4882a593Smuzhiyun 				.first = 0x00,
400*4882a593Smuzhiyun 				.last = 0x0F,
401*4882a593Smuzhiyun 			},
402*4882a593Smuzhiyun 		},
403*4882a593Smuzhiyun 	},
404*4882a593Smuzhiyun 	[AB8500_MISC] = {
405*4882a593Smuzhiyun 		.num_ranges = 8,
406*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
407*4882a593Smuzhiyun 			{
408*4882a593Smuzhiyun 				.first = 0x00,
409*4882a593Smuzhiyun 				.last = 0x05,
410*4882a593Smuzhiyun 			},
411*4882a593Smuzhiyun 			{
412*4882a593Smuzhiyun 				.first = 0x10,
413*4882a593Smuzhiyun 				.last = 0x15,
414*4882a593Smuzhiyun 			},
415*4882a593Smuzhiyun 			{
416*4882a593Smuzhiyun 				.first = 0x20,
417*4882a593Smuzhiyun 				.last = 0x25,
418*4882a593Smuzhiyun 			},
419*4882a593Smuzhiyun 			{
420*4882a593Smuzhiyun 				.first = 0x30,
421*4882a593Smuzhiyun 				.last = 0x35,
422*4882a593Smuzhiyun 			},
423*4882a593Smuzhiyun 			{
424*4882a593Smuzhiyun 				.first = 0x40,
425*4882a593Smuzhiyun 				.last = 0x45,
426*4882a593Smuzhiyun 			},
427*4882a593Smuzhiyun 			{
428*4882a593Smuzhiyun 				.first = 0x50,
429*4882a593Smuzhiyun 				.last = 0x50,
430*4882a593Smuzhiyun 			},
431*4882a593Smuzhiyun 			{
432*4882a593Smuzhiyun 				.first = 0x60,
433*4882a593Smuzhiyun 				.last = 0x67,
434*4882a593Smuzhiyun 			},
435*4882a593Smuzhiyun 			{
436*4882a593Smuzhiyun 				.first = 0x80,
437*4882a593Smuzhiyun 				.last = 0x80,
438*4882a593Smuzhiyun 			},
439*4882a593Smuzhiyun 		},
440*4882a593Smuzhiyun 	},
441*4882a593Smuzhiyun 	[AB8500_DEVELOPMENT] = {
442*4882a593Smuzhiyun 		.num_ranges = 1,
443*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
444*4882a593Smuzhiyun 			{
445*4882a593Smuzhiyun 				.first = 0x00,
446*4882a593Smuzhiyun 				.last = 0x00,
447*4882a593Smuzhiyun 			},
448*4882a593Smuzhiyun 		},
449*4882a593Smuzhiyun 	},
450*4882a593Smuzhiyun 	[AB8500_DEBUG] = {
451*4882a593Smuzhiyun 		.num_ranges = 1,
452*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
453*4882a593Smuzhiyun 			{
454*4882a593Smuzhiyun 				.first = 0x05,
455*4882a593Smuzhiyun 				.last = 0x07,
456*4882a593Smuzhiyun 			},
457*4882a593Smuzhiyun 		},
458*4882a593Smuzhiyun 	},
459*4882a593Smuzhiyun 	[AB8500_PROD_TEST] = {
460*4882a593Smuzhiyun 		.num_ranges = 0,
461*4882a593Smuzhiyun 		.range = NULL,
462*4882a593Smuzhiyun 	},
463*4882a593Smuzhiyun 	[AB8500_STE_TEST] = {
464*4882a593Smuzhiyun 		.num_ranges = 0,
465*4882a593Smuzhiyun 		.range = NULL,
466*4882a593Smuzhiyun 	},
467*4882a593Smuzhiyun 	[AB8500_OTP_EMUL] = {
468*4882a593Smuzhiyun 		.num_ranges = 1,
469*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
470*4882a593Smuzhiyun 			{
471*4882a593Smuzhiyun 				.first = 0x01,
472*4882a593Smuzhiyun 				.last = 0x0F,
473*4882a593Smuzhiyun 			},
474*4882a593Smuzhiyun 		},
475*4882a593Smuzhiyun 	},
476*4882a593Smuzhiyun };
477*4882a593Smuzhiyun 
478*4882a593Smuzhiyun static struct ab8500_prcmu_ranges ab8505_debug_ranges[AB8500_NUM_BANKS] = {
479*4882a593Smuzhiyun 	[0x0] = {
480*4882a593Smuzhiyun 		.num_ranges = 0,
481*4882a593Smuzhiyun 		.range = NULL,
482*4882a593Smuzhiyun 	},
483*4882a593Smuzhiyun 	[AB8500_SYS_CTRL1_BLOCK] = {
484*4882a593Smuzhiyun 		.num_ranges = 5,
485*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
486*4882a593Smuzhiyun 			{
487*4882a593Smuzhiyun 				.first = 0x00,
488*4882a593Smuzhiyun 				.last = 0x04,
489*4882a593Smuzhiyun 			},
490*4882a593Smuzhiyun 			{
491*4882a593Smuzhiyun 				.first = 0x42,
492*4882a593Smuzhiyun 				.last = 0x42,
493*4882a593Smuzhiyun 			},
494*4882a593Smuzhiyun 			{
495*4882a593Smuzhiyun 				.first = 0x52,
496*4882a593Smuzhiyun 				.last = 0x52,
497*4882a593Smuzhiyun 			},
498*4882a593Smuzhiyun 			{
499*4882a593Smuzhiyun 				.first = 0x54,
500*4882a593Smuzhiyun 				.last = 0x57,
501*4882a593Smuzhiyun 			},
502*4882a593Smuzhiyun 			{
503*4882a593Smuzhiyun 				.first = 0x80,
504*4882a593Smuzhiyun 				.last = 0x83,
505*4882a593Smuzhiyun 			},
506*4882a593Smuzhiyun 		},
507*4882a593Smuzhiyun 	},
508*4882a593Smuzhiyun 	[AB8500_SYS_CTRL2_BLOCK] = {
509*4882a593Smuzhiyun 		.num_ranges = 5,
510*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
511*4882a593Smuzhiyun 			{
512*4882a593Smuzhiyun 				.first = 0x00,
513*4882a593Smuzhiyun 				.last = 0x0D,
514*4882a593Smuzhiyun 			},
515*4882a593Smuzhiyun 			{
516*4882a593Smuzhiyun 				.first = 0x0F,
517*4882a593Smuzhiyun 				.last = 0x17,
518*4882a593Smuzhiyun 			},
519*4882a593Smuzhiyun 			{
520*4882a593Smuzhiyun 				.first = 0x20,
521*4882a593Smuzhiyun 				.last = 0x20,
522*4882a593Smuzhiyun 			},
523*4882a593Smuzhiyun 			{
524*4882a593Smuzhiyun 				.first = 0x30,
525*4882a593Smuzhiyun 				.last = 0x30,
526*4882a593Smuzhiyun 			},
527*4882a593Smuzhiyun 			{
528*4882a593Smuzhiyun 				.first = 0x32,
529*4882a593Smuzhiyun 				.last = 0x3A,
530*4882a593Smuzhiyun 			},
531*4882a593Smuzhiyun 		},
532*4882a593Smuzhiyun 	},
533*4882a593Smuzhiyun 	[AB8500_REGU_CTRL1] = {
534*4882a593Smuzhiyun 		.num_ranges = 3,
535*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
536*4882a593Smuzhiyun 			{
537*4882a593Smuzhiyun 				.first = 0x00,
538*4882a593Smuzhiyun 				.last = 0x00,
539*4882a593Smuzhiyun 			},
540*4882a593Smuzhiyun 			{
541*4882a593Smuzhiyun 				.first = 0x03,
542*4882a593Smuzhiyun 				.last = 0x11,
543*4882a593Smuzhiyun 			},
544*4882a593Smuzhiyun 			{
545*4882a593Smuzhiyun 				.first = 0x80,
546*4882a593Smuzhiyun 				.last = 0x86,
547*4882a593Smuzhiyun 			},
548*4882a593Smuzhiyun 		},
549*4882a593Smuzhiyun 	},
550*4882a593Smuzhiyun 	[AB8500_REGU_CTRL2] = {
551*4882a593Smuzhiyun 		.num_ranges = 6,
552*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
553*4882a593Smuzhiyun 			{
554*4882a593Smuzhiyun 				.first = 0x00,
555*4882a593Smuzhiyun 				.last = 0x06,
556*4882a593Smuzhiyun 			},
557*4882a593Smuzhiyun 			{
558*4882a593Smuzhiyun 				.first = 0x08,
559*4882a593Smuzhiyun 				.last = 0x15,
560*4882a593Smuzhiyun 			},
561*4882a593Smuzhiyun 			{
562*4882a593Smuzhiyun 				.first = 0x17,
563*4882a593Smuzhiyun 				.last = 0x19,
564*4882a593Smuzhiyun 			},
565*4882a593Smuzhiyun 			{
566*4882a593Smuzhiyun 				.first = 0x1B,
567*4882a593Smuzhiyun 				.last = 0x1D,
568*4882a593Smuzhiyun 			},
569*4882a593Smuzhiyun 			{
570*4882a593Smuzhiyun 				.first = 0x1F,
571*4882a593Smuzhiyun 				.last = 0x30,
572*4882a593Smuzhiyun 			},
573*4882a593Smuzhiyun 			{
574*4882a593Smuzhiyun 				.first = 0x40,
575*4882a593Smuzhiyun 				.last = 0x48,
576*4882a593Smuzhiyun 			},
577*4882a593Smuzhiyun 			/*
578*4882a593Smuzhiyun 			 * 0x80-0x8B are SIM registers and should
579*4882a593Smuzhiyun 			 * not be accessed from here
580*4882a593Smuzhiyun 			 */
581*4882a593Smuzhiyun 		},
582*4882a593Smuzhiyun 	},
583*4882a593Smuzhiyun 	[AB8500_USB] = {
584*4882a593Smuzhiyun 		.num_ranges = 3,
585*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
586*4882a593Smuzhiyun 			{
587*4882a593Smuzhiyun 				.first = 0x80,
588*4882a593Smuzhiyun 				.last = 0x83,
589*4882a593Smuzhiyun 			},
590*4882a593Smuzhiyun 			{
591*4882a593Smuzhiyun 				.first = 0x87,
592*4882a593Smuzhiyun 				.last = 0x8A,
593*4882a593Smuzhiyun 			},
594*4882a593Smuzhiyun 			{
595*4882a593Smuzhiyun 				.first = 0x91,
596*4882a593Smuzhiyun 				.last = 0x94,
597*4882a593Smuzhiyun 			},
598*4882a593Smuzhiyun 		},
599*4882a593Smuzhiyun 	},
600*4882a593Smuzhiyun 	[AB8500_TVOUT] = {
601*4882a593Smuzhiyun 		.num_ranges = 0,
602*4882a593Smuzhiyun 		.range = NULL,
603*4882a593Smuzhiyun 	},
604*4882a593Smuzhiyun 	[AB8500_DBI] = {
605*4882a593Smuzhiyun 		.num_ranges = 0,
606*4882a593Smuzhiyun 		.range = NULL,
607*4882a593Smuzhiyun 	},
608*4882a593Smuzhiyun 	[AB8500_ECI_AV_ACC] = {
609*4882a593Smuzhiyun 		.num_ranges = 1,
610*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
611*4882a593Smuzhiyun 			{
612*4882a593Smuzhiyun 				.first = 0x80,
613*4882a593Smuzhiyun 				.last = 0x82,
614*4882a593Smuzhiyun 			},
615*4882a593Smuzhiyun 		},
616*4882a593Smuzhiyun 	},
617*4882a593Smuzhiyun 	[AB8500_RESERVED] = {
618*4882a593Smuzhiyun 		.num_ranges = 0,
619*4882a593Smuzhiyun 		.range = NULL,
620*4882a593Smuzhiyun 	},
621*4882a593Smuzhiyun 	[AB8500_GPADC] = {
622*4882a593Smuzhiyun 		.num_ranges = 1,
623*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
624*4882a593Smuzhiyun 			{
625*4882a593Smuzhiyun 				.first = 0x00,
626*4882a593Smuzhiyun 				.last = 0x08,
627*4882a593Smuzhiyun 			},
628*4882a593Smuzhiyun 		},
629*4882a593Smuzhiyun 	},
630*4882a593Smuzhiyun 	[AB8500_CHARGER] = {
631*4882a593Smuzhiyun 		.num_ranges = 9,
632*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
633*4882a593Smuzhiyun 			{
634*4882a593Smuzhiyun 				.first = 0x02,
635*4882a593Smuzhiyun 				.last = 0x03,
636*4882a593Smuzhiyun 			},
637*4882a593Smuzhiyun 			{
638*4882a593Smuzhiyun 				.first = 0x05,
639*4882a593Smuzhiyun 				.last = 0x05,
640*4882a593Smuzhiyun 			},
641*4882a593Smuzhiyun 			{
642*4882a593Smuzhiyun 				.first = 0x40,
643*4882a593Smuzhiyun 				.last = 0x44,
644*4882a593Smuzhiyun 			},
645*4882a593Smuzhiyun 			{
646*4882a593Smuzhiyun 				.first = 0x50,
647*4882a593Smuzhiyun 				.last = 0x57,
648*4882a593Smuzhiyun 			},
649*4882a593Smuzhiyun 			{
650*4882a593Smuzhiyun 				.first = 0x60,
651*4882a593Smuzhiyun 				.last = 0x60,
652*4882a593Smuzhiyun 			},
653*4882a593Smuzhiyun 			{
654*4882a593Smuzhiyun 				.first = 0xA0,
655*4882a593Smuzhiyun 				.last = 0xA7,
656*4882a593Smuzhiyun 			},
657*4882a593Smuzhiyun 			{
658*4882a593Smuzhiyun 				.first = 0xAF,
659*4882a593Smuzhiyun 				.last = 0xB2,
660*4882a593Smuzhiyun 			},
661*4882a593Smuzhiyun 			{
662*4882a593Smuzhiyun 				.first = 0xC0,
663*4882a593Smuzhiyun 				.last = 0xC2,
664*4882a593Smuzhiyun 			},
665*4882a593Smuzhiyun 			{
666*4882a593Smuzhiyun 				.first = 0xF5,
667*4882a593Smuzhiyun 				.last = 0xF5,
668*4882a593Smuzhiyun 			},
669*4882a593Smuzhiyun 		},
670*4882a593Smuzhiyun 	},
671*4882a593Smuzhiyun 	[AB8500_GAS_GAUGE] = {
672*4882a593Smuzhiyun 		.num_ranges = 3,
673*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
674*4882a593Smuzhiyun 			{
675*4882a593Smuzhiyun 				.first = 0x00,
676*4882a593Smuzhiyun 				.last = 0x00,
677*4882a593Smuzhiyun 			},
678*4882a593Smuzhiyun 			{
679*4882a593Smuzhiyun 				.first = 0x07,
680*4882a593Smuzhiyun 				.last = 0x0A,
681*4882a593Smuzhiyun 			},
682*4882a593Smuzhiyun 			{
683*4882a593Smuzhiyun 				.first = 0x10,
684*4882a593Smuzhiyun 				.last = 0x14,
685*4882a593Smuzhiyun 			},
686*4882a593Smuzhiyun 		},
687*4882a593Smuzhiyun 	},
688*4882a593Smuzhiyun 	[AB8500_AUDIO] = {
689*4882a593Smuzhiyun 		.num_ranges = 1,
690*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
691*4882a593Smuzhiyun 			{
692*4882a593Smuzhiyun 				.first = 0x00,
693*4882a593Smuzhiyun 				.last = 0x83,
694*4882a593Smuzhiyun 			},
695*4882a593Smuzhiyun 		},
696*4882a593Smuzhiyun 	},
697*4882a593Smuzhiyun 	[AB8500_INTERRUPT] = {
698*4882a593Smuzhiyun 		.num_ranges = 11,
699*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
700*4882a593Smuzhiyun 			{
701*4882a593Smuzhiyun 				.first = 0x00,
702*4882a593Smuzhiyun 				.last = 0x04,
703*4882a593Smuzhiyun 			},
704*4882a593Smuzhiyun 			{
705*4882a593Smuzhiyun 				.first = 0x06,
706*4882a593Smuzhiyun 				.last = 0x07,
707*4882a593Smuzhiyun 			},
708*4882a593Smuzhiyun 			{
709*4882a593Smuzhiyun 				.first = 0x09,
710*4882a593Smuzhiyun 				.last = 0x09,
711*4882a593Smuzhiyun 			},
712*4882a593Smuzhiyun 			{
713*4882a593Smuzhiyun 				.first = 0x0B,
714*4882a593Smuzhiyun 				.last = 0x0C,
715*4882a593Smuzhiyun 			},
716*4882a593Smuzhiyun 			{
717*4882a593Smuzhiyun 				.first = 0x12,
718*4882a593Smuzhiyun 				.last = 0x15,
719*4882a593Smuzhiyun 			},
720*4882a593Smuzhiyun 			{
721*4882a593Smuzhiyun 				.first = 0x18,
722*4882a593Smuzhiyun 				.last = 0x18,
723*4882a593Smuzhiyun 			},
724*4882a593Smuzhiyun 			/* Latch registers should not be read here */
725*4882a593Smuzhiyun 			{
726*4882a593Smuzhiyun 				.first = 0x40,
727*4882a593Smuzhiyun 				.last = 0x44,
728*4882a593Smuzhiyun 			},
729*4882a593Smuzhiyun 			{
730*4882a593Smuzhiyun 				.first = 0x46,
731*4882a593Smuzhiyun 				.last = 0x49,
732*4882a593Smuzhiyun 			},
733*4882a593Smuzhiyun 			{
734*4882a593Smuzhiyun 				.first = 0x4B,
735*4882a593Smuzhiyun 				.last = 0x4D,
736*4882a593Smuzhiyun 			},
737*4882a593Smuzhiyun 			{
738*4882a593Smuzhiyun 				.first = 0x52,
739*4882a593Smuzhiyun 				.last = 0x55,
740*4882a593Smuzhiyun 			},
741*4882a593Smuzhiyun 			{
742*4882a593Smuzhiyun 				.first = 0x58,
743*4882a593Smuzhiyun 				.last = 0x58,
744*4882a593Smuzhiyun 			},
745*4882a593Smuzhiyun 			/* LatchHier registers should not be read here */
746*4882a593Smuzhiyun 		},
747*4882a593Smuzhiyun 	},
748*4882a593Smuzhiyun 	[AB8500_RTC] = {
749*4882a593Smuzhiyun 		.num_ranges = 2,
750*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
751*4882a593Smuzhiyun 			{
752*4882a593Smuzhiyun 				.first = 0x00,
753*4882a593Smuzhiyun 				.last = 0x14,
754*4882a593Smuzhiyun 			},
755*4882a593Smuzhiyun 			{
756*4882a593Smuzhiyun 				.first = 0x16,
757*4882a593Smuzhiyun 				.last = 0x17,
758*4882a593Smuzhiyun 			},
759*4882a593Smuzhiyun 		},
760*4882a593Smuzhiyun 	},
761*4882a593Smuzhiyun 	[AB8500_MISC] = {
762*4882a593Smuzhiyun 		.num_ranges = 8,
763*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
764*4882a593Smuzhiyun 			{
765*4882a593Smuzhiyun 				.first = 0x00,
766*4882a593Smuzhiyun 				.last = 0x06,
767*4882a593Smuzhiyun 			},
768*4882a593Smuzhiyun 			{
769*4882a593Smuzhiyun 				.first = 0x10,
770*4882a593Smuzhiyun 				.last = 0x16,
771*4882a593Smuzhiyun 			},
772*4882a593Smuzhiyun 			{
773*4882a593Smuzhiyun 				.first = 0x20,
774*4882a593Smuzhiyun 				.last = 0x26,
775*4882a593Smuzhiyun 			},
776*4882a593Smuzhiyun 			{
777*4882a593Smuzhiyun 				.first = 0x30,
778*4882a593Smuzhiyun 				.last = 0x36,
779*4882a593Smuzhiyun 			},
780*4882a593Smuzhiyun 			{
781*4882a593Smuzhiyun 				.first = 0x40,
782*4882a593Smuzhiyun 				.last = 0x46,
783*4882a593Smuzhiyun 			},
784*4882a593Smuzhiyun 			{
785*4882a593Smuzhiyun 				.first = 0x50,
786*4882a593Smuzhiyun 				.last = 0x50,
787*4882a593Smuzhiyun 			},
788*4882a593Smuzhiyun 			{
789*4882a593Smuzhiyun 				.first = 0x60,
790*4882a593Smuzhiyun 				.last = 0x6B,
791*4882a593Smuzhiyun 			},
792*4882a593Smuzhiyun 			{
793*4882a593Smuzhiyun 				.first = 0x80,
794*4882a593Smuzhiyun 				.last = 0x82,
795*4882a593Smuzhiyun 			},
796*4882a593Smuzhiyun 		},
797*4882a593Smuzhiyun 	},
798*4882a593Smuzhiyun 	[AB8500_DEVELOPMENT] = {
799*4882a593Smuzhiyun 		.num_ranges = 2,
800*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
801*4882a593Smuzhiyun 			{
802*4882a593Smuzhiyun 				.first = 0x00,
803*4882a593Smuzhiyun 				.last = 0x00,
804*4882a593Smuzhiyun 			},
805*4882a593Smuzhiyun 			{
806*4882a593Smuzhiyun 				.first = 0x05,
807*4882a593Smuzhiyun 				.last = 0x05,
808*4882a593Smuzhiyun 			},
809*4882a593Smuzhiyun 		},
810*4882a593Smuzhiyun 	},
811*4882a593Smuzhiyun 	[AB8500_DEBUG] = {
812*4882a593Smuzhiyun 		.num_ranges = 1,
813*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
814*4882a593Smuzhiyun 			{
815*4882a593Smuzhiyun 				.first = 0x05,
816*4882a593Smuzhiyun 				.last = 0x07,
817*4882a593Smuzhiyun 			},
818*4882a593Smuzhiyun 		},
819*4882a593Smuzhiyun 	},
820*4882a593Smuzhiyun 	[AB8500_PROD_TEST] = {
821*4882a593Smuzhiyun 		.num_ranges = 0,
822*4882a593Smuzhiyun 		.range = NULL,
823*4882a593Smuzhiyun 	},
824*4882a593Smuzhiyun 	[AB8500_STE_TEST] = {
825*4882a593Smuzhiyun 		.num_ranges = 0,
826*4882a593Smuzhiyun 		.range = NULL,
827*4882a593Smuzhiyun 	},
828*4882a593Smuzhiyun 	[AB8500_OTP_EMUL] = {
829*4882a593Smuzhiyun 		.num_ranges = 1,
830*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
831*4882a593Smuzhiyun 			{
832*4882a593Smuzhiyun 				.first = 0x01,
833*4882a593Smuzhiyun 				.last = 0x15,
834*4882a593Smuzhiyun 			},
835*4882a593Smuzhiyun 		},
836*4882a593Smuzhiyun 	},
837*4882a593Smuzhiyun };
838*4882a593Smuzhiyun 
839*4882a593Smuzhiyun static struct ab8500_prcmu_ranges ab8540_debug_ranges[AB8500_NUM_BANKS] = {
840*4882a593Smuzhiyun 	[AB8500_M_FSM_RANK] = {
841*4882a593Smuzhiyun 		.num_ranges = 1,
842*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
843*4882a593Smuzhiyun 			{
844*4882a593Smuzhiyun 				.first = 0x00,
845*4882a593Smuzhiyun 				.last = 0x0B,
846*4882a593Smuzhiyun 			},
847*4882a593Smuzhiyun 		},
848*4882a593Smuzhiyun 	},
849*4882a593Smuzhiyun 	[AB8500_SYS_CTRL1_BLOCK] = {
850*4882a593Smuzhiyun 		.num_ranges = 6,
851*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
852*4882a593Smuzhiyun 			{
853*4882a593Smuzhiyun 				.first = 0x00,
854*4882a593Smuzhiyun 				.last = 0x04,
855*4882a593Smuzhiyun 			},
856*4882a593Smuzhiyun 			{
857*4882a593Smuzhiyun 				.first = 0x42,
858*4882a593Smuzhiyun 				.last = 0x42,
859*4882a593Smuzhiyun 			},
860*4882a593Smuzhiyun 			{
861*4882a593Smuzhiyun 				.first = 0x50,
862*4882a593Smuzhiyun 				.last = 0x54,
863*4882a593Smuzhiyun 			},
864*4882a593Smuzhiyun 			{
865*4882a593Smuzhiyun 				.first = 0x57,
866*4882a593Smuzhiyun 				.last = 0x57,
867*4882a593Smuzhiyun 			},
868*4882a593Smuzhiyun 			{
869*4882a593Smuzhiyun 				.first = 0x80,
870*4882a593Smuzhiyun 				.last = 0x83,
871*4882a593Smuzhiyun 			},
872*4882a593Smuzhiyun 			{
873*4882a593Smuzhiyun 				.first = 0x90,
874*4882a593Smuzhiyun 				.last = 0x90,
875*4882a593Smuzhiyun 			},
876*4882a593Smuzhiyun 		},
877*4882a593Smuzhiyun 	},
878*4882a593Smuzhiyun 	[AB8500_SYS_CTRL2_BLOCK] = {
879*4882a593Smuzhiyun 		.num_ranges = 5,
880*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
881*4882a593Smuzhiyun 			{
882*4882a593Smuzhiyun 				.first = 0x00,
883*4882a593Smuzhiyun 				.last = 0x0D,
884*4882a593Smuzhiyun 			},
885*4882a593Smuzhiyun 			{
886*4882a593Smuzhiyun 				.first = 0x0F,
887*4882a593Smuzhiyun 				.last = 0x10,
888*4882a593Smuzhiyun 			},
889*4882a593Smuzhiyun 			{
890*4882a593Smuzhiyun 				.first = 0x20,
891*4882a593Smuzhiyun 				.last = 0x21,
892*4882a593Smuzhiyun 			},
893*4882a593Smuzhiyun 			{
894*4882a593Smuzhiyun 				.first = 0x32,
895*4882a593Smuzhiyun 				.last = 0x3C,
896*4882a593Smuzhiyun 			},
897*4882a593Smuzhiyun 			{
898*4882a593Smuzhiyun 				.first = 0x40,
899*4882a593Smuzhiyun 				.last = 0x42,
900*4882a593Smuzhiyun 			},
901*4882a593Smuzhiyun 		},
902*4882a593Smuzhiyun 	},
903*4882a593Smuzhiyun 	[AB8500_REGU_CTRL1] = {
904*4882a593Smuzhiyun 		.num_ranges = 4,
905*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
906*4882a593Smuzhiyun 			{
907*4882a593Smuzhiyun 				.first = 0x03,
908*4882a593Smuzhiyun 				.last = 0x15,
909*4882a593Smuzhiyun 			},
910*4882a593Smuzhiyun 			{
911*4882a593Smuzhiyun 				.first = 0x20,
912*4882a593Smuzhiyun 				.last = 0x20,
913*4882a593Smuzhiyun 			},
914*4882a593Smuzhiyun 			{
915*4882a593Smuzhiyun 				.first = 0x80,
916*4882a593Smuzhiyun 				.last = 0x85,
917*4882a593Smuzhiyun 			},
918*4882a593Smuzhiyun 			{
919*4882a593Smuzhiyun 				.first = 0x87,
920*4882a593Smuzhiyun 				.last = 0x88,
921*4882a593Smuzhiyun 			},
922*4882a593Smuzhiyun 		},
923*4882a593Smuzhiyun 	},
924*4882a593Smuzhiyun 	[AB8500_REGU_CTRL2] = {
925*4882a593Smuzhiyun 		.num_ranges = 8,
926*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
927*4882a593Smuzhiyun 			{
928*4882a593Smuzhiyun 				.first = 0x00,
929*4882a593Smuzhiyun 				.last = 0x06,
930*4882a593Smuzhiyun 			},
931*4882a593Smuzhiyun 			{
932*4882a593Smuzhiyun 				.first = 0x08,
933*4882a593Smuzhiyun 				.last = 0x15,
934*4882a593Smuzhiyun 			},
935*4882a593Smuzhiyun 			{
936*4882a593Smuzhiyun 				.first = 0x17,
937*4882a593Smuzhiyun 				.last = 0x19,
938*4882a593Smuzhiyun 			},
939*4882a593Smuzhiyun 			{
940*4882a593Smuzhiyun 				.first = 0x1B,
941*4882a593Smuzhiyun 				.last = 0x1D,
942*4882a593Smuzhiyun 			},
943*4882a593Smuzhiyun 			{
944*4882a593Smuzhiyun 				.first = 0x1F,
945*4882a593Smuzhiyun 				.last = 0x2F,
946*4882a593Smuzhiyun 			},
947*4882a593Smuzhiyun 			{
948*4882a593Smuzhiyun 				.first = 0x31,
949*4882a593Smuzhiyun 				.last = 0x3A,
950*4882a593Smuzhiyun 			},
951*4882a593Smuzhiyun 			{
952*4882a593Smuzhiyun 				.first = 0x43,
953*4882a593Smuzhiyun 				.last = 0x44,
954*4882a593Smuzhiyun 			},
955*4882a593Smuzhiyun 			{
956*4882a593Smuzhiyun 				.first = 0x48,
957*4882a593Smuzhiyun 				.last = 0x49,
958*4882a593Smuzhiyun 			},
959*4882a593Smuzhiyun 		},
960*4882a593Smuzhiyun 	},
961*4882a593Smuzhiyun 	[AB8500_USB] = {
962*4882a593Smuzhiyun 		.num_ranges = 3,
963*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
964*4882a593Smuzhiyun 			{
965*4882a593Smuzhiyun 				.first = 0x80,
966*4882a593Smuzhiyun 				.last = 0x83,
967*4882a593Smuzhiyun 			},
968*4882a593Smuzhiyun 			{
969*4882a593Smuzhiyun 				.first = 0x87,
970*4882a593Smuzhiyun 				.last = 0x8A,
971*4882a593Smuzhiyun 			},
972*4882a593Smuzhiyun 			{
973*4882a593Smuzhiyun 				.first = 0x91,
974*4882a593Smuzhiyun 				.last = 0x94,
975*4882a593Smuzhiyun 			},
976*4882a593Smuzhiyun 		},
977*4882a593Smuzhiyun 	},
978*4882a593Smuzhiyun 	[AB8500_TVOUT] = {
979*4882a593Smuzhiyun 		.num_ranges = 0,
980*4882a593Smuzhiyun 		.range = NULL
981*4882a593Smuzhiyun 	},
982*4882a593Smuzhiyun 	[AB8500_DBI] = {
983*4882a593Smuzhiyun 		.num_ranges = 4,
984*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
985*4882a593Smuzhiyun 			{
986*4882a593Smuzhiyun 				.first = 0x00,
987*4882a593Smuzhiyun 				.last = 0x07,
988*4882a593Smuzhiyun 			},
989*4882a593Smuzhiyun 			{
990*4882a593Smuzhiyun 				.first = 0x10,
991*4882a593Smuzhiyun 				.last = 0x11,
992*4882a593Smuzhiyun 			},
993*4882a593Smuzhiyun 			{
994*4882a593Smuzhiyun 				.first = 0x20,
995*4882a593Smuzhiyun 				.last = 0x21,
996*4882a593Smuzhiyun 			},
997*4882a593Smuzhiyun 			{
998*4882a593Smuzhiyun 				.first = 0x30,
999*4882a593Smuzhiyun 				.last = 0x43,
1000*4882a593Smuzhiyun 			},
1001*4882a593Smuzhiyun 		},
1002*4882a593Smuzhiyun 	},
1003*4882a593Smuzhiyun 	[AB8500_ECI_AV_ACC] = {
1004*4882a593Smuzhiyun 		.num_ranges = 2,
1005*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
1006*4882a593Smuzhiyun 			{
1007*4882a593Smuzhiyun 				.first = 0x00,
1008*4882a593Smuzhiyun 				.last = 0x03,
1009*4882a593Smuzhiyun 			},
1010*4882a593Smuzhiyun 			{
1011*4882a593Smuzhiyun 				.first = 0x80,
1012*4882a593Smuzhiyun 				.last = 0x82,
1013*4882a593Smuzhiyun 			},
1014*4882a593Smuzhiyun 		},
1015*4882a593Smuzhiyun 	},
1016*4882a593Smuzhiyun 	[AB8500_RESERVED] = {
1017*4882a593Smuzhiyun 		.num_ranges = 0,
1018*4882a593Smuzhiyun 		.range = NULL,
1019*4882a593Smuzhiyun 	},
1020*4882a593Smuzhiyun 	[AB8500_GPADC] = {
1021*4882a593Smuzhiyun 		.num_ranges = 4,
1022*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
1023*4882a593Smuzhiyun 			{
1024*4882a593Smuzhiyun 				.first = 0x00,
1025*4882a593Smuzhiyun 				.last = 0x01,
1026*4882a593Smuzhiyun 			},
1027*4882a593Smuzhiyun 			{
1028*4882a593Smuzhiyun 				.first = 0x04,
1029*4882a593Smuzhiyun 				.last = 0x06,
1030*4882a593Smuzhiyun 			},
1031*4882a593Smuzhiyun 			{
1032*4882a593Smuzhiyun 				.first = 0x09,
1033*4882a593Smuzhiyun 				.last = 0x0A,
1034*4882a593Smuzhiyun 			},
1035*4882a593Smuzhiyun 			{
1036*4882a593Smuzhiyun 				.first = 0x10,
1037*4882a593Smuzhiyun 				.last = 0x14,
1038*4882a593Smuzhiyun 			},
1039*4882a593Smuzhiyun 		},
1040*4882a593Smuzhiyun 	},
1041*4882a593Smuzhiyun 	[AB8500_CHARGER] = {
1042*4882a593Smuzhiyun 		.num_ranges = 10,
1043*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
1044*4882a593Smuzhiyun 			{
1045*4882a593Smuzhiyun 				.first = 0x00,
1046*4882a593Smuzhiyun 				.last = 0x00,
1047*4882a593Smuzhiyun 			},
1048*4882a593Smuzhiyun 			{
1049*4882a593Smuzhiyun 				.first = 0x02,
1050*4882a593Smuzhiyun 				.last = 0x05,
1051*4882a593Smuzhiyun 			},
1052*4882a593Smuzhiyun 			{
1053*4882a593Smuzhiyun 				.first = 0x40,
1054*4882a593Smuzhiyun 				.last = 0x44,
1055*4882a593Smuzhiyun 			},
1056*4882a593Smuzhiyun 			{
1057*4882a593Smuzhiyun 				.first = 0x50,
1058*4882a593Smuzhiyun 				.last = 0x57,
1059*4882a593Smuzhiyun 			},
1060*4882a593Smuzhiyun 			{
1061*4882a593Smuzhiyun 				.first = 0x60,
1062*4882a593Smuzhiyun 				.last = 0x60,
1063*4882a593Smuzhiyun 			},
1064*4882a593Smuzhiyun 			{
1065*4882a593Smuzhiyun 				.first = 0x70,
1066*4882a593Smuzhiyun 				.last = 0x70,
1067*4882a593Smuzhiyun 			},
1068*4882a593Smuzhiyun 			{
1069*4882a593Smuzhiyun 				.first = 0xA0,
1070*4882a593Smuzhiyun 				.last = 0xA9,
1071*4882a593Smuzhiyun 			},
1072*4882a593Smuzhiyun 			{
1073*4882a593Smuzhiyun 				.first = 0xAF,
1074*4882a593Smuzhiyun 				.last = 0xB2,
1075*4882a593Smuzhiyun 			},
1076*4882a593Smuzhiyun 			{
1077*4882a593Smuzhiyun 				.first = 0xC0,
1078*4882a593Smuzhiyun 				.last = 0xC6,
1079*4882a593Smuzhiyun 			},
1080*4882a593Smuzhiyun 			{
1081*4882a593Smuzhiyun 				.first = 0xF5,
1082*4882a593Smuzhiyun 				.last = 0xF5,
1083*4882a593Smuzhiyun 			},
1084*4882a593Smuzhiyun 		},
1085*4882a593Smuzhiyun 	},
1086*4882a593Smuzhiyun 	[AB8500_GAS_GAUGE] = {
1087*4882a593Smuzhiyun 		.num_ranges = 3,
1088*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
1089*4882a593Smuzhiyun 			{
1090*4882a593Smuzhiyun 				.first = 0x00,
1091*4882a593Smuzhiyun 				.last = 0x00,
1092*4882a593Smuzhiyun 			},
1093*4882a593Smuzhiyun 			{
1094*4882a593Smuzhiyun 				.first = 0x07,
1095*4882a593Smuzhiyun 				.last = 0x0A,
1096*4882a593Smuzhiyun 			},
1097*4882a593Smuzhiyun 			{
1098*4882a593Smuzhiyun 				.first = 0x10,
1099*4882a593Smuzhiyun 				.last = 0x14,
1100*4882a593Smuzhiyun 			},
1101*4882a593Smuzhiyun 		},
1102*4882a593Smuzhiyun 	},
1103*4882a593Smuzhiyun 	[AB8500_AUDIO] = {
1104*4882a593Smuzhiyun 		.num_ranges = 1,
1105*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
1106*4882a593Smuzhiyun 			{
1107*4882a593Smuzhiyun 				.first = 0x00,
1108*4882a593Smuzhiyun 				.last = 0x9f,
1109*4882a593Smuzhiyun 			},
1110*4882a593Smuzhiyun 		},
1111*4882a593Smuzhiyun 	},
1112*4882a593Smuzhiyun 	[AB8500_INTERRUPT] = {
1113*4882a593Smuzhiyun 		.num_ranges = 6,
1114*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
1115*4882a593Smuzhiyun 			{
1116*4882a593Smuzhiyun 				.first = 0x00,
1117*4882a593Smuzhiyun 				.last = 0x05,
1118*4882a593Smuzhiyun 			},
1119*4882a593Smuzhiyun 			{
1120*4882a593Smuzhiyun 				.first = 0x0B,
1121*4882a593Smuzhiyun 				.last = 0x0D,
1122*4882a593Smuzhiyun 			},
1123*4882a593Smuzhiyun 			{
1124*4882a593Smuzhiyun 				.first = 0x12,
1125*4882a593Smuzhiyun 				.last = 0x20,
1126*4882a593Smuzhiyun 			},
1127*4882a593Smuzhiyun 			/* Latch registers should not be read here */
1128*4882a593Smuzhiyun 			{
1129*4882a593Smuzhiyun 				.first = 0x40,
1130*4882a593Smuzhiyun 				.last = 0x45,
1131*4882a593Smuzhiyun 			},
1132*4882a593Smuzhiyun 			{
1133*4882a593Smuzhiyun 				.first = 0x4B,
1134*4882a593Smuzhiyun 				.last = 0x4D,
1135*4882a593Smuzhiyun 			},
1136*4882a593Smuzhiyun 			{
1137*4882a593Smuzhiyun 				.first = 0x52,
1138*4882a593Smuzhiyun 				.last = 0x60,
1139*4882a593Smuzhiyun 			},
1140*4882a593Smuzhiyun 			/* LatchHier registers should not be read here */
1141*4882a593Smuzhiyun 		},
1142*4882a593Smuzhiyun 	},
1143*4882a593Smuzhiyun 	[AB8500_RTC] = {
1144*4882a593Smuzhiyun 		.num_ranges = 3,
1145*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
1146*4882a593Smuzhiyun 			{
1147*4882a593Smuzhiyun 				.first = 0x00,
1148*4882a593Smuzhiyun 				.last = 0x07,
1149*4882a593Smuzhiyun 			},
1150*4882a593Smuzhiyun 			{
1151*4882a593Smuzhiyun 				.first = 0x0B,
1152*4882a593Smuzhiyun 				.last = 0x18,
1153*4882a593Smuzhiyun 			},
1154*4882a593Smuzhiyun 			{
1155*4882a593Smuzhiyun 				.first = 0x20,
1156*4882a593Smuzhiyun 				.last = 0x25,
1157*4882a593Smuzhiyun 			},
1158*4882a593Smuzhiyun 		},
1159*4882a593Smuzhiyun 	},
1160*4882a593Smuzhiyun 	[AB8500_MISC] = {
1161*4882a593Smuzhiyun 		.num_ranges = 9,
1162*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
1163*4882a593Smuzhiyun 			{
1164*4882a593Smuzhiyun 				.first = 0x00,
1165*4882a593Smuzhiyun 				.last = 0x06,
1166*4882a593Smuzhiyun 			},
1167*4882a593Smuzhiyun 			{
1168*4882a593Smuzhiyun 				.first = 0x10,
1169*4882a593Smuzhiyun 				.last = 0x16,
1170*4882a593Smuzhiyun 			},
1171*4882a593Smuzhiyun 			{
1172*4882a593Smuzhiyun 				.first = 0x20,
1173*4882a593Smuzhiyun 				.last = 0x26,
1174*4882a593Smuzhiyun 			},
1175*4882a593Smuzhiyun 			{
1176*4882a593Smuzhiyun 				.first = 0x30,
1177*4882a593Smuzhiyun 				.last = 0x36,
1178*4882a593Smuzhiyun 			},
1179*4882a593Smuzhiyun 			{
1180*4882a593Smuzhiyun 				.first = 0x40,
1181*4882a593Smuzhiyun 				.last = 0x49,
1182*4882a593Smuzhiyun 			},
1183*4882a593Smuzhiyun 			{
1184*4882a593Smuzhiyun 				.first = 0x50,
1185*4882a593Smuzhiyun 				.last = 0x50,
1186*4882a593Smuzhiyun 			},
1187*4882a593Smuzhiyun 			{
1188*4882a593Smuzhiyun 				.first = 0x60,
1189*4882a593Smuzhiyun 				.last = 0x6B,
1190*4882a593Smuzhiyun 			},
1191*4882a593Smuzhiyun 			{
1192*4882a593Smuzhiyun 				.first = 0x70,
1193*4882a593Smuzhiyun 				.last = 0x74,
1194*4882a593Smuzhiyun 			},
1195*4882a593Smuzhiyun 			{
1196*4882a593Smuzhiyun 				.first = 0x80,
1197*4882a593Smuzhiyun 				.last = 0x82,
1198*4882a593Smuzhiyun 			},
1199*4882a593Smuzhiyun 		},
1200*4882a593Smuzhiyun 	},
1201*4882a593Smuzhiyun 	[AB8500_DEVELOPMENT] = {
1202*4882a593Smuzhiyun 		.num_ranges = 3,
1203*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
1204*4882a593Smuzhiyun 			{
1205*4882a593Smuzhiyun 				.first = 0x00,
1206*4882a593Smuzhiyun 				.last = 0x01,
1207*4882a593Smuzhiyun 			},
1208*4882a593Smuzhiyun 			{
1209*4882a593Smuzhiyun 				.first = 0x06,
1210*4882a593Smuzhiyun 				.last = 0x06,
1211*4882a593Smuzhiyun 			},
1212*4882a593Smuzhiyun 			{
1213*4882a593Smuzhiyun 				.first = 0x10,
1214*4882a593Smuzhiyun 				.last = 0x21,
1215*4882a593Smuzhiyun 			},
1216*4882a593Smuzhiyun 		},
1217*4882a593Smuzhiyun 	},
1218*4882a593Smuzhiyun 	[AB8500_DEBUG] = {
1219*4882a593Smuzhiyun 		.num_ranges = 3,
1220*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
1221*4882a593Smuzhiyun 			{
1222*4882a593Smuzhiyun 				.first = 0x01,
1223*4882a593Smuzhiyun 				.last = 0x0C,
1224*4882a593Smuzhiyun 			},
1225*4882a593Smuzhiyun 			{
1226*4882a593Smuzhiyun 				.first = 0x0E,
1227*4882a593Smuzhiyun 				.last = 0x11,
1228*4882a593Smuzhiyun 			},
1229*4882a593Smuzhiyun 			{
1230*4882a593Smuzhiyun 				.first = 0x80,
1231*4882a593Smuzhiyun 				.last = 0x81,
1232*4882a593Smuzhiyun 			},
1233*4882a593Smuzhiyun 		},
1234*4882a593Smuzhiyun 	},
1235*4882a593Smuzhiyun 	[AB8500_PROD_TEST] = {
1236*4882a593Smuzhiyun 		.num_ranges = 0,
1237*4882a593Smuzhiyun 		.range = NULL,
1238*4882a593Smuzhiyun 	},
1239*4882a593Smuzhiyun 	[AB8500_STE_TEST] = {
1240*4882a593Smuzhiyun 		.num_ranges = 0,
1241*4882a593Smuzhiyun 		.range = NULL,
1242*4882a593Smuzhiyun 	},
1243*4882a593Smuzhiyun 	[AB8500_OTP_EMUL] = {
1244*4882a593Smuzhiyun 		.num_ranges = 1,
1245*4882a593Smuzhiyun 		.range = (struct ab8500_reg_range[]) {
1246*4882a593Smuzhiyun 			{
1247*4882a593Smuzhiyun 				.first = 0x00,
1248*4882a593Smuzhiyun 				.last = 0x3F,
1249*4882a593Smuzhiyun 			},
1250*4882a593Smuzhiyun 		},
1251*4882a593Smuzhiyun 	},
1252*4882a593Smuzhiyun };
1253*4882a593Smuzhiyun 
ab8500_debug_handler(int irq,void * data)1254*4882a593Smuzhiyun static irqreturn_t ab8500_debug_handler(int irq, void *data)
1255*4882a593Smuzhiyun {
1256*4882a593Smuzhiyun 	char buf[16];
1257*4882a593Smuzhiyun 	struct kobject *kobj = (struct kobject *)data;
1258*4882a593Smuzhiyun 	unsigned int irq_abb = irq - irq_first;
1259*4882a593Smuzhiyun 
1260*4882a593Smuzhiyun 	if (irq_abb < num_irqs)
1261*4882a593Smuzhiyun 		irq_count[irq_abb]++;
1262*4882a593Smuzhiyun 	/*
1263*4882a593Smuzhiyun 	 * This makes it possible to use poll for events (EPOLLPRI | EPOLLERR)
1264*4882a593Smuzhiyun 	 * from userspace on sysfs file named <irq-nr>
1265*4882a593Smuzhiyun 	 */
1266*4882a593Smuzhiyun 	sprintf(buf, "%d", irq);
1267*4882a593Smuzhiyun 	sysfs_notify(kobj, NULL, buf);
1268*4882a593Smuzhiyun 
1269*4882a593Smuzhiyun 	return IRQ_HANDLED;
1270*4882a593Smuzhiyun }
1271*4882a593Smuzhiyun 
1272*4882a593Smuzhiyun /* Prints to seq_file or log_buf */
ab8500_registers_print(struct device * dev,u32 bank,struct seq_file * s)1273*4882a593Smuzhiyun static int ab8500_registers_print(struct device *dev, u32 bank,
1274*4882a593Smuzhiyun 				  struct seq_file *s)
1275*4882a593Smuzhiyun {
1276*4882a593Smuzhiyun 	unsigned int i;
1277*4882a593Smuzhiyun 
1278*4882a593Smuzhiyun 	for (i = 0; i < debug_ranges[bank].num_ranges; i++) {
1279*4882a593Smuzhiyun 		u32 reg;
1280*4882a593Smuzhiyun 
1281*4882a593Smuzhiyun 		for (reg = debug_ranges[bank].range[i].first;
1282*4882a593Smuzhiyun 			reg <= debug_ranges[bank].range[i].last;
1283*4882a593Smuzhiyun 			reg++) {
1284*4882a593Smuzhiyun 			u8 value;
1285*4882a593Smuzhiyun 			int err;
1286*4882a593Smuzhiyun 
1287*4882a593Smuzhiyun 			err = abx500_get_register_interruptible(dev,
1288*4882a593Smuzhiyun 				(u8)bank, (u8)reg, &value);
1289*4882a593Smuzhiyun 			if (err < 0) {
1290*4882a593Smuzhiyun 				dev_err(dev, "ab->read fail %d\n", err);
1291*4882a593Smuzhiyun 				return err;
1292*4882a593Smuzhiyun 			}
1293*4882a593Smuzhiyun 
1294*4882a593Smuzhiyun 			if (s) {
1295*4882a593Smuzhiyun 				seq_printf(s, "  [0x%02X/0x%02X]: 0x%02X\n",
1296*4882a593Smuzhiyun 					   bank, reg, value);
1297*4882a593Smuzhiyun 				/*
1298*4882a593Smuzhiyun 				 * Error is not returned here since
1299*4882a593Smuzhiyun 				 * the output is wanted in any case
1300*4882a593Smuzhiyun 				 */
1301*4882a593Smuzhiyun 				if (seq_has_overflowed(s))
1302*4882a593Smuzhiyun 					return 0;
1303*4882a593Smuzhiyun 			} else {
1304*4882a593Smuzhiyun 				dev_info(dev, " [0x%02X/0x%02X]: 0x%02X\n",
1305*4882a593Smuzhiyun 					 bank, reg, value);
1306*4882a593Smuzhiyun 			}
1307*4882a593Smuzhiyun 		}
1308*4882a593Smuzhiyun 	}
1309*4882a593Smuzhiyun 
1310*4882a593Smuzhiyun 	return 0;
1311*4882a593Smuzhiyun }
1312*4882a593Smuzhiyun 
ab8500_bank_registers_show(struct seq_file * s,void * p)1313*4882a593Smuzhiyun static int ab8500_bank_registers_show(struct seq_file *s, void *p)
1314*4882a593Smuzhiyun {
1315*4882a593Smuzhiyun 	struct device *dev = s->private;
1316*4882a593Smuzhiyun 	u32 bank = debug_bank;
1317*4882a593Smuzhiyun 
1318*4882a593Smuzhiyun 	seq_puts(s, AB8500_NAME_STRING " register values:\n");
1319*4882a593Smuzhiyun 
1320*4882a593Smuzhiyun 	seq_printf(s, " bank 0x%02X:\n", bank);
1321*4882a593Smuzhiyun 
1322*4882a593Smuzhiyun 	return ab8500_registers_print(dev, bank, s);
1323*4882a593Smuzhiyun }
1324*4882a593Smuzhiyun 
1325*4882a593Smuzhiyun DEFINE_SHOW_ATTRIBUTE(ab8500_bank_registers);
1326*4882a593Smuzhiyun 
ab8500_print_all_banks(struct seq_file * s,void * p)1327*4882a593Smuzhiyun static int ab8500_print_all_banks(struct seq_file *s, void *p)
1328*4882a593Smuzhiyun {
1329*4882a593Smuzhiyun 	struct device *dev = s->private;
1330*4882a593Smuzhiyun 	unsigned int i;
1331*4882a593Smuzhiyun 
1332*4882a593Smuzhiyun 	seq_puts(s, AB8500_NAME_STRING " register values:\n");
1333*4882a593Smuzhiyun 
1334*4882a593Smuzhiyun 	for (i = 0; i < AB8500_NUM_BANKS; i++) {
1335*4882a593Smuzhiyun 		int err;
1336*4882a593Smuzhiyun 
1337*4882a593Smuzhiyun 		seq_printf(s, " bank 0x%02X:\n", i);
1338*4882a593Smuzhiyun 		err = ab8500_registers_print(dev, i, s);
1339*4882a593Smuzhiyun 		if (err)
1340*4882a593Smuzhiyun 			return err;
1341*4882a593Smuzhiyun 	}
1342*4882a593Smuzhiyun 	return 0;
1343*4882a593Smuzhiyun }
1344*4882a593Smuzhiyun 
1345*4882a593Smuzhiyun /* Dump registers to kernel log */
ab8500_dump_all_banks(struct device * dev)1346*4882a593Smuzhiyun void ab8500_dump_all_banks(struct device *dev)
1347*4882a593Smuzhiyun {
1348*4882a593Smuzhiyun 	unsigned int i;
1349*4882a593Smuzhiyun 
1350*4882a593Smuzhiyun 	dev_info(dev, "ab8500 register values:\n");
1351*4882a593Smuzhiyun 
1352*4882a593Smuzhiyun 	for (i = 1; i < AB8500_NUM_BANKS; i++) {
1353*4882a593Smuzhiyun 		dev_info(dev, " bank 0x%02X:\n", i);
1354*4882a593Smuzhiyun 		ab8500_registers_print(dev, i, NULL);
1355*4882a593Smuzhiyun 	}
1356*4882a593Smuzhiyun }
1357*4882a593Smuzhiyun 
ab8500_all_banks_open(struct inode * inode,struct file * file)1358*4882a593Smuzhiyun static int ab8500_all_banks_open(struct inode *inode, struct file *file)
1359*4882a593Smuzhiyun {
1360*4882a593Smuzhiyun 	struct seq_file *s;
1361*4882a593Smuzhiyun 	int err;
1362*4882a593Smuzhiyun 
1363*4882a593Smuzhiyun 	err = single_open(file, ab8500_print_all_banks, inode->i_private);
1364*4882a593Smuzhiyun 	if (!err) {
1365*4882a593Smuzhiyun 		/* Default buf size in seq_read is not enough */
1366*4882a593Smuzhiyun 		s = (struct seq_file *)file->private_data;
1367*4882a593Smuzhiyun 		s->size = (PAGE_SIZE * 2);
1368*4882a593Smuzhiyun 		s->buf = kmalloc(s->size, GFP_KERNEL);
1369*4882a593Smuzhiyun 		if (!s->buf) {
1370*4882a593Smuzhiyun 			single_release(inode, file);
1371*4882a593Smuzhiyun 			err = -ENOMEM;
1372*4882a593Smuzhiyun 		}
1373*4882a593Smuzhiyun 	}
1374*4882a593Smuzhiyun 	return err;
1375*4882a593Smuzhiyun }
1376*4882a593Smuzhiyun 
1377*4882a593Smuzhiyun static const struct file_operations ab8500_all_banks_fops = {
1378*4882a593Smuzhiyun 	.open = ab8500_all_banks_open,
1379*4882a593Smuzhiyun 	.read = seq_read,
1380*4882a593Smuzhiyun 	.llseek = seq_lseek,
1381*4882a593Smuzhiyun 	.release = single_release,
1382*4882a593Smuzhiyun 	.owner = THIS_MODULE,
1383*4882a593Smuzhiyun };
1384*4882a593Smuzhiyun 
ab8500_bank_print(struct seq_file * s,void * p)1385*4882a593Smuzhiyun static int ab8500_bank_print(struct seq_file *s, void *p)
1386*4882a593Smuzhiyun {
1387*4882a593Smuzhiyun 	seq_printf(s, "0x%02X\n", debug_bank);
1388*4882a593Smuzhiyun 	return 0;
1389*4882a593Smuzhiyun }
1390*4882a593Smuzhiyun 
ab8500_bank_open(struct inode * inode,struct file * file)1391*4882a593Smuzhiyun static int ab8500_bank_open(struct inode *inode, struct file *file)
1392*4882a593Smuzhiyun {
1393*4882a593Smuzhiyun 	return single_open(file, ab8500_bank_print, inode->i_private);
1394*4882a593Smuzhiyun }
1395*4882a593Smuzhiyun 
ab8500_bank_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)1396*4882a593Smuzhiyun static ssize_t ab8500_bank_write(struct file *file,
1397*4882a593Smuzhiyun 	const char __user *user_buf,
1398*4882a593Smuzhiyun 	size_t count, loff_t *ppos)
1399*4882a593Smuzhiyun {
1400*4882a593Smuzhiyun 	struct device *dev = ((struct seq_file *)(file->private_data))->private;
1401*4882a593Smuzhiyun 	unsigned long user_bank;
1402*4882a593Smuzhiyun 	int err;
1403*4882a593Smuzhiyun 
1404*4882a593Smuzhiyun 	err = kstrtoul_from_user(user_buf, count, 0, &user_bank);
1405*4882a593Smuzhiyun 	if (err)
1406*4882a593Smuzhiyun 		return err;
1407*4882a593Smuzhiyun 
1408*4882a593Smuzhiyun 	if (user_bank >= AB8500_NUM_BANKS) {
1409*4882a593Smuzhiyun 		dev_err(dev, "debugfs error input > number of banks\n");
1410*4882a593Smuzhiyun 		return -EINVAL;
1411*4882a593Smuzhiyun 	}
1412*4882a593Smuzhiyun 
1413*4882a593Smuzhiyun 	debug_bank = user_bank;
1414*4882a593Smuzhiyun 
1415*4882a593Smuzhiyun 	return count;
1416*4882a593Smuzhiyun }
1417*4882a593Smuzhiyun 
ab8500_address_print(struct seq_file * s,void * p)1418*4882a593Smuzhiyun static int ab8500_address_print(struct seq_file *s, void *p)
1419*4882a593Smuzhiyun {
1420*4882a593Smuzhiyun 	seq_printf(s, "0x%02X\n", debug_address);
1421*4882a593Smuzhiyun 	return 0;
1422*4882a593Smuzhiyun }
1423*4882a593Smuzhiyun 
ab8500_address_open(struct inode * inode,struct file * file)1424*4882a593Smuzhiyun static int ab8500_address_open(struct inode *inode, struct file *file)
1425*4882a593Smuzhiyun {
1426*4882a593Smuzhiyun 	return single_open(file, ab8500_address_print, inode->i_private);
1427*4882a593Smuzhiyun }
1428*4882a593Smuzhiyun 
ab8500_address_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)1429*4882a593Smuzhiyun static ssize_t ab8500_address_write(struct file *file,
1430*4882a593Smuzhiyun 				    const char __user *user_buf,
1431*4882a593Smuzhiyun 				    size_t count, loff_t *ppos)
1432*4882a593Smuzhiyun {
1433*4882a593Smuzhiyun 	struct device *dev = ((struct seq_file *)(file->private_data))->private;
1434*4882a593Smuzhiyun 	unsigned long user_address;
1435*4882a593Smuzhiyun 	int err;
1436*4882a593Smuzhiyun 
1437*4882a593Smuzhiyun 	err = kstrtoul_from_user(user_buf, count, 0, &user_address);
1438*4882a593Smuzhiyun 	if (err)
1439*4882a593Smuzhiyun 		return err;
1440*4882a593Smuzhiyun 
1441*4882a593Smuzhiyun 	if (user_address > 0xff) {
1442*4882a593Smuzhiyun 		dev_err(dev, "debugfs error input > 0xff\n");
1443*4882a593Smuzhiyun 		return -EINVAL;
1444*4882a593Smuzhiyun 	}
1445*4882a593Smuzhiyun 	debug_address = user_address;
1446*4882a593Smuzhiyun 
1447*4882a593Smuzhiyun 	return count;
1448*4882a593Smuzhiyun }
1449*4882a593Smuzhiyun 
ab8500_val_print(struct seq_file * s,void * p)1450*4882a593Smuzhiyun static int ab8500_val_print(struct seq_file *s, void *p)
1451*4882a593Smuzhiyun {
1452*4882a593Smuzhiyun 	struct device *dev = s->private;
1453*4882a593Smuzhiyun 	int ret;
1454*4882a593Smuzhiyun 	u8 regvalue;
1455*4882a593Smuzhiyun 
1456*4882a593Smuzhiyun 	ret = abx500_get_register_interruptible(dev,
1457*4882a593Smuzhiyun 		(u8)debug_bank, (u8)debug_address, &regvalue);
1458*4882a593Smuzhiyun 	if (ret < 0) {
1459*4882a593Smuzhiyun 		dev_err(dev, "abx500_get_reg fail %d, %d\n",
1460*4882a593Smuzhiyun 			ret, __LINE__);
1461*4882a593Smuzhiyun 		return -EINVAL;
1462*4882a593Smuzhiyun 	}
1463*4882a593Smuzhiyun 	seq_printf(s, "0x%02X\n", regvalue);
1464*4882a593Smuzhiyun 
1465*4882a593Smuzhiyun 	return 0;
1466*4882a593Smuzhiyun }
1467*4882a593Smuzhiyun 
ab8500_val_open(struct inode * inode,struct file * file)1468*4882a593Smuzhiyun static int ab8500_val_open(struct inode *inode, struct file *file)
1469*4882a593Smuzhiyun {
1470*4882a593Smuzhiyun 	return single_open(file, ab8500_val_print, inode->i_private);
1471*4882a593Smuzhiyun }
1472*4882a593Smuzhiyun 
ab8500_val_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)1473*4882a593Smuzhiyun static ssize_t ab8500_val_write(struct file *file,
1474*4882a593Smuzhiyun 				const char __user *user_buf,
1475*4882a593Smuzhiyun 				size_t count, loff_t *ppos)
1476*4882a593Smuzhiyun {
1477*4882a593Smuzhiyun 	struct device *dev = ((struct seq_file *)(file->private_data))->private;
1478*4882a593Smuzhiyun 	unsigned long user_val;
1479*4882a593Smuzhiyun 	int err;
1480*4882a593Smuzhiyun 
1481*4882a593Smuzhiyun 	err = kstrtoul_from_user(user_buf, count, 0, &user_val);
1482*4882a593Smuzhiyun 	if (err)
1483*4882a593Smuzhiyun 		return err;
1484*4882a593Smuzhiyun 
1485*4882a593Smuzhiyun 	if (user_val > 0xff) {
1486*4882a593Smuzhiyun 		dev_err(dev, "debugfs error input > 0xff\n");
1487*4882a593Smuzhiyun 		return -EINVAL;
1488*4882a593Smuzhiyun 	}
1489*4882a593Smuzhiyun 	err = abx500_set_register_interruptible(dev,
1490*4882a593Smuzhiyun 		(u8)debug_bank, debug_address, (u8)user_val);
1491*4882a593Smuzhiyun 	if (err < 0) {
1492*4882a593Smuzhiyun 		pr_err("abx500_set_reg failed %d, %d", err, __LINE__);
1493*4882a593Smuzhiyun 		return -EINVAL;
1494*4882a593Smuzhiyun 	}
1495*4882a593Smuzhiyun 
1496*4882a593Smuzhiyun 	return count;
1497*4882a593Smuzhiyun }
1498*4882a593Smuzhiyun 
1499*4882a593Smuzhiyun /*
1500*4882a593Smuzhiyun  * Interrupt status
1501*4882a593Smuzhiyun  */
1502*4882a593Smuzhiyun static u32 num_interrupts[AB8500_MAX_NR_IRQS];
1503*4882a593Smuzhiyun static u32 num_wake_interrupts[AB8500_MAX_NR_IRQS];
1504*4882a593Smuzhiyun static int num_interrupt_lines;
1505*4882a593Smuzhiyun 
ab8500_debug_register_interrupt(int line)1506*4882a593Smuzhiyun void ab8500_debug_register_interrupt(int line)
1507*4882a593Smuzhiyun {
1508*4882a593Smuzhiyun 	if (line < num_interrupt_lines)
1509*4882a593Smuzhiyun 		num_interrupts[line]++;
1510*4882a593Smuzhiyun }
1511*4882a593Smuzhiyun 
ab8500_interrupts_show(struct seq_file * s,void * p)1512*4882a593Smuzhiyun static int ab8500_interrupts_show(struct seq_file *s, void *p)
1513*4882a593Smuzhiyun {
1514*4882a593Smuzhiyun 	int line;
1515*4882a593Smuzhiyun 
1516*4882a593Smuzhiyun 	seq_puts(s, "name: number:  number of: wake:\n");
1517*4882a593Smuzhiyun 
1518*4882a593Smuzhiyun 	for (line = 0; line < num_interrupt_lines; line++) {
1519*4882a593Smuzhiyun 		struct irq_desc *desc = irq_to_desc(line + irq_first);
1520*4882a593Smuzhiyun 
1521*4882a593Smuzhiyun 		seq_printf(s, "%3i:  %6i %4i",
1522*4882a593Smuzhiyun 			   line,
1523*4882a593Smuzhiyun 			   num_interrupts[line],
1524*4882a593Smuzhiyun 			   num_wake_interrupts[line]);
1525*4882a593Smuzhiyun 
1526*4882a593Smuzhiyun 		if (desc && desc->name)
1527*4882a593Smuzhiyun 			seq_printf(s, "-%-8s", desc->name);
1528*4882a593Smuzhiyun 		if (desc && desc->action) {
1529*4882a593Smuzhiyun 			struct irqaction *action = desc->action;
1530*4882a593Smuzhiyun 
1531*4882a593Smuzhiyun 			seq_printf(s, "  %s", action->name);
1532*4882a593Smuzhiyun 			while ((action = action->next) != NULL)
1533*4882a593Smuzhiyun 				seq_printf(s, ", %s", action->name);
1534*4882a593Smuzhiyun 		}
1535*4882a593Smuzhiyun 		seq_putc(s, '\n');
1536*4882a593Smuzhiyun 	}
1537*4882a593Smuzhiyun 
1538*4882a593Smuzhiyun 	return 0;
1539*4882a593Smuzhiyun }
1540*4882a593Smuzhiyun 
1541*4882a593Smuzhiyun DEFINE_SHOW_ATTRIBUTE(ab8500_interrupts);
1542*4882a593Smuzhiyun 
1543*4882a593Smuzhiyun /*
1544*4882a593Smuzhiyun  * - HWREG DB8500 formated routines
1545*4882a593Smuzhiyun  */
ab8500_hwreg_print(struct seq_file * s,void * d)1546*4882a593Smuzhiyun static int ab8500_hwreg_print(struct seq_file *s, void *d)
1547*4882a593Smuzhiyun {
1548*4882a593Smuzhiyun 	struct device *dev = s->private;
1549*4882a593Smuzhiyun 	int ret;
1550*4882a593Smuzhiyun 	u8 regvalue;
1551*4882a593Smuzhiyun 
1552*4882a593Smuzhiyun 	ret = abx500_get_register_interruptible(dev,
1553*4882a593Smuzhiyun 		(u8)hwreg_cfg.bank, (u8)hwreg_cfg.addr, &regvalue);
1554*4882a593Smuzhiyun 	if (ret < 0) {
1555*4882a593Smuzhiyun 		dev_err(dev, "abx500_get_reg fail %d, %d\n",
1556*4882a593Smuzhiyun 			ret, __LINE__);
1557*4882a593Smuzhiyun 		return -EINVAL;
1558*4882a593Smuzhiyun 	}
1559*4882a593Smuzhiyun 
1560*4882a593Smuzhiyun 	if (hwreg_cfg.shift >= 0)
1561*4882a593Smuzhiyun 		regvalue >>= hwreg_cfg.shift;
1562*4882a593Smuzhiyun 	else
1563*4882a593Smuzhiyun 		regvalue <<= -hwreg_cfg.shift;
1564*4882a593Smuzhiyun 	regvalue &= hwreg_cfg.mask;
1565*4882a593Smuzhiyun 
1566*4882a593Smuzhiyun 	if (REG_FMT_DEC(&hwreg_cfg))
1567*4882a593Smuzhiyun 		seq_printf(s, "%d\n", regvalue);
1568*4882a593Smuzhiyun 	else
1569*4882a593Smuzhiyun 		seq_printf(s, "0x%02X\n", regvalue);
1570*4882a593Smuzhiyun 	return 0;
1571*4882a593Smuzhiyun }
1572*4882a593Smuzhiyun 
ab8500_hwreg_open(struct inode * inode,struct file * file)1573*4882a593Smuzhiyun static int ab8500_hwreg_open(struct inode *inode, struct file *file)
1574*4882a593Smuzhiyun {
1575*4882a593Smuzhiyun 	return single_open(file, ab8500_hwreg_print, inode->i_private);
1576*4882a593Smuzhiyun }
1577*4882a593Smuzhiyun 
1578*4882a593Smuzhiyun #define AB8500_SUPPLY_CONTROL_CONFIG_1 0x01
1579*4882a593Smuzhiyun #define AB8500_SUPPLY_CONTROL_REG 0x00
1580*4882a593Smuzhiyun #define AB8500_FIRST_SIM_REG 0x80
1581*4882a593Smuzhiyun #define AB8500_LAST_SIM_REG 0x8B
1582*4882a593Smuzhiyun #define AB8505_LAST_SIM_REG 0x8C
1583*4882a593Smuzhiyun 
ab8500_modem_show(struct seq_file * s,void * p)1584*4882a593Smuzhiyun static int ab8500_modem_show(struct seq_file *s, void *p)
1585*4882a593Smuzhiyun {
1586*4882a593Smuzhiyun 	struct device *dev = s->private;
1587*4882a593Smuzhiyun 	struct ab8500 *ab8500;
1588*4882a593Smuzhiyun 	int err;
1589*4882a593Smuzhiyun 	u8 value;
1590*4882a593Smuzhiyun 	u8 orig_value;
1591*4882a593Smuzhiyun 	u32 bank = AB8500_REGU_CTRL2;
1592*4882a593Smuzhiyun 	u32 last_sim_reg = AB8500_LAST_SIM_REG;
1593*4882a593Smuzhiyun 	u32 reg;
1594*4882a593Smuzhiyun 
1595*4882a593Smuzhiyun 	ab8500 = dev_get_drvdata(dev->parent);
1596*4882a593Smuzhiyun 	dev_warn(dev, "WARNING! This operation can interfer with modem side\n"
1597*4882a593Smuzhiyun 		"and should only be done with care\n");
1598*4882a593Smuzhiyun 
1599*4882a593Smuzhiyun 	err = abx500_get_register_interruptible(dev,
1600*4882a593Smuzhiyun 		AB8500_REGU_CTRL1, AB8500_SUPPLY_CONTROL_REG, &orig_value);
1601*4882a593Smuzhiyun 	if (err < 0)
1602*4882a593Smuzhiyun 		goto report_read_failure;
1603*4882a593Smuzhiyun 
1604*4882a593Smuzhiyun 	/* Config 1 will allow APE side to read SIM registers */
1605*4882a593Smuzhiyun 	err = abx500_set_register_interruptible(dev,
1606*4882a593Smuzhiyun 		AB8500_REGU_CTRL1, AB8500_SUPPLY_CONTROL_REG,
1607*4882a593Smuzhiyun 		AB8500_SUPPLY_CONTROL_CONFIG_1);
1608*4882a593Smuzhiyun 	if (err < 0)
1609*4882a593Smuzhiyun 		goto report_write_failure;
1610*4882a593Smuzhiyun 
1611*4882a593Smuzhiyun 	seq_printf(s, " bank 0x%02X:\n", bank);
1612*4882a593Smuzhiyun 
1613*4882a593Smuzhiyun 	if (is_ab9540(ab8500) || is_ab8505(ab8500))
1614*4882a593Smuzhiyun 		last_sim_reg = AB8505_LAST_SIM_REG;
1615*4882a593Smuzhiyun 
1616*4882a593Smuzhiyun 	for (reg = AB8500_FIRST_SIM_REG; reg <= last_sim_reg; reg++) {
1617*4882a593Smuzhiyun 		err = abx500_get_register_interruptible(dev,
1618*4882a593Smuzhiyun 			bank, reg, &value);
1619*4882a593Smuzhiyun 		if (err < 0)
1620*4882a593Smuzhiyun 			goto report_read_failure;
1621*4882a593Smuzhiyun 
1622*4882a593Smuzhiyun 		seq_printf(s, "  [0x%02X/0x%02X]: 0x%02X\n", bank, reg, value);
1623*4882a593Smuzhiyun 	}
1624*4882a593Smuzhiyun 	err = abx500_set_register_interruptible(dev,
1625*4882a593Smuzhiyun 		AB8500_REGU_CTRL1, AB8500_SUPPLY_CONTROL_REG, orig_value);
1626*4882a593Smuzhiyun 	if (err < 0)
1627*4882a593Smuzhiyun 		goto report_write_failure;
1628*4882a593Smuzhiyun 
1629*4882a593Smuzhiyun 	return 0;
1630*4882a593Smuzhiyun 
1631*4882a593Smuzhiyun report_read_failure:
1632*4882a593Smuzhiyun 	dev_err(dev, "ab->read fail %d\n", err);
1633*4882a593Smuzhiyun 	return err;
1634*4882a593Smuzhiyun 
1635*4882a593Smuzhiyun report_write_failure:
1636*4882a593Smuzhiyun 	dev_err(dev, "ab->write fail %d\n", err);
1637*4882a593Smuzhiyun 	return err;
1638*4882a593Smuzhiyun }
1639*4882a593Smuzhiyun 
1640*4882a593Smuzhiyun DEFINE_SHOW_ATTRIBUTE(ab8500_modem);
1641*4882a593Smuzhiyun 
1642*4882a593Smuzhiyun /*
1643*4882a593Smuzhiyun  * return length of an ASCII numerical value, 0 is string is not a
1644*4882a593Smuzhiyun  * numerical value.
1645*4882a593Smuzhiyun  * string shall start at value 1st char.
1646*4882a593Smuzhiyun  * string can be tailed with \0 or space or newline chars only.
1647*4882a593Smuzhiyun  * value can be decimal or hexadecimal (prefixed 0x or 0X).
1648*4882a593Smuzhiyun  */
strval_len(char * b)1649*4882a593Smuzhiyun static int strval_len(char *b)
1650*4882a593Smuzhiyun {
1651*4882a593Smuzhiyun 	char *s = b;
1652*4882a593Smuzhiyun 
1653*4882a593Smuzhiyun 	if ((*s == '0') && ((*(s+1) == 'x') || (*(s+1) == 'X'))) {
1654*4882a593Smuzhiyun 		s += 2;
1655*4882a593Smuzhiyun 		for (; *s && (*s != ' ') && (*s != '\n'); s++) {
1656*4882a593Smuzhiyun 			if (!isxdigit(*s))
1657*4882a593Smuzhiyun 				return 0;
1658*4882a593Smuzhiyun 		}
1659*4882a593Smuzhiyun 	} else {
1660*4882a593Smuzhiyun 		if (*s == '-')
1661*4882a593Smuzhiyun 			s++;
1662*4882a593Smuzhiyun 		for (; *s && (*s != ' ') && (*s != '\n'); s++) {
1663*4882a593Smuzhiyun 			if (!isdigit(*s))
1664*4882a593Smuzhiyun 				return 0;
1665*4882a593Smuzhiyun 		}
1666*4882a593Smuzhiyun 	}
1667*4882a593Smuzhiyun 	return (int) (s-b);
1668*4882a593Smuzhiyun }
1669*4882a593Smuzhiyun 
1670*4882a593Smuzhiyun /*
1671*4882a593Smuzhiyun  * parse hwreg input data.
1672*4882a593Smuzhiyun  * update global hwreg_cfg only if input data syntax is ok.
1673*4882a593Smuzhiyun  */
hwreg_common_write(char * b,struct hwreg_cfg * cfg,struct device * dev)1674*4882a593Smuzhiyun static ssize_t hwreg_common_write(char *b, struct hwreg_cfg *cfg,
1675*4882a593Smuzhiyun 		struct device *dev)
1676*4882a593Smuzhiyun {
1677*4882a593Smuzhiyun 	uint write, val = 0;
1678*4882a593Smuzhiyun 	u8  regvalue;
1679*4882a593Smuzhiyun 	int ret;
1680*4882a593Smuzhiyun 	struct hwreg_cfg loc = {
1681*4882a593Smuzhiyun 		.bank = 0,          /* default: invalid phys addr */
1682*4882a593Smuzhiyun 		.addr = 0,          /* default: invalid phys addr */
1683*4882a593Smuzhiyun 		.fmt = 0,           /* default: 32bit access, hex output */
1684*4882a593Smuzhiyun 		.mask = 0xFFFFFFFF, /* default: no mask */
1685*4882a593Smuzhiyun 		.shift = 0,         /* default: no bit shift */
1686*4882a593Smuzhiyun 	};
1687*4882a593Smuzhiyun 
1688*4882a593Smuzhiyun 	/* read or write ? */
1689*4882a593Smuzhiyun 	if (!strncmp(b, "read ", 5)) {
1690*4882a593Smuzhiyun 		write = 0;
1691*4882a593Smuzhiyun 		b += 5;
1692*4882a593Smuzhiyun 	} else if (!strncmp(b, "write ", 6)) {
1693*4882a593Smuzhiyun 		write = 1;
1694*4882a593Smuzhiyun 		b += 6;
1695*4882a593Smuzhiyun 	} else
1696*4882a593Smuzhiyun 		return -EINVAL;
1697*4882a593Smuzhiyun 
1698*4882a593Smuzhiyun 	/* OPTIONS -l|-w|-b -s -m -o */
1699*4882a593Smuzhiyun 	while ((*b == ' ') || (*b == '-')) {
1700*4882a593Smuzhiyun 		if (*(b-1) != ' ') {
1701*4882a593Smuzhiyun 			b++;
1702*4882a593Smuzhiyun 			continue;
1703*4882a593Smuzhiyun 		}
1704*4882a593Smuzhiyun 		if ((!strncmp(b, "-d ", 3)) ||
1705*4882a593Smuzhiyun 				(!strncmp(b, "-dec ", 5))) {
1706*4882a593Smuzhiyun 			b += (*(b+2) == ' ') ? 3 : 5;
1707*4882a593Smuzhiyun 			loc.fmt |= (1<<0);
1708*4882a593Smuzhiyun 		} else if ((!strncmp(b, "-h ", 3)) ||
1709*4882a593Smuzhiyun 				(!strncmp(b, "-hex ", 5))) {
1710*4882a593Smuzhiyun 			b += (*(b+2) == ' ') ? 3 : 5;
1711*4882a593Smuzhiyun 			loc.fmt &= ~(1<<0);
1712*4882a593Smuzhiyun 		} else if ((!strncmp(b, "-m ", 3)) ||
1713*4882a593Smuzhiyun 				(!strncmp(b, "-mask ", 6))) {
1714*4882a593Smuzhiyun 			b += (*(b+2) == ' ') ? 3 : 6;
1715*4882a593Smuzhiyun 			if (strval_len(b) == 0)
1716*4882a593Smuzhiyun 				return -EINVAL;
1717*4882a593Smuzhiyun 			ret = kstrtoul(b, 0, &loc.mask);
1718*4882a593Smuzhiyun 			if (ret)
1719*4882a593Smuzhiyun 				return ret;
1720*4882a593Smuzhiyun 		} else if ((!strncmp(b, "-s ", 3)) ||
1721*4882a593Smuzhiyun 				(!strncmp(b, "-shift ", 7))) {
1722*4882a593Smuzhiyun 			b += (*(b+2) == ' ') ? 3 : 7;
1723*4882a593Smuzhiyun 			if (strval_len(b) == 0)
1724*4882a593Smuzhiyun 				return -EINVAL;
1725*4882a593Smuzhiyun 			ret = kstrtol(b, 0, &loc.shift);
1726*4882a593Smuzhiyun 			if (ret)
1727*4882a593Smuzhiyun 				return ret;
1728*4882a593Smuzhiyun 		} else {
1729*4882a593Smuzhiyun 			return -EINVAL;
1730*4882a593Smuzhiyun 		}
1731*4882a593Smuzhiyun 	}
1732*4882a593Smuzhiyun 	/* get arg BANK and ADDRESS */
1733*4882a593Smuzhiyun 	if (strval_len(b) == 0)
1734*4882a593Smuzhiyun 		return -EINVAL;
1735*4882a593Smuzhiyun 	ret = kstrtouint(b, 0, &loc.bank);
1736*4882a593Smuzhiyun 	if (ret)
1737*4882a593Smuzhiyun 		return ret;
1738*4882a593Smuzhiyun 	while (*b == ' ')
1739*4882a593Smuzhiyun 		b++;
1740*4882a593Smuzhiyun 	if (strval_len(b) == 0)
1741*4882a593Smuzhiyun 		return -EINVAL;
1742*4882a593Smuzhiyun 	ret = kstrtoul(b, 0, &loc.addr);
1743*4882a593Smuzhiyun 	if (ret)
1744*4882a593Smuzhiyun 		return ret;
1745*4882a593Smuzhiyun 
1746*4882a593Smuzhiyun 	if (write) {
1747*4882a593Smuzhiyun 		while (*b == ' ')
1748*4882a593Smuzhiyun 			b++;
1749*4882a593Smuzhiyun 		if (strval_len(b) == 0)
1750*4882a593Smuzhiyun 			return -EINVAL;
1751*4882a593Smuzhiyun 		ret = kstrtouint(b, 0, &val);
1752*4882a593Smuzhiyun 		if (ret)
1753*4882a593Smuzhiyun 			return ret;
1754*4882a593Smuzhiyun 	}
1755*4882a593Smuzhiyun 
1756*4882a593Smuzhiyun 	/* args are ok, update target cfg (mainly for read) */
1757*4882a593Smuzhiyun 	*cfg = loc;
1758*4882a593Smuzhiyun 
1759*4882a593Smuzhiyun #ifdef ABB_HWREG_DEBUG
1760*4882a593Smuzhiyun 	pr_warn("HWREG request: %s, %s,\n", (write) ? "write" : "read",
1761*4882a593Smuzhiyun 		REG_FMT_DEC(cfg) ? "decimal" : "hexa");
1762*4882a593Smuzhiyun 	pr_warn("  addr=0x%08X, mask=0x%X, shift=%d" "value=0x%X\n",
1763*4882a593Smuzhiyun 		cfg->addr, cfg->mask, cfg->shift, val);
1764*4882a593Smuzhiyun #endif
1765*4882a593Smuzhiyun 
1766*4882a593Smuzhiyun 	if (!write)
1767*4882a593Smuzhiyun 		return 0;
1768*4882a593Smuzhiyun 
1769*4882a593Smuzhiyun 	ret = abx500_get_register_interruptible(dev,
1770*4882a593Smuzhiyun 			(u8)cfg->bank, (u8)cfg->addr, &regvalue);
1771*4882a593Smuzhiyun 	if (ret < 0) {
1772*4882a593Smuzhiyun 		dev_err(dev, "abx500_get_reg fail %d, %d\n",
1773*4882a593Smuzhiyun 			ret, __LINE__);
1774*4882a593Smuzhiyun 		return -EINVAL;
1775*4882a593Smuzhiyun 	}
1776*4882a593Smuzhiyun 
1777*4882a593Smuzhiyun 	if (cfg->shift >= 0) {
1778*4882a593Smuzhiyun 		regvalue &= ~(cfg->mask << (cfg->shift));
1779*4882a593Smuzhiyun 		val = (val & cfg->mask) << (cfg->shift);
1780*4882a593Smuzhiyun 	} else {
1781*4882a593Smuzhiyun 		regvalue &= ~(cfg->mask >> (-cfg->shift));
1782*4882a593Smuzhiyun 		val = (val & cfg->mask) >> (-cfg->shift);
1783*4882a593Smuzhiyun 	}
1784*4882a593Smuzhiyun 	val = val | regvalue;
1785*4882a593Smuzhiyun 
1786*4882a593Smuzhiyun 	ret = abx500_set_register_interruptible(dev,
1787*4882a593Smuzhiyun 			(u8)cfg->bank, (u8)cfg->addr, (u8)val);
1788*4882a593Smuzhiyun 	if (ret < 0) {
1789*4882a593Smuzhiyun 		pr_err("abx500_set_reg failed %d, %d", ret, __LINE__);
1790*4882a593Smuzhiyun 		return -EINVAL;
1791*4882a593Smuzhiyun 	}
1792*4882a593Smuzhiyun 
1793*4882a593Smuzhiyun 	return 0;
1794*4882a593Smuzhiyun }
1795*4882a593Smuzhiyun 
ab8500_hwreg_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)1796*4882a593Smuzhiyun static ssize_t ab8500_hwreg_write(struct file *file,
1797*4882a593Smuzhiyun 	const char __user *user_buf, size_t count, loff_t *ppos)
1798*4882a593Smuzhiyun {
1799*4882a593Smuzhiyun 	struct device *dev = ((struct seq_file *)(file->private_data))->private;
1800*4882a593Smuzhiyun 	char buf[128];
1801*4882a593Smuzhiyun 	int buf_size, ret;
1802*4882a593Smuzhiyun 
1803*4882a593Smuzhiyun 	/* Get userspace string and assure termination */
1804*4882a593Smuzhiyun 	buf_size = min((int)count, (int)(sizeof(buf)-1));
1805*4882a593Smuzhiyun 	if (copy_from_user(buf, user_buf, buf_size))
1806*4882a593Smuzhiyun 		return -EFAULT;
1807*4882a593Smuzhiyun 	buf[buf_size] = 0;
1808*4882a593Smuzhiyun 
1809*4882a593Smuzhiyun 	/* get args and process */
1810*4882a593Smuzhiyun 	ret = hwreg_common_write(buf, &hwreg_cfg, dev);
1811*4882a593Smuzhiyun 	return (ret) ? ret : buf_size;
1812*4882a593Smuzhiyun }
1813*4882a593Smuzhiyun 
1814*4882a593Smuzhiyun /*
1815*4882a593Smuzhiyun  * - irq subscribe/unsubscribe stuff
1816*4882a593Smuzhiyun  */
ab8500_subscribe_unsubscribe_print(struct seq_file * s,void * p)1817*4882a593Smuzhiyun static int ab8500_subscribe_unsubscribe_print(struct seq_file *s, void *p)
1818*4882a593Smuzhiyun {
1819*4882a593Smuzhiyun 	seq_printf(s, "%d\n", irq_first);
1820*4882a593Smuzhiyun 
1821*4882a593Smuzhiyun 	return 0;
1822*4882a593Smuzhiyun }
1823*4882a593Smuzhiyun 
ab8500_subscribe_unsubscribe_open(struct inode * inode,struct file * file)1824*4882a593Smuzhiyun static int ab8500_subscribe_unsubscribe_open(struct inode *inode,
1825*4882a593Smuzhiyun 					     struct file *file)
1826*4882a593Smuzhiyun {
1827*4882a593Smuzhiyun 	return single_open(file, ab8500_subscribe_unsubscribe_print,
1828*4882a593Smuzhiyun 		inode->i_private);
1829*4882a593Smuzhiyun }
1830*4882a593Smuzhiyun 
1831*4882a593Smuzhiyun /*
1832*4882a593Smuzhiyun  * Userspace should use poll() on this file. When an event occur
1833*4882a593Smuzhiyun  * the blocking poll will be released.
1834*4882a593Smuzhiyun  */
show_irq(struct device * dev,struct device_attribute * attr,char * buf)1835*4882a593Smuzhiyun static ssize_t show_irq(struct device *dev,
1836*4882a593Smuzhiyun 			struct device_attribute *attr, char *buf)
1837*4882a593Smuzhiyun {
1838*4882a593Smuzhiyun 	unsigned long name;
1839*4882a593Smuzhiyun 	unsigned int irq_index;
1840*4882a593Smuzhiyun 	int err;
1841*4882a593Smuzhiyun 
1842*4882a593Smuzhiyun 	err = kstrtoul(attr->attr.name, 0, &name);
1843*4882a593Smuzhiyun 	if (err)
1844*4882a593Smuzhiyun 		return err;
1845*4882a593Smuzhiyun 
1846*4882a593Smuzhiyun 	irq_index = name - irq_first;
1847*4882a593Smuzhiyun 	if (irq_index >= num_irqs)
1848*4882a593Smuzhiyun 		return -EINVAL;
1849*4882a593Smuzhiyun 
1850*4882a593Smuzhiyun 	return sprintf(buf, "%u\n", irq_count[irq_index]);
1851*4882a593Smuzhiyun }
1852*4882a593Smuzhiyun 
ab8500_subscribe_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)1853*4882a593Smuzhiyun static ssize_t ab8500_subscribe_write(struct file *file,
1854*4882a593Smuzhiyun 				      const char __user *user_buf,
1855*4882a593Smuzhiyun 				      size_t count, loff_t *ppos)
1856*4882a593Smuzhiyun {
1857*4882a593Smuzhiyun 	struct device *dev = ((struct seq_file *)(file->private_data))->private;
1858*4882a593Smuzhiyun 	unsigned long user_val;
1859*4882a593Smuzhiyun 	int err;
1860*4882a593Smuzhiyun 	unsigned int irq_index;
1861*4882a593Smuzhiyun 
1862*4882a593Smuzhiyun 	err = kstrtoul_from_user(user_buf, count, 0, &user_val);
1863*4882a593Smuzhiyun 	if (err)
1864*4882a593Smuzhiyun 		return err;
1865*4882a593Smuzhiyun 
1866*4882a593Smuzhiyun 	if (user_val < irq_first) {
1867*4882a593Smuzhiyun 		dev_err(dev, "debugfs error input < %d\n", irq_first);
1868*4882a593Smuzhiyun 		return -EINVAL;
1869*4882a593Smuzhiyun 	}
1870*4882a593Smuzhiyun 	if (user_val > irq_last) {
1871*4882a593Smuzhiyun 		dev_err(dev, "debugfs error input > %d\n", irq_last);
1872*4882a593Smuzhiyun 		return -EINVAL;
1873*4882a593Smuzhiyun 	}
1874*4882a593Smuzhiyun 
1875*4882a593Smuzhiyun 	irq_index = user_val - irq_first;
1876*4882a593Smuzhiyun 	if (irq_index >= num_irqs)
1877*4882a593Smuzhiyun 		return -EINVAL;
1878*4882a593Smuzhiyun 
1879*4882a593Smuzhiyun 	/*
1880*4882a593Smuzhiyun 	 * This will create a sysfs file named <irq-nr> which userspace can
1881*4882a593Smuzhiyun 	 * use to select or poll and get the AB8500 events
1882*4882a593Smuzhiyun 	 */
1883*4882a593Smuzhiyun 	dev_attr[irq_index] = kmalloc(sizeof(struct device_attribute),
1884*4882a593Smuzhiyun 		GFP_KERNEL);
1885*4882a593Smuzhiyun 	if (!dev_attr[irq_index])
1886*4882a593Smuzhiyun 		return -ENOMEM;
1887*4882a593Smuzhiyun 
1888*4882a593Smuzhiyun 	event_name[irq_index] = kasprintf(GFP_KERNEL, "%lu", user_val);
1889*4882a593Smuzhiyun 	if (!event_name[irq_index])
1890*4882a593Smuzhiyun 		return -ENOMEM;
1891*4882a593Smuzhiyun 
1892*4882a593Smuzhiyun 	dev_attr[irq_index]->show = show_irq;
1893*4882a593Smuzhiyun 	dev_attr[irq_index]->store = NULL;
1894*4882a593Smuzhiyun 	dev_attr[irq_index]->attr.name = event_name[irq_index];
1895*4882a593Smuzhiyun 	dev_attr[irq_index]->attr.mode = S_IRUGO;
1896*4882a593Smuzhiyun 	err = sysfs_create_file(&dev->kobj, &dev_attr[irq_index]->attr);
1897*4882a593Smuzhiyun 	if (err < 0) {
1898*4882a593Smuzhiyun 		pr_info("sysfs_create_file failed %d\n", err);
1899*4882a593Smuzhiyun 		return err;
1900*4882a593Smuzhiyun 	}
1901*4882a593Smuzhiyun 
1902*4882a593Smuzhiyun 	err = request_threaded_irq(user_val, NULL, ab8500_debug_handler,
1903*4882a593Smuzhiyun 				   IRQF_SHARED | IRQF_NO_SUSPEND | IRQF_ONESHOT,
1904*4882a593Smuzhiyun 				   "ab8500-debug", &dev->kobj);
1905*4882a593Smuzhiyun 	if (err < 0) {
1906*4882a593Smuzhiyun 		pr_info("request_threaded_irq failed %d, %lu\n",
1907*4882a593Smuzhiyun 			err, user_val);
1908*4882a593Smuzhiyun 		sysfs_remove_file(&dev->kobj, &dev_attr[irq_index]->attr);
1909*4882a593Smuzhiyun 		return err;
1910*4882a593Smuzhiyun 	}
1911*4882a593Smuzhiyun 
1912*4882a593Smuzhiyun 	return count;
1913*4882a593Smuzhiyun }
1914*4882a593Smuzhiyun 
ab8500_unsubscribe_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)1915*4882a593Smuzhiyun static ssize_t ab8500_unsubscribe_write(struct file *file,
1916*4882a593Smuzhiyun 					const char __user *user_buf,
1917*4882a593Smuzhiyun 					size_t count, loff_t *ppos)
1918*4882a593Smuzhiyun {
1919*4882a593Smuzhiyun 	struct device *dev = ((struct seq_file *)(file->private_data))->private;
1920*4882a593Smuzhiyun 	unsigned long user_val;
1921*4882a593Smuzhiyun 	int err;
1922*4882a593Smuzhiyun 	unsigned int irq_index;
1923*4882a593Smuzhiyun 
1924*4882a593Smuzhiyun 	err = kstrtoul_from_user(user_buf, count, 0, &user_val);
1925*4882a593Smuzhiyun 	if (err)
1926*4882a593Smuzhiyun 		return err;
1927*4882a593Smuzhiyun 
1928*4882a593Smuzhiyun 	if (user_val < irq_first) {
1929*4882a593Smuzhiyun 		dev_err(dev, "debugfs error input < %d\n", irq_first);
1930*4882a593Smuzhiyun 		return -EINVAL;
1931*4882a593Smuzhiyun 	}
1932*4882a593Smuzhiyun 	if (user_val > irq_last) {
1933*4882a593Smuzhiyun 		dev_err(dev, "debugfs error input > %d\n", irq_last);
1934*4882a593Smuzhiyun 		return -EINVAL;
1935*4882a593Smuzhiyun 	}
1936*4882a593Smuzhiyun 
1937*4882a593Smuzhiyun 	irq_index = user_val - irq_first;
1938*4882a593Smuzhiyun 	if (irq_index >= num_irqs)
1939*4882a593Smuzhiyun 		return -EINVAL;
1940*4882a593Smuzhiyun 
1941*4882a593Smuzhiyun 	/* Set irq count to 0 when unsubscribe */
1942*4882a593Smuzhiyun 	irq_count[irq_index] = 0;
1943*4882a593Smuzhiyun 
1944*4882a593Smuzhiyun 	if (dev_attr[irq_index])
1945*4882a593Smuzhiyun 		sysfs_remove_file(&dev->kobj, &dev_attr[irq_index]->attr);
1946*4882a593Smuzhiyun 
1947*4882a593Smuzhiyun 
1948*4882a593Smuzhiyun 	free_irq(user_val, &dev->kobj);
1949*4882a593Smuzhiyun 	kfree(event_name[irq_index]);
1950*4882a593Smuzhiyun 	kfree(dev_attr[irq_index]);
1951*4882a593Smuzhiyun 
1952*4882a593Smuzhiyun 	return count;
1953*4882a593Smuzhiyun }
1954*4882a593Smuzhiyun 
1955*4882a593Smuzhiyun /*
1956*4882a593Smuzhiyun  * - several debugfs nodes fops
1957*4882a593Smuzhiyun  */
1958*4882a593Smuzhiyun 
1959*4882a593Smuzhiyun static const struct file_operations ab8500_bank_fops = {
1960*4882a593Smuzhiyun 	.open = ab8500_bank_open,
1961*4882a593Smuzhiyun 	.write = ab8500_bank_write,
1962*4882a593Smuzhiyun 	.read = seq_read,
1963*4882a593Smuzhiyun 	.llseek = seq_lseek,
1964*4882a593Smuzhiyun 	.release = single_release,
1965*4882a593Smuzhiyun 	.owner = THIS_MODULE,
1966*4882a593Smuzhiyun };
1967*4882a593Smuzhiyun 
1968*4882a593Smuzhiyun static const struct file_operations ab8500_address_fops = {
1969*4882a593Smuzhiyun 	.open = ab8500_address_open,
1970*4882a593Smuzhiyun 	.write = ab8500_address_write,
1971*4882a593Smuzhiyun 	.read = seq_read,
1972*4882a593Smuzhiyun 	.llseek = seq_lseek,
1973*4882a593Smuzhiyun 	.release = single_release,
1974*4882a593Smuzhiyun 	.owner = THIS_MODULE,
1975*4882a593Smuzhiyun };
1976*4882a593Smuzhiyun 
1977*4882a593Smuzhiyun static const struct file_operations ab8500_val_fops = {
1978*4882a593Smuzhiyun 	.open = ab8500_val_open,
1979*4882a593Smuzhiyun 	.write = ab8500_val_write,
1980*4882a593Smuzhiyun 	.read = seq_read,
1981*4882a593Smuzhiyun 	.llseek = seq_lseek,
1982*4882a593Smuzhiyun 	.release = single_release,
1983*4882a593Smuzhiyun 	.owner = THIS_MODULE,
1984*4882a593Smuzhiyun };
1985*4882a593Smuzhiyun 
1986*4882a593Smuzhiyun static const struct file_operations ab8500_subscribe_fops = {
1987*4882a593Smuzhiyun 	.open = ab8500_subscribe_unsubscribe_open,
1988*4882a593Smuzhiyun 	.write = ab8500_subscribe_write,
1989*4882a593Smuzhiyun 	.read = seq_read,
1990*4882a593Smuzhiyun 	.llseek = seq_lseek,
1991*4882a593Smuzhiyun 	.release = single_release,
1992*4882a593Smuzhiyun 	.owner = THIS_MODULE,
1993*4882a593Smuzhiyun };
1994*4882a593Smuzhiyun 
1995*4882a593Smuzhiyun static const struct file_operations ab8500_unsubscribe_fops = {
1996*4882a593Smuzhiyun 	.open = ab8500_subscribe_unsubscribe_open,
1997*4882a593Smuzhiyun 	.write = ab8500_unsubscribe_write,
1998*4882a593Smuzhiyun 	.read = seq_read,
1999*4882a593Smuzhiyun 	.llseek = seq_lseek,
2000*4882a593Smuzhiyun 	.release = single_release,
2001*4882a593Smuzhiyun 	.owner = THIS_MODULE,
2002*4882a593Smuzhiyun };
2003*4882a593Smuzhiyun 
2004*4882a593Smuzhiyun static const struct file_operations ab8500_hwreg_fops = {
2005*4882a593Smuzhiyun 	.open = ab8500_hwreg_open,
2006*4882a593Smuzhiyun 	.write = ab8500_hwreg_write,
2007*4882a593Smuzhiyun 	.read = seq_read,
2008*4882a593Smuzhiyun 	.llseek = seq_lseek,
2009*4882a593Smuzhiyun 	.release = single_release,
2010*4882a593Smuzhiyun 	.owner = THIS_MODULE,
2011*4882a593Smuzhiyun };
2012*4882a593Smuzhiyun 
ab8500_debug_probe(struct platform_device * plf)2013*4882a593Smuzhiyun static int ab8500_debug_probe(struct platform_device *plf)
2014*4882a593Smuzhiyun {
2015*4882a593Smuzhiyun 	struct dentry *ab8500_dir;
2016*4882a593Smuzhiyun 	struct ab8500 *ab8500;
2017*4882a593Smuzhiyun 	struct resource *res;
2018*4882a593Smuzhiyun 
2019*4882a593Smuzhiyun 	debug_bank = AB8500_MISC;
2020*4882a593Smuzhiyun 	debug_address = AB8500_REV_REG & 0x00FF;
2021*4882a593Smuzhiyun 
2022*4882a593Smuzhiyun 	ab8500 = dev_get_drvdata(plf->dev.parent);
2023*4882a593Smuzhiyun 	num_irqs = ab8500->mask_size;
2024*4882a593Smuzhiyun 
2025*4882a593Smuzhiyun 	irq_count = devm_kcalloc(&plf->dev,
2026*4882a593Smuzhiyun 				 num_irqs, sizeof(*irq_count), GFP_KERNEL);
2027*4882a593Smuzhiyun 	if (!irq_count)
2028*4882a593Smuzhiyun 		return -ENOMEM;
2029*4882a593Smuzhiyun 
2030*4882a593Smuzhiyun 	dev_attr = devm_kcalloc(&plf->dev,
2031*4882a593Smuzhiyun 				num_irqs, sizeof(*dev_attr), GFP_KERNEL);
2032*4882a593Smuzhiyun 	if (!dev_attr)
2033*4882a593Smuzhiyun 		return -ENOMEM;
2034*4882a593Smuzhiyun 
2035*4882a593Smuzhiyun 	event_name = devm_kcalloc(&plf->dev,
2036*4882a593Smuzhiyun 				  num_irqs, sizeof(*event_name), GFP_KERNEL);
2037*4882a593Smuzhiyun 	if (!event_name)
2038*4882a593Smuzhiyun 		return -ENOMEM;
2039*4882a593Smuzhiyun 
2040*4882a593Smuzhiyun 	res = platform_get_resource_byname(plf, 0, "IRQ_AB8500");
2041*4882a593Smuzhiyun 	if (!res) {
2042*4882a593Smuzhiyun 		dev_err(&plf->dev, "AB8500 irq not found, err %d\n", irq_first);
2043*4882a593Smuzhiyun 		return -ENXIO;
2044*4882a593Smuzhiyun 	}
2045*4882a593Smuzhiyun 	irq_ab8500 = res->start;
2046*4882a593Smuzhiyun 
2047*4882a593Smuzhiyun 	irq_first = platform_get_irq_byname(plf, "IRQ_FIRST");
2048*4882a593Smuzhiyun 	if (irq_first < 0)
2049*4882a593Smuzhiyun 		return irq_first;
2050*4882a593Smuzhiyun 
2051*4882a593Smuzhiyun 	irq_last = platform_get_irq_byname(plf, "IRQ_LAST");
2052*4882a593Smuzhiyun 	if (irq_last < 0)
2053*4882a593Smuzhiyun 		return irq_last;
2054*4882a593Smuzhiyun 
2055*4882a593Smuzhiyun 	ab8500_dir = debugfs_create_dir(AB8500_NAME_STRING, NULL);
2056*4882a593Smuzhiyun 
2057*4882a593Smuzhiyun 	debugfs_create_file("all-bank-registers", S_IRUGO, ab8500_dir,
2058*4882a593Smuzhiyun 			    &plf->dev, &ab8500_bank_registers_fops);
2059*4882a593Smuzhiyun 	debugfs_create_file("all-banks", S_IRUGO, ab8500_dir,
2060*4882a593Smuzhiyun 			    &plf->dev, &ab8500_all_banks_fops);
2061*4882a593Smuzhiyun 	debugfs_create_file("register-bank", (S_IRUGO | S_IWUSR | S_IWGRP),
2062*4882a593Smuzhiyun 			    ab8500_dir, &plf->dev, &ab8500_bank_fops);
2063*4882a593Smuzhiyun 	debugfs_create_file("register-address", (S_IRUGO | S_IWUSR | S_IWGRP),
2064*4882a593Smuzhiyun 			    ab8500_dir, &plf->dev, &ab8500_address_fops);
2065*4882a593Smuzhiyun 	debugfs_create_file("register-value", (S_IRUGO | S_IWUSR | S_IWGRP),
2066*4882a593Smuzhiyun 			    ab8500_dir, &plf->dev, &ab8500_val_fops);
2067*4882a593Smuzhiyun 	debugfs_create_file("irq-subscribe", (S_IRUGO | S_IWUSR | S_IWGRP),
2068*4882a593Smuzhiyun 			    ab8500_dir, &plf->dev, &ab8500_subscribe_fops);
2069*4882a593Smuzhiyun 
2070*4882a593Smuzhiyun 	if (is_ab8500(ab8500)) {
2071*4882a593Smuzhiyun 		debug_ranges = ab8500_debug_ranges;
2072*4882a593Smuzhiyun 		num_interrupt_lines = AB8500_NR_IRQS;
2073*4882a593Smuzhiyun 	} else if (is_ab8505(ab8500)) {
2074*4882a593Smuzhiyun 		debug_ranges = ab8505_debug_ranges;
2075*4882a593Smuzhiyun 		num_interrupt_lines = AB8505_NR_IRQS;
2076*4882a593Smuzhiyun 	} else if (is_ab9540(ab8500)) {
2077*4882a593Smuzhiyun 		debug_ranges = ab8505_debug_ranges;
2078*4882a593Smuzhiyun 		num_interrupt_lines = AB9540_NR_IRQS;
2079*4882a593Smuzhiyun 	} else if (is_ab8540(ab8500)) {
2080*4882a593Smuzhiyun 		debug_ranges = ab8540_debug_ranges;
2081*4882a593Smuzhiyun 		num_interrupt_lines = AB8540_NR_IRQS;
2082*4882a593Smuzhiyun 	}
2083*4882a593Smuzhiyun 
2084*4882a593Smuzhiyun 	debugfs_create_file("interrupts", (S_IRUGO), ab8500_dir, &plf->dev,
2085*4882a593Smuzhiyun 			    &ab8500_interrupts_fops);
2086*4882a593Smuzhiyun 	debugfs_create_file("irq-unsubscribe", (S_IRUGO | S_IWUSR | S_IWGRP),
2087*4882a593Smuzhiyun 			    ab8500_dir, &plf->dev, &ab8500_unsubscribe_fops);
2088*4882a593Smuzhiyun 	debugfs_create_file("hwreg", (S_IRUGO | S_IWUSR | S_IWGRP), ab8500_dir,
2089*4882a593Smuzhiyun 			    &plf->dev, &ab8500_hwreg_fops);
2090*4882a593Smuzhiyun 	debugfs_create_file("all-modem-registers", (S_IRUGO | S_IWUSR | S_IWGRP),
2091*4882a593Smuzhiyun 			    ab8500_dir, &plf->dev, &ab8500_modem_fops);
2092*4882a593Smuzhiyun 
2093*4882a593Smuzhiyun 	return 0;
2094*4882a593Smuzhiyun }
2095*4882a593Smuzhiyun 
2096*4882a593Smuzhiyun static struct platform_driver ab8500_debug_driver = {
2097*4882a593Smuzhiyun 	.driver = {
2098*4882a593Smuzhiyun 		.name = "ab8500-debug",
2099*4882a593Smuzhiyun 		.suppress_bind_attrs = true,
2100*4882a593Smuzhiyun 	},
2101*4882a593Smuzhiyun 	.probe  = ab8500_debug_probe,
2102*4882a593Smuzhiyun };
2103*4882a593Smuzhiyun 
ab8500_debug_init(void)2104*4882a593Smuzhiyun static int __init ab8500_debug_init(void)
2105*4882a593Smuzhiyun {
2106*4882a593Smuzhiyun 	return platform_driver_register(&ab8500_debug_driver);
2107*4882a593Smuzhiyun }
2108*4882a593Smuzhiyun subsys_initcall(ab8500_debug_init);
2109