xref: /OK3568_Linux_fs/kernel/drivers/mfd/ab8500-core.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) ST-Ericsson SA 2010
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
6*4882a593Smuzhiyun  * Author: Rabin Vincent <rabin.vincent@stericsson.com>
7*4882a593Smuzhiyun  * Author: Mattias Wallin <mattias.wallin@stericsson.com>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/slab.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/irq.h>
14*4882a593Smuzhiyun #include <linux/irqdomain.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/interrupt.h>
17*4882a593Smuzhiyun #include <linux/moduleparam.h>
18*4882a593Smuzhiyun #include <linux/platform_device.h>
19*4882a593Smuzhiyun #include <linux/mfd/core.h>
20*4882a593Smuzhiyun #include <linux/mfd/abx500.h>
21*4882a593Smuzhiyun #include <linux/mfd/abx500/ab8500.h>
22*4882a593Smuzhiyun #include <linux/mfd/abx500/ab8500-bm.h>
23*4882a593Smuzhiyun #include <linux/mfd/dbx500-prcmu.h>
24*4882a593Smuzhiyun #include <linux/regulator/ab8500.h>
25*4882a593Smuzhiyun #include <linux/of.h>
26*4882a593Smuzhiyun #include <linux/of_device.h>
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun  * Interrupt register offsets
30*4882a593Smuzhiyun  * Bank : 0x0E
31*4882a593Smuzhiyun  */
32*4882a593Smuzhiyun #define AB8500_IT_SOURCE1_REG		0x00
33*4882a593Smuzhiyun #define AB8500_IT_SOURCE2_REG		0x01
34*4882a593Smuzhiyun #define AB8500_IT_SOURCE3_REG		0x02
35*4882a593Smuzhiyun #define AB8500_IT_SOURCE4_REG		0x03
36*4882a593Smuzhiyun #define AB8500_IT_SOURCE5_REG		0x04
37*4882a593Smuzhiyun #define AB8500_IT_SOURCE6_REG		0x05
38*4882a593Smuzhiyun #define AB8500_IT_SOURCE7_REG		0x06
39*4882a593Smuzhiyun #define AB8500_IT_SOURCE8_REG		0x07
40*4882a593Smuzhiyun #define AB9540_IT_SOURCE13_REG		0x0C
41*4882a593Smuzhiyun #define AB8500_IT_SOURCE19_REG		0x12
42*4882a593Smuzhiyun #define AB8500_IT_SOURCE20_REG		0x13
43*4882a593Smuzhiyun #define AB8500_IT_SOURCE21_REG		0x14
44*4882a593Smuzhiyun #define AB8500_IT_SOURCE22_REG		0x15
45*4882a593Smuzhiyun #define AB8500_IT_SOURCE23_REG		0x16
46*4882a593Smuzhiyun #define AB8500_IT_SOURCE24_REG		0x17
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun  * latch registers
50*4882a593Smuzhiyun  */
51*4882a593Smuzhiyun #define AB8500_IT_LATCH1_REG		0x20
52*4882a593Smuzhiyun #define AB8500_IT_LATCH2_REG		0x21
53*4882a593Smuzhiyun #define AB8500_IT_LATCH3_REG		0x22
54*4882a593Smuzhiyun #define AB8500_IT_LATCH4_REG		0x23
55*4882a593Smuzhiyun #define AB8500_IT_LATCH5_REG		0x24
56*4882a593Smuzhiyun #define AB8500_IT_LATCH6_REG		0x25
57*4882a593Smuzhiyun #define AB8500_IT_LATCH7_REG		0x26
58*4882a593Smuzhiyun #define AB8500_IT_LATCH8_REG		0x27
59*4882a593Smuzhiyun #define AB8500_IT_LATCH9_REG		0x28
60*4882a593Smuzhiyun #define AB8500_IT_LATCH10_REG		0x29
61*4882a593Smuzhiyun #define AB8500_IT_LATCH12_REG		0x2B
62*4882a593Smuzhiyun #define AB9540_IT_LATCH13_REG		0x2C
63*4882a593Smuzhiyun #define AB8500_IT_LATCH19_REG		0x32
64*4882a593Smuzhiyun #define AB8500_IT_LATCH20_REG		0x33
65*4882a593Smuzhiyun #define AB8500_IT_LATCH21_REG		0x34
66*4882a593Smuzhiyun #define AB8500_IT_LATCH22_REG		0x35
67*4882a593Smuzhiyun #define AB8500_IT_LATCH23_REG		0x36
68*4882a593Smuzhiyun #define AB8500_IT_LATCH24_REG		0x37
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun /*
71*4882a593Smuzhiyun  * mask registers
72*4882a593Smuzhiyun  */
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #define AB8500_IT_MASK1_REG		0x40
75*4882a593Smuzhiyun #define AB8500_IT_MASK2_REG		0x41
76*4882a593Smuzhiyun #define AB8500_IT_MASK3_REG		0x42
77*4882a593Smuzhiyun #define AB8500_IT_MASK4_REG		0x43
78*4882a593Smuzhiyun #define AB8500_IT_MASK5_REG		0x44
79*4882a593Smuzhiyun #define AB8500_IT_MASK6_REG		0x45
80*4882a593Smuzhiyun #define AB8500_IT_MASK7_REG		0x46
81*4882a593Smuzhiyun #define AB8500_IT_MASK8_REG		0x47
82*4882a593Smuzhiyun #define AB8500_IT_MASK9_REG		0x48
83*4882a593Smuzhiyun #define AB8500_IT_MASK10_REG		0x49
84*4882a593Smuzhiyun #define AB8500_IT_MASK11_REG		0x4A
85*4882a593Smuzhiyun #define AB8500_IT_MASK12_REG		0x4B
86*4882a593Smuzhiyun #define AB8500_IT_MASK13_REG		0x4C
87*4882a593Smuzhiyun #define AB8500_IT_MASK14_REG		0x4D
88*4882a593Smuzhiyun #define AB8500_IT_MASK15_REG		0x4E
89*4882a593Smuzhiyun #define AB8500_IT_MASK16_REG		0x4F
90*4882a593Smuzhiyun #define AB8500_IT_MASK17_REG		0x50
91*4882a593Smuzhiyun #define AB8500_IT_MASK18_REG		0x51
92*4882a593Smuzhiyun #define AB8500_IT_MASK19_REG		0x52
93*4882a593Smuzhiyun #define AB8500_IT_MASK20_REG		0x53
94*4882a593Smuzhiyun #define AB8500_IT_MASK21_REG		0x54
95*4882a593Smuzhiyun #define AB8500_IT_MASK22_REG		0x55
96*4882a593Smuzhiyun #define AB8500_IT_MASK23_REG		0x56
97*4882a593Smuzhiyun #define AB8500_IT_MASK24_REG		0x57
98*4882a593Smuzhiyun #define AB8500_IT_MASK25_REG		0x58
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun /*
101*4882a593Smuzhiyun  * latch hierarchy registers
102*4882a593Smuzhiyun  */
103*4882a593Smuzhiyun #define AB8500_IT_LATCHHIER1_REG	0x60
104*4882a593Smuzhiyun #define AB8500_IT_LATCHHIER2_REG	0x61
105*4882a593Smuzhiyun #define AB8500_IT_LATCHHIER3_REG	0x62
106*4882a593Smuzhiyun #define AB8540_IT_LATCHHIER4_REG	0x63
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun #define AB8500_IT_LATCHHIER_NUM		3
109*4882a593Smuzhiyun #define AB8540_IT_LATCHHIER_NUM		4
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun #define AB8500_REV_REG			0x80
112*4882a593Smuzhiyun #define AB8500_IC_NAME_REG		0x82
113*4882a593Smuzhiyun #define AB8500_SWITCH_OFF_STATUS	0x00
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun #define AB8500_TURN_ON_STATUS		0x00
116*4882a593Smuzhiyun #define AB8505_TURN_ON_STATUS_2		0x04
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun #define AB8500_CH_USBCH_STAT1_REG	0x02
119*4882a593Smuzhiyun #define VBUS_DET_DBNC100		0x02
120*4882a593Smuzhiyun #define VBUS_DET_DBNC1			0x01
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun static DEFINE_SPINLOCK(on_stat_lock);
123*4882a593Smuzhiyun static u8 turn_on_stat_mask = 0xFF;
124*4882a593Smuzhiyun static u8 turn_on_stat_set;
125*4882a593Smuzhiyun static bool no_bm; /* No battery management */
126*4882a593Smuzhiyun /*
127*4882a593Smuzhiyun  * not really modular, but the easiest way to keep compat with existing
128*4882a593Smuzhiyun  * bootargs behaviour is to continue using module_param here.
129*4882a593Smuzhiyun  */
130*4882a593Smuzhiyun module_param(no_bm, bool, S_IRUGO);
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun #define AB9540_MODEM_CTRL2_REG			0x23
133*4882a593Smuzhiyun #define AB9540_MODEM_CTRL2_SWDBBRSTN_BIT	BIT(2)
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun /*
136*4882a593Smuzhiyun  * Map interrupt numbers to the LATCH and MASK register offsets, Interrupt
137*4882a593Smuzhiyun  * numbers are indexed into this array with (num / 8). The interupts are
138*4882a593Smuzhiyun  * defined in linux/mfd/ab8500.h
139*4882a593Smuzhiyun  *
140*4882a593Smuzhiyun  * This is one off from the register names, i.e. AB8500_IT_MASK1_REG is at
141*4882a593Smuzhiyun  * offset 0.
142*4882a593Smuzhiyun  */
143*4882a593Smuzhiyun /* AB8500 support */
144*4882a593Smuzhiyun static const int ab8500_irq_regoffset[AB8500_NUM_IRQ_REGS] = {
145*4882a593Smuzhiyun 	0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21,
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun /* AB9540 / AB8505 support */
149*4882a593Smuzhiyun static const int ab9540_irq_regoffset[AB9540_NUM_IRQ_REGS] = {
150*4882a593Smuzhiyun 	0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21, 12, 13, 24, 5, 22, 23
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun /* AB8540 support */
154*4882a593Smuzhiyun static const int ab8540_irq_regoffset[AB8540_NUM_IRQ_REGS] = {
155*4882a593Smuzhiyun 	0, 1, 2, 3, 4, -1, -1, -1, -1, 11, 18, 19, 20, 21, 12, 13, 24, 5, 22,
156*4882a593Smuzhiyun 	23, 25, 26, 27, 28, 29, 30, 31,
157*4882a593Smuzhiyun };
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun static const char ab8500_version_str[][7] = {
160*4882a593Smuzhiyun 	[AB8500_VERSION_AB8500] = "AB8500",
161*4882a593Smuzhiyun 	[AB8500_VERSION_AB8505] = "AB8505",
162*4882a593Smuzhiyun 	[AB8500_VERSION_AB9540] = "AB9540",
163*4882a593Smuzhiyun 	[AB8500_VERSION_AB8540] = "AB8540",
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun 
ab8500_prcmu_write(struct ab8500 * ab8500,u16 addr,u8 data)166*4882a593Smuzhiyun static int ab8500_prcmu_write(struct ab8500 *ab8500, u16 addr, u8 data)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun 	int ret;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	ret = prcmu_abb_write((u8)(addr >> 8), (u8)(addr & 0xFF), &data, 1);
171*4882a593Smuzhiyun 	if (ret < 0)
172*4882a593Smuzhiyun 		dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
173*4882a593Smuzhiyun 	return ret;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun 
ab8500_prcmu_write_masked(struct ab8500 * ab8500,u16 addr,u8 mask,u8 data)176*4882a593Smuzhiyun static int ab8500_prcmu_write_masked(struct ab8500 *ab8500, u16 addr, u8 mask,
177*4882a593Smuzhiyun 	u8 data)
178*4882a593Smuzhiyun {
179*4882a593Smuzhiyun 	int ret;
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	ret = prcmu_abb_write_masked((u8)(addr >> 8), (u8)(addr & 0xFF), &data,
182*4882a593Smuzhiyun 		&mask, 1);
183*4882a593Smuzhiyun 	if (ret < 0)
184*4882a593Smuzhiyun 		dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
185*4882a593Smuzhiyun 	return ret;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun 
ab8500_prcmu_read(struct ab8500 * ab8500,u16 addr)188*4882a593Smuzhiyun static int ab8500_prcmu_read(struct ab8500 *ab8500, u16 addr)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	int ret;
191*4882a593Smuzhiyun 	u8 data;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	ret = prcmu_abb_read((u8)(addr >> 8), (u8)(addr & 0xFF), &data, 1);
194*4882a593Smuzhiyun 	if (ret < 0) {
195*4882a593Smuzhiyun 		dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
196*4882a593Smuzhiyun 		return ret;
197*4882a593Smuzhiyun 	}
198*4882a593Smuzhiyun 	return (int)data;
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun 
ab8500_get_chip_id(struct device * dev)201*4882a593Smuzhiyun static int ab8500_get_chip_id(struct device *dev)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun 	struct ab8500 *ab8500;
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	if (!dev)
206*4882a593Smuzhiyun 		return -EINVAL;
207*4882a593Smuzhiyun 	ab8500 = dev_get_drvdata(dev->parent);
208*4882a593Smuzhiyun 	return ab8500 ? (int)ab8500->chip_id : -EINVAL;
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun 
set_register_interruptible(struct ab8500 * ab8500,u8 bank,u8 reg,u8 data)211*4882a593Smuzhiyun static int set_register_interruptible(struct ab8500 *ab8500, u8 bank,
212*4882a593Smuzhiyun 	u8 reg, u8 data)
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun 	int ret;
215*4882a593Smuzhiyun 	/*
216*4882a593Smuzhiyun 	 * Put the u8 bank and u8 register together into a an u16.
217*4882a593Smuzhiyun 	 * The bank on higher 8 bits and register in lower 8 bits.
218*4882a593Smuzhiyun 	 */
219*4882a593Smuzhiyun 	u16 addr = ((u16)bank) << 8 | reg;
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	dev_vdbg(ab8500->dev, "wr: addr %#x <= %#x\n", addr, data);
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	mutex_lock(&ab8500->lock);
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	ret = ab8500->write(ab8500, addr, data);
226*4882a593Smuzhiyun 	if (ret < 0)
227*4882a593Smuzhiyun 		dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
228*4882a593Smuzhiyun 			addr, ret);
229*4882a593Smuzhiyun 	mutex_unlock(&ab8500->lock);
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	return ret;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun 
ab8500_set_register(struct device * dev,u8 bank,u8 reg,u8 value)234*4882a593Smuzhiyun static int ab8500_set_register(struct device *dev, u8 bank,
235*4882a593Smuzhiyun 	u8 reg, u8 value)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun 	int ret;
238*4882a593Smuzhiyun 	struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	atomic_inc(&ab8500->transfer_ongoing);
241*4882a593Smuzhiyun 	ret = set_register_interruptible(ab8500, bank, reg, value);
242*4882a593Smuzhiyun 	atomic_dec(&ab8500->transfer_ongoing);
243*4882a593Smuzhiyun 	return ret;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun 
get_register_interruptible(struct ab8500 * ab8500,u8 bank,u8 reg,u8 * value)246*4882a593Smuzhiyun static int get_register_interruptible(struct ab8500 *ab8500, u8 bank,
247*4882a593Smuzhiyun 	u8 reg, u8 *value)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun 	int ret;
250*4882a593Smuzhiyun 	u16 addr = ((u16)bank) << 8 | reg;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	mutex_lock(&ab8500->lock);
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	ret = ab8500->read(ab8500, addr);
255*4882a593Smuzhiyun 	if (ret < 0)
256*4882a593Smuzhiyun 		dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
257*4882a593Smuzhiyun 			addr, ret);
258*4882a593Smuzhiyun 	else
259*4882a593Smuzhiyun 		*value = ret;
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	mutex_unlock(&ab8500->lock);
262*4882a593Smuzhiyun 	dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret);
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	return (ret < 0) ? ret : 0;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun 
ab8500_get_register(struct device * dev,u8 bank,u8 reg,u8 * value)267*4882a593Smuzhiyun static int ab8500_get_register(struct device *dev, u8 bank,
268*4882a593Smuzhiyun 	u8 reg, u8 *value)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun 	int ret;
271*4882a593Smuzhiyun 	struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	atomic_inc(&ab8500->transfer_ongoing);
274*4882a593Smuzhiyun 	ret = get_register_interruptible(ab8500, bank, reg, value);
275*4882a593Smuzhiyun 	atomic_dec(&ab8500->transfer_ongoing);
276*4882a593Smuzhiyun 	return ret;
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun 
mask_and_set_register_interruptible(struct ab8500 * ab8500,u8 bank,u8 reg,u8 bitmask,u8 bitvalues)279*4882a593Smuzhiyun static int mask_and_set_register_interruptible(struct ab8500 *ab8500, u8 bank,
280*4882a593Smuzhiyun 	u8 reg, u8 bitmask, u8 bitvalues)
281*4882a593Smuzhiyun {
282*4882a593Smuzhiyun 	int ret;
283*4882a593Smuzhiyun 	u16 addr = ((u16)bank) << 8 | reg;
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	mutex_lock(&ab8500->lock);
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	if (ab8500->write_masked == NULL) {
288*4882a593Smuzhiyun 		u8 data;
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 		ret = ab8500->read(ab8500, addr);
291*4882a593Smuzhiyun 		if (ret < 0) {
292*4882a593Smuzhiyun 			dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
293*4882a593Smuzhiyun 				addr, ret);
294*4882a593Smuzhiyun 			goto out;
295*4882a593Smuzhiyun 		}
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 		data = (u8)ret;
298*4882a593Smuzhiyun 		data = (~bitmask & data) | (bitmask & bitvalues);
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 		ret = ab8500->write(ab8500, addr, data);
301*4882a593Smuzhiyun 		if (ret < 0)
302*4882a593Smuzhiyun 			dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
303*4882a593Smuzhiyun 				addr, ret);
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 		dev_vdbg(ab8500->dev, "mask: addr %#x => data %#x\n", addr,
306*4882a593Smuzhiyun 			data);
307*4882a593Smuzhiyun 		goto out;
308*4882a593Smuzhiyun 	}
309*4882a593Smuzhiyun 	ret = ab8500->write_masked(ab8500, addr, bitmask, bitvalues);
310*4882a593Smuzhiyun 	if (ret < 0)
311*4882a593Smuzhiyun 		dev_err(ab8500->dev, "failed to modify reg %#x: %d\n", addr,
312*4882a593Smuzhiyun 			ret);
313*4882a593Smuzhiyun out:
314*4882a593Smuzhiyun 	mutex_unlock(&ab8500->lock);
315*4882a593Smuzhiyun 	return ret;
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun 
ab8500_mask_and_set_register(struct device * dev,u8 bank,u8 reg,u8 bitmask,u8 bitvalues)318*4882a593Smuzhiyun static int ab8500_mask_and_set_register(struct device *dev,
319*4882a593Smuzhiyun 	u8 bank, u8 reg, u8 bitmask, u8 bitvalues)
320*4882a593Smuzhiyun {
321*4882a593Smuzhiyun 	int ret;
322*4882a593Smuzhiyun 	struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	atomic_inc(&ab8500->transfer_ongoing);
325*4882a593Smuzhiyun 	ret = mask_and_set_register_interruptible(ab8500, bank, reg,
326*4882a593Smuzhiyun 						 bitmask, bitvalues);
327*4882a593Smuzhiyun 	atomic_dec(&ab8500->transfer_ongoing);
328*4882a593Smuzhiyun 	return ret;
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun static struct abx500_ops ab8500_ops = {
332*4882a593Smuzhiyun 	.get_chip_id = ab8500_get_chip_id,
333*4882a593Smuzhiyun 	.get_register = ab8500_get_register,
334*4882a593Smuzhiyun 	.set_register = ab8500_set_register,
335*4882a593Smuzhiyun 	.get_register_page = NULL,
336*4882a593Smuzhiyun 	.set_register_page = NULL,
337*4882a593Smuzhiyun 	.mask_and_set_register = ab8500_mask_and_set_register,
338*4882a593Smuzhiyun 	.event_registers_startup_state_get = NULL,
339*4882a593Smuzhiyun 	.startup_irq_enabled = NULL,
340*4882a593Smuzhiyun 	.dump_all_banks = ab8500_dump_all_banks,
341*4882a593Smuzhiyun };
342*4882a593Smuzhiyun 
ab8500_irq_lock(struct irq_data * data)343*4882a593Smuzhiyun static void ab8500_irq_lock(struct irq_data *data)
344*4882a593Smuzhiyun {
345*4882a593Smuzhiyun 	struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	mutex_lock(&ab8500->irq_lock);
348*4882a593Smuzhiyun 	atomic_inc(&ab8500->transfer_ongoing);
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun 
ab8500_irq_sync_unlock(struct irq_data * data)351*4882a593Smuzhiyun static void ab8500_irq_sync_unlock(struct irq_data *data)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun 	struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
354*4882a593Smuzhiyun 	int i;
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 	for (i = 0; i < ab8500->mask_size; i++) {
357*4882a593Smuzhiyun 		u8 old = ab8500->oldmask[i];
358*4882a593Smuzhiyun 		u8 new = ab8500->mask[i];
359*4882a593Smuzhiyun 		int reg;
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun 		if (new == old)
362*4882a593Smuzhiyun 			continue;
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 		/*
365*4882a593Smuzhiyun 		 * Interrupt register 12 doesn't exist prior to AB8500 version
366*4882a593Smuzhiyun 		 * 2.0
367*4882a593Smuzhiyun 		 */
368*4882a593Smuzhiyun 		if (ab8500->irq_reg_offset[i] == 11 &&
369*4882a593Smuzhiyun 			is_ab8500_1p1_or_earlier(ab8500))
370*4882a593Smuzhiyun 			continue;
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 		if (ab8500->irq_reg_offset[i] < 0)
373*4882a593Smuzhiyun 			continue;
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun 		ab8500->oldmask[i] = new;
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 		reg = AB8500_IT_MASK1_REG + ab8500->irq_reg_offset[i];
378*4882a593Smuzhiyun 		set_register_interruptible(ab8500, AB8500_INTERRUPT, reg, new);
379*4882a593Smuzhiyun 	}
380*4882a593Smuzhiyun 	atomic_dec(&ab8500->transfer_ongoing);
381*4882a593Smuzhiyun 	mutex_unlock(&ab8500->irq_lock);
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun 
ab8500_irq_mask(struct irq_data * data)384*4882a593Smuzhiyun static void ab8500_irq_mask(struct irq_data *data)
385*4882a593Smuzhiyun {
386*4882a593Smuzhiyun 	struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
387*4882a593Smuzhiyun 	int offset = data->hwirq;
388*4882a593Smuzhiyun 	int index = offset / 8;
389*4882a593Smuzhiyun 	int mask = 1 << (offset % 8);
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 	ab8500->mask[index] |= mask;
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 	/* The AB8500 GPIOs have two interrupts each (rising & falling). */
394*4882a593Smuzhiyun 	if (offset >= AB8500_INT_GPIO6R && offset <= AB8500_INT_GPIO41R)
395*4882a593Smuzhiyun 		ab8500->mask[index + 2] |= mask;
396*4882a593Smuzhiyun 	if (offset >= AB9540_INT_GPIO50R && offset <= AB9540_INT_GPIO54R)
397*4882a593Smuzhiyun 		ab8500->mask[index + 1] |= mask;
398*4882a593Smuzhiyun 	if (offset == AB8540_INT_GPIO43R || offset == AB8540_INT_GPIO44R)
399*4882a593Smuzhiyun 		/* Here the falling IRQ is one bit lower */
400*4882a593Smuzhiyun 		ab8500->mask[index] |= (mask << 1);
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun 
ab8500_irq_unmask(struct irq_data * data)403*4882a593Smuzhiyun static void ab8500_irq_unmask(struct irq_data *data)
404*4882a593Smuzhiyun {
405*4882a593Smuzhiyun 	struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
406*4882a593Smuzhiyun 	unsigned int type = irqd_get_trigger_type(data);
407*4882a593Smuzhiyun 	int offset = data->hwirq;
408*4882a593Smuzhiyun 	int index = offset / 8;
409*4882a593Smuzhiyun 	int mask = 1 << (offset % 8);
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun 	if (type & IRQ_TYPE_EDGE_RISING)
412*4882a593Smuzhiyun 		ab8500->mask[index] &= ~mask;
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	/* The AB8500 GPIOs have two interrupts each (rising & falling). */
415*4882a593Smuzhiyun 	if (type & IRQ_TYPE_EDGE_FALLING) {
416*4882a593Smuzhiyun 		if (offset >= AB8500_INT_GPIO6R && offset <= AB8500_INT_GPIO41R)
417*4882a593Smuzhiyun 			ab8500->mask[index + 2] &= ~mask;
418*4882a593Smuzhiyun 		else if (offset >= AB9540_INT_GPIO50R &&
419*4882a593Smuzhiyun 			 offset <= AB9540_INT_GPIO54R)
420*4882a593Smuzhiyun 			ab8500->mask[index + 1] &= ~mask;
421*4882a593Smuzhiyun 		else if (offset == AB8540_INT_GPIO43R ||
422*4882a593Smuzhiyun 			 offset == AB8540_INT_GPIO44R)
423*4882a593Smuzhiyun 			/* Here the falling IRQ is one bit lower */
424*4882a593Smuzhiyun 			ab8500->mask[index] &= ~(mask << 1);
425*4882a593Smuzhiyun 		else
426*4882a593Smuzhiyun 			ab8500->mask[index] &= ~mask;
427*4882a593Smuzhiyun 	} else {
428*4882a593Smuzhiyun 		/* Satisfies the case where type is not set. */
429*4882a593Smuzhiyun 		ab8500->mask[index] &= ~mask;
430*4882a593Smuzhiyun 	}
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun 
ab8500_irq_set_type(struct irq_data * data,unsigned int type)433*4882a593Smuzhiyun static int ab8500_irq_set_type(struct irq_data *data, unsigned int type)
434*4882a593Smuzhiyun {
435*4882a593Smuzhiyun 	return 0;
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun static struct irq_chip ab8500_irq_chip = {
439*4882a593Smuzhiyun 	.name			= "ab8500",
440*4882a593Smuzhiyun 	.irq_bus_lock		= ab8500_irq_lock,
441*4882a593Smuzhiyun 	.irq_bus_sync_unlock	= ab8500_irq_sync_unlock,
442*4882a593Smuzhiyun 	.irq_mask		= ab8500_irq_mask,
443*4882a593Smuzhiyun 	.irq_disable		= ab8500_irq_mask,
444*4882a593Smuzhiyun 	.irq_unmask		= ab8500_irq_unmask,
445*4882a593Smuzhiyun 	.irq_set_type		= ab8500_irq_set_type,
446*4882a593Smuzhiyun };
447*4882a593Smuzhiyun 
update_latch_offset(u8 * offset,int i)448*4882a593Smuzhiyun static void update_latch_offset(u8 *offset, int i)
449*4882a593Smuzhiyun {
450*4882a593Smuzhiyun 	/* Fix inconsistent ITFromLatch25 bit mapping... */
451*4882a593Smuzhiyun 	if (unlikely(*offset == 17))
452*4882a593Smuzhiyun 		*offset = 24;
453*4882a593Smuzhiyun 	/* Fix inconsistent ab8540 bit mapping... */
454*4882a593Smuzhiyun 	if (unlikely(*offset == 16))
455*4882a593Smuzhiyun 		*offset = 25;
456*4882a593Smuzhiyun 	if ((i == 3) && (*offset >= 24))
457*4882a593Smuzhiyun 		*offset += 2;
458*4882a593Smuzhiyun }
459*4882a593Smuzhiyun 
ab8500_handle_hierarchical_line(struct ab8500 * ab8500,int latch_offset,u8 latch_val)460*4882a593Smuzhiyun static int ab8500_handle_hierarchical_line(struct ab8500 *ab8500,
461*4882a593Smuzhiyun 					int latch_offset, u8 latch_val)
462*4882a593Smuzhiyun {
463*4882a593Smuzhiyun 	int int_bit, line, i;
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun 	for (i = 0; i < ab8500->mask_size; i++)
466*4882a593Smuzhiyun 		if (ab8500->irq_reg_offset[i] == latch_offset)
467*4882a593Smuzhiyun 			break;
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun 	if (i >= ab8500->mask_size) {
470*4882a593Smuzhiyun 		dev_err(ab8500->dev, "Register offset 0x%2x not declared\n",
471*4882a593Smuzhiyun 				latch_offset);
472*4882a593Smuzhiyun 		return -ENXIO;
473*4882a593Smuzhiyun 	}
474*4882a593Smuzhiyun 
475*4882a593Smuzhiyun 	/* ignore masked out interrupts */
476*4882a593Smuzhiyun 	latch_val &= ~ab8500->mask[i];
477*4882a593Smuzhiyun 
478*4882a593Smuzhiyun 	while (latch_val) {
479*4882a593Smuzhiyun 		int_bit = __ffs(latch_val);
480*4882a593Smuzhiyun 		line = (i << 3) + int_bit;
481*4882a593Smuzhiyun 		latch_val &= ~(1 << int_bit);
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 		/*
484*4882a593Smuzhiyun 		 * This handles the falling edge hwirqs from the GPIO
485*4882a593Smuzhiyun 		 * lines. Route them back to the line registered for the
486*4882a593Smuzhiyun 		 * rising IRQ, as this is merely a flag for the same IRQ
487*4882a593Smuzhiyun 		 * in linux terms.
488*4882a593Smuzhiyun 		 */
489*4882a593Smuzhiyun 		if (line >= AB8500_INT_GPIO6F && line <= AB8500_INT_GPIO41F)
490*4882a593Smuzhiyun 			line -= 16;
491*4882a593Smuzhiyun 		if (line >= AB9540_INT_GPIO50F && line <= AB9540_INT_GPIO54F)
492*4882a593Smuzhiyun 			line -= 8;
493*4882a593Smuzhiyun 		if (line == AB8540_INT_GPIO43F || line == AB8540_INT_GPIO44F)
494*4882a593Smuzhiyun 			line += 1;
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun 		handle_nested_irq(irq_find_mapping(ab8500->domain, line));
497*4882a593Smuzhiyun 	}
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 	return 0;
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun 
ab8500_handle_hierarchical_latch(struct ab8500 * ab8500,int hier_offset,u8 hier_val)502*4882a593Smuzhiyun static int ab8500_handle_hierarchical_latch(struct ab8500 *ab8500,
503*4882a593Smuzhiyun 					int hier_offset, u8 hier_val)
504*4882a593Smuzhiyun {
505*4882a593Smuzhiyun 	int latch_bit, status;
506*4882a593Smuzhiyun 	u8 latch_offset, latch_val;
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 	do {
509*4882a593Smuzhiyun 		latch_bit = __ffs(hier_val);
510*4882a593Smuzhiyun 		latch_offset = (hier_offset << 3) + latch_bit;
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 		update_latch_offset(&latch_offset, hier_offset);
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun 		status = get_register_interruptible(ab8500,
515*4882a593Smuzhiyun 				AB8500_INTERRUPT,
516*4882a593Smuzhiyun 				AB8500_IT_LATCH1_REG + latch_offset,
517*4882a593Smuzhiyun 				&latch_val);
518*4882a593Smuzhiyun 		if (status < 0 || latch_val == 0)
519*4882a593Smuzhiyun 			goto discard;
520*4882a593Smuzhiyun 
521*4882a593Smuzhiyun 		status = ab8500_handle_hierarchical_line(ab8500,
522*4882a593Smuzhiyun 				latch_offset, latch_val);
523*4882a593Smuzhiyun 		if (status < 0)
524*4882a593Smuzhiyun 			return status;
525*4882a593Smuzhiyun discard:
526*4882a593Smuzhiyun 		hier_val &= ~(1 << latch_bit);
527*4882a593Smuzhiyun 	} while (hier_val);
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 	return 0;
530*4882a593Smuzhiyun }
531*4882a593Smuzhiyun 
ab8500_hierarchical_irq(int irq,void * dev)532*4882a593Smuzhiyun static irqreturn_t ab8500_hierarchical_irq(int irq, void *dev)
533*4882a593Smuzhiyun {
534*4882a593Smuzhiyun 	struct ab8500 *ab8500 = dev;
535*4882a593Smuzhiyun 	u8 i;
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun 	dev_vdbg(ab8500->dev, "interrupt\n");
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun 	/*  Hierarchical interrupt version */
540*4882a593Smuzhiyun 	for (i = 0; i < (ab8500->it_latchhier_num); i++) {
541*4882a593Smuzhiyun 		int status;
542*4882a593Smuzhiyun 		u8 hier_val;
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun 		status = get_register_interruptible(ab8500, AB8500_INTERRUPT,
545*4882a593Smuzhiyun 			AB8500_IT_LATCHHIER1_REG + i, &hier_val);
546*4882a593Smuzhiyun 		if (status < 0 || hier_val == 0)
547*4882a593Smuzhiyun 			continue;
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun 		status = ab8500_handle_hierarchical_latch(ab8500, i, hier_val);
550*4882a593Smuzhiyun 		if (status < 0)
551*4882a593Smuzhiyun 			break;
552*4882a593Smuzhiyun 	}
553*4882a593Smuzhiyun 	return IRQ_HANDLED;
554*4882a593Smuzhiyun }
555*4882a593Smuzhiyun 
ab8500_irq_map(struct irq_domain * d,unsigned int virq,irq_hw_number_t hwirq)556*4882a593Smuzhiyun static int ab8500_irq_map(struct irq_domain *d, unsigned int virq,
557*4882a593Smuzhiyun 				irq_hw_number_t hwirq)
558*4882a593Smuzhiyun {
559*4882a593Smuzhiyun 	struct ab8500 *ab8500 = d->host_data;
560*4882a593Smuzhiyun 
561*4882a593Smuzhiyun 	if (!ab8500)
562*4882a593Smuzhiyun 		return -EINVAL;
563*4882a593Smuzhiyun 
564*4882a593Smuzhiyun 	irq_set_chip_data(virq, ab8500);
565*4882a593Smuzhiyun 	irq_set_chip_and_handler(virq, &ab8500_irq_chip,
566*4882a593Smuzhiyun 				handle_simple_irq);
567*4882a593Smuzhiyun 	irq_set_nested_thread(virq, 1);
568*4882a593Smuzhiyun 	irq_set_noprobe(virq);
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun 	return 0;
571*4882a593Smuzhiyun }
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun static const struct irq_domain_ops ab8500_irq_ops = {
574*4882a593Smuzhiyun 	.map    = ab8500_irq_map,
575*4882a593Smuzhiyun 	.xlate  = irq_domain_xlate_twocell,
576*4882a593Smuzhiyun };
577*4882a593Smuzhiyun 
ab8500_irq_init(struct ab8500 * ab8500,struct device_node * np)578*4882a593Smuzhiyun static int ab8500_irq_init(struct ab8500 *ab8500, struct device_node *np)
579*4882a593Smuzhiyun {
580*4882a593Smuzhiyun 	int num_irqs;
581*4882a593Smuzhiyun 
582*4882a593Smuzhiyun 	if (is_ab8540(ab8500))
583*4882a593Smuzhiyun 		num_irqs = AB8540_NR_IRQS;
584*4882a593Smuzhiyun 	else if (is_ab9540(ab8500))
585*4882a593Smuzhiyun 		num_irqs = AB9540_NR_IRQS;
586*4882a593Smuzhiyun 	else if (is_ab8505(ab8500))
587*4882a593Smuzhiyun 		num_irqs = AB8505_NR_IRQS;
588*4882a593Smuzhiyun 	else
589*4882a593Smuzhiyun 		num_irqs = AB8500_NR_IRQS;
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun 	/* If ->irq_base is zero this will give a linear mapping */
592*4882a593Smuzhiyun 	ab8500->domain = irq_domain_add_simple(ab8500->dev->of_node,
593*4882a593Smuzhiyun 					       num_irqs, 0,
594*4882a593Smuzhiyun 					       &ab8500_irq_ops, ab8500);
595*4882a593Smuzhiyun 
596*4882a593Smuzhiyun 	if (!ab8500->domain) {
597*4882a593Smuzhiyun 		dev_err(ab8500->dev, "Failed to create irqdomain\n");
598*4882a593Smuzhiyun 		return -ENODEV;
599*4882a593Smuzhiyun 	}
600*4882a593Smuzhiyun 
601*4882a593Smuzhiyun 	return 0;
602*4882a593Smuzhiyun }
603*4882a593Smuzhiyun 
ab8500_suspend(struct ab8500 * ab8500)604*4882a593Smuzhiyun int ab8500_suspend(struct ab8500 *ab8500)
605*4882a593Smuzhiyun {
606*4882a593Smuzhiyun 	if (atomic_read(&ab8500->transfer_ongoing))
607*4882a593Smuzhiyun 		return -EINVAL;
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	return 0;
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun 
612*4882a593Smuzhiyun static const struct mfd_cell ab8500_bm_devs[] = {
613*4882a593Smuzhiyun 	OF_MFD_CELL("ab8500-charger", NULL, &ab8500_bm_data,
614*4882a593Smuzhiyun 		    sizeof(ab8500_bm_data), 0, "stericsson,ab8500-charger"),
615*4882a593Smuzhiyun 	OF_MFD_CELL("ab8500-btemp", NULL, &ab8500_bm_data,
616*4882a593Smuzhiyun 		    sizeof(ab8500_bm_data), 0, "stericsson,ab8500-btemp"),
617*4882a593Smuzhiyun 	OF_MFD_CELL("ab8500-fg", NULL, &ab8500_bm_data,
618*4882a593Smuzhiyun 		    sizeof(ab8500_bm_data), 0, "stericsson,ab8500-fg"),
619*4882a593Smuzhiyun 	OF_MFD_CELL("ab8500-chargalg", NULL, &ab8500_bm_data,
620*4882a593Smuzhiyun 		    sizeof(ab8500_bm_data), 0, "stericsson,ab8500-chargalg"),
621*4882a593Smuzhiyun };
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun static const struct mfd_cell ab8500_devs[] = {
624*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS
625*4882a593Smuzhiyun 	OF_MFD_CELL("ab8500-debug",
626*4882a593Smuzhiyun 		    NULL, NULL, 0, 0, "stericsson,ab8500-debug"),
627*4882a593Smuzhiyun #endif
628*4882a593Smuzhiyun 	OF_MFD_CELL("ab8500-sysctrl",
629*4882a593Smuzhiyun 		    NULL, NULL, 0, 0, "stericsson,ab8500-sysctrl"),
630*4882a593Smuzhiyun 	OF_MFD_CELL("ab8500-ext-regulator",
631*4882a593Smuzhiyun 		    NULL, NULL, 0, 0, "stericsson,ab8500-ext-regulator"),
632*4882a593Smuzhiyun 	OF_MFD_CELL("ab8500-regulator",
633*4882a593Smuzhiyun 		    NULL, NULL, 0, 0, "stericsson,ab8500-regulator"),
634*4882a593Smuzhiyun 	OF_MFD_CELL("ab8500-clk",
635*4882a593Smuzhiyun 		    NULL, NULL, 0, 0, "stericsson,ab8500-clk"),
636*4882a593Smuzhiyun 	OF_MFD_CELL("ab8500-gpadc",
637*4882a593Smuzhiyun 		    NULL, NULL, 0, 0, "stericsson,ab8500-gpadc"),
638*4882a593Smuzhiyun 	OF_MFD_CELL("ab8500-rtc",
639*4882a593Smuzhiyun 		    NULL, NULL, 0, 0, "stericsson,ab8500-rtc"),
640*4882a593Smuzhiyun 	OF_MFD_CELL("ab8500-acc-det",
641*4882a593Smuzhiyun 		    NULL, NULL, 0, 0, "stericsson,ab8500-acc-det"),
642*4882a593Smuzhiyun 	OF_MFD_CELL("ab8500-poweron-key",
643*4882a593Smuzhiyun 		    NULL, NULL, 0, 0, "stericsson,ab8500-poweron-key"),
644*4882a593Smuzhiyun 	OF_MFD_CELL("ab8500-pwm",
645*4882a593Smuzhiyun 		    NULL, NULL, 0, 1, "stericsson,ab8500-pwm"),
646*4882a593Smuzhiyun 	OF_MFD_CELL("ab8500-pwm",
647*4882a593Smuzhiyun 		    NULL, NULL, 0, 2, "stericsson,ab8500-pwm"),
648*4882a593Smuzhiyun 	OF_MFD_CELL("ab8500-pwm",
649*4882a593Smuzhiyun 		    NULL, NULL, 0, 3, "stericsson,ab8500-pwm"),
650*4882a593Smuzhiyun 	OF_MFD_CELL("ab8500-denc",
651*4882a593Smuzhiyun 		    NULL, NULL, 0, 0, "stericsson,ab8500-denc"),
652*4882a593Smuzhiyun 	OF_MFD_CELL("pinctrl-ab8500",
653*4882a593Smuzhiyun 		    NULL, NULL, 0, 0, "stericsson,ab8500-gpio"),
654*4882a593Smuzhiyun 	OF_MFD_CELL("abx500-temp",
655*4882a593Smuzhiyun 		    NULL, NULL, 0, 0, "stericsson,abx500-temp"),
656*4882a593Smuzhiyun 	OF_MFD_CELL("ab8500-usb",
657*4882a593Smuzhiyun 		    NULL, NULL, 0, 0, "stericsson,ab8500-usb"),
658*4882a593Smuzhiyun 	OF_MFD_CELL("ab8500-codec",
659*4882a593Smuzhiyun 		    NULL, NULL, 0, 0, "stericsson,ab8500-codec"),
660*4882a593Smuzhiyun };
661*4882a593Smuzhiyun 
662*4882a593Smuzhiyun static const struct mfd_cell ab9540_devs[] = {
663*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS
664*4882a593Smuzhiyun 	{
665*4882a593Smuzhiyun 		.name = "ab8500-debug",
666*4882a593Smuzhiyun 	},
667*4882a593Smuzhiyun #endif
668*4882a593Smuzhiyun 	{
669*4882a593Smuzhiyun 		.name = "ab8500-sysctrl",
670*4882a593Smuzhiyun 	},
671*4882a593Smuzhiyun 	{
672*4882a593Smuzhiyun 		.name = "ab8500-ext-regulator",
673*4882a593Smuzhiyun 	},
674*4882a593Smuzhiyun 	{
675*4882a593Smuzhiyun 		.name = "ab8500-regulator",
676*4882a593Smuzhiyun 	},
677*4882a593Smuzhiyun 	{
678*4882a593Smuzhiyun 		.name = "abx500-clk",
679*4882a593Smuzhiyun 		.of_compatible = "stericsson,abx500-clk",
680*4882a593Smuzhiyun 	},
681*4882a593Smuzhiyun 	{
682*4882a593Smuzhiyun 		.name = "ab8500-gpadc",
683*4882a593Smuzhiyun 		.of_compatible = "stericsson,ab8500-gpadc",
684*4882a593Smuzhiyun 	},
685*4882a593Smuzhiyun 	{
686*4882a593Smuzhiyun 		.name = "ab8500-rtc",
687*4882a593Smuzhiyun 	},
688*4882a593Smuzhiyun 	{
689*4882a593Smuzhiyun 		.name = "ab8500-acc-det",
690*4882a593Smuzhiyun 	},
691*4882a593Smuzhiyun 	{
692*4882a593Smuzhiyun 		.name = "ab8500-poweron-key",
693*4882a593Smuzhiyun 	},
694*4882a593Smuzhiyun 	{
695*4882a593Smuzhiyun 		.name = "ab8500-pwm",
696*4882a593Smuzhiyun 		.id = 1,
697*4882a593Smuzhiyun 	},
698*4882a593Smuzhiyun 	{
699*4882a593Smuzhiyun 		.name = "abx500-temp",
700*4882a593Smuzhiyun 	},
701*4882a593Smuzhiyun 	{
702*4882a593Smuzhiyun 		.name = "pinctrl-ab9540",
703*4882a593Smuzhiyun 		.of_compatible = "stericsson,ab9540-gpio",
704*4882a593Smuzhiyun 	},
705*4882a593Smuzhiyun 	{
706*4882a593Smuzhiyun 		.name = "ab9540-usb",
707*4882a593Smuzhiyun 	},
708*4882a593Smuzhiyun 	{
709*4882a593Smuzhiyun 		.name = "ab9540-codec",
710*4882a593Smuzhiyun 	},
711*4882a593Smuzhiyun 	{
712*4882a593Smuzhiyun 		.name = "ab-iddet",
713*4882a593Smuzhiyun 	},
714*4882a593Smuzhiyun };
715*4882a593Smuzhiyun 
716*4882a593Smuzhiyun /* Device list for ab8505  */
717*4882a593Smuzhiyun static const struct mfd_cell ab8505_devs[] = {
718*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS
719*4882a593Smuzhiyun 	{
720*4882a593Smuzhiyun 		.name = "ab8500-debug",
721*4882a593Smuzhiyun 		.of_compatible = "stericsson,ab8500-debug",
722*4882a593Smuzhiyun 	},
723*4882a593Smuzhiyun #endif
724*4882a593Smuzhiyun 	{
725*4882a593Smuzhiyun 		.name = "ab8500-sysctrl",
726*4882a593Smuzhiyun 		.of_compatible = "stericsson,ab8500-sysctrl",
727*4882a593Smuzhiyun 	},
728*4882a593Smuzhiyun 	{
729*4882a593Smuzhiyun 		.name = "ab8500-regulator",
730*4882a593Smuzhiyun 		.of_compatible = "stericsson,ab8505-regulator",
731*4882a593Smuzhiyun 	},
732*4882a593Smuzhiyun 	{
733*4882a593Smuzhiyun 		.name = "abx500-clk",
734*4882a593Smuzhiyun 		.of_compatible = "stericsson,ab8500-clk",
735*4882a593Smuzhiyun 	},
736*4882a593Smuzhiyun 	{
737*4882a593Smuzhiyun 		.name = "ab8500-gpadc",
738*4882a593Smuzhiyun 		.of_compatible = "stericsson,ab8500-gpadc",
739*4882a593Smuzhiyun 	},
740*4882a593Smuzhiyun 	{
741*4882a593Smuzhiyun 		.name = "ab8500-rtc",
742*4882a593Smuzhiyun 		.of_compatible = "stericsson,ab8500-rtc",
743*4882a593Smuzhiyun 	},
744*4882a593Smuzhiyun 	{
745*4882a593Smuzhiyun 		.name = "ab8500-acc-det",
746*4882a593Smuzhiyun 		.of_compatible = "stericsson,ab8500-acc-det",
747*4882a593Smuzhiyun 	},
748*4882a593Smuzhiyun 	{
749*4882a593Smuzhiyun 		.name = "ab8500-poweron-key",
750*4882a593Smuzhiyun 		.of_compatible = "stericsson,ab8500-poweron-key",
751*4882a593Smuzhiyun 	},
752*4882a593Smuzhiyun 	{
753*4882a593Smuzhiyun 		.name = "ab8500-pwm",
754*4882a593Smuzhiyun 		.of_compatible = "stericsson,ab8500-pwm",
755*4882a593Smuzhiyun 		.id = 1,
756*4882a593Smuzhiyun 	},
757*4882a593Smuzhiyun 	{
758*4882a593Smuzhiyun 		.name = "pinctrl-ab8505",
759*4882a593Smuzhiyun 		.of_compatible = "stericsson,ab8505-gpio",
760*4882a593Smuzhiyun 	},
761*4882a593Smuzhiyun 	{
762*4882a593Smuzhiyun 		.name = "ab8500-usb",
763*4882a593Smuzhiyun 		.of_compatible = "stericsson,ab8500-usb",
764*4882a593Smuzhiyun 	},
765*4882a593Smuzhiyun 	{
766*4882a593Smuzhiyun 		.name = "ab8500-codec",
767*4882a593Smuzhiyun 		.of_compatible = "stericsson,ab8500-codec",
768*4882a593Smuzhiyun 	},
769*4882a593Smuzhiyun 	{
770*4882a593Smuzhiyun 		.name = "ab-iddet",
771*4882a593Smuzhiyun 	},
772*4882a593Smuzhiyun };
773*4882a593Smuzhiyun 
774*4882a593Smuzhiyun static const struct mfd_cell ab8540_devs[] = {
775*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS
776*4882a593Smuzhiyun 	{
777*4882a593Smuzhiyun 		.name = "ab8500-debug",
778*4882a593Smuzhiyun 	},
779*4882a593Smuzhiyun #endif
780*4882a593Smuzhiyun 	{
781*4882a593Smuzhiyun 		.name = "ab8500-sysctrl",
782*4882a593Smuzhiyun 	},
783*4882a593Smuzhiyun 	{
784*4882a593Smuzhiyun 		.name = "ab8500-ext-regulator",
785*4882a593Smuzhiyun 	},
786*4882a593Smuzhiyun 	{
787*4882a593Smuzhiyun 		.name = "ab8500-regulator",
788*4882a593Smuzhiyun 	},
789*4882a593Smuzhiyun 	{
790*4882a593Smuzhiyun 		.name = "abx500-clk",
791*4882a593Smuzhiyun 		.of_compatible = "stericsson,abx500-clk",
792*4882a593Smuzhiyun 	},
793*4882a593Smuzhiyun 	{
794*4882a593Smuzhiyun 		.name = "ab8500-gpadc",
795*4882a593Smuzhiyun 		.of_compatible = "stericsson,ab8500-gpadc",
796*4882a593Smuzhiyun 	},
797*4882a593Smuzhiyun 	{
798*4882a593Smuzhiyun 		.name = "ab8500-acc-det",
799*4882a593Smuzhiyun 	},
800*4882a593Smuzhiyun 	{
801*4882a593Smuzhiyun 		.name = "ab8500-poweron-key",
802*4882a593Smuzhiyun 	},
803*4882a593Smuzhiyun 	{
804*4882a593Smuzhiyun 		.name = "ab8500-pwm",
805*4882a593Smuzhiyun 		.id = 1,
806*4882a593Smuzhiyun 	},
807*4882a593Smuzhiyun 	{
808*4882a593Smuzhiyun 		.name = "abx500-temp",
809*4882a593Smuzhiyun 	},
810*4882a593Smuzhiyun 	{
811*4882a593Smuzhiyun 		.name = "pinctrl-ab8540",
812*4882a593Smuzhiyun 	},
813*4882a593Smuzhiyun 	{
814*4882a593Smuzhiyun 		.name = "ab8540-usb",
815*4882a593Smuzhiyun 	},
816*4882a593Smuzhiyun 	{
817*4882a593Smuzhiyun 		.name = "ab8540-codec",
818*4882a593Smuzhiyun 	},
819*4882a593Smuzhiyun 	{
820*4882a593Smuzhiyun 		.name = "ab-iddet",
821*4882a593Smuzhiyun 	},
822*4882a593Smuzhiyun };
823*4882a593Smuzhiyun 
824*4882a593Smuzhiyun static const struct mfd_cell ab8540_cut1_devs[] = {
825*4882a593Smuzhiyun 	{
826*4882a593Smuzhiyun 		.name = "ab8500-rtc",
827*4882a593Smuzhiyun 		.of_compatible = "stericsson,ab8500-rtc",
828*4882a593Smuzhiyun 	},
829*4882a593Smuzhiyun };
830*4882a593Smuzhiyun 
831*4882a593Smuzhiyun static const struct mfd_cell ab8540_cut2_devs[] = {
832*4882a593Smuzhiyun 	{
833*4882a593Smuzhiyun 		.name = "ab8540-rtc",
834*4882a593Smuzhiyun 		.of_compatible = "stericsson,ab8540-rtc",
835*4882a593Smuzhiyun 	},
836*4882a593Smuzhiyun };
837*4882a593Smuzhiyun 
show_chip_id(struct device * dev,struct device_attribute * attr,char * buf)838*4882a593Smuzhiyun static ssize_t show_chip_id(struct device *dev,
839*4882a593Smuzhiyun 				struct device_attribute *attr, char *buf)
840*4882a593Smuzhiyun {
841*4882a593Smuzhiyun 	struct ab8500 *ab8500;
842*4882a593Smuzhiyun 
843*4882a593Smuzhiyun 	ab8500 = dev_get_drvdata(dev);
844*4882a593Smuzhiyun 
845*4882a593Smuzhiyun 	return sprintf(buf, "%#x\n", ab8500 ? ab8500->chip_id : -EINVAL);
846*4882a593Smuzhiyun }
847*4882a593Smuzhiyun 
848*4882a593Smuzhiyun /*
849*4882a593Smuzhiyun  * ab8500 has switched off due to (SWITCH_OFF_STATUS):
850*4882a593Smuzhiyun  * 0x01 Swoff bit programming
851*4882a593Smuzhiyun  * 0x02 Thermal protection activation
852*4882a593Smuzhiyun  * 0x04 Vbat lower then BattOk falling threshold
853*4882a593Smuzhiyun  * 0x08 Watchdog expired
854*4882a593Smuzhiyun  * 0x10 Non presence of 32kHz clock
855*4882a593Smuzhiyun  * 0x20 Battery level lower than power on reset threshold
856*4882a593Smuzhiyun  * 0x40 Power on key 1 pressed longer than 10 seconds
857*4882a593Smuzhiyun  * 0x80 DB8500 thermal shutdown
858*4882a593Smuzhiyun  */
show_switch_off_status(struct device * dev,struct device_attribute * attr,char * buf)859*4882a593Smuzhiyun static ssize_t show_switch_off_status(struct device *dev,
860*4882a593Smuzhiyun 				struct device_attribute *attr, char *buf)
861*4882a593Smuzhiyun {
862*4882a593Smuzhiyun 	int ret;
863*4882a593Smuzhiyun 	u8 value;
864*4882a593Smuzhiyun 	struct ab8500 *ab8500;
865*4882a593Smuzhiyun 
866*4882a593Smuzhiyun 	ab8500 = dev_get_drvdata(dev);
867*4882a593Smuzhiyun 	ret = get_register_interruptible(ab8500, AB8500_RTC,
868*4882a593Smuzhiyun 		AB8500_SWITCH_OFF_STATUS, &value);
869*4882a593Smuzhiyun 	if (ret < 0)
870*4882a593Smuzhiyun 		return ret;
871*4882a593Smuzhiyun 	return sprintf(buf, "%#x\n", value);
872*4882a593Smuzhiyun }
873*4882a593Smuzhiyun 
874*4882a593Smuzhiyun /* use mask and set to override the register turn_on_stat value */
ab8500_override_turn_on_stat(u8 mask,u8 set)875*4882a593Smuzhiyun void ab8500_override_turn_on_stat(u8 mask, u8 set)
876*4882a593Smuzhiyun {
877*4882a593Smuzhiyun 	spin_lock(&on_stat_lock);
878*4882a593Smuzhiyun 	turn_on_stat_mask = mask;
879*4882a593Smuzhiyun 	turn_on_stat_set = set;
880*4882a593Smuzhiyun 	spin_unlock(&on_stat_lock);
881*4882a593Smuzhiyun }
882*4882a593Smuzhiyun 
883*4882a593Smuzhiyun /*
884*4882a593Smuzhiyun  * ab8500 has turned on due to (TURN_ON_STATUS):
885*4882a593Smuzhiyun  * 0x01 PORnVbat
886*4882a593Smuzhiyun  * 0x02 PonKey1dbF
887*4882a593Smuzhiyun  * 0x04 PonKey2dbF
888*4882a593Smuzhiyun  * 0x08 RTCAlarm
889*4882a593Smuzhiyun  * 0x10 MainChDet
890*4882a593Smuzhiyun  * 0x20 VbusDet
891*4882a593Smuzhiyun  * 0x40 UsbIDDetect
892*4882a593Smuzhiyun  * 0x80 Reserved
893*4882a593Smuzhiyun  */
show_turn_on_status(struct device * dev,struct device_attribute * attr,char * buf)894*4882a593Smuzhiyun static ssize_t show_turn_on_status(struct device *dev,
895*4882a593Smuzhiyun 				struct device_attribute *attr, char *buf)
896*4882a593Smuzhiyun {
897*4882a593Smuzhiyun 	int ret;
898*4882a593Smuzhiyun 	u8 value;
899*4882a593Smuzhiyun 	struct ab8500 *ab8500;
900*4882a593Smuzhiyun 
901*4882a593Smuzhiyun 	ab8500 = dev_get_drvdata(dev);
902*4882a593Smuzhiyun 	ret = get_register_interruptible(ab8500, AB8500_SYS_CTRL1_BLOCK,
903*4882a593Smuzhiyun 		AB8500_TURN_ON_STATUS, &value);
904*4882a593Smuzhiyun 	if (ret < 0)
905*4882a593Smuzhiyun 		return ret;
906*4882a593Smuzhiyun 
907*4882a593Smuzhiyun 	/*
908*4882a593Smuzhiyun 	 * In L9540, turn_on_status register is not updated correctly if
909*4882a593Smuzhiyun 	 * the device is rebooted with AC/USB charger connected. Due to
910*4882a593Smuzhiyun 	 * this, the device boots android instead of entering into charge
911*4882a593Smuzhiyun 	 * only mode. Read the AC/USB status register to detect the charger
912*4882a593Smuzhiyun 	 * presence and update the turn on status manually.
913*4882a593Smuzhiyun 	 */
914*4882a593Smuzhiyun 	if (is_ab9540(ab8500)) {
915*4882a593Smuzhiyun 		spin_lock(&on_stat_lock);
916*4882a593Smuzhiyun 		value = (value & turn_on_stat_mask) | turn_on_stat_set;
917*4882a593Smuzhiyun 		spin_unlock(&on_stat_lock);
918*4882a593Smuzhiyun 	}
919*4882a593Smuzhiyun 
920*4882a593Smuzhiyun 	return sprintf(buf, "%#x\n", value);
921*4882a593Smuzhiyun }
922*4882a593Smuzhiyun 
show_turn_on_status_2(struct device * dev,struct device_attribute * attr,char * buf)923*4882a593Smuzhiyun static ssize_t show_turn_on_status_2(struct device *dev,
924*4882a593Smuzhiyun 				struct device_attribute *attr, char *buf)
925*4882a593Smuzhiyun {
926*4882a593Smuzhiyun 	int ret;
927*4882a593Smuzhiyun 	u8 value;
928*4882a593Smuzhiyun 	struct ab8500 *ab8500;
929*4882a593Smuzhiyun 
930*4882a593Smuzhiyun 	ab8500 = dev_get_drvdata(dev);
931*4882a593Smuzhiyun 	ret = get_register_interruptible(ab8500, AB8500_SYS_CTRL1_BLOCK,
932*4882a593Smuzhiyun 		AB8505_TURN_ON_STATUS_2, &value);
933*4882a593Smuzhiyun 	if (ret < 0)
934*4882a593Smuzhiyun 		return ret;
935*4882a593Smuzhiyun 	return sprintf(buf, "%#x\n", (value & 0x1));
936*4882a593Smuzhiyun }
937*4882a593Smuzhiyun 
show_ab9540_dbbrstn(struct device * dev,struct device_attribute * attr,char * buf)938*4882a593Smuzhiyun static ssize_t show_ab9540_dbbrstn(struct device *dev,
939*4882a593Smuzhiyun 				struct device_attribute *attr, char *buf)
940*4882a593Smuzhiyun {
941*4882a593Smuzhiyun 	struct ab8500 *ab8500;
942*4882a593Smuzhiyun 	int ret;
943*4882a593Smuzhiyun 	u8 value;
944*4882a593Smuzhiyun 
945*4882a593Smuzhiyun 	ab8500 = dev_get_drvdata(dev);
946*4882a593Smuzhiyun 
947*4882a593Smuzhiyun 	ret = get_register_interruptible(ab8500, AB8500_REGU_CTRL2,
948*4882a593Smuzhiyun 		AB9540_MODEM_CTRL2_REG, &value);
949*4882a593Smuzhiyun 	if (ret < 0)
950*4882a593Smuzhiyun 		return ret;
951*4882a593Smuzhiyun 
952*4882a593Smuzhiyun 	return sprintf(buf, "%d\n",
953*4882a593Smuzhiyun 			(value & AB9540_MODEM_CTRL2_SWDBBRSTN_BIT) ? 1 : 0);
954*4882a593Smuzhiyun }
955*4882a593Smuzhiyun 
store_ab9540_dbbrstn(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)956*4882a593Smuzhiyun static ssize_t store_ab9540_dbbrstn(struct device *dev,
957*4882a593Smuzhiyun 	struct device_attribute *attr, const char *buf, size_t count)
958*4882a593Smuzhiyun {
959*4882a593Smuzhiyun 	struct ab8500 *ab8500;
960*4882a593Smuzhiyun 	int ret = count;
961*4882a593Smuzhiyun 	int err;
962*4882a593Smuzhiyun 	u8 bitvalues;
963*4882a593Smuzhiyun 
964*4882a593Smuzhiyun 	ab8500 = dev_get_drvdata(dev);
965*4882a593Smuzhiyun 
966*4882a593Smuzhiyun 	if (count > 0) {
967*4882a593Smuzhiyun 		switch (buf[0]) {
968*4882a593Smuzhiyun 		case '0':
969*4882a593Smuzhiyun 			bitvalues = 0;
970*4882a593Smuzhiyun 			break;
971*4882a593Smuzhiyun 		case '1':
972*4882a593Smuzhiyun 			bitvalues = AB9540_MODEM_CTRL2_SWDBBRSTN_BIT;
973*4882a593Smuzhiyun 			break;
974*4882a593Smuzhiyun 		default:
975*4882a593Smuzhiyun 			goto exit;
976*4882a593Smuzhiyun 		}
977*4882a593Smuzhiyun 
978*4882a593Smuzhiyun 		err = mask_and_set_register_interruptible(ab8500,
979*4882a593Smuzhiyun 			AB8500_REGU_CTRL2, AB9540_MODEM_CTRL2_REG,
980*4882a593Smuzhiyun 			AB9540_MODEM_CTRL2_SWDBBRSTN_BIT, bitvalues);
981*4882a593Smuzhiyun 		if (err)
982*4882a593Smuzhiyun 			dev_info(ab8500->dev,
983*4882a593Smuzhiyun 				"Failed to set DBBRSTN %c, err %#x\n",
984*4882a593Smuzhiyun 				buf[0], err);
985*4882a593Smuzhiyun 	}
986*4882a593Smuzhiyun 
987*4882a593Smuzhiyun exit:
988*4882a593Smuzhiyun 	return ret;
989*4882a593Smuzhiyun }
990*4882a593Smuzhiyun 
991*4882a593Smuzhiyun static DEVICE_ATTR(chip_id, S_IRUGO, show_chip_id, NULL);
992*4882a593Smuzhiyun static DEVICE_ATTR(switch_off_status, S_IRUGO, show_switch_off_status, NULL);
993*4882a593Smuzhiyun static DEVICE_ATTR(turn_on_status, S_IRUGO, show_turn_on_status, NULL);
994*4882a593Smuzhiyun static DEVICE_ATTR(turn_on_status_2, S_IRUGO, show_turn_on_status_2, NULL);
995*4882a593Smuzhiyun static DEVICE_ATTR(dbbrstn, S_IRUGO | S_IWUSR,
996*4882a593Smuzhiyun 			show_ab9540_dbbrstn, store_ab9540_dbbrstn);
997*4882a593Smuzhiyun 
998*4882a593Smuzhiyun static struct attribute *ab8500_sysfs_entries[] = {
999*4882a593Smuzhiyun 	&dev_attr_chip_id.attr,
1000*4882a593Smuzhiyun 	&dev_attr_switch_off_status.attr,
1001*4882a593Smuzhiyun 	&dev_attr_turn_on_status.attr,
1002*4882a593Smuzhiyun 	NULL,
1003*4882a593Smuzhiyun };
1004*4882a593Smuzhiyun 
1005*4882a593Smuzhiyun static struct attribute *ab8505_sysfs_entries[] = {
1006*4882a593Smuzhiyun 	&dev_attr_turn_on_status_2.attr,
1007*4882a593Smuzhiyun 	NULL,
1008*4882a593Smuzhiyun };
1009*4882a593Smuzhiyun 
1010*4882a593Smuzhiyun static struct attribute *ab9540_sysfs_entries[] = {
1011*4882a593Smuzhiyun 	&dev_attr_chip_id.attr,
1012*4882a593Smuzhiyun 	&dev_attr_switch_off_status.attr,
1013*4882a593Smuzhiyun 	&dev_attr_turn_on_status.attr,
1014*4882a593Smuzhiyun 	&dev_attr_dbbrstn.attr,
1015*4882a593Smuzhiyun 	NULL,
1016*4882a593Smuzhiyun };
1017*4882a593Smuzhiyun 
1018*4882a593Smuzhiyun static const struct attribute_group ab8500_attr_group = {
1019*4882a593Smuzhiyun 	.attrs	= ab8500_sysfs_entries,
1020*4882a593Smuzhiyun };
1021*4882a593Smuzhiyun 
1022*4882a593Smuzhiyun static const struct attribute_group ab8505_attr_group = {
1023*4882a593Smuzhiyun 	.attrs	= ab8505_sysfs_entries,
1024*4882a593Smuzhiyun };
1025*4882a593Smuzhiyun 
1026*4882a593Smuzhiyun static const struct attribute_group ab9540_attr_group = {
1027*4882a593Smuzhiyun 	.attrs	= ab9540_sysfs_entries,
1028*4882a593Smuzhiyun };
1029*4882a593Smuzhiyun 
ab8500_probe(struct platform_device * pdev)1030*4882a593Smuzhiyun static int ab8500_probe(struct platform_device *pdev)
1031*4882a593Smuzhiyun {
1032*4882a593Smuzhiyun 	static const char * const switch_off_status[] = {
1033*4882a593Smuzhiyun 		"Swoff bit programming",
1034*4882a593Smuzhiyun 		"Thermal protection activation",
1035*4882a593Smuzhiyun 		"Vbat lower then BattOk falling threshold",
1036*4882a593Smuzhiyun 		"Watchdog expired",
1037*4882a593Smuzhiyun 		"Non presence of 32kHz clock",
1038*4882a593Smuzhiyun 		"Battery level lower than power on reset threshold",
1039*4882a593Smuzhiyun 		"Power on key 1 pressed longer than 10 seconds",
1040*4882a593Smuzhiyun 		"DB8500 thermal shutdown"};
1041*4882a593Smuzhiyun 	static const char * const turn_on_status[] = {
1042*4882a593Smuzhiyun 		"Battery rising (Vbat)",
1043*4882a593Smuzhiyun 		"Power On Key 1 dbF",
1044*4882a593Smuzhiyun 		"Power On Key 2 dbF",
1045*4882a593Smuzhiyun 		"RTC Alarm",
1046*4882a593Smuzhiyun 		"Main Charger Detect",
1047*4882a593Smuzhiyun 		"Vbus Detect (USB)",
1048*4882a593Smuzhiyun 		"USB ID Detect",
1049*4882a593Smuzhiyun 		"UART Factory Mode Detect"};
1050*4882a593Smuzhiyun 	const struct platform_device_id *platid = platform_get_device_id(pdev);
1051*4882a593Smuzhiyun 	enum ab8500_version version = AB8500_VERSION_UNDEFINED;
1052*4882a593Smuzhiyun 	struct device_node *np = pdev->dev.of_node;
1053*4882a593Smuzhiyun 	struct ab8500 *ab8500;
1054*4882a593Smuzhiyun 	struct resource *resource;
1055*4882a593Smuzhiyun 	int ret;
1056*4882a593Smuzhiyun 	int i;
1057*4882a593Smuzhiyun 	u8 value;
1058*4882a593Smuzhiyun 
1059*4882a593Smuzhiyun 	ab8500 = devm_kzalloc(&pdev->dev, sizeof(*ab8500), GFP_KERNEL);
1060*4882a593Smuzhiyun 	if (!ab8500)
1061*4882a593Smuzhiyun 		return -ENOMEM;
1062*4882a593Smuzhiyun 
1063*4882a593Smuzhiyun 	ab8500->dev = &pdev->dev;
1064*4882a593Smuzhiyun 
1065*4882a593Smuzhiyun 	resource = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1066*4882a593Smuzhiyun 	if (!resource) {
1067*4882a593Smuzhiyun 		dev_err(&pdev->dev, "no IRQ resource\n");
1068*4882a593Smuzhiyun 		return -ENODEV;
1069*4882a593Smuzhiyun 	}
1070*4882a593Smuzhiyun 
1071*4882a593Smuzhiyun 	ab8500->irq = resource->start;
1072*4882a593Smuzhiyun 
1073*4882a593Smuzhiyun 	ab8500->read = ab8500_prcmu_read;
1074*4882a593Smuzhiyun 	ab8500->write = ab8500_prcmu_write;
1075*4882a593Smuzhiyun 	ab8500->write_masked = ab8500_prcmu_write_masked;
1076*4882a593Smuzhiyun 
1077*4882a593Smuzhiyun 	mutex_init(&ab8500->lock);
1078*4882a593Smuzhiyun 	mutex_init(&ab8500->irq_lock);
1079*4882a593Smuzhiyun 	atomic_set(&ab8500->transfer_ongoing, 0);
1080*4882a593Smuzhiyun 
1081*4882a593Smuzhiyun 	platform_set_drvdata(pdev, ab8500);
1082*4882a593Smuzhiyun 
1083*4882a593Smuzhiyun 	if (platid)
1084*4882a593Smuzhiyun 		version = platid->driver_data;
1085*4882a593Smuzhiyun 
1086*4882a593Smuzhiyun 	if (version != AB8500_VERSION_UNDEFINED)
1087*4882a593Smuzhiyun 		ab8500->version = version;
1088*4882a593Smuzhiyun 	else {
1089*4882a593Smuzhiyun 		ret = get_register_interruptible(ab8500, AB8500_MISC,
1090*4882a593Smuzhiyun 			AB8500_IC_NAME_REG, &value);
1091*4882a593Smuzhiyun 		if (ret < 0) {
1092*4882a593Smuzhiyun 			dev_err(&pdev->dev, "could not probe HW\n");
1093*4882a593Smuzhiyun 			return ret;
1094*4882a593Smuzhiyun 		}
1095*4882a593Smuzhiyun 
1096*4882a593Smuzhiyun 		ab8500->version = value;
1097*4882a593Smuzhiyun 	}
1098*4882a593Smuzhiyun 
1099*4882a593Smuzhiyun 	ret = get_register_interruptible(ab8500, AB8500_MISC,
1100*4882a593Smuzhiyun 		AB8500_REV_REG, &value);
1101*4882a593Smuzhiyun 	if (ret < 0)
1102*4882a593Smuzhiyun 		return ret;
1103*4882a593Smuzhiyun 
1104*4882a593Smuzhiyun 	ab8500->chip_id = value;
1105*4882a593Smuzhiyun 
1106*4882a593Smuzhiyun 	dev_info(ab8500->dev, "detected chip, %s rev. %1x.%1x\n",
1107*4882a593Smuzhiyun 			ab8500_version_str[ab8500->version],
1108*4882a593Smuzhiyun 			ab8500->chip_id >> 4,
1109*4882a593Smuzhiyun 			ab8500->chip_id & 0x0F);
1110*4882a593Smuzhiyun 
1111*4882a593Smuzhiyun 	/* Configure AB8540 */
1112*4882a593Smuzhiyun 	if (is_ab8540(ab8500)) {
1113*4882a593Smuzhiyun 		ab8500->mask_size = AB8540_NUM_IRQ_REGS;
1114*4882a593Smuzhiyun 		ab8500->irq_reg_offset = ab8540_irq_regoffset;
1115*4882a593Smuzhiyun 		ab8500->it_latchhier_num = AB8540_IT_LATCHHIER_NUM;
1116*4882a593Smuzhiyun 	} /* Configure AB8500 or AB9540 IRQ */
1117*4882a593Smuzhiyun 	else if (is_ab9540(ab8500) || is_ab8505(ab8500)) {
1118*4882a593Smuzhiyun 		ab8500->mask_size = AB9540_NUM_IRQ_REGS;
1119*4882a593Smuzhiyun 		ab8500->irq_reg_offset = ab9540_irq_regoffset;
1120*4882a593Smuzhiyun 		ab8500->it_latchhier_num = AB8500_IT_LATCHHIER_NUM;
1121*4882a593Smuzhiyun 	} else {
1122*4882a593Smuzhiyun 		ab8500->mask_size = AB8500_NUM_IRQ_REGS;
1123*4882a593Smuzhiyun 		ab8500->irq_reg_offset = ab8500_irq_regoffset;
1124*4882a593Smuzhiyun 		ab8500->it_latchhier_num = AB8500_IT_LATCHHIER_NUM;
1125*4882a593Smuzhiyun 	}
1126*4882a593Smuzhiyun 	ab8500->mask = devm_kzalloc(&pdev->dev, ab8500->mask_size,
1127*4882a593Smuzhiyun 				    GFP_KERNEL);
1128*4882a593Smuzhiyun 	if (!ab8500->mask)
1129*4882a593Smuzhiyun 		return -ENOMEM;
1130*4882a593Smuzhiyun 	ab8500->oldmask = devm_kzalloc(&pdev->dev, ab8500->mask_size,
1131*4882a593Smuzhiyun 				       GFP_KERNEL);
1132*4882a593Smuzhiyun 	if (!ab8500->oldmask)
1133*4882a593Smuzhiyun 		return -ENOMEM;
1134*4882a593Smuzhiyun 
1135*4882a593Smuzhiyun 	/*
1136*4882a593Smuzhiyun 	 * ab8500 has switched off due to (SWITCH_OFF_STATUS):
1137*4882a593Smuzhiyun 	 * 0x01 Swoff bit programming
1138*4882a593Smuzhiyun 	 * 0x02 Thermal protection activation
1139*4882a593Smuzhiyun 	 * 0x04 Vbat lower then BattOk falling threshold
1140*4882a593Smuzhiyun 	 * 0x08 Watchdog expired
1141*4882a593Smuzhiyun 	 * 0x10 Non presence of 32kHz clock
1142*4882a593Smuzhiyun 	 * 0x20 Battery level lower than power on reset threshold
1143*4882a593Smuzhiyun 	 * 0x40 Power on key 1 pressed longer than 10 seconds
1144*4882a593Smuzhiyun 	 * 0x80 DB8500 thermal shutdown
1145*4882a593Smuzhiyun 	 */
1146*4882a593Smuzhiyun 
1147*4882a593Smuzhiyun 	ret = get_register_interruptible(ab8500, AB8500_RTC,
1148*4882a593Smuzhiyun 		AB8500_SWITCH_OFF_STATUS, &value);
1149*4882a593Smuzhiyun 	if (ret < 0)
1150*4882a593Smuzhiyun 		return ret;
1151*4882a593Smuzhiyun 	dev_info(ab8500->dev, "switch off cause(s) (%#x): ", value);
1152*4882a593Smuzhiyun 
1153*4882a593Smuzhiyun 	if (value) {
1154*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(switch_off_status); i++) {
1155*4882a593Smuzhiyun 			if (value & 1)
1156*4882a593Smuzhiyun 				pr_cont(" \"%s\"", switch_off_status[i]);
1157*4882a593Smuzhiyun 			value = value >> 1;
1158*4882a593Smuzhiyun 
1159*4882a593Smuzhiyun 		}
1160*4882a593Smuzhiyun 		pr_cont("\n");
1161*4882a593Smuzhiyun 	} else {
1162*4882a593Smuzhiyun 		pr_cont(" None\n");
1163*4882a593Smuzhiyun 	}
1164*4882a593Smuzhiyun 	ret = get_register_interruptible(ab8500, AB8500_SYS_CTRL1_BLOCK,
1165*4882a593Smuzhiyun 		AB8500_TURN_ON_STATUS, &value);
1166*4882a593Smuzhiyun 	if (ret < 0)
1167*4882a593Smuzhiyun 		return ret;
1168*4882a593Smuzhiyun 	dev_info(ab8500->dev, "turn on reason(s) (%#x): ", value);
1169*4882a593Smuzhiyun 
1170*4882a593Smuzhiyun 	if (value) {
1171*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(turn_on_status); i++) {
1172*4882a593Smuzhiyun 			if (value & 1)
1173*4882a593Smuzhiyun 				pr_cont("\"%s\" ", turn_on_status[i]);
1174*4882a593Smuzhiyun 			value = value >> 1;
1175*4882a593Smuzhiyun 		}
1176*4882a593Smuzhiyun 		pr_cont("\n");
1177*4882a593Smuzhiyun 	} else {
1178*4882a593Smuzhiyun 		pr_cont("None\n");
1179*4882a593Smuzhiyun 	}
1180*4882a593Smuzhiyun 
1181*4882a593Smuzhiyun 	if (is_ab9540(ab8500)) {
1182*4882a593Smuzhiyun 		ret = get_register_interruptible(ab8500, AB8500_CHARGER,
1183*4882a593Smuzhiyun 			AB8500_CH_USBCH_STAT1_REG, &value);
1184*4882a593Smuzhiyun 		if (ret < 0)
1185*4882a593Smuzhiyun 			return ret;
1186*4882a593Smuzhiyun 		if ((value & VBUS_DET_DBNC1) && (value & VBUS_DET_DBNC100))
1187*4882a593Smuzhiyun 			ab8500_override_turn_on_stat(~AB8500_POW_KEY_1_ON,
1188*4882a593Smuzhiyun 						     AB8500_VBUS_DET);
1189*4882a593Smuzhiyun 	}
1190*4882a593Smuzhiyun 
1191*4882a593Smuzhiyun 	/* Clear and mask all interrupts */
1192*4882a593Smuzhiyun 	for (i = 0; i < ab8500->mask_size; i++) {
1193*4882a593Smuzhiyun 		/*
1194*4882a593Smuzhiyun 		 * Interrupt register 12 doesn't exist prior to AB8500 version
1195*4882a593Smuzhiyun 		 * 2.0
1196*4882a593Smuzhiyun 		 */
1197*4882a593Smuzhiyun 		if (ab8500->irq_reg_offset[i] == 11 &&
1198*4882a593Smuzhiyun 				is_ab8500_1p1_or_earlier(ab8500))
1199*4882a593Smuzhiyun 			continue;
1200*4882a593Smuzhiyun 
1201*4882a593Smuzhiyun 		if (ab8500->irq_reg_offset[i] < 0)
1202*4882a593Smuzhiyun 			continue;
1203*4882a593Smuzhiyun 
1204*4882a593Smuzhiyun 		get_register_interruptible(ab8500, AB8500_INTERRUPT,
1205*4882a593Smuzhiyun 			AB8500_IT_LATCH1_REG + ab8500->irq_reg_offset[i],
1206*4882a593Smuzhiyun 			&value);
1207*4882a593Smuzhiyun 		set_register_interruptible(ab8500, AB8500_INTERRUPT,
1208*4882a593Smuzhiyun 			AB8500_IT_MASK1_REG + ab8500->irq_reg_offset[i], 0xff);
1209*4882a593Smuzhiyun 	}
1210*4882a593Smuzhiyun 
1211*4882a593Smuzhiyun 	ret = abx500_register_ops(ab8500->dev, &ab8500_ops);
1212*4882a593Smuzhiyun 	if (ret)
1213*4882a593Smuzhiyun 		return ret;
1214*4882a593Smuzhiyun 
1215*4882a593Smuzhiyun 	for (i = 0; i < ab8500->mask_size; i++)
1216*4882a593Smuzhiyun 		ab8500->mask[i] = ab8500->oldmask[i] = 0xff;
1217*4882a593Smuzhiyun 
1218*4882a593Smuzhiyun 	ret = ab8500_irq_init(ab8500, np);
1219*4882a593Smuzhiyun 	if (ret)
1220*4882a593Smuzhiyun 		return ret;
1221*4882a593Smuzhiyun 
1222*4882a593Smuzhiyun 	ret = devm_request_threaded_irq(&pdev->dev, ab8500->irq, NULL,
1223*4882a593Smuzhiyun 			ab8500_hierarchical_irq,
1224*4882a593Smuzhiyun 			IRQF_ONESHOT | IRQF_NO_SUSPEND,
1225*4882a593Smuzhiyun 			"ab8500", ab8500);
1226*4882a593Smuzhiyun 	if (ret)
1227*4882a593Smuzhiyun 		return ret;
1228*4882a593Smuzhiyun 
1229*4882a593Smuzhiyun 	if (is_ab9540(ab8500))
1230*4882a593Smuzhiyun 		ret = mfd_add_devices(ab8500->dev, 0, ab9540_devs,
1231*4882a593Smuzhiyun 				ARRAY_SIZE(ab9540_devs), NULL,
1232*4882a593Smuzhiyun 				0, ab8500->domain);
1233*4882a593Smuzhiyun 	else if (is_ab8540(ab8500)) {
1234*4882a593Smuzhiyun 		ret = mfd_add_devices(ab8500->dev, 0, ab8540_devs,
1235*4882a593Smuzhiyun 			      ARRAY_SIZE(ab8540_devs), NULL,
1236*4882a593Smuzhiyun 			      0, ab8500->domain);
1237*4882a593Smuzhiyun 		if (ret)
1238*4882a593Smuzhiyun 			return ret;
1239*4882a593Smuzhiyun 
1240*4882a593Smuzhiyun 		if (is_ab8540_1p2_or_earlier(ab8500))
1241*4882a593Smuzhiyun 			ret = mfd_add_devices(ab8500->dev, 0, ab8540_cut1_devs,
1242*4882a593Smuzhiyun 			      ARRAY_SIZE(ab8540_cut1_devs), NULL,
1243*4882a593Smuzhiyun 			      0, ab8500->domain);
1244*4882a593Smuzhiyun 		else /* ab8540 >= cut2 */
1245*4882a593Smuzhiyun 			ret = mfd_add_devices(ab8500->dev, 0, ab8540_cut2_devs,
1246*4882a593Smuzhiyun 			      ARRAY_SIZE(ab8540_cut2_devs), NULL,
1247*4882a593Smuzhiyun 			      0, ab8500->domain);
1248*4882a593Smuzhiyun 	} else if (is_ab8505(ab8500))
1249*4882a593Smuzhiyun 		ret = mfd_add_devices(ab8500->dev, 0, ab8505_devs,
1250*4882a593Smuzhiyun 			      ARRAY_SIZE(ab8505_devs), NULL,
1251*4882a593Smuzhiyun 			      0, ab8500->domain);
1252*4882a593Smuzhiyun 	else
1253*4882a593Smuzhiyun 		ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs,
1254*4882a593Smuzhiyun 				ARRAY_SIZE(ab8500_devs), NULL,
1255*4882a593Smuzhiyun 				0, ab8500->domain);
1256*4882a593Smuzhiyun 	if (ret)
1257*4882a593Smuzhiyun 		return ret;
1258*4882a593Smuzhiyun 
1259*4882a593Smuzhiyun 	if (!no_bm) {
1260*4882a593Smuzhiyun 		/* Add battery management devices */
1261*4882a593Smuzhiyun 		ret = mfd_add_devices(ab8500->dev, 0, ab8500_bm_devs,
1262*4882a593Smuzhiyun 				      ARRAY_SIZE(ab8500_bm_devs), NULL,
1263*4882a593Smuzhiyun 				      0, ab8500->domain);
1264*4882a593Smuzhiyun 		if (ret)
1265*4882a593Smuzhiyun 			dev_err(ab8500->dev, "error adding bm devices\n");
1266*4882a593Smuzhiyun 	}
1267*4882a593Smuzhiyun 
1268*4882a593Smuzhiyun 	if (((is_ab8505(ab8500) || is_ab9540(ab8500)) &&
1269*4882a593Smuzhiyun 			ab8500->chip_id >= AB8500_CUT2P0) || is_ab8540(ab8500))
1270*4882a593Smuzhiyun 		ret = sysfs_create_group(&ab8500->dev->kobj,
1271*4882a593Smuzhiyun 					&ab9540_attr_group);
1272*4882a593Smuzhiyun 	else
1273*4882a593Smuzhiyun 		ret = sysfs_create_group(&ab8500->dev->kobj,
1274*4882a593Smuzhiyun 					&ab8500_attr_group);
1275*4882a593Smuzhiyun 
1276*4882a593Smuzhiyun 	if ((is_ab8505(ab8500) || is_ab9540(ab8500)) &&
1277*4882a593Smuzhiyun 			ab8500->chip_id >= AB8500_CUT2P0)
1278*4882a593Smuzhiyun 		ret = sysfs_create_group(&ab8500->dev->kobj,
1279*4882a593Smuzhiyun 					 &ab8505_attr_group);
1280*4882a593Smuzhiyun 
1281*4882a593Smuzhiyun 	if (ret)
1282*4882a593Smuzhiyun 		dev_err(ab8500->dev, "error creating sysfs entries\n");
1283*4882a593Smuzhiyun 
1284*4882a593Smuzhiyun 	return ret;
1285*4882a593Smuzhiyun }
1286*4882a593Smuzhiyun 
1287*4882a593Smuzhiyun static const struct platform_device_id ab8500_id[] = {
1288*4882a593Smuzhiyun 	{ "ab8500-core", AB8500_VERSION_AB8500 },
1289*4882a593Smuzhiyun 	{ "ab8505-core", AB8500_VERSION_AB8505 },
1290*4882a593Smuzhiyun 	{ "ab9540-i2c", AB8500_VERSION_AB9540 },
1291*4882a593Smuzhiyun 	{ "ab8540-i2c", AB8500_VERSION_AB8540 },
1292*4882a593Smuzhiyun 	{ }
1293*4882a593Smuzhiyun };
1294*4882a593Smuzhiyun 
1295*4882a593Smuzhiyun static struct platform_driver ab8500_core_driver = {
1296*4882a593Smuzhiyun 	.driver = {
1297*4882a593Smuzhiyun 		.name = "ab8500-core",
1298*4882a593Smuzhiyun 		.suppress_bind_attrs = true,
1299*4882a593Smuzhiyun 	},
1300*4882a593Smuzhiyun 	.probe	= ab8500_probe,
1301*4882a593Smuzhiyun 	.id_table = ab8500_id,
1302*4882a593Smuzhiyun };
1303*4882a593Smuzhiyun 
ab8500_core_init(void)1304*4882a593Smuzhiyun static int __init ab8500_core_init(void)
1305*4882a593Smuzhiyun {
1306*4882a593Smuzhiyun 	return platform_driver_register(&ab8500_core_driver);
1307*4882a593Smuzhiyun }
1308*4882a593Smuzhiyun core_initcall(ab8500_core_init);
1309