xref: /OK3568_Linux_fs/kernel/drivers/mfd/88pm805.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Base driver for Marvell 88PM805
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright (C) 2012 Marvell International Ltd.
5*4882a593Smuzhiyun  * Haojian Zhuang <haojian.zhuang@marvell.com>
6*4882a593Smuzhiyun  * Joseph(Yossi) Hanin <yhanin@marvell.com>
7*4882a593Smuzhiyun  * Qiao Zhou <zhouqiao@marvell.com>
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This file is subject to the terms and conditions of the GNU General
10*4882a593Smuzhiyun  * Public License. See the file "COPYING" in the main directory of this
11*4882a593Smuzhiyun  * archive for more details.
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful,
14*4882a593Smuzhiyun  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15*4882a593Smuzhiyun  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16*4882a593Smuzhiyun  * GNU General Public License for more details.
17*4882a593Smuzhiyun  *
18*4882a593Smuzhiyun  * You should have received a copy of the GNU General Public License
19*4882a593Smuzhiyun  * along with this program; if not, write to the Free Software
20*4882a593Smuzhiyun  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21*4882a593Smuzhiyun  */
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #include <linux/kernel.h>
24*4882a593Smuzhiyun #include <linux/module.h>
25*4882a593Smuzhiyun #include <linux/i2c.h>
26*4882a593Smuzhiyun #include <linux/irq.h>
27*4882a593Smuzhiyun #include <linux/mfd/core.h>
28*4882a593Smuzhiyun #include <linux/mfd/88pm80x.h>
29*4882a593Smuzhiyun #include <linux/slab.h>
30*4882a593Smuzhiyun #include <linux/delay.h>
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun static const struct i2c_device_id pm80x_id_table[] = {
33*4882a593Smuzhiyun 	{"88PM805", 0},
34*4882a593Smuzhiyun 	{} /* NULL terminated */
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, pm80x_id_table);
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun /* Interrupt Number in 88PM805 */
39*4882a593Smuzhiyun enum {
40*4882a593Smuzhiyun 	PM805_IRQ_LDO_OFF,	/*0 */
41*4882a593Smuzhiyun 	PM805_IRQ_SRC_DPLL_LOCK,	/*1 */
42*4882a593Smuzhiyun 	PM805_IRQ_CLIP_FAULT,
43*4882a593Smuzhiyun 	PM805_IRQ_MIC_CONFLICT,
44*4882a593Smuzhiyun 	PM805_IRQ_HP2_SHRT,
45*4882a593Smuzhiyun 	PM805_IRQ_HP1_SHRT,	/*5 */
46*4882a593Smuzhiyun 	PM805_IRQ_FINE_PLL_FAULT,
47*4882a593Smuzhiyun 	PM805_IRQ_RAW_PLL_FAULT,
48*4882a593Smuzhiyun 	PM805_IRQ_VOLP_BTN_DET,
49*4882a593Smuzhiyun 	PM805_IRQ_VOLM_BTN_DET,
50*4882a593Smuzhiyun 	PM805_IRQ_SHRT_BTN_DET,	/*10 */
51*4882a593Smuzhiyun 	PM805_IRQ_MIC_DET,	/*11 */
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 	PM805_MAX_IRQ,
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun static struct resource codec_resources[] = {
57*4882a593Smuzhiyun 	{
58*4882a593Smuzhiyun 	 /* Headset microphone insertion or removal */
59*4882a593Smuzhiyun 	 .name = "micin",
60*4882a593Smuzhiyun 	 .start = PM805_IRQ_MIC_DET,
61*4882a593Smuzhiyun 	 .end = PM805_IRQ_MIC_DET,
62*4882a593Smuzhiyun 	 .flags = IORESOURCE_IRQ,
63*4882a593Smuzhiyun 	 },
64*4882a593Smuzhiyun 	{
65*4882a593Smuzhiyun 	 /* Audio short HP1 */
66*4882a593Smuzhiyun 	 .name = "audio-short1",
67*4882a593Smuzhiyun 	 .start = PM805_IRQ_HP1_SHRT,
68*4882a593Smuzhiyun 	 .end = PM805_IRQ_HP1_SHRT,
69*4882a593Smuzhiyun 	 .flags = IORESOURCE_IRQ,
70*4882a593Smuzhiyun 	 },
71*4882a593Smuzhiyun 	{
72*4882a593Smuzhiyun 	 /* Audio short HP2 */
73*4882a593Smuzhiyun 	 .name = "audio-short2",
74*4882a593Smuzhiyun 	 .start = PM805_IRQ_HP2_SHRT,
75*4882a593Smuzhiyun 	 .end = PM805_IRQ_HP2_SHRT,
76*4882a593Smuzhiyun 	 .flags = IORESOURCE_IRQ,
77*4882a593Smuzhiyun 	 },
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun static const struct mfd_cell codec_devs[] = {
81*4882a593Smuzhiyun 	{
82*4882a593Smuzhiyun 	 .name = "88pm80x-codec",
83*4882a593Smuzhiyun 	 .num_resources = ARRAY_SIZE(codec_resources),
84*4882a593Smuzhiyun 	 .resources = &codec_resources[0],
85*4882a593Smuzhiyun 	 .id = -1,
86*4882a593Smuzhiyun 	 },
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun static struct regmap_irq pm805_irqs[] = {
90*4882a593Smuzhiyun 	/* INT0 */
91*4882a593Smuzhiyun 	[PM805_IRQ_LDO_OFF] = {
92*4882a593Smuzhiyun 		.mask = PM805_INT1_HP1_SHRT,
93*4882a593Smuzhiyun 	},
94*4882a593Smuzhiyun 	[PM805_IRQ_SRC_DPLL_LOCK] = {
95*4882a593Smuzhiyun 		.mask = PM805_INT1_HP2_SHRT,
96*4882a593Smuzhiyun 	},
97*4882a593Smuzhiyun 	[PM805_IRQ_CLIP_FAULT] = {
98*4882a593Smuzhiyun 		.mask = PM805_INT1_MIC_CONFLICT,
99*4882a593Smuzhiyun 	},
100*4882a593Smuzhiyun 	[PM805_IRQ_MIC_CONFLICT] = {
101*4882a593Smuzhiyun 		.mask = PM805_INT1_CLIP_FAULT,
102*4882a593Smuzhiyun 	},
103*4882a593Smuzhiyun 	[PM805_IRQ_HP2_SHRT] = {
104*4882a593Smuzhiyun 		.mask = PM805_INT1_LDO_OFF,
105*4882a593Smuzhiyun 	},
106*4882a593Smuzhiyun 	[PM805_IRQ_HP1_SHRT] = {
107*4882a593Smuzhiyun 		.mask = PM805_INT1_SRC_DPLL_LOCK,
108*4882a593Smuzhiyun 	},
109*4882a593Smuzhiyun 	/* INT1 */
110*4882a593Smuzhiyun 	[PM805_IRQ_FINE_PLL_FAULT] = {
111*4882a593Smuzhiyun 		.reg_offset = 1,
112*4882a593Smuzhiyun 		.mask = PM805_INT2_MIC_DET,
113*4882a593Smuzhiyun 	},
114*4882a593Smuzhiyun 	[PM805_IRQ_RAW_PLL_FAULT] = {
115*4882a593Smuzhiyun 		.reg_offset = 1,
116*4882a593Smuzhiyun 		.mask = PM805_INT2_SHRT_BTN_DET,
117*4882a593Smuzhiyun 	},
118*4882a593Smuzhiyun 	[PM805_IRQ_VOLP_BTN_DET] = {
119*4882a593Smuzhiyun 		.reg_offset = 1,
120*4882a593Smuzhiyun 		.mask = PM805_INT2_VOLM_BTN_DET,
121*4882a593Smuzhiyun 	},
122*4882a593Smuzhiyun 	[PM805_IRQ_VOLM_BTN_DET] = {
123*4882a593Smuzhiyun 		.reg_offset = 1,
124*4882a593Smuzhiyun 		.mask = PM805_INT2_VOLP_BTN_DET,
125*4882a593Smuzhiyun 	},
126*4882a593Smuzhiyun 	[PM805_IRQ_SHRT_BTN_DET] = {
127*4882a593Smuzhiyun 		.reg_offset = 1,
128*4882a593Smuzhiyun 		.mask = PM805_INT2_RAW_PLL_FAULT,
129*4882a593Smuzhiyun 	},
130*4882a593Smuzhiyun 	[PM805_IRQ_MIC_DET] = {
131*4882a593Smuzhiyun 		.reg_offset = 1,
132*4882a593Smuzhiyun 		.mask = PM805_INT2_FINE_PLL_FAULT,
133*4882a593Smuzhiyun 	},
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun 
device_irq_init_805(struct pm80x_chip * chip)136*4882a593Smuzhiyun static int device_irq_init_805(struct pm80x_chip *chip)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun 	struct regmap *map = chip->regmap;
139*4882a593Smuzhiyun 	unsigned long flags = IRQF_ONESHOT;
140*4882a593Smuzhiyun 	int data, mask, ret = -EINVAL;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	if (!map || !chip->irq) {
143*4882a593Smuzhiyun 		dev_err(chip->dev, "incorrect parameters\n");
144*4882a593Smuzhiyun 		return -EINVAL;
145*4882a593Smuzhiyun 	}
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	/*
148*4882a593Smuzhiyun 	 * irq_mode defines the way of clearing interrupt. it's read-clear by
149*4882a593Smuzhiyun 	 * default.
150*4882a593Smuzhiyun 	 */
151*4882a593Smuzhiyun 	mask =
152*4882a593Smuzhiyun 	    PM805_STATUS0_INT_CLEAR | PM805_STATUS0_INV_INT |
153*4882a593Smuzhiyun 	    PM800_STATUS0_INT_MASK;
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	data = PM805_STATUS0_INT_CLEAR;
156*4882a593Smuzhiyun 	ret = regmap_update_bits(map, PM805_INT_STATUS0, mask, data);
157*4882a593Smuzhiyun 	/*
158*4882a593Smuzhiyun 	 * PM805_INT_STATUS is under 32K clock domain, so need to
159*4882a593Smuzhiyun 	 * add proper delay before the next I2C register access.
160*4882a593Smuzhiyun 	 */
161*4882a593Smuzhiyun 	usleep_range(1000, 3000);
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	if (ret < 0)
164*4882a593Smuzhiyun 		goto out;
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	ret =
167*4882a593Smuzhiyun 	    regmap_add_irq_chip(chip->regmap, chip->irq, flags, -1,
168*4882a593Smuzhiyun 				chip->regmap_irq_chip, &chip->irq_data);
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun out:
171*4882a593Smuzhiyun 	return ret;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun 
device_irq_exit_805(struct pm80x_chip * chip)174*4882a593Smuzhiyun static void device_irq_exit_805(struct pm80x_chip *chip)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun 	regmap_del_irq_chip(chip->irq, chip->irq_data);
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun static struct regmap_irq_chip pm805_irq_chip = {
180*4882a593Smuzhiyun 	.name = "88pm805",
181*4882a593Smuzhiyun 	.irqs = pm805_irqs,
182*4882a593Smuzhiyun 	.num_irqs = ARRAY_SIZE(pm805_irqs),
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	.num_regs = 2,
185*4882a593Smuzhiyun 	.status_base = PM805_INT_STATUS1,
186*4882a593Smuzhiyun 	.mask_base = PM805_INT_MASK1,
187*4882a593Smuzhiyun 	.ack_base = PM805_INT_STATUS1,
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun 
device_805_init(struct pm80x_chip * chip)190*4882a593Smuzhiyun static int device_805_init(struct pm80x_chip *chip)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun 	int ret = 0;
193*4882a593Smuzhiyun 	struct regmap *map = chip->regmap;
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	if (!map) {
196*4882a593Smuzhiyun 		dev_err(chip->dev, "regmap is invalid\n");
197*4882a593Smuzhiyun 		return -EINVAL;
198*4882a593Smuzhiyun 	}
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	chip->regmap_irq_chip = &pm805_irq_chip;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	ret = device_irq_init_805(chip);
203*4882a593Smuzhiyun 	if (ret < 0) {
204*4882a593Smuzhiyun 		dev_err(chip->dev, "Failed to init pm805 irq!\n");
205*4882a593Smuzhiyun 		goto out_irq_init;
206*4882a593Smuzhiyun 	}
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	ret = mfd_add_devices(chip->dev, 0, &codec_devs[0],
209*4882a593Smuzhiyun 			      ARRAY_SIZE(codec_devs), &codec_resources[0], 0,
210*4882a593Smuzhiyun 			      NULL);
211*4882a593Smuzhiyun 	if (ret < 0) {
212*4882a593Smuzhiyun 		dev_err(chip->dev, "Failed to add codec subdev\n");
213*4882a593Smuzhiyun 		goto out_codec;
214*4882a593Smuzhiyun 	} else
215*4882a593Smuzhiyun 		dev_info(chip->dev, "[%s]:Added mfd codec_devs\n", __func__);
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	return 0;
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun out_codec:
220*4882a593Smuzhiyun 	device_irq_exit_805(chip);
221*4882a593Smuzhiyun out_irq_init:
222*4882a593Smuzhiyun 	return ret;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun 
pm805_probe(struct i2c_client * client,const struct i2c_device_id * id)225*4882a593Smuzhiyun static int pm805_probe(struct i2c_client *client,
226*4882a593Smuzhiyun 				 const struct i2c_device_id *id)
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun 	int ret = 0;
229*4882a593Smuzhiyun 	struct pm80x_chip *chip;
230*4882a593Smuzhiyun 	struct pm80x_platform_data *pdata = dev_get_platdata(&client->dev);
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	ret = pm80x_init(client);
233*4882a593Smuzhiyun 	if (ret) {
234*4882a593Smuzhiyun 		dev_err(&client->dev, "pm805_init fail!\n");
235*4882a593Smuzhiyun 		goto out_init;
236*4882a593Smuzhiyun 	}
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	chip = i2c_get_clientdata(client);
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	ret = device_805_init(chip);
241*4882a593Smuzhiyun 	if (ret) {
242*4882a593Smuzhiyun 		dev_err(chip->dev, "Failed to initialize 88pm805 devices\n");
243*4882a593Smuzhiyun 		goto err_805_init;
244*4882a593Smuzhiyun 	}
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	if (pdata && pdata->plat_config)
247*4882a593Smuzhiyun 		pdata->plat_config(chip, pdata);
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun err_805_init:
250*4882a593Smuzhiyun 	pm80x_deinit();
251*4882a593Smuzhiyun out_init:
252*4882a593Smuzhiyun 	return ret;
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun 
pm805_remove(struct i2c_client * client)255*4882a593Smuzhiyun static int pm805_remove(struct i2c_client *client)
256*4882a593Smuzhiyun {
257*4882a593Smuzhiyun 	struct pm80x_chip *chip = i2c_get_clientdata(client);
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	mfd_remove_devices(chip->dev);
260*4882a593Smuzhiyun 	device_irq_exit_805(chip);
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	pm80x_deinit();
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	return 0;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun static struct i2c_driver pm805_driver = {
268*4882a593Smuzhiyun 	.driver = {
269*4882a593Smuzhiyun 		.name = "88PM805",
270*4882a593Smuzhiyun 		.pm = &pm80x_pm_ops,
271*4882a593Smuzhiyun 		},
272*4882a593Smuzhiyun 	.probe = pm805_probe,
273*4882a593Smuzhiyun 	.remove = pm805_remove,
274*4882a593Smuzhiyun 	.id_table = pm80x_id_table,
275*4882a593Smuzhiyun };
276*4882a593Smuzhiyun 
pm805_i2c_init(void)277*4882a593Smuzhiyun static int __init pm805_i2c_init(void)
278*4882a593Smuzhiyun {
279*4882a593Smuzhiyun 	return i2c_add_driver(&pm805_driver);
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun subsys_initcall(pm805_i2c_init);
282*4882a593Smuzhiyun 
pm805_i2c_exit(void)283*4882a593Smuzhiyun static void __exit pm805_i2c_exit(void)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun 	i2c_del_driver(&pm805_driver);
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun module_exit(pm805_i2c_exit);
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM805");
290*4882a593Smuzhiyun MODULE_AUTHOR("Qiao Zhou <zhouqiao@marvell.com>");
291*4882a593Smuzhiyun MODULE_LICENSE("GPL");
292