1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Base driver for Marvell 88PM800
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2012 Marvell International Ltd.
5*4882a593Smuzhiyun * Haojian Zhuang <haojian.zhuang@marvell.com>
6*4882a593Smuzhiyun * Joseph(Yossi) Hanin <yhanin@marvell.com>
7*4882a593Smuzhiyun * Qiao Zhou <zhouqiao@marvell.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General
10*4882a593Smuzhiyun * Public License. See the file "COPYING" in the main directory of this
11*4882a593Smuzhiyun * archive for more details.
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful,
14*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of
15*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16*4882a593Smuzhiyun * GNU General Public License for more details.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License
19*4882a593Smuzhiyun * along with this program; if not, write to the Free Software
20*4882a593Smuzhiyun * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <linux/kernel.h>
24*4882a593Smuzhiyun #include <linux/module.h>
25*4882a593Smuzhiyun #include <linux/err.h>
26*4882a593Smuzhiyun #include <linux/i2c.h>
27*4882a593Smuzhiyun #include <linux/mfd/core.h>
28*4882a593Smuzhiyun #include <linux/mfd/88pm80x.h>
29*4882a593Smuzhiyun #include <linux/slab.h>
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Interrupt Registers */
32*4882a593Smuzhiyun #define PM800_INT_STATUS1 (0x05)
33*4882a593Smuzhiyun #define PM800_ONKEY_INT_STS1 (1 << 0)
34*4882a593Smuzhiyun #define PM800_EXTON_INT_STS1 (1 << 1)
35*4882a593Smuzhiyun #define PM800_CHG_INT_STS1 (1 << 2)
36*4882a593Smuzhiyun #define PM800_BAT_INT_STS1 (1 << 3)
37*4882a593Smuzhiyun #define PM800_RTC_INT_STS1 (1 << 4)
38*4882a593Smuzhiyun #define PM800_CLASSD_OC_INT_STS1 (1 << 5)
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define PM800_INT_STATUS2 (0x06)
41*4882a593Smuzhiyun #define PM800_VBAT_INT_STS2 (1 << 0)
42*4882a593Smuzhiyun #define PM800_VSYS_INT_STS2 (1 << 1)
43*4882a593Smuzhiyun #define PM800_VCHG_INT_STS2 (1 << 2)
44*4882a593Smuzhiyun #define PM800_TINT_INT_STS2 (1 << 3)
45*4882a593Smuzhiyun #define PM800_GPADC0_INT_STS2 (1 << 4)
46*4882a593Smuzhiyun #define PM800_TBAT_INT_STS2 (1 << 5)
47*4882a593Smuzhiyun #define PM800_GPADC2_INT_STS2 (1 << 6)
48*4882a593Smuzhiyun #define PM800_GPADC3_INT_STS2 (1 << 7)
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #define PM800_INT_STATUS3 (0x07)
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #define PM800_INT_STATUS4 (0x08)
53*4882a593Smuzhiyun #define PM800_GPIO0_INT_STS4 (1 << 0)
54*4882a593Smuzhiyun #define PM800_GPIO1_INT_STS4 (1 << 1)
55*4882a593Smuzhiyun #define PM800_GPIO2_INT_STS4 (1 << 2)
56*4882a593Smuzhiyun #define PM800_GPIO3_INT_STS4 (1 << 3)
57*4882a593Smuzhiyun #define PM800_GPIO4_INT_STS4 (1 << 4)
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #define PM800_INT_ENA_1 (0x09)
60*4882a593Smuzhiyun #define PM800_ONKEY_INT_ENA1 (1 << 0)
61*4882a593Smuzhiyun #define PM800_EXTON_INT_ENA1 (1 << 1)
62*4882a593Smuzhiyun #define PM800_CHG_INT_ENA1 (1 << 2)
63*4882a593Smuzhiyun #define PM800_BAT_INT_ENA1 (1 << 3)
64*4882a593Smuzhiyun #define PM800_RTC_INT_ENA1 (1 << 4)
65*4882a593Smuzhiyun #define PM800_CLASSD_OC_INT_ENA1 (1 << 5)
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #define PM800_INT_ENA_2 (0x0A)
68*4882a593Smuzhiyun #define PM800_VBAT_INT_ENA2 (1 << 0)
69*4882a593Smuzhiyun #define PM800_VSYS_INT_ENA2 (1 << 1)
70*4882a593Smuzhiyun #define PM800_VCHG_INT_ENA2 (1 << 2)
71*4882a593Smuzhiyun #define PM800_TINT_INT_ENA2 (1 << 3)
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun #define PM800_INT_ENA_3 (0x0B)
74*4882a593Smuzhiyun #define PM800_GPADC0_INT_ENA3 (1 << 0)
75*4882a593Smuzhiyun #define PM800_GPADC1_INT_ENA3 (1 << 1)
76*4882a593Smuzhiyun #define PM800_GPADC2_INT_ENA3 (1 << 2)
77*4882a593Smuzhiyun #define PM800_GPADC3_INT_ENA3 (1 << 3)
78*4882a593Smuzhiyun #define PM800_GPADC4_INT_ENA3 (1 << 4)
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun #define PM800_INT_ENA_4 (0x0C)
81*4882a593Smuzhiyun #define PM800_GPIO0_INT_ENA4 (1 << 0)
82*4882a593Smuzhiyun #define PM800_GPIO1_INT_ENA4 (1 << 1)
83*4882a593Smuzhiyun #define PM800_GPIO2_INT_ENA4 (1 << 2)
84*4882a593Smuzhiyun #define PM800_GPIO3_INT_ENA4 (1 << 3)
85*4882a593Smuzhiyun #define PM800_GPIO4_INT_ENA4 (1 << 4)
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* number of INT_ENA & INT_STATUS regs */
88*4882a593Smuzhiyun #define PM800_INT_REG_NUM (4)
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* Interrupt Number in 88PM800 */
91*4882a593Smuzhiyun enum {
92*4882a593Smuzhiyun PM800_IRQ_ONKEY, /*EN1b0 *//*0 */
93*4882a593Smuzhiyun PM800_IRQ_EXTON, /*EN1b1 */
94*4882a593Smuzhiyun PM800_IRQ_CHG, /*EN1b2 */
95*4882a593Smuzhiyun PM800_IRQ_BAT, /*EN1b3 */
96*4882a593Smuzhiyun PM800_IRQ_RTC, /*EN1b4 */
97*4882a593Smuzhiyun PM800_IRQ_CLASSD, /*EN1b5 *//*5 */
98*4882a593Smuzhiyun PM800_IRQ_VBAT, /*EN2b0 */
99*4882a593Smuzhiyun PM800_IRQ_VSYS, /*EN2b1 */
100*4882a593Smuzhiyun PM800_IRQ_VCHG, /*EN2b2 */
101*4882a593Smuzhiyun PM800_IRQ_TINT, /*EN2b3 */
102*4882a593Smuzhiyun PM800_IRQ_GPADC0, /*EN3b0 *//*10 */
103*4882a593Smuzhiyun PM800_IRQ_GPADC1, /*EN3b1 */
104*4882a593Smuzhiyun PM800_IRQ_GPADC2, /*EN3b2 */
105*4882a593Smuzhiyun PM800_IRQ_GPADC3, /*EN3b3 */
106*4882a593Smuzhiyun PM800_IRQ_GPADC4, /*EN3b4 */
107*4882a593Smuzhiyun PM800_IRQ_GPIO0, /*EN4b0 *//*15 */
108*4882a593Smuzhiyun PM800_IRQ_GPIO1, /*EN4b1 */
109*4882a593Smuzhiyun PM800_IRQ_GPIO2, /*EN4b2 */
110*4882a593Smuzhiyun PM800_IRQ_GPIO3, /*EN4b3 */
111*4882a593Smuzhiyun PM800_IRQ_GPIO4, /*EN4b4 *//*19 */
112*4882a593Smuzhiyun PM800_MAX_IRQ,
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /* PM800: generation identification number */
116*4882a593Smuzhiyun #define PM800_CHIP_GEN_ID_NUM 0x3
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun static const struct i2c_device_id pm80x_id_table[] = {
119*4882a593Smuzhiyun {"88PM800", 0},
120*4882a593Smuzhiyun {} /* NULL terminated */
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, pm80x_id_table);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun static struct resource rtc_resources[] = {
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun .name = "88pm80x-rtc",
127*4882a593Smuzhiyun .start = PM800_IRQ_RTC,
128*4882a593Smuzhiyun .end = PM800_IRQ_RTC,
129*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
130*4882a593Smuzhiyun },
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun static struct mfd_cell rtc_devs[] = {
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun .name = "88pm80x-rtc",
136*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(rtc_resources),
137*4882a593Smuzhiyun .resources = &rtc_resources[0],
138*4882a593Smuzhiyun .id = -1,
139*4882a593Smuzhiyun },
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun static struct resource onkey_resources[] = {
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun .name = "88pm80x-onkey",
145*4882a593Smuzhiyun .start = PM800_IRQ_ONKEY,
146*4882a593Smuzhiyun .end = PM800_IRQ_ONKEY,
147*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
148*4882a593Smuzhiyun },
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun static const struct mfd_cell onkey_devs[] = {
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun .name = "88pm80x-onkey",
154*4882a593Smuzhiyun .num_resources = 1,
155*4882a593Smuzhiyun .resources = &onkey_resources[0],
156*4882a593Smuzhiyun .id = -1,
157*4882a593Smuzhiyun },
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun static const struct mfd_cell regulator_devs[] = {
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun .name = "88pm80x-regulator",
163*4882a593Smuzhiyun .id = -1,
164*4882a593Smuzhiyun },
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun static const struct regmap_irq pm800_irqs[] = {
168*4882a593Smuzhiyun /* INT0 */
169*4882a593Smuzhiyun [PM800_IRQ_ONKEY] = {
170*4882a593Smuzhiyun .mask = PM800_ONKEY_INT_ENA1,
171*4882a593Smuzhiyun },
172*4882a593Smuzhiyun [PM800_IRQ_EXTON] = {
173*4882a593Smuzhiyun .mask = PM800_EXTON_INT_ENA1,
174*4882a593Smuzhiyun },
175*4882a593Smuzhiyun [PM800_IRQ_CHG] = {
176*4882a593Smuzhiyun .mask = PM800_CHG_INT_ENA1,
177*4882a593Smuzhiyun },
178*4882a593Smuzhiyun [PM800_IRQ_BAT] = {
179*4882a593Smuzhiyun .mask = PM800_BAT_INT_ENA1,
180*4882a593Smuzhiyun },
181*4882a593Smuzhiyun [PM800_IRQ_RTC] = {
182*4882a593Smuzhiyun .mask = PM800_RTC_INT_ENA1,
183*4882a593Smuzhiyun },
184*4882a593Smuzhiyun [PM800_IRQ_CLASSD] = {
185*4882a593Smuzhiyun .mask = PM800_CLASSD_OC_INT_ENA1,
186*4882a593Smuzhiyun },
187*4882a593Smuzhiyun /* INT1 */
188*4882a593Smuzhiyun [PM800_IRQ_VBAT] = {
189*4882a593Smuzhiyun .reg_offset = 1,
190*4882a593Smuzhiyun .mask = PM800_VBAT_INT_ENA2,
191*4882a593Smuzhiyun },
192*4882a593Smuzhiyun [PM800_IRQ_VSYS] = {
193*4882a593Smuzhiyun .reg_offset = 1,
194*4882a593Smuzhiyun .mask = PM800_VSYS_INT_ENA2,
195*4882a593Smuzhiyun },
196*4882a593Smuzhiyun [PM800_IRQ_VCHG] = {
197*4882a593Smuzhiyun .reg_offset = 1,
198*4882a593Smuzhiyun .mask = PM800_VCHG_INT_ENA2,
199*4882a593Smuzhiyun },
200*4882a593Smuzhiyun [PM800_IRQ_TINT] = {
201*4882a593Smuzhiyun .reg_offset = 1,
202*4882a593Smuzhiyun .mask = PM800_TINT_INT_ENA2,
203*4882a593Smuzhiyun },
204*4882a593Smuzhiyun /* INT2 */
205*4882a593Smuzhiyun [PM800_IRQ_GPADC0] = {
206*4882a593Smuzhiyun .reg_offset = 2,
207*4882a593Smuzhiyun .mask = PM800_GPADC0_INT_ENA3,
208*4882a593Smuzhiyun },
209*4882a593Smuzhiyun [PM800_IRQ_GPADC1] = {
210*4882a593Smuzhiyun .reg_offset = 2,
211*4882a593Smuzhiyun .mask = PM800_GPADC1_INT_ENA3,
212*4882a593Smuzhiyun },
213*4882a593Smuzhiyun [PM800_IRQ_GPADC2] = {
214*4882a593Smuzhiyun .reg_offset = 2,
215*4882a593Smuzhiyun .mask = PM800_GPADC2_INT_ENA3,
216*4882a593Smuzhiyun },
217*4882a593Smuzhiyun [PM800_IRQ_GPADC3] = {
218*4882a593Smuzhiyun .reg_offset = 2,
219*4882a593Smuzhiyun .mask = PM800_GPADC3_INT_ENA3,
220*4882a593Smuzhiyun },
221*4882a593Smuzhiyun [PM800_IRQ_GPADC4] = {
222*4882a593Smuzhiyun .reg_offset = 2,
223*4882a593Smuzhiyun .mask = PM800_GPADC4_INT_ENA3,
224*4882a593Smuzhiyun },
225*4882a593Smuzhiyun /* INT3 */
226*4882a593Smuzhiyun [PM800_IRQ_GPIO0] = {
227*4882a593Smuzhiyun .reg_offset = 3,
228*4882a593Smuzhiyun .mask = PM800_GPIO0_INT_ENA4,
229*4882a593Smuzhiyun },
230*4882a593Smuzhiyun [PM800_IRQ_GPIO1] = {
231*4882a593Smuzhiyun .reg_offset = 3,
232*4882a593Smuzhiyun .mask = PM800_GPIO1_INT_ENA4,
233*4882a593Smuzhiyun },
234*4882a593Smuzhiyun [PM800_IRQ_GPIO2] = {
235*4882a593Smuzhiyun .reg_offset = 3,
236*4882a593Smuzhiyun .mask = PM800_GPIO2_INT_ENA4,
237*4882a593Smuzhiyun },
238*4882a593Smuzhiyun [PM800_IRQ_GPIO3] = {
239*4882a593Smuzhiyun .reg_offset = 3,
240*4882a593Smuzhiyun .mask = PM800_GPIO3_INT_ENA4,
241*4882a593Smuzhiyun },
242*4882a593Smuzhiyun [PM800_IRQ_GPIO4] = {
243*4882a593Smuzhiyun .reg_offset = 3,
244*4882a593Smuzhiyun .mask = PM800_GPIO4_INT_ENA4,
245*4882a593Smuzhiyun },
246*4882a593Smuzhiyun };
247*4882a593Smuzhiyun
device_gpadc_init(struct pm80x_chip * chip,struct pm80x_platform_data * pdata)248*4882a593Smuzhiyun static int device_gpadc_init(struct pm80x_chip *chip,
249*4882a593Smuzhiyun struct pm80x_platform_data *pdata)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun struct pm80x_subchip *subchip = chip->subchip;
252*4882a593Smuzhiyun struct regmap *map = subchip->regmap_gpadc;
253*4882a593Smuzhiyun int data = 0, mask = 0, ret = 0;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun if (!map) {
256*4882a593Smuzhiyun dev_warn(chip->dev,
257*4882a593Smuzhiyun "Warning: gpadc regmap is not available!\n");
258*4882a593Smuzhiyun return -EINVAL;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun /*
261*4882a593Smuzhiyun * initialize GPADC without activating it turn on GPADC
262*4882a593Smuzhiyun * measurments
263*4882a593Smuzhiyun */
264*4882a593Smuzhiyun ret = regmap_update_bits(map,
265*4882a593Smuzhiyun PM800_GPADC_MISC_CONFIG2,
266*4882a593Smuzhiyun PM800_GPADC_MISC_GPFSM_EN,
267*4882a593Smuzhiyun PM800_GPADC_MISC_GPFSM_EN);
268*4882a593Smuzhiyun if (ret < 0)
269*4882a593Smuzhiyun goto out;
270*4882a593Smuzhiyun /*
271*4882a593Smuzhiyun * This function configures the ADC as requires for
272*4882a593Smuzhiyun * CP implementation.CP does not "own" the ADC configuration
273*4882a593Smuzhiyun * registers and relies on AP.
274*4882a593Smuzhiyun * Reason: enable automatic ADC measurements needed
275*4882a593Smuzhiyun * for CP to get VBAT and RF temperature readings.
276*4882a593Smuzhiyun */
277*4882a593Smuzhiyun ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN1,
278*4882a593Smuzhiyun PM800_MEAS_EN1_VBAT, PM800_MEAS_EN1_VBAT);
279*4882a593Smuzhiyun if (ret < 0)
280*4882a593Smuzhiyun goto out;
281*4882a593Smuzhiyun ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN2,
282*4882a593Smuzhiyun (PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN),
283*4882a593Smuzhiyun (PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN));
284*4882a593Smuzhiyun if (ret < 0)
285*4882a593Smuzhiyun goto out;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun /*
288*4882a593Smuzhiyun * the defult of PM800 is GPADC operates at 100Ks/s rate
289*4882a593Smuzhiyun * and Number of GPADC slots with active current bias prior
290*4882a593Smuzhiyun * to GPADC sampling = 1 slot for all GPADCs set for
291*4882a593Smuzhiyun * Temprature mesurmants
292*4882a593Smuzhiyun */
293*4882a593Smuzhiyun mask = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
294*4882a593Smuzhiyun PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun if (pdata && (pdata->batt_det == 0))
297*4882a593Smuzhiyun data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
298*4882a593Smuzhiyun PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);
299*4882a593Smuzhiyun else
300*4882a593Smuzhiyun data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN2 |
301*4882a593Smuzhiyun PM800_GPADC_GP_BIAS_EN3);
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun ret = regmap_update_bits(map, PM800_GP_BIAS_ENA1, mask, data);
304*4882a593Smuzhiyun if (ret < 0)
305*4882a593Smuzhiyun goto out;
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun dev_info(chip->dev, "pm800 device_gpadc_init: Done\n");
308*4882a593Smuzhiyun return 0;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun out:
311*4882a593Smuzhiyun dev_info(chip->dev, "pm800 device_gpadc_init: Failed!\n");
312*4882a593Smuzhiyun return ret;
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
device_onkey_init(struct pm80x_chip * chip,struct pm80x_platform_data * pdata)315*4882a593Smuzhiyun static int device_onkey_init(struct pm80x_chip *chip,
316*4882a593Smuzhiyun struct pm80x_platform_data *pdata)
317*4882a593Smuzhiyun {
318*4882a593Smuzhiyun int ret;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0],
321*4882a593Smuzhiyun ARRAY_SIZE(onkey_devs), &onkey_resources[0], 0,
322*4882a593Smuzhiyun NULL);
323*4882a593Smuzhiyun if (ret) {
324*4882a593Smuzhiyun dev_err(chip->dev, "Failed to add onkey subdev\n");
325*4882a593Smuzhiyun return ret;
326*4882a593Smuzhiyun }
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun return 0;
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun
device_rtc_init(struct pm80x_chip * chip,struct pm80x_platform_data * pdata)331*4882a593Smuzhiyun static int device_rtc_init(struct pm80x_chip *chip,
332*4882a593Smuzhiyun struct pm80x_platform_data *pdata)
333*4882a593Smuzhiyun {
334*4882a593Smuzhiyun int ret;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun if (pdata) {
337*4882a593Smuzhiyun rtc_devs[0].platform_data = pdata->rtc;
338*4882a593Smuzhiyun rtc_devs[0].pdata_size =
339*4882a593Smuzhiyun pdata->rtc ? sizeof(struct pm80x_rtc_pdata) : 0;
340*4882a593Smuzhiyun }
341*4882a593Smuzhiyun ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
342*4882a593Smuzhiyun ARRAY_SIZE(rtc_devs), NULL, 0, NULL);
343*4882a593Smuzhiyun if (ret) {
344*4882a593Smuzhiyun dev_err(chip->dev, "Failed to add rtc subdev\n");
345*4882a593Smuzhiyun return ret;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun return 0;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun
device_regulator_init(struct pm80x_chip * chip,struct pm80x_platform_data * pdata)351*4882a593Smuzhiyun static int device_regulator_init(struct pm80x_chip *chip,
352*4882a593Smuzhiyun struct pm80x_platform_data *pdata)
353*4882a593Smuzhiyun {
354*4882a593Smuzhiyun int ret;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun ret = mfd_add_devices(chip->dev, 0, ®ulator_devs[0],
357*4882a593Smuzhiyun ARRAY_SIZE(regulator_devs), NULL, 0, NULL);
358*4882a593Smuzhiyun if (ret) {
359*4882a593Smuzhiyun dev_err(chip->dev, "Failed to add regulator subdev\n");
360*4882a593Smuzhiyun return ret;
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun return 0;
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun
device_irq_init_800(struct pm80x_chip * chip)366*4882a593Smuzhiyun static int device_irq_init_800(struct pm80x_chip *chip)
367*4882a593Smuzhiyun {
368*4882a593Smuzhiyun struct regmap *map = chip->regmap;
369*4882a593Smuzhiyun unsigned long flags = IRQF_ONESHOT;
370*4882a593Smuzhiyun int data, mask, ret = -EINVAL;
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun if (!map || !chip->irq) {
373*4882a593Smuzhiyun dev_err(chip->dev, "incorrect parameters\n");
374*4882a593Smuzhiyun return -EINVAL;
375*4882a593Smuzhiyun }
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun /*
378*4882a593Smuzhiyun * irq_mode defines the way of clearing interrupt. it's read-clear by
379*4882a593Smuzhiyun * default.
380*4882a593Smuzhiyun */
381*4882a593Smuzhiyun mask =
382*4882a593Smuzhiyun PM800_WAKEUP2_INV_INT | PM800_WAKEUP2_INT_CLEAR |
383*4882a593Smuzhiyun PM800_WAKEUP2_INT_MASK;
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun data = PM800_WAKEUP2_INT_CLEAR;
386*4882a593Smuzhiyun ret = regmap_update_bits(map, PM800_WAKEUP2, mask, data);
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun if (ret < 0)
389*4882a593Smuzhiyun goto out;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun ret =
392*4882a593Smuzhiyun regmap_add_irq_chip(chip->regmap, chip->irq, flags, -1,
393*4882a593Smuzhiyun chip->regmap_irq_chip, &chip->irq_data);
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun out:
396*4882a593Smuzhiyun return ret;
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun
device_irq_exit_800(struct pm80x_chip * chip)399*4882a593Smuzhiyun static void device_irq_exit_800(struct pm80x_chip *chip)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun regmap_del_irq_chip(chip->irq, chip->irq_data);
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun static struct regmap_irq_chip pm800_irq_chip = {
405*4882a593Smuzhiyun .name = "88pm800",
406*4882a593Smuzhiyun .irqs = pm800_irqs,
407*4882a593Smuzhiyun .num_irqs = ARRAY_SIZE(pm800_irqs),
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun .num_regs = 4,
410*4882a593Smuzhiyun .status_base = PM800_INT_STATUS1,
411*4882a593Smuzhiyun .mask_base = PM800_INT_ENA_1,
412*4882a593Smuzhiyun .ack_base = PM800_INT_STATUS1,
413*4882a593Smuzhiyun .mask_invert = 1,
414*4882a593Smuzhiyun };
415*4882a593Smuzhiyun
pm800_pages_init(struct pm80x_chip * chip)416*4882a593Smuzhiyun static int pm800_pages_init(struct pm80x_chip *chip)
417*4882a593Smuzhiyun {
418*4882a593Smuzhiyun struct pm80x_subchip *subchip;
419*4882a593Smuzhiyun struct i2c_client *client = chip->client;
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun int ret = 0;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun subchip = chip->subchip;
424*4882a593Smuzhiyun if (!subchip || !subchip->power_page_addr || !subchip->gpadc_page_addr)
425*4882a593Smuzhiyun return -ENODEV;
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun /* PM800 block power page */
428*4882a593Smuzhiyun subchip->power_page = i2c_new_dummy_device(client->adapter,
429*4882a593Smuzhiyun subchip->power_page_addr);
430*4882a593Smuzhiyun if (IS_ERR(subchip->power_page)) {
431*4882a593Smuzhiyun ret = PTR_ERR(subchip->power_page);
432*4882a593Smuzhiyun goto out;
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun subchip->regmap_power = devm_regmap_init_i2c(subchip->power_page,
436*4882a593Smuzhiyun &pm80x_regmap_config);
437*4882a593Smuzhiyun if (IS_ERR(subchip->regmap_power)) {
438*4882a593Smuzhiyun ret = PTR_ERR(subchip->regmap_power);
439*4882a593Smuzhiyun dev_err(chip->dev,
440*4882a593Smuzhiyun "Failed to allocate regmap_power: %d\n", ret);
441*4882a593Smuzhiyun goto out;
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun i2c_set_clientdata(subchip->power_page, chip);
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun /* PM800 block GPADC */
447*4882a593Smuzhiyun subchip->gpadc_page = i2c_new_dummy_device(client->adapter,
448*4882a593Smuzhiyun subchip->gpadc_page_addr);
449*4882a593Smuzhiyun if (IS_ERR(subchip->gpadc_page)) {
450*4882a593Smuzhiyun ret = PTR_ERR(subchip->gpadc_page);
451*4882a593Smuzhiyun goto out;
452*4882a593Smuzhiyun }
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun subchip->regmap_gpadc = devm_regmap_init_i2c(subchip->gpadc_page,
455*4882a593Smuzhiyun &pm80x_regmap_config);
456*4882a593Smuzhiyun if (IS_ERR(subchip->regmap_gpadc)) {
457*4882a593Smuzhiyun ret = PTR_ERR(subchip->regmap_gpadc);
458*4882a593Smuzhiyun dev_err(chip->dev,
459*4882a593Smuzhiyun "Failed to allocate regmap_gpadc: %d\n", ret);
460*4882a593Smuzhiyun goto out;
461*4882a593Smuzhiyun }
462*4882a593Smuzhiyun i2c_set_clientdata(subchip->gpadc_page, chip);
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun out:
465*4882a593Smuzhiyun return ret;
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun
pm800_pages_exit(struct pm80x_chip * chip)468*4882a593Smuzhiyun static void pm800_pages_exit(struct pm80x_chip *chip)
469*4882a593Smuzhiyun {
470*4882a593Smuzhiyun struct pm80x_subchip *subchip;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun subchip = chip->subchip;
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun if (subchip && subchip->power_page)
475*4882a593Smuzhiyun i2c_unregister_device(subchip->power_page);
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun if (subchip && subchip->gpadc_page)
478*4882a593Smuzhiyun i2c_unregister_device(subchip->gpadc_page);
479*4882a593Smuzhiyun }
480*4882a593Smuzhiyun
device_800_init(struct pm80x_chip * chip,struct pm80x_platform_data * pdata)481*4882a593Smuzhiyun static int device_800_init(struct pm80x_chip *chip,
482*4882a593Smuzhiyun struct pm80x_platform_data *pdata)
483*4882a593Smuzhiyun {
484*4882a593Smuzhiyun int ret;
485*4882a593Smuzhiyun unsigned int val;
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun /*
488*4882a593Smuzhiyun * alarm wake up bit will be clear in device_irq_init(),
489*4882a593Smuzhiyun * read before that
490*4882a593Smuzhiyun */
491*4882a593Smuzhiyun ret = regmap_read(chip->regmap, PM800_RTC_CONTROL, &val);
492*4882a593Smuzhiyun if (ret < 0) {
493*4882a593Smuzhiyun dev_err(chip->dev, "Failed to read RTC register: %d\n", ret);
494*4882a593Smuzhiyun goto out;
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun if (val & PM800_ALARM_WAKEUP) {
497*4882a593Smuzhiyun if (pdata && pdata->rtc)
498*4882a593Smuzhiyun pdata->rtc->rtc_wakeup = 1;
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun ret = device_gpadc_init(chip, pdata);
502*4882a593Smuzhiyun if (ret < 0) {
503*4882a593Smuzhiyun dev_err(chip->dev, "[%s]Failed to init gpadc\n", __func__);
504*4882a593Smuzhiyun goto out;
505*4882a593Smuzhiyun }
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun chip->regmap_irq_chip = &pm800_irq_chip;
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun ret = device_irq_init_800(chip);
510*4882a593Smuzhiyun if (ret < 0) {
511*4882a593Smuzhiyun dev_err(chip->dev, "[%s]Failed to init pm800 irq\n", __func__);
512*4882a593Smuzhiyun goto out;
513*4882a593Smuzhiyun }
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun ret = device_onkey_init(chip, pdata);
516*4882a593Smuzhiyun if (ret) {
517*4882a593Smuzhiyun dev_err(chip->dev, "Failed to add onkey subdev\n");
518*4882a593Smuzhiyun goto out_dev;
519*4882a593Smuzhiyun }
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun ret = device_rtc_init(chip, pdata);
522*4882a593Smuzhiyun if (ret) {
523*4882a593Smuzhiyun dev_err(chip->dev, "Failed to add rtc subdev\n");
524*4882a593Smuzhiyun goto out;
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun ret = device_regulator_init(chip, pdata);
528*4882a593Smuzhiyun if (ret) {
529*4882a593Smuzhiyun dev_err(chip->dev, "Failed to add regulators subdev\n");
530*4882a593Smuzhiyun goto out;
531*4882a593Smuzhiyun }
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun return 0;
534*4882a593Smuzhiyun out_dev:
535*4882a593Smuzhiyun mfd_remove_devices(chip->dev);
536*4882a593Smuzhiyun device_irq_exit_800(chip);
537*4882a593Smuzhiyun out:
538*4882a593Smuzhiyun return ret;
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun
pm800_probe(struct i2c_client * client,const struct i2c_device_id * id)541*4882a593Smuzhiyun static int pm800_probe(struct i2c_client *client,
542*4882a593Smuzhiyun const struct i2c_device_id *id)
543*4882a593Smuzhiyun {
544*4882a593Smuzhiyun int ret = 0;
545*4882a593Smuzhiyun struct pm80x_chip *chip;
546*4882a593Smuzhiyun struct pm80x_platform_data *pdata = dev_get_platdata(&client->dev);
547*4882a593Smuzhiyun struct pm80x_subchip *subchip;
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun ret = pm80x_init(client);
550*4882a593Smuzhiyun if (ret) {
551*4882a593Smuzhiyun dev_err(&client->dev, "pm800_init fail\n");
552*4882a593Smuzhiyun goto out_init;
553*4882a593Smuzhiyun }
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun chip = i2c_get_clientdata(client);
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun /* init subchip for PM800 */
558*4882a593Smuzhiyun subchip =
559*4882a593Smuzhiyun devm_kzalloc(&client->dev, sizeof(struct pm80x_subchip),
560*4882a593Smuzhiyun GFP_KERNEL);
561*4882a593Smuzhiyun if (!subchip) {
562*4882a593Smuzhiyun ret = -ENOMEM;
563*4882a593Smuzhiyun goto err_subchip_alloc;
564*4882a593Smuzhiyun }
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun /* pm800 has 2 addtional pages to support power and gpadc. */
567*4882a593Smuzhiyun subchip->power_page_addr = client->addr + 1;
568*4882a593Smuzhiyun subchip->gpadc_page_addr = client->addr + 2;
569*4882a593Smuzhiyun chip->subchip = subchip;
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun ret = pm800_pages_init(chip);
572*4882a593Smuzhiyun if (ret) {
573*4882a593Smuzhiyun dev_err(&client->dev, "pm800_pages_init failed!\n");
574*4882a593Smuzhiyun goto err_device_init;
575*4882a593Smuzhiyun }
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun ret = device_800_init(chip, pdata);
578*4882a593Smuzhiyun if (ret) {
579*4882a593Smuzhiyun dev_err(chip->dev, "Failed to initialize 88pm800 devices\n");
580*4882a593Smuzhiyun goto err_device_init;
581*4882a593Smuzhiyun }
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun if (pdata && pdata->plat_config)
584*4882a593Smuzhiyun pdata->plat_config(chip, pdata);
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun return 0;
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun err_device_init:
589*4882a593Smuzhiyun pm800_pages_exit(chip);
590*4882a593Smuzhiyun err_subchip_alloc:
591*4882a593Smuzhiyun pm80x_deinit();
592*4882a593Smuzhiyun out_init:
593*4882a593Smuzhiyun return ret;
594*4882a593Smuzhiyun }
595*4882a593Smuzhiyun
pm800_remove(struct i2c_client * client)596*4882a593Smuzhiyun static int pm800_remove(struct i2c_client *client)
597*4882a593Smuzhiyun {
598*4882a593Smuzhiyun struct pm80x_chip *chip = i2c_get_clientdata(client);
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun mfd_remove_devices(chip->dev);
601*4882a593Smuzhiyun device_irq_exit_800(chip);
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun pm800_pages_exit(chip);
604*4882a593Smuzhiyun pm80x_deinit();
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun return 0;
607*4882a593Smuzhiyun }
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun static struct i2c_driver pm800_driver = {
610*4882a593Smuzhiyun .driver = {
611*4882a593Smuzhiyun .name = "88PM800",
612*4882a593Smuzhiyun .pm = &pm80x_pm_ops,
613*4882a593Smuzhiyun },
614*4882a593Smuzhiyun .probe = pm800_probe,
615*4882a593Smuzhiyun .remove = pm800_remove,
616*4882a593Smuzhiyun .id_table = pm80x_id_table,
617*4882a593Smuzhiyun };
618*4882a593Smuzhiyun
pm800_i2c_init(void)619*4882a593Smuzhiyun static int __init pm800_i2c_init(void)
620*4882a593Smuzhiyun {
621*4882a593Smuzhiyun return i2c_add_driver(&pm800_driver);
622*4882a593Smuzhiyun }
623*4882a593Smuzhiyun subsys_initcall(pm800_i2c_init);
624*4882a593Smuzhiyun
pm800_i2c_exit(void)625*4882a593Smuzhiyun static void __exit pm800_i2c_exit(void)
626*4882a593Smuzhiyun {
627*4882a593Smuzhiyun i2c_del_driver(&pm800_driver);
628*4882a593Smuzhiyun }
629*4882a593Smuzhiyun module_exit(pm800_i2c_exit);
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM800");
632*4882a593Smuzhiyun MODULE_AUTHOR("Qiao Zhou <zhouqiao@marvell.com>");
633*4882a593Smuzhiyun MODULE_LICENSE("GPL");
634