1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef TEGRA210_MC_H 7*4882a593Smuzhiyun #define TEGRA210_MC_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include "mc.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* register definitions */ 12*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4 13*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_HC_0 0x310 14*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_HC_1 0x314 15*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320 16*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_NVENC_0 0x328 17*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_PPCS_0 0x344 18*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_PPCS_1 0x348 19*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_ISP2_0 0x370 20*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_ISP2_1 0x374 21*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c 22*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_XUSB_1 0x380 23*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_TSEC_0 0x390 24*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_VIC_0 0x394 25*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_VI2_0 0x398 26*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_GPU_0 0x3ac 27*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3b8 28*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3bc 29*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3c0 30*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3c4 31*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_GPU2_0 0x3e8 32*4882a593Smuzhiyun #define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3d8 33*4882a593Smuzhiyun #define MC_MLL_MPCORER_PTSA_RATE 0x44c 34*4882a593Smuzhiyun #define MC_FTOP_PTSA_RATE 0x50c 35*4882a593Smuzhiyun #define MC_EMEM_ARB_TIMING_RFCPB 0x6c0 36*4882a593Smuzhiyun #define MC_EMEM_ARB_TIMING_CCDMW 0x6c4 37*4882a593Smuzhiyun #define MC_EMEM_ARB_REFPB_HP_CTRL 0x6f0 38*4882a593Smuzhiyun #define MC_EMEM_ARB_REFPB_BANK_CTRL 0x6f4 39*4882a593Smuzhiyun #define MC_PTSA_GRANT_DECREMENT 0x960 40*4882a593Smuzhiyun #define MC_EMEM_ARB_DHYST_CTRL 0xbcc 41*4882a593Smuzhiyun #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xbd0 42*4882a593Smuzhiyun #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xbd4 43*4882a593Smuzhiyun #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xbd8 44*4882a593Smuzhiyun #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xbdc 45*4882a593Smuzhiyun #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xbe0 46*4882a593Smuzhiyun #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xbe4 47*4882a593Smuzhiyun #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xbe8 48*4882a593Smuzhiyun #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xbec 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #endif 51