1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2015 Samsung Electronics Co., Ltd. 4*4882a593Smuzhiyun * http://www.samsung.com 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Exynos SROMC register definitions 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __EXYNOS_SROM_H 10*4882a593Smuzhiyun #define __EXYNOS_SROM_H __FILE__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define EXYNOS_SROMREG(x) (x) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define EXYNOS_SROM_BW EXYNOS_SROMREG(0x0) 15*4882a593Smuzhiyun #define EXYNOS_SROM_BC0 EXYNOS_SROMREG(0x4) 16*4882a593Smuzhiyun #define EXYNOS_SROM_BC1 EXYNOS_SROMREG(0x8) 17*4882a593Smuzhiyun #define EXYNOS_SROM_BC2 EXYNOS_SROMREG(0xc) 18*4882a593Smuzhiyun #define EXYNOS_SROM_BC3 EXYNOS_SROMREG(0x10) 19*4882a593Smuzhiyun #define EXYNOS_SROM_BC4 EXYNOS_SROMREG(0x14) 20*4882a593Smuzhiyun #define EXYNOS_SROM_BC5 EXYNOS_SROMREG(0x18) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define EXYNOS_SROM_BW__DATAWIDTH__SHIFT 0 25*4882a593Smuzhiyun #define EXYNOS_SROM_BW__ADDRMODE__SHIFT 1 26*4882a593Smuzhiyun #define EXYNOS_SROM_BW__WAITENABLE__SHIFT 2 27*4882a593Smuzhiyun #define EXYNOS_SROM_BW__BYTEENABLE__SHIFT 3 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define EXYNOS_SROM_BW__CS_MASK 0xf 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define EXYNOS_SROM_BW__NCS0__SHIFT 0 32*4882a593Smuzhiyun #define EXYNOS_SROM_BW__NCS1__SHIFT 4 33*4882a593Smuzhiyun #define EXYNOS_SROM_BW__NCS2__SHIFT 8 34*4882a593Smuzhiyun #define EXYNOS_SROM_BW__NCS3__SHIFT 12 35*4882a593Smuzhiyun #define EXYNOS_SROM_BW__NCS4__SHIFT 16 36*4882a593Smuzhiyun #define EXYNOS_SROM_BW__NCS5__SHIFT 20 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* applies to same to BCS0 - BCS3 */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define EXYNOS_SROM_BCX__PMC__SHIFT 0 41*4882a593Smuzhiyun #define EXYNOS_SROM_BCX__TACP__SHIFT 4 42*4882a593Smuzhiyun #define EXYNOS_SROM_BCX__TCAH__SHIFT 8 43*4882a593Smuzhiyun #define EXYNOS_SROM_BCX__TCOH__SHIFT 12 44*4882a593Smuzhiyun #define EXYNOS_SROM_BCX__TACC__SHIFT 16 45*4882a593Smuzhiyun #define EXYNOS_SROM_BCX__TCOS__SHIFT 24 46*4882a593Smuzhiyun #define EXYNOS_SROM_BCX__TACS__SHIFT 28 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #endif /* __EXYNOS_SROM_H */ 49