xref: /OK3568_Linux_fs/kernel/drivers/media/usb/stk1160/stk1160-ac97.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * STK1160 driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2012 Ezequiel Garcia
6*4882a593Smuzhiyun  * <elezegarcia--a.t--gmail.com>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Copyright (C) 2016 Marcel Hasler
9*4882a593Smuzhiyun  * <mahasler--a.t--gmail.com>
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * Based on Easycap driver by R.M. Thomas
12*4882a593Smuzhiyun  *	Copyright (C) 2010 R.M. Thomas
13*4882a593Smuzhiyun  *	<rmthomas--a.t--sciolus.org>
14*4882a593Smuzhiyun  */
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include <linux/delay.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include "stk1160.h"
19*4882a593Smuzhiyun #include "stk1160-reg.h"
20*4882a593Smuzhiyun 
stk1160_ac97_wait_transfer_complete(struct stk1160 * dev)21*4882a593Smuzhiyun static int stk1160_ac97_wait_transfer_complete(struct stk1160 *dev)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun 	unsigned long timeout = jiffies + msecs_to_jiffies(STK1160_AC97_TIMEOUT);
24*4882a593Smuzhiyun 	u8 value;
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun 	/* Wait for AC97 transfer to complete */
27*4882a593Smuzhiyun 	while (time_is_after_jiffies(timeout)) {
28*4882a593Smuzhiyun 		stk1160_read_reg(dev, STK1160_AC97CTL_0, &value);
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun 		if (!(value & (STK1160_AC97CTL_0_CR | STK1160_AC97CTL_0_CW)))
31*4882a593Smuzhiyun 			return 0;
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun 		usleep_range(50, 100);
34*4882a593Smuzhiyun 	}
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun 	stk1160_err("AC97 transfer took too long, this should never happen!");
37*4882a593Smuzhiyun 	return -EBUSY;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun 
stk1160_write_ac97(struct stk1160 * dev,u16 reg,u16 value)40*4882a593Smuzhiyun static void stk1160_write_ac97(struct stk1160 *dev, u16 reg, u16 value)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun 	/* Set codec register address */
43*4882a593Smuzhiyun 	stk1160_write_reg(dev, STK1160_AC97_ADDR, reg);
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	/* Set codec command */
46*4882a593Smuzhiyun 	stk1160_write_reg(dev, STK1160_AC97_CMD, value & 0xff);
47*4882a593Smuzhiyun 	stk1160_write_reg(dev, STK1160_AC97_CMD + 1, (value & 0xff00) >> 8);
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	/* Set command write bit to initiate write operation */
50*4882a593Smuzhiyun 	stk1160_write_reg(dev, STK1160_AC97CTL_0, 0x8c);
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	/* Wait for command write bit to be cleared */
53*4882a593Smuzhiyun 	stk1160_ac97_wait_transfer_complete(dev);
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun #ifdef DEBUG
stk1160_read_ac97(struct stk1160 * dev,u16 reg)57*4882a593Smuzhiyun static u16 stk1160_read_ac97(struct stk1160 *dev, u16 reg)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun 	u8 vall = 0;
60*4882a593Smuzhiyun 	u8 valh = 0;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	/* Set codec register address */
63*4882a593Smuzhiyun 	stk1160_write_reg(dev, STK1160_AC97_ADDR, reg);
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	/* Set command read bit to initiate read operation */
66*4882a593Smuzhiyun 	stk1160_write_reg(dev, STK1160_AC97CTL_0, 0x8b);
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	/* Wait for command read bit to be cleared */
69*4882a593Smuzhiyun 	if (stk1160_ac97_wait_transfer_complete(dev) < 0)
70*4882a593Smuzhiyun 		return 0;
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	/* Retrieve register value */
74*4882a593Smuzhiyun 	stk1160_read_reg(dev, STK1160_AC97_CMD, &vall);
75*4882a593Smuzhiyun 	stk1160_read_reg(dev, STK1160_AC97_CMD + 1, &valh);
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	return (valh << 8) | vall;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun 
stk1160_ac97_dump_regs(struct stk1160 * dev)80*4882a593Smuzhiyun void stk1160_ac97_dump_regs(struct stk1160 *dev)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun 	u16 value;
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	value = stk1160_read_ac97(dev, 0x12); /* CD volume */
85*4882a593Smuzhiyun 	stk1160_dbg("0x12 == 0x%04x", value);
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	value = stk1160_read_ac97(dev, 0x10); /* Line-in volume */
88*4882a593Smuzhiyun 	stk1160_dbg("0x10 == 0x%04x", value);
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	value = stk1160_read_ac97(dev, 0x0e); /* MIC volume (mono) */
91*4882a593Smuzhiyun 	stk1160_dbg("0x0e == 0x%04x", value);
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	value = stk1160_read_ac97(dev, 0x16); /* Aux volume */
94*4882a593Smuzhiyun 	stk1160_dbg("0x16 == 0x%04x", value);
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	value = stk1160_read_ac97(dev, 0x1a); /* Record select */
97*4882a593Smuzhiyun 	stk1160_dbg("0x1a == 0x%04x", value);
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	value = stk1160_read_ac97(dev, 0x02); /* Master volume */
100*4882a593Smuzhiyun 	stk1160_dbg("0x02 == 0x%04x", value);
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	value = stk1160_read_ac97(dev, 0x1c); /* Record gain */
103*4882a593Smuzhiyun 	stk1160_dbg("0x1c == 0x%04x", value);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun #endif
106*4882a593Smuzhiyun 
stk1160_has_audio(struct stk1160 * dev)107*4882a593Smuzhiyun static int stk1160_has_audio(struct stk1160 *dev)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun 	u8 value;
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	stk1160_read_reg(dev, STK1160_POSV_L, &value);
112*4882a593Smuzhiyun 	return !(value & STK1160_POSV_L_ACDOUT);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun 
stk1160_has_ac97(struct stk1160 * dev)115*4882a593Smuzhiyun static int stk1160_has_ac97(struct stk1160 *dev)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun 	u8 value;
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	stk1160_read_reg(dev, STK1160_POSV_L, &value);
120*4882a593Smuzhiyun 	return !(value & STK1160_POSV_L_ACSYNC);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun 
stk1160_ac97_setup(struct stk1160 * dev)123*4882a593Smuzhiyun void stk1160_ac97_setup(struct stk1160 *dev)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun 	if (!stk1160_has_audio(dev)) {
126*4882a593Smuzhiyun 		stk1160_info("Device doesn't support audio, skipping AC97 setup.");
127*4882a593Smuzhiyun 		return;
128*4882a593Smuzhiyun 	}
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	if (!stk1160_has_ac97(dev)) {
131*4882a593Smuzhiyun 		stk1160_info("Device uses internal 8-bit ADC, skipping AC97 setup.");
132*4882a593Smuzhiyun 		return;
133*4882a593Smuzhiyun 	}
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	/* Two-step reset AC97 interface and hardware codec */
136*4882a593Smuzhiyun 	stk1160_write_reg(dev, STK1160_AC97CTL_0, 0x94);
137*4882a593Smuzhiyun 	stk1160_write_reg(dev, STK1160_AC97CTL_0, 0x8c);
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	/* Set 16-bit audio data and choose L&R channel*/
140*4882a593Smuzhiyun 	stk1160_write_reg(dev, STK1160_AC97CTL_1 + 2, 0x01);
141*4882a593Smuzhiyun 	stk1160_write_reg(dev, STK1160_AC97CTL_1 + 3, 0x00);
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	/* Setup channels */
144*4882a593Smuzhiyun 	stk1160_write_ac97(dev, 0x12, 0x8808); /* CD volume */
145*4882a593Smuzhiyun 	stk1160_write_ac97(dev, 0x10, 0x0808); /* Line-in volume */
146*4882a593Smuzhiyun 	stk1160_write_ac97(dev, 0x0e, 0x0008); /* MIC volume (mono) */
147*4882a593Smuzhiyun 	stk1160_write_ac97(dev, 0x16, 0x0808); /* Aux volume */
148*4882a593Smuzhiyun 	stk1160_write_ac97(dev, 0x1a, 0x0404); /* Record select */
149*4882a593Smuzhiyun 	stk1160_write_ac97(dev, 0x02, 0x0000); /* Master volume */
150*4882a593Smuzhiyun 	stk1160_write_ac97(dev, 0x1c, 0x0808); /* Record gain */
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun #ifdef DEBUG
153*4882a593Smuzhiyun 	stk1160_ac97_dump_regs(dev);
154*4882a593Smuzhiyun #endif
155*4882a593Smuzhiyun }
156