xref: /OK3568_Linux_fs/kernel/drivers/media/usb/pvrusb2/pvrusb2-hdw-internal.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun #ifndef __PVRUSB2_HDW_INTERNAL_H
7*4882a593Smuzhiyun #define __PVRUSB2_HDW_INTERNAL_H
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun /*
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun   This header sets up all the internal structures and definitions needed to
12*4882a593Smuzhiyun   track and coordinate the driver's interaction with the hardware.  ONLY
13*4882a593Smuzhiyun   source files which actually implement part of that whole circus should be
14*4882a593Smuzhiyun   including this header.  Higher levels, like the external layers to the
15*4882a593Smuzhiyun   various public APIs (V4L, sysfs, etc) should NOT ever include this
16*4882a593Smuzhiyun   private, internal header.  This means that pvrusb2-hdw, pvrusb2-encoder,
17*4882a593Smuzhiyun   etc will include this, but pvrusb2-v4l should not.
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun */
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #include <linux/videodev2.h>
22*4882a593Smuzhiyun #include <linux/i2c.h>
23*4882a593Smuzhiyun #include <linux/workqueue.h>
24*4882a593Smuzhiyun #include <linux/mutex.h>
25*4882a593Smuzhiyun #include "pvrusb2-hdw.h"
26*4882a593Smuzhiyun #include "pvrusb2-io.h"
27*4882a593Smuzhiyun #include <media/v4l2-device.h>
28*4882a593Smuzhiyun #include <media/drv-intf/cx2341x.h>
29*4882a593Smuzhiyun #include <media/i2c/ir-kbd-i2c.h>
30*4882a593Smuzhiyun #include "pvrusb2-devattr.h"
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun /* Legal values for PVR2_CID_HSM */
33*4882a593Smuzhiyun #define PVR2_CVAL_HSM_FAIL 0
34*4882a593Smuzhiyun #define PVR2_CVAL_HSM_FULL 1
35*4882a593Smuzhiyun #define PVR2_CVAL_HSM_HIGH 2
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #define PVR2_VID_ENDPOINT        0x84
38*4882a593Smuzhiyun #define PVR2_UNK_ENDPOINT        0x86    /* maybe raw yuv ? */
39*4882a593Smuzhiyun #define PVR2_VBI_ENDPOINT        0x88
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define PVR2_CTL_BUFFSIZE        64
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define FREQTABLE_SIZE 500
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #define LOCK_TAKE(x) do { mutex_lock(&x##_mutex); x##_held = !0; } while (0)
46*4882a593Smuzhiyun #define LOCK_GIVE(x) do { x##_held = 0; mutex_unlock(&x##_mutex); } while (0)
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun typedef int (*pvr2_ctlf_is_dirty)(struct pvr2_ctrl *);
49*4882a593Smuzhiyun typedef void (*pvr2_ctlf_clear_dirty)(struct pvr2_ctrl *);
50*4882a593Smuzhiyun typedef int (*pvr2_ctlf_check_value)(struct pvr2_ctrl *,int);
51*4882a593Smuzhiyun typedef int (*pvr2_ctlf_get_value)(struct pvr2_ctrl *,int *);
52*4882a593Smuzhiyun typedef int (*pvr2_ctlf_set_value)(struct pvr2_ctrl *,int msk,int val);
53*4882a593Smuzhiyun typedef int (*pvr2_ctlf_val_to_sym)(struct pvr2_ctrl *,int msk,int val,
54*4882a593Smuzhiyun 				    char *,unsigned int,unsigned int *);
55*4882a593Smuzhiyun typedef int (*pvr2_ctlf_sym_to_val)(struct pvr2_ctrl *,
56*4882a593Smuzhiyun 				    const char *,unsigned int,
57*4882a593Smuzhiyun 				    int *mskp,int *valp);
58*4882a593Smuzhiyun typedef unsigned int (*pvr2_ctlf_get_v4lflags)(struct pvr2_ctrl *);
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun /* This structure describes a specific control.  A table of these is set up
61*4882a593Smuzhiyun    in pvrusb2-hdw.c. */
62*4882a593Smuzhiyun struct pvr2_ctl_info {
63*4882a593Smuzhiyun 	/* Control's name suitable for use as an identifier */
64*4882a593Smuzhiyun 	const char *name;
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	/* Short description of control */
67*4882a593Smuzhiyun 	const char *desc;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	/* Control's implementation */
70*4882a593Smuzhiyun 	pvr2_ctlf_get_value get_value;      /* Get its value */
71*4882a593Smuzhiyun 	pvr2_ctlf_get_value get_def_value;  /* Get its default value */
72*4882a593Smuzhiyun 	pvr2_ctlf_get_value get_min_value;  /* Get minimum allowed value */
73*4882a593Smuzhiyun 	pvr2_ctlf_get_value get_max_value;  /* Get maximum allowed value */
74*4882a593Smuzhiyun 	pvr2_ctlf_set_value set_value;      /* Set its value */
75*4882a593Smuzhiyun 	pvr2_ctlf_check_value check_value;  /* Check that value is valid */
76*4882a593Smuzhiyun 	pvr2_ctlf_val_to_sym val_to_sym;    /* Custom convert value->symbol */
77*4882a593Smuzhiyun 	pvr2_ctlf_sym_to_val sym_to_val;    /* Custom convert symbol->value */
78*4882a593Smuzhiyun 	pvr2_ctlf_is_dirty is_dirty;        /* Return true if dirty */
79*4882a593Smuzhiyun 	pvr2_ctlf_clear_dirty clear_dirty;  /* Clear dirty state */
80*4882a593Smuzhiyun 	pvr2_ctlf_get_v4lflags get_v4lflags;/* Retrieve v4l flags */
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	/* Control's type (int, enum, bitmask) */
83*4882a593Smuzhiyun 	enum pvr2_ctl_type type;
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	/* Associated V4L control ID, if any */
86*4882a593Smuzhiyun 	int v4l_id;
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	/* Associated driver internal ID, if any */
89*4882a593Smuzhiyun 	int internal_id;
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	/* Don't implicitly initialize this control's value */
92*4882a593Smuzhiyun 	int skip_init;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	/* Starting value for this control */
95*4882a593Smuzhiyun 	int default_value;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	/* Type-specific control information */
98*4882a593Smuzhiyun 	union {
99*4882a593Smuzhiyun 		struct { /* Integer control */
100*4882a593Smuzhiyun 			long min_value; /* lower limit */
101*4882a593Smuzhiyun 			long max_value; /* upper limit */
102*4882a593Smuzhiyun 		} type_int;
103*4882a593Smuzhiyun 		struct { /* enumerated control */
104*4882a593Smuzhiyun 			unsigned int count;       /* enum value count */
105*4882a593Smuzhiyun 			const char * const *value_names; /* symbol names */
106*4882a593Smuzhiyun 		} type_enum;
107*4882a593Smuzhiyun 		struct { /* bitmask control */
108*4882a593Smuzhiyun 			unsigned int valid_bits; /* bits in use */
109*4882a593Smuzhiyun 			const char **bit_names;  /* symbol name/bit */
110*4882a593Smuzhiyun 		} type_bitmask;
111*4882a593Smuzhiyun 	} def;
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun /* Same as pvr2_ctl_info, but includes storage for the control description */
116*4882a593Smuzhiyun #define PVR2_CTLD_INFO_DESC_SIZE 32
117*4882a593Smuzhiyun struct pvr2_ctld_info {
118*4882a593Smuzhiyun 	struct pvr2_ctl_info info;
119*4882a593Smuzhiyun 	char desc[PVR2_CTLD_INFO_DESC_SIZE];
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun struct pvr2_ctrl {
123*4882a593Smuzhiyun 	const struct pvr2_ctl_info *info;
124*4882a593Smuzhiyun 	struct pvr2_hdw *hdw;
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun /* Disposition of firmware1 loading situation */
130*4882a593Smuzhiyun #define FW1_STATE_UNKNOWN 0
131*4882a593Smuzhiyun #define FW1_STATE_MISSING 1
132*4882a593Smuzhiyun #define FW1_STATE_FAILED 2
133*4882a593Smuzhiyun #define FW1_STATE_RELOAD 3
134*4882a593Smuzhiyun #define FW1_STATE_OK 4
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun /* What state the device is in if it is a hybrid */
137*4882a593Smuzhiyun #define PVR2_PATHWAY_UNKNOWN 0
138*4882a593Smuzhiyun #define PVR2_PATHWAY_ANALOG 1
139*4882a593Smuzhiyun #define PVR2_PATHWAY_DIGITAL 2
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun typedef int (*pvr2_i2c_func)(struct pvr2_hdw *,u8,u8 *,u16,u8 *, u16);
142*4882a593Smuzhiyun #define PVR2_I2C_FUNC_CNT 128
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun /* This structure contains all state data directly needed to
145*4882a593Smuzhiyun    manipulate the hardware (as opposed to complying with a kernel
146*4882a593Smuzhiyun    interface) */
147*4882a593Smuzhiyun struct pvr2_hdw {
148*4882a593Smuzhiyun 	/* Underlying USB device handle */
149*4882a593Smuzhiyun 	struct usb_device *usb_dev;
150*4882a593Smuzhiyun 	struct usb_interface *usb_intf;
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	/* Our handle into the v4l2 sub-device architecture */
153*4882a593Smuzhiyun 	struct v4l2_device v4l2_dev;
154*4882a593Smuzhiyun 	/* Device description, anything that must adjust behavior based on
155*4882a593Smuzhiyun 	   device specific info will use information held here. */
156*4882a593Smuzhiyun 	const struct pvr2_device_desc *hdw_desc;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	/* Kernel worker thread handling */
159*4882a593Smuzhiyun 	struct work_struct workpoll;     /* Update driver state */
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	/* Video spigot */
162*4882a593Smuzhiyun 	struct pvr2_stream *vid_stream;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	/* Mutex for all hardware state control */
165*4882a593Smuzhiyun 	struct mutex big_lock_mutex;
166*4882a593Smuzhiyun 	int big_lock_held;  /* For debugging */
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	/* This is a simple string which identifies the instance of this
169*4882a593Smuzhiyun 	   driver.  It is unique within the set of existing devices, but
170*4882a593Smuzhiyun 	   there is no attempt to keep the name consistent with the same
171*4882a593Smuzhiyun 	   physical device each time. */
172*4882a593Smuzhiyun 	char name[32];
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	/* This is a simple string which identifies the physical device
175*4882a593Smuzhiyun 	   instance itself - if possible.  (If not possible, then it is
176*4882a593Smuzhiyun 	   based on the specific driver instance, similar to name above.)
177*4882a593Smuzhiyun 	   The idea here is that userspace might hopefully be able to use
178*4882a593Smuzhiyun 	   this recognize specific tuners.  It will encode a serial number,
179*4882a593Smuzhiyun 	   if available. */
180*4882a593Smuzhiyun 	char identifier[32];
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	/* I2C stuff */
183*4882a593Smuzhiyun 	struct i2c_adapter i2c_adap;
184*4882a593Smuzhiyun 	struct i2c_algorithm i2c_algo;
185*4882a593Smuzhiyun 	pvr2_i2c_func i2c_func[PVR2_I2C_FUNC_CNT];
186*4882a593Smuzhiyun 	int i2c_cx25840_hack_state;
187*4882a593Smuzhiyun 	int i2c_linked;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	/* IR related */
190*4882a593Smuzhiyun 	unsigned int ir_scheme_active; /* IR scheme as seen from the outside */
191*4882a593Smuzhiyun 	struct IR_i2c_init_data ir_init_data; /* params passed to IR modules */
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	/* Frequency table */
194*4882a593Smuzhiyun 	unsigned int freqTable[FREQTABLE_SIZE];
195*4882a593Smuzhiyun 	unsigned int freqProgSlot;
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	/* Stuff for handling low level control interaction with device */
198*4882a593Smuzhiyun 	struct mutex ctl_lock_mutex;
199*4882a593Smuzhiyun 	int ctl_lock_held;  /* For debugging */
200*4882a593Smuzhiyun 	struct urb *ctl_write_urb;
201*4882a593Smuzhiyun 	struct urb *ctl_read_urb;
202*4882a593Smuzhiyun 	unsigned char *ctl_write_buffer;
203*4882a593Smuzhiyun 	unsigned char *ctl_read_buffer;
204*4882a593Smuzhiyun 	int ctl_write_pend_flag;
205*4882a593Smuzhiyun 	int ctl_read_pend_flag;
206*4882a593Smuzhiyun 	int ctl_timeout_flag;
207*4882a593Smuzhiyun 	struct completion ctl_done;
208*4882a593Smuzhiyun 	unsigned char cmd_buffer[PVR2_CTL_BUFFSIZE];
209*4882a593Smuzhiyun 	int cmd_debug_state;               // Low level command debugging info
210*4882a593Smuzhiyun 	unsigned char cmd_debug_code;      //
211*4882a593Smuzhiyun 	unsigned int cmd_debug_write_len;  //
212*4882a593Smuzhiyun 	unsigned int cmd_debug_read_len;   //
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	/* Bits of state that describe what is going on with various parts
215*4882a593Smuzhiyun 	   of the driver. */
216*4882a593Smuzhiyun 	int state_pathway_ok;         /* Pathway config is ok */
217*4882a593Smuzhiyun 	int state_encoder_ok;         /* Encoder is operational */
218*4882a593Smuzhiyun 	int state_encoder_run;        /* Encoder is running */
219*4882a593Smuzhiyun 	int state_encoder_config;     /* Encoder is configured */
220*4882a593Smuzhiyun 	int state_encoder_waitok;     /* Encoder pre-wait done */
221*4882a593Smuzhiyun 	int state_encoder_runok;      /* Encoder has run for >= .25 sec */
222*4882a593Smuzhiyun 	int state_decoder_run;        /* Decoder is running */
223*4882a593Smuzhiyun 	int state_decoder_ready;      /* Decoder is stabilized & streamable */
224*4882a593Smuzhiyun 	int state_usbstream_run;      /* FX2 is streaming */
225*4882a593Smuzhiyun 	int state_decoder_quiescent;  /* Decoder idle for minimal interval */
226*4882a593Smuzhiyun 	int state_pipeline_config;    /* Pipeline is configured */
227*4882a593Smuzhiyun 	int state_pipeline_req;       /* Somebody wants to stream */
228*4882a593Smuzhiyun 	int state_pipeline_pause;     /* Pipeline must be paused */
229*4882a593Smuzhiyun 	int state_pipeline_idle;      /* Pipeline not running */
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	/* This is the master state of the driver.  It is the combined
232*4882a593Smuzhiyun 	   result of other bits of state.  Examining this will indicate the
233*4882a593Smuzhiyun 	   overall state of the driver.  Values here are one of
234*4882a593Smuzhiyun 	   PVR2_STATE_xxxx */
235*4882a593Smuzhiyun 	unsigned int master_state;
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	/* True if device led is currently on */
238*4882a593Smuzhiyun 	int led_on;
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	/* True if states must be re-evaluated */
241*4882a593Smuzhiyun 	int state_stale;
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	void (*state_func)(void *);
244*4882a593Smuzhiyun 	void *state_data;
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	/* Timer for measuring required decoder settling time before we're
247*4882a593Smuzhiyun 	   allowed to fire it up again. */
248*4882a593Smuzhiyun 	struct timer_list quiescent_timer;
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	/* Timer for measuring decoder stabilization time, which is the
251*4882a593Smuzhiyun 	   amount of time we need to let the decoder run before we can
252*4882a593Smuzhiyun 	   trust its output (otherwise the encoder might see garbage and
253*4882a593Smuzhiyun 	   then fail to start correctly). */
254*4882a593Smuzhiyun 	struct timer_list decoder_stabilization_timer;
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	/* Timer for measuring encoder pre-wait time */
257*4882a593Smuzhiyun 	struct timer_list encoder_wait_timer;
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	/* Timer for measuring encoder minimum run time */
260*4882a593Smuzhiyun 	struct timer_list encoder_run_timer;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	/* Place to block while waiting for state changes */
263*4882a593Smuzhiyun 	wait_queue_head_t state_wait_data;
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	int force_dirty;        /* consider all controls dirty if true */
267*4882a593Smuzhiyun 	int flag_ok;            /* device in known good state */
268*4882a593Smuzhiyun 	int flag_modulefail;    /* true if at least one module failed to load */
269*4882a593Smuzhiyun 	int flag_disconnected;  /* flag_ok == 0 due to disconnect */
270*4882a593Smuzhiyun 	int flag_init_ok;       /* true if structure is fully initialized */
271*4882a593Smuzhiyun 	int fw1_state;          /* current situation with fw1 */
272*4882a593Smuzhiyun 	int pathway_state;      /* one of PVR2_PATHWAY_xxx */
273*4882a593Smuzhiyun 	int flag_decoder_missed;/* We've noticed missing decoder */
274*4882a593Smuzhiyun 	int flag_tripped;       /* Indicates overall failure to start */
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	unsigned int decoder_client_id;
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	// CPU firmware info (used to help find / save firmware data)
279*4882a593Smuzhiyun 	char *fw_buffer;
280*4882a593Smuzhiyun 	unsigned int fw_size;
281*4882a593Smuzhiyun 	int fw_cpu_flag; /* True if we are dealing with the CPU */
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 	/* Tuner / frequency control stuff */
284*4882a593Smuzhiyun 	unsigned int tuner_type;
285*4882a593Smuzhiyun 	int tuner_updated;
286*4882a593Smuzhiyun 	unsigned int freqValTelevision;  /* Current freq for tv mode */
287*4882a593Smuzhiyun 	unsigned int freqValRadio;       /* Current freq for radio mode */
288*4882a593Smuzhiyun 	unsigned int freqSlotTelevision; /* Current slot for tv mode */
289*4882a593Smuzhiyun 	unsigned int freqSlotRadio;      /* Current slot for radio mode */
290*4882a593Smuzhiyun 	unsigned int freqSelector;       /* 0=radio 1=television */
291*4882a593Smuzhiyun 	int freqDirty;
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	/* Current tuner info - this information is polled from the I2C bus */
294*4882a593Smuzhiyun 	struct v4l2_tuner tuner_signal_info;
295*4882a593Smuzhiyun 	int tuner_signal_stale;
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 	/* Cropping capability info */
298*4882a593Smuzhiyun 	struct v4l2_cropcap cropcap_info;
299*4882a593Smuzhiyun 	int cropcap_stale;
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	/* Video standard handling */
302*4882a593Smuzhiyun 	v4l2_std_id std_mask_eeprom; // Hardware supported selections
303*4882a593Smuzhiyun 	v4l2_std_id std_mask_avail;  // Which standards we may select from
304*4882a593Smuzhiyun 	v4l2_std_id std_mask_cur;    // Currently selected standard(s)
305*4882a593Smuzhiyun 	int std_enum_cur;            // selected standard enumeration value
306*4882a593Smuzhiyun 	int std_dirty;               // True if std_mask_cur has changed
307*4882a593Smuzhiyun 	struct pvr2_ctl_info std_info_enum;
308*4882a593Smuzhiyun 	struct pvr2_ctl_info std_info_avail;
309*4882a593Smuzhiyun 	struct pvr2_ctl_info std_info_cur;
310*4882a593Smuzhiyun 	struct pvr2_ctl_info std_info_detect;
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	// Generated string names, one per actual V4L2 standard
313*4882a593Smuzhiyun 	const char *std_mask_ptrs[32];
314*4882a593Smuzhiyun 	char std_mask_names[32][16];
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 	int unit_number;             /* ID for driver instance */
317*4882a593Smuzhiyun 	unsigned long serial_number; /* ID for hardware itself */
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	char bus_info[32]; /* Bus location info */
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	/* Minor numbers used by v4l logic (yes, this is a hack, as there
322*4882a593Smuzhiyun 	   should be no v4l junk here).  Probably a better way to do this. */
323*4882a593Smuzhiyun 	int v4l_minor_number_video;
324*4882a593Smuzhiyun 	int v4l_minor_number_vbi;
325*4882a593Smuzhiyun 	int v4l_minor_number_radio;
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	/* Bit mask of PVR2_CVAL_INPUT choices which are valid for the hardware */
328*4882a593Smuzhiyun 	unsigned int input_avail_mask;
329*4882a593Smuzhiyun 	/* Bit mask of PVR2_CVAL_INPUT choices which are currently allowed */
330*4882a593Smuzhiyun 	unsigned int input_allowed_mask;
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	/* Location of eeprom or a negative number if none */
333*4882a593Smuzhiyun 	int eeprom_addr;
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 	enum pvr2_config active_stream_type;
336*4882a593Smuzhiyun 	enum pvr2_config desired_stream_type;
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 	/* Control state needed for cx2341x module */
339*4882a593Smuzhiyun 	struct cx2341x_mpeg_params enc_cur_state;
340*4882a593Smuzhiyun 	struct cx2341x_mpeg_params enc_ctl_state;
341*4882a593Smuzhiyun 	/* True if an encoder attribute has changed */
342*4882a593Smuzhiyun 	int enc_stale;
343*4882a593Smuzhiyun 	/* True if an unsafe encoder attribute has changed */
344*4882a593Smuzhiyun 	int enc_unsafe_stale;
345*4882a593Smuzhiyun 	/* True if enc_cur_state is valid */
346*4882a593Smuzhiyun 	int enc_cur_valid;
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	/* Control state */
349*4882a593Smuzhiyun #define VCREATE_DATA(lab) int lab##_val; int lab##_dirty
350*4882a593Smuzhiyun 	VCREATE_DATA(brightness);
351*4882a593Smuzhiyun 	VCREATE_DATA(contrast);
352*4882a593Smuzhiyun 	VCREATE_DATA(saturation);
353*4882a593Smuzhiyun 	VCREATE_DATA(hue);
354*4882a593Smuzhiyun 	VCREATE_DATA(volume);
355*4882a593Smuzhiyun 	VCREATE_DATA(balance);
356*4882a593Smuzhiyun 	VCREATE_DATA(bass);
357*4882a593Smuzhiyun 	VCREATE_DATA(treble);
358*4882a593Smuzhiyun 	VCREATE_DATA(mute);
359*4882a593Smuzhiyun 	VCREATE_DATA(cropl);
360*4882a593Smuzhiyun 	VCREATE_DATA(cropt);
361*4882a593Smuzhiyun 	VCREATE_DATA(cropw);
362*4882a593Smuzhiyun 	VCREATE_DATA(croph);
363*4882a593Smuzhiyun 	VCREATE_DATA(input);
364*4882a593Smuzhiyun 	VCREATE_DATA(audiomode);
365*4882a593Smuzhiyun 	VCREATE_DATA(res_hor);
366*4882a593Smuzhiyun 	VCREATE_DATA(res_ver);
367*4882a593Smuzhiyun 	VCREATE_DATA(srate);
368*4882a593Smuzhiyun #undef VCREATE_DATA
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun 	struct pvr2_ctld_info *mpeg_ctrl_info;
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	struct pvr2_ctrl *controls;
373*4882a593Smuzhiyun 	unsigned int control_cnt;
374*4882a593Smuzhiyun };
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun /* This function gets the current frequency */
377*4882a593Smuzhiyun unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *);
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun void pvr2_hdw_status_poll(struct pvr2_hdw *);
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun #endif /* __PVRUSB2_HDW_INTERNAL_H */
382