xref: /OK3568_Linux_fs/kernel/drivers/media/usb/pvrusb2/pvrusb2-encoder.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
5*4882a593Smuzhiyun  *  Copyright (C) 2004 Aurelien Alleaume <slts@free.fr>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/device.h>   // for linux/firmware.h
9*4882a593Smuzhiyun #include <linux/firmware.h>
10*4882a593Smuzhiyun #include "pvrusb2-util.h"
11*4882a593Smuzhiyun #include "pvrusb2-encoder.h"
12*4882a593Smuzhiyun #include "pvrusb2-hdw-internal.h"
13*4882a593Smuzhiyun #include "pvrusb2-debug.h"
14*4882a593Smuzhiyun #include "pvrusb2-fx2-cmd.h"
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun /* Firmware mailbox flags - definitions found from ivtv */
19*4882a593Smuzhiyun #define IVTV_MBOX_FIRMWARE_DONE 0x00000004
20*4882a593Smuzhiyun #define IVTV_MBOX_DRIVER_DONE 0x00000002
21*4882a593Smuzhiyun #define IVTV_MBOX_DRIVER_BUSY 0x00000001
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define MBOX_BASE 0x44
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun 
pvr2_encoder_write_words(struct pvr2_hdw * hdw,unsigned int offs,const u32 * data,unsigned int dlen)26*4882a593Smuzhiyun static int pvr2_encoder_write_words(struct pvr2_hdw *hdw,
27*4882a593Smuzhiyun 				    unsigned int offs,
28*4882a593Smuzhiyun 				    const u32 *data, unsigned int dlen)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun 	unsigned int idx,addr;
31*4882a593Smuzhiyun 	unsigned int bAddr;
32*4882a593Smuzhiyun 	int ret;
33*4882a593Smuzhiyun 	unsigned int chunkCnt;
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun 	/*
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun 	Format: First byte must be 0x01.  Remaining 32 bit words are
38*4882a593Smuzhiyun 	spread out into chunks of 7 bytes each, with the first 4 bytes
39*4882a593Smuzhiyun 	being the data word (little endian), and the next 3 bytes
40*4882a593Smuzhiyun 	being the address where that data word is to be written (big
41*4882a593Smuzhiyun 	endian).  Repeat request for additional words, with offset
42*4882a593Smuzhiyun 	adjusted accordingly.
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun 	*/
45*4882a593Smuzhiyun 	while (dlen) {
46*4882a593Smuzhiyun 		chunkCnt = 8;
47*4882a593Smuzhiyun 		if (chunkCnt > dlen) chunkCnt = dlen;
48*4882a593Smuzhiyun 		memset(hdw->cmd_buffer,0,sizeof(hdw->cmd_buffer));
49*4882a593Smuzhiyun 		bAddr = 0;
50*4882a593Smuzhiyun 		hdw->cmd_buffer[bAddr++] = FX2CMD_MEM_WRITE_DWORD;
51*4882a593Smuzhiyun 		for (idx = 0; idx < chunkCnt; idx++) {
52*4882a593Smuzhiyun 			addr = idx + offs;
53*4882a593Smuzhiyun 			hdw->cmd_buffer[bAddr+6] = (addr & 0xffu);
54*4882a593Smuzhiyun 			hdw->cmd_buffer[bAddr+5] = ((addr>>8) & 0xffu);
55*4882a593Smuzhiyun 			hdw->cmd_buffer[bAddr+4] = ((addr>>16) & 0xffu);
56*4882a593Smuzhiyun 			PVR2_DECOMPOSE_LE(hdw->cmd_buffer, bAddr,data[idx]);
57*4882a593Smuzhiyun 			bAddr += 7;
58*4882a593Smuzhiyun 		}
59*4882a593Smuzhiyun 		ret = pvr2_send_request(hdw,
60*4882a593Smuzhiyun 					hdw->cmd_buffer,1+(chunkCnt*7),
61*4882a593Smuzhiyun 					NULL,0);
62*4882a593Smuzhiyun 		if (ret) return ret;
63*4882a593Smuzhiyun 		data += chunkCnt;
64*4882a593Smuzhiyun 		dlen -= chunkCnt;
65*4882a593Smuzhiyun 		offs += chunkCnt;
66*4882a593Smuzhiyun 	}
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	return 0;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 
pvr2_encoder_read_words(struct pvr2_hdw * hdw,unsigned int offs,u32 * data,unsigned int dlen)72*4882a593Smuzhiyun static int pvr2_encoder_read_words(struct pvr2_hdw *hdw,
73*4882a593Smuzhiyun 				   unsigned int offs,
74*4882a593Smuzhiyun 				   u32 *data, unsigned int dlen)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun 	unsigned int idx;
77*4882a593Smuzhiyun 	int ret;
78*4882a593Smuzhiyun 	unsigned int chunkCnt;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	/*
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	Format: First byte must be 0x02 (status check) or 0x28 (read
83*4882a593Smuzhiyun 	back block of 32 bit words).  Next 6 bytes must be zero,
84*4882a593Smuzhiyun 	followed by a single byte of MBOX_BASE+offset for portion to
85*4882a593Smuzhiyun 	be read.  Returned data is packed set of 32 bits words that
86*4882a593Smuzhiyun 	were read.
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	*/
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	while (dlen) {
91*4882a593Smuzhiyun 		chunkCnt = 16;
92*4882a593Smuzhiyun 		if (chunkCnt > dlen) chunkCnt = dlen;
93*4882a593Smuzhiyun 		if (chunkCnt < 16) chunkCnt = 1;
94*4882a593Smuzhiyun 		hdw->cmd_buffer[0] =
95*4882a593Smuzhiyun 			((chunkCnt == 1) ?
96*4882a593Smuzhiyun 			 FX2CMD_MEM_READ_DWORD : FX2CMD_MEM_READ_64BYTES);
97*4882a593Smuzhiyun 		hdw->cmd_buffer[1] = 0;
98*4882a593Smuzhiyun 		hdw->cmd_buffer[2] = 0;
99*4882a593Smuzhiyun 		hdw->cmd_buffer[3] = 0;
100*4882a593Smuzhiyun 		hdw->cmd_buffer[4] = 0;
101*4882a593Smuzhiyun 		hdw->cmd_buffer[5] = ((offs>>16) & 0xffu);
102*4882a593Smuzhiyun 		hdw->cmd_buffer[6] = ((offs>>8) & 0xffu);
103*4882a593Smuzhiyun 		hdw->cmd_buffer[7] = (offs & 0xffu);
104*4882a593Smuzhiyun 		ret = pvr2_send_request(hdw,
105*4882a593Smuzhiyun 					hdw->cmd_buffer,8,
106*4882a593Smuzhiyun 					hdw->cmd_buffer,
107*4882a593Smuzhiyun 					(chunkCnt == 1 ? 4 : 16 * 4));
108*4882a593Smuzhiyun 		if (ret) return ret;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 		for (idx = 0; idx < chunkCnt; idx++) {
111*4882a593Smuzhiyun 			data[idx] = PVR2_COMPOSE_LE(hdw->cmd_buffer,idx*4);
112*4882a593Smuzhiyun 		}
113*4882a593Smuzhiyun 		data += chunkCnt;
114*4882a593Smuzhiyun 		dlen -= chunkCnt;
115*4882a593Smuzhiyun 		offs += chunkCnt;
116*4882a593Smuzhiyun 	}
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	return 0;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun /* This prototype is set up to be compatible with the
123*4882a593Smuzhiyun    cx2341x_mbox_func prototype in cx2341x.h, which should be in
124*4882a593Smuzhiyun    kernels 2.6.18 or later.  We do this so that we can enable
125*4882a593Smuzhiyun    cx2341x.ko to write to our encoder (by handing it a pointer to this
126*4882a593Smuzhiyun    function).  For earlier kernels this doesn't really matter. */
pvr2_encoder_cmd(void * ctxt,u32 cmd,int arg_cnt_send,int arg_cnt_recv,u32 * argp)127*4882a593Smuzhiyun static int pvr2_encoder_cmd(void *ctxt,
128*4882a593Smuzhiyun 			    u32 cmd,
129*4882a593Smuzhiyun 			    int arg_cnt_send,
130*4882a593Smuzhiyun 			    int arg_cnt_recv,
131*4882a593Smuzhiyun 			    u32 *argp)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun 	unsigned int poll_count;
134*4882a593Smuzhiyun 	unsigned int try_count = 0;
135*4882a593Smuzhiyun 	int retry_flag;
136*4882a593Smuzhiyun 	int ret = 0;
137*4882a593Smuzhiyun 	unsigned int idx;
138*4882a593Smuzhiyun 	/* These sizes look to be limited by the FX2 firmware implementation */
139*4882a593Smuzhiyun 	u32 wrData[16];
140*4882a593Smuzhiyun 	u32 rdData[16];
141*4882a593Smuzhiyun 	struct pvr2_hdw *hdw = (struct pvr2_hdw *)ctxt;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	/*
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	The encoder seems to speak entirely using blocks 32 bit words.
147*4882a593Smuzhiyun 	In ivtv driver terms, this is a mailbox at MBOX_BASE which we
148*4882a593Smuzhiyun 	populate with data and watch what the hardware does with it.
149*4882a593Smuzhiyun 	The first word is a set of flags used to control the
150*4882a593Smuzhiyun 	transaction, the second word is the command to execute, the
151*4882a593Smuzhiyun 	third byte is zero (ivtv driver suggests that this is some
152*4882a593Smuzhiyun 	kind of return value), and the fourth byte is a specified
153*4882a593Smuzhiyun 	timeout (windows driver always uses 0x00060000 except for one
154*4882a593Smuzhiyun 	case when it is zero).  All successive words are the argument
155*4882a593Smuzhiyun 	words for the command.
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	First, write out the entire set of words, with the first word
158*4882a593Smuzhiyun 	being zero.
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	Next, write out just the first word again, but set it to
161*4882a593Smuzhiyun 	IVTV_MBOX_DRIVER_DONE | IVTV_DRIVER_BUSY this time (which
162*4882a593Smuzhiyun 	probably means "go").
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	Next, read back the return count words.  Check the first word,
165*4882a593Smuzhiyun 	which should have IVTV_MBOX_FIRMWARE_DONE set.  If however
166*4882a593Smuzhiyun 	that bit is not set, then the command isn't done so repeat the
167*4882a593Smuzhiyun 	read until it is set.
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	Finally, write out just the first word again, but set it to
170*4882a593Smuzhiyun 	0x0 this time (which probably means "idle").
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	*/
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	if (arg_cnt_send > (ARRAY_SIZE(wrData) - 4)) {
175*4882a593Smuzhiyun 		pvr2_trace(
176*4882a593Smuzhiyun 			PVR2_TRACE_ERROR_LEGS,
177*4882a593Smuzhiyun 			"Failed to write cx23416 command - too many input arguments (was given %u limit %lu)",
178*4882a593Smuzhiyun 			arg_cnt_send, (long unsigned) ARRAY_SIZE(wrData) - 4);
179*4882a593Smuzhiyun 		return -EINVAL;
180*4882a593Smuzhiyun 	}
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	if (arg_cnt_recv > (ARRAY_SIZE(rdData) - 4)) {
183*4882a593Smuzhiyun 		pvr2_trace(
184*4882a593Smuzhiyun 			PVR2_TRACE_ERROR_LEGS,
185*4882a593Smuzhiyun 			"Failed to write cx23416 command - too many return arguments (was given %u limit %lu)",
186*4882a593Smuzhiyun 			arg_cnt_recv, (long unsigned) ARRAY_SIZE(rdData) - 4);
187*4882a593Smuzhiyun 		return -EINVAL;
188*4882a593Smuzhiyun 	}
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	LOCK_TAKE(hdw->ctl_lock); while (1) {
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 		if (!hdw->state_encoder_ok) {
194*4882a593Smuzhiyun 			ret = -EIO;
195*4882a593Smuzhiyun 			break;
196*4882a593Smuzhiyun 		}
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 		retry_flag = 0;
199*4882a593Smuzhiyun 		try_count++;
200*4882a593Smuzhiyun 		ret = 0;
201*4882a593Smuzhiyun 		wrData[0] = 0;
202*4882a593Smuzhiyun 		wrData[1] = cmd;
203*4882a593Smuzhiyun 		wrData[2] = 0;
204*4882a593Smuzhiyun 		wrData[3] = 0x00060000;
205*4882a593Smuzhiyun 		for (idx = 0; idx < arg_cnt_send; idx++) {
206*4882a593Smuzhiyun 			wrData[idx+4] = argp[idx];
207*4882a593Smuzhiyun 		}
208*4882a593Smuzhiyun 		for (; idx < ARRAY_SIZE(wrData) - 4; idx++) {
209*4882a593Smuzhiyun 			wrData[idx+4] = 0;
210*4882a593Smuzhiyun 		}
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 		ret = pvr2_encoder_write_words(hdw,MBOX_BASE,wrData,idx);
213*4882a593Smuzhiyun 		if (ret) break;
214*4882a593Smuzhiyun 		wrData[0] = IVTV_MBOX_DRIVER_DONE|IVTV_MBOX_DRIVER_BUSY;
215*4882a593Smuzhiyun 		ret = pvr2_encoder_write_words(hdw,MBOX_BASE,wrData,1);
216*4882a593Smuzhiyun 		if (ret) break;
217*4882a593Smuzhiyun 		poll_count = 0;
218*4882a593Smuzhiyun 		while (1) {
219*4882a593Smuzhiyun 			poll_count++;
220*4882a593Smuzhiyun 			ret = pvr2_encoder_read_words(hdw,MBOX_BASE,rdData,
221*4882a593Smuzhiyun 						      arg_cnt_recv+4);
222*4882a593Smuzhiyun 			if (ret) {
223*4882a593Smuzhiyun 				break;
224*4882a593Smuzhiyun 			}
225*4882a593Smuzhiyun 			if (rdData[0] & IVTV_MBOX_FIRMWARE_DONE) {
226*4882a593Smuzhiyun 				break;
227*4882a593Smuzhiyun 			}
228*4882a593Smuzhiyun 			if (rdData[0] && (poll_count < 1000)) continue;
229*4882a593Smuzhiyun 			if (!rdData[0]) {
230*4882a593Smuzhiyun 				retry_flag = !0;
231*4882a593Smuzhiyun 				pvr2_trace(
232*4882a593Smuzhiyun 					PVR2_TRACE_ERROR_LEGS,
233*4882a593Smuzhiyun 					"Encoder timed out waiting for us; arranging to retry");
234*4882a593Smuzhiyun 			} else {
235*4882a593Smuzhiyun 				pvr2_trace(
236*4882a593Smuzhiyun 					PVR2_TRACE_ERROR_LEGS,
237*4882a593Smuzhiyun 					"***WARNING*** device's encoder appears to be stuck (status=0x%08x)",
238*4882a593Smuzhiyun rdData[0]);
239*4882a593Smuzhiyun 			}
240*4882a593Smuzhiyun 			pvr2_trace(
241*4882a593Smuzhiyun 				PVR2_TRACE_ERROR_LEGS,
242*4882a593Smuzhiyun 				"Encoder command: 0x%02x",cmd);
243*4882a593Smuzhiyun 			for (idx = 4; idx < arg_cnt_send; idx++) {
244*4882a593Smuzhiyun 				pvr2_trace(
245*4882a593Smuzhiyun 					PVR2_TRACE_ERROR_LEGS,
246*4882a593Smuzhiyun 					"Encoder arg%d: 0x%08x",
247*4882a593Smuzhiyun 					idx-3,wrData[idx]);
248*4882a593Smuzhiyun 			}
249*4882a593Smuzhiyun 			ret = -EBUSY;
250*4882a593Smuzhiyun 			break;
251*4882a593Smuzhiyun 		}
252*4882a593Smuzhiyun 		if (retry_flag) {
253*4882a593Smuzhiyun 			if (try_count < 20) continue;
254*4882a593Smuzhiyun 			pvr2_trace(
255*4882a593Smuzhiyun 				PVR2_TRACE_ERROR_LEGS,
256*4882a593Smuzhiyun 				"Too many retries...");
257*4882a593Smuzhiyun 			ret = -EBUSY;
258*4882a593Smuzhiyun 		}
259*4882a593Smuzhiyun 		if (ret) {
260*4882a593Smuzhiyun 			del_timer_sync(&hdw->encoder_run_timer);
261*4882a593Smuzhiyun 			hdw->state_encoder_ok = 0;
262*4882a593Smuzhiyun 			pvr2_trace(PVR2_TRACE_STBITS,
263*4882a593Smuzhiyun 				   "State bit %s <-- %s",
264*4882a593Smuzhiyun 				   "state_encoder_ok",
265*4882a593Smuzhiyun 				   (hdw->state_encoder_ok ? "true" : "false"));
266*4882a593Smuzhiyun 			if (hdw->state_encoder_runok) {
267*4882a593Smuzhiyun 				hdw->state_encoder_runok = 0;
268*4882a593Smuzhiyun 				pvr2_trace(PVR2_TRACE_STBITS,
269*4882a593Smuzhiyun 				   "State bit %s <-- %s",
270*4882a593Smuzhiyun 					   "state_encoder_runok",
271*4882a593Smuzhiyun 					   (hdw->state_encoder_runok ?
272*4882a593Smuzhiyun 					    "true" : "false"));
273*4882a593Smuzhiyun 			}
274*4882a593Smuzhiyun 			pvr2_trace(
275*4882a593Smuzhiyun 				PVR2_TRACE_ERROR_LEGS,
276*4882a593Smuzhiyun 				"Giving up on command.  This is normally recovered via a firmware reload and re-initialization; concern is only warranted if this happens repeatedly and rapidly.");
277*4882a593Smuzhiyun 			break;
278*4882a593Smuzhiyun 		}
279*4882a593Smuzhiyun 		wrData[0] = 0x7;
280*4882a593Smuzhiyun 		for (idx = 0; idx < arg_cnt_recv; idx++) {
281*4882a593Smuzhiyun 			argp[idx] = rdData[idx+4];
282*4882a593Smuzhiyun 		}
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 		wrData[0] = 0x0;
285*4882a593Smuzhiyun 		ret = pvr2_encoder_write_words(hdw,MBOX_BASE,wrData,1);
286*4882a593Smuzhiyun 		break;
287*4882a593Smuzhiyun 	}
288*4882a593Smuzhiyun 	LOCK_GIVE(hdw->ctl_lock);
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	return ret;
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 
pvr2_encoder_vcmd(struct pvr2_hdw * hdw,int cmd,int args,...)294*4882a593Smuzhiyun static int pvr2_encoder_vcmd(struct pvr2_hdw *hdw, int cmd,
295*4882a593Smuzhiyun 			     int args, ...)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun 	va_list vl;
298*4882a593Smuzhiyun 	unsigned int idx;
299*4882a593Smuzhiyun 	u32 data[12];
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	if (args > ARRAY_SIZE(data)) {
302*4882a593Smuzhiyun 		pvr2_trace(
303*4882a593Smuzhiyun 			PVR2_TRACE_ERROR_LEGS,
304*4882a593Smuzhiyun 			"Failed to write cx23416 command - too many arguments (was given %u limit %lu)",
305*4882a593Smuzhiyun 			args, (long unsigned) ARRAY_SIZE(data));
306*4882a593Smuzhiyun 		return -EINVAL;
307*4882a593Smuzhiyun 	}
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	va_start(vl, args);
310*4882a593Smuzhiyun 	for (idx = 0; idx < args; idx++) {
311*4882a593Smuzhiyun 		data[idx] = va_arg(vl, u32);
312*4882a593Smuzhiyun 	}
313*4882a593Smuzhiyun 	va_end(vl);
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	return pvr2_encoder_cmd(hdw,cmd,args,0,data);
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun /* This implements some extra setup for the encoder that seems to be
320*4882a593Smuzhiyun    specific to the PVR USB2 hardware. */
pvr2_encoder_prep_config(struct pvr2_hdw * hdw)321*4882a593Smuzhiyun static int pvr2_encoder_prep_config(struct pvr2_hdw *hdw)
322*4882a593Smuzhiyun {
323*4882a593Smuzhiyun 	int ret = 0;
324*4882a593Smuzhiyun 	int encMisc3Arg = 0;
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun #if 0
327*4882a593Smuzhiyun 	/* This inexplicable bit happens in the Hauppauge windows
328*4882a593Smuzhiyun 	   driver (for both 24xxx and 29xxx devices).  However I
329*4882a593Smuzhiyun 	   currently see no difference in behavior with or without
330*4882a593Smuzhiyun 	   this stuff.  Leave this here as a note of its existence,
331*4882a593Smuzhiyun 	   but don't use it. */
332*4882a593Smuzhiyun 	LOCK_TAKE(hdw->ctl_lock); do {
333*4882a593Smuzhiyun 		u32 dat[1];
334*4882a593Smuzhiyun 		dat[0] = 0x80000640;
335*4882a593Smuzhiyun 		pvr2_encoder_write_words(hdw,0x01fe,dat,1);
336*4882a593Smuzhiyun 		pvr2_encoder_write_words(hdw,0x023e,dat,1);
337*4882a593Smuzhiyun 	} while(0); LOCK_GIVE(hdw->ctl_lock);
338*4882a593Smuzhiyun #endif
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	/* Mike Isely <isely@pobox.com> 26-Jan-2006 The windows driver
341*4882a593Smuzhiyun 	   sends the following list of ENC_MISC commands (for both
342*4882a593Smuzhiyun 	   24xxx and 29xxx devices).  Meanings are not entirely clear,
343*4882a593Smuzhiyun 	   however without the ENC_MISC(3,1) command then we risk
344*4882a593Smuzhiyun 	   random perpetual video corruption whenever the video input
345*4882a593Smuzhiyun 	   breaks up for a moment (like when switching channels). */
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun #if 0
349*4882a593Smuzhiyun 	/* This ENC_MISC(5,0) command seems to hurt 29xxx sync
350*4882a593Smuzhiyun 	   performance on channel changes, but is not a problem on
351*4882a593Smuzhiyun 	   24xxx devices. */
352*4882a593Smuzhiyun 	ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 5,0,0,0);
353*4882a593Smuzhiyun #endif
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	/* This ENC_MISC(3,encMisc3Arg) command is critical - without
356*4882a593Smuzhiyun 	   it there will eventually be video corruption.  Also, the
357*4882a593Smuzhiyun 	   saa7115 case is strange - the Windows driver is passing 1
358*4882a593Smuzhiyun 	   regardless of device type but if we have 1 for saa7115
359*4882a593Smuzhiyun 	   devices the video turns sluggish.  */
360*4882a593Smuzhiyun 	if (hdw->hdw_desc->flag_has_cx25840) {
361*4882a593Smuzhiyun 		encMisc3Arg = 1;
362*4882a593Smuzhiyun 	} else {
363*4882a593Smuzhiyun 		encMisc3Arg = 0;
364*4882a593Smuzhiyun 	}
365*4882a593Smuzhiyun 	ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 3,
366*4882a593Smuzhiyun 				 encMisc3Arg,0,0);
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 8,0,0,0);
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun #if 0
371*4882a593Smuzhiyun 	/* This ENC_MISC(4,1) command is poisonous, so it is commented
372*4882a593Smuzhiyun 	   out.  But I'm leaving it here anyway to document its
373*4882a593Smuzhiyun 	   existence in the Windows driver.  The effect of this
374*4882a593Smuzhiyun 	   command is that apps displaying the stream become sluggish
375*4882a593Smuzhiyun 	   with stuttering video. */
376*4882a593Smuzhiyun 	ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 4,1,0,0);
377*4882a593Smuzhiyun #endif
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun 	ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 0,3,0,0);
380*4882a593Smuzhiyun 	ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4,15,0,0,0);
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	/* prevent the PTSs from slowly drifting away in the generated
383*4882a593Smuzhiyun 	   MPEG stream */
384*4882a593Smuzhiyun 	ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC, 2, 4, 1);
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun 	return ret;
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun 
pvr2_encoder_adjust(struct pvr2_hdw * hdw)389*4882a593Smuzhiyun int pvr2_encoder_adjust(struct pvr2_hdw *hdw)
390*4882a593Smuzhiyun {
391*4882a593Smuzhiyun 	int ret;
392*4882a593Smuzhiyun 	ret = cx2341x_update(hdw,pvr2_encoder_cmd,
393*4882a593Smuzhiyun 			     (hdw->enc_cur_valid ? &hdw->enc_cur_state : NULL),
394*4882a593Smuzhiyun 			     &hdw->enc_ctl_state);
395*4882a593Smuzhiyun 	if (ret) {
396*4882a593Smuzhiyun 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
397*4882a593Smuzhiyun 			   "Error from cx2341x module code=%d",ret);
398*4882a593Smuzhiyun 	} else {
399*4882a593Smuzhiyun 		hdw->enc_cur_state = hdw->enc_ctl_state;
400*4882a593Smuzhiyun 		hdw->enc_cur_valid = !0;
401*4882a593Smuzhiyun 	}
402*4882a593Smuzhiyun 	return ret;
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun 
pvr2_encoder_configure(struct pvr2_hdw * hdw)406*4882a593Smuzhiyun int pvr2_encoder_configure(struct pvr2_hdw *hdw)
407*4882a593Smuzhiyun {
408*4882a593Smuzhiyun 	int ret;
409*4882a593Smuzhiyun 	int val;
410*4882a593Smuzhiyun 	pvr2_trace(PVR2_TRACE_ENCODER, "pvr2_encoder_configure (cx2341x module)");
411*4882a593Smuzhiyun 	hdw->enc_ctl_state.port = CX2341X_PORT_STREAMING;
412*4882a593Smuzhiyun 	hdw->enc_ctl_state.width = hdw->res_hor_val;
413*4882a593Smuzhiyun 	hdw->enc_ctl_state.height = hdw->res_ver_val;
414*4882a593Smuzhiyun 	hdw->enc_ctl_state.is_50hz = ((hdw->std_mask_cur & V4L2_STD_525_60) ?
415*4882a593Smuzhiyun 				      0 : 1);
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	ret = 0;
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	ret |= pvr2_encoder_prep_config(hdw);
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun 	/* saa7115: 0xf0 */
422*4882a593Smuzhiyun 	val = 0xf0;
423*4882a593Smuzhiyun 	if (hdw->hdw_desc->flag_has_cx25840) {
424*4882a593Smuzhiyun 		/* ivtv cx25840: 0x140 */
425*4882a593Smuzhiyun 		val = 0x140;
426*4882a593Smuzhiyun 	}
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	if (!ret) ret = pvr2_encoder_vcmd(
429*4882a593Smuzhiyun 		hdw,CX2341X_ENC_SET_NUM_VSYNC_LINES, 2,
430*4882a593Smuzhiyun 		val, val);
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	/* setup firmware to notify us about some events (don't know why...) */
433*4882a593Smuzhiyun 	if (!ret) ret = pvr2_encoder_vcmd(
434*4882a593Smuzhiyun 		hdw,CX2341X_ENC_SET_EVENT_NOTIFICATION, 4,
435*4882a593Smuzhiyun 		0, 0, 0x10000000, 0xffffffff);
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 	if (!ret) ret = pvr2_encoder_vcmd(
438*4882a593Smuzhiyun 		hdw,CX2341X_ENC_SET_VBI_LINE, 5,
439*4882a593Smuzhiyun 		0xffffffff,0,0,0,0);
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun 	if (ret) {
442*4882a593Smuzhiyun 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
443*4882a593Smuzhiyun 			   "Failed to configure cx23416");
444*4882a593Smuzhiyun 		return ret;
445*4882a593Smuzhiyun 	}
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun 	ret = pvr2_encoder_adjust(hdw);
448*4882a593Smuzhiyun 	if (ret) return ret;
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun 	ret = pvr2_encoder_vcmd(
451*4882a593Smuzhiyun 		hdw, CX2341X_ENC_INITIALIZE_INPUT, 0);
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun 	if (ret) {
454*4882a593Smuzhiyun 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
455*4882a593Smuzhiyun 			   "Failed to initialize cx23416 video input");
456*4882a593Smuzhiyun 		return ret;
457*4882a593Smuzhiyun 	}
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun 	return 0;
460*4882a593Smuzhiyun }
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 
pvr2_encoder_start(struct pvr2_hdw * hdw)463*4882a593Smuzhiyun int pvr2_encoder_start(struct pvr2_hdw *hdw)
464*4882a593Smuzhiyun {
465*4882a593Smuzhiyun 	int status;
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun 	/* unmask some interrupts */
468*4882a593Smuzhiyun 	pvr2_write_register(hdw, 0x0048, 0xbfffffff);
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 	pvr2_encoder_vcmd(hdw,CX2341X_ENC_MUTE_VIDEO,1,
471*4882a593Smuzhiyun 			  hdw->input_val == PVR2_CVAL_INPUT_RADIO ? 1 : 0);
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun 	switch (hdw->active_stream_type) {
474*4882a593Smuzhiyun 	case pvr2_config_vbi:
475*4882a593Smuzhiyun 		status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
476*4882a593Smuzhiyun 					   0x01,0x14);
477*4882a593Smuzhiyun 		break;
478*4882a593Smuzhiyun 	case pvr2_config_mpeg:
479*4882a593Smuzhiyun 		status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
480*4882a593Smuzhiyun 					   0,0x13);
481*4882a593Smuzhiyun 		break;
482*4882a593Smuzhiyun 	default: /* Unhandled cases for now */
483*4882a593Smuzhiyun 		status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
484*4882a593Smuzhiyun 					   0,0x13);
485*4882a593Smuzhiyun 		break;
486*4882a593Smuzhiyun 	}
487*4882a593Smuzhiyun 	return status;
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun 
pvr2_encoder_stop(struct pvr2_hdw * hdw)490*4882a593Smuzhiyun int pvr2_encoder_stop(struct pvr2_hdw *hdw)
491*4882a593Smuzhiyun {
492*4882a593Smuzhiyun 	int status;
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun 	/* mask all interrupts */
495*4882a593Smuzhiyun 	pvr2_write_register(hdw, 0x0048, 0xffffffff);
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun 	switch (hdw->active_stream_type) {
498*4882a593Smuzhiyun 	case pvr2_config_vbi:
499*4882a593Smuzhiyun 		status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
500*4882a593Smuzhiyun 					   0x01,0x01,0x14);
501*4882a593Smuzhiyun 		break;
502*4882a593Smuzhiyun 	case pvr2_config_mpeg:
503*4882a593Smuzhiyun 		status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
504*4882a593Smuzhiyun 					   0x01,0,0x13);
505*4882a593Smuzhiyun 		break;
506*4882a593Smuzhiyun 	default: /* Unhandled cases for now */
507*4882a593Smuzhiyun 		status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
508*4882a593Smuzhiyun 					   0x01,0,0x13);
509*4882a593Smuzhiyun 		break;
510*4882a593Smuzhiyun 	}
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	return status;
513*4882a593Smuzhiyun }
514