xref: /OK3568_Linux_fs/kernel/drivers/media/usb/hdpvr/hdpvr.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Hauppauge HD PVR USB driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2008      Janne Grunau (j@jannau.net)
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/usb.h>
9*4882a593Smuzhiyun #include <linux/i2c.h>
10*4882a593Smuzhiyun #include <linux/mutex.h>
11*4882a593Smuzhiyun #include <linux/workqueue.h>
12*4882a593Smuzhiyun #include <linux/videodev2.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <media/v4l2-device.h>
15*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
16*4882a593Smuzhiyun #include <media/i2c/ir-kbd-i2c.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define HDPVR_MAX 8
19*4882a593Smuzhiyun #define HDPVR_I2C_MAX_SIZE 128
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun /* Define these values to match your devices */
22*4882a593Smuzhiyun #define HD_PVR_VENDOR_ID	0x2040
23*4882a593Smuzhiyun #define HD_PVR_PRODUCT_ID	0x4900
24*4882a593Smuzhiyun #define HD_PVR_PRODUCT_ID1	0x4901
25*4882a593Smuzhiyun #define HD_PVR_PRODUCT_ID2	0x4902
26*4882a593Smuzhiyun #define HD_PVR_PRODUCT_ID4	0x4903
27*4882a593Smuzhiyun #define HD_PVR_PRODUCT_ID3	0x4982
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define UNSET    (-1U)
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #define NUM_BUFFERS 64
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define HDPVR_FIRMWARE_VERSION		0x08
34*4882a593Smuzhiyun #define HDPVR_FIRMWARE_VERSION_AC3	0x0d
35*4882a593Smuzhiyun #define HDPVR_FIRMWARE_VERSION_0X12	0x12
36*4882a593Smuzhiyun #define HDPVR_FIRMWARE_VERSION_0X15	0x15
37*4882a593Smuzhiyun #define HDPVR_FIRMWARE_VERSION_0X1E	0x1e
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun /* #define HDPVR_DEBUG */
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun extern int hdpvr_debug;
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define MSG_INFO	1
44*4882a593Smuzhiyun #define MSG_BUFFER	2
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun struct hdpvr_options {
47*4882a593Smuzhiyun 	u8	video_std;
48*4882a593Smuzhiyun 	u8	video_input;
49*4882a593Smuzhiyun 	u8	audio_input;
50*4882a593Smuzhiyun 	u8	bitrate;	/* in 100kbps */
51*4882a593Smuzhiyun 	u8	peak_bitrate;	/* in 100kbps */
52*4882a593Smuzhiyun 	u8	bitrate_mode;
53*4882a593Smuzhiyun 	u8	gop_mode;
54*4882a593Smuzhiyun 	enum v4l2_mpeg_audio_encoding	audio_codec;
55*4882a593Smuzhiyun 	u8	brightness;
56*4882a593Smuzhiyun 	u8	contrast;
57*4882a593Smuzhiyun 	u8	hue;
58*4882a593Smuzhiyun 	u8	saturation;
59*4882a593Smuzhiyun 	u8	sharpness;
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun /* Structure to hold all of our device specific stuff */
63*4882a593Smuzhiyun struct hdpvr_device {
64*4882a593Smuzhiyun 	/* the v4l device for this device */
65*4882a593Smuzhiyun 	struct video_device	video_dev;
66*4882a593Smuzhiyun 	/* the control handler for this device */
67*4882a593Smuzhiyun 	struct v4l2_ctrl_handler hdl;
68*4882a593Smuzhiyun 	/* the usb device for this device */
69*4882a593Smuzhiyun 	struct usb_device	*udev;
70*4882a593Smuzhiyun 	/* v4l2-device unused */
71*4882a593Smuzhiyun 	struct v4l2_device	v4l2_dev;
72*4882a593Smuzhiyun 	struct { /* video mode/bitrate control cluster */
73*4882a593Smuzhiyun 		struct v4l2_ctrl *video_mode;
74*4882a593Smuzhiyun 		struct v4l2_ctrl *video_bitrate;
75*4882a593Smuzhiyun 		struct v4l2_ctrl *video_bitrate_peak;
76*4882a593Smuzhiyun 	};
77*4882a593Smuzhiyun 	/* v4l2 format */
78*4882a593Smuzhiyun 	uint width, height;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	/* the max packet size of the bulk endpoint */
81*4882a593Smuzhiyun 	size_t			bulk_in_size;
82*4882a593Smuzhiyun 	/* the address of the bulk in endpoint */
83*4882a593Smuzhiyun 	__u8			bulk_in_endpointAddr;
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	/* holds the current device status */
86*4882a593Smuzhiyun 	__u8			status;
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	/* holds the current set options */
89*4882a593Smuzhiyun 	struct hdpvr_options	options;
90*4882a593Smuzhiyun 	v4l2_std_id		cur_std;
91*4882a593Smuzhiyun 	struct v4l2_dv_timings	cur_dv_timings;
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	uint			flags;
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	/* synchronize I/O */
96*4882a593Smuzhiyun 	struct mutex		io_mutex;
97*4882a593Smuzhiyun 	/* available buffers */
98*4882a593Smuzhiyun 	struct list_head	free_buff_list;
99*4882a593Smuzhiyun 	/* in progress buffers */
100*4882a593Smuzhiyun 	struct list_head	rec_buff_list;
101*4882a593Smuzhiyun 	/* waitqueue for buffers */
102*4882a593Smuzhiyun 	wait_queue_head_t	wait_buffer;
103*4882a593Smuzhiyun 	/* waitqueue for data */
104*4882a593Smuzhiyun 	wait_queue_head_t	wait_data;
105*4882a593Smuzhiyun 	/**/
106*4882a593Smuzhiyun 	struct work_struct	worker;
107*4882a593Smuzhiyun 	/* current stream owner */
108*4882a593Smuzhiyun 	struct v4l2_fh		*owner;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	/* I2C adapter */
111*4882a593Smuzhiyun 	struct i2c_adapter	i2c_adapter;
112*4882a593Smuzhiyun 	/* I2C lock */
113*4882a593Smuzhiyun 	struct mutex		i2c_mutex;
114*4882a593Smuzhiyun 	/* I2C message buffer space */
115*4882a593Smuzhiyun 	char			i2c_buf[HDPVR_I2C_MAX_SIZE];
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	/* For passing data to ir-kbd-i2c */
118*4882a593Smuzhiyun 	struct IR_i2c_init_data	ir_i2c_init_data;
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	/* usb control transfer buffer and lock */
121*4882a593Smuzhiyun 	struct mutex		usbc_mutex;
122*4882a593Smuzhiyun 	u8			*usbc_buf;
123*4882a593Smuzhiyun 	u8			fw_ver;
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun 
to_hdpvr_dev(struct v4l2_device * v4l2_dev)126*4882a593Smuzhiyun static inline struct hdpvr_device *to_hdpvr_dev(struct v4l2_device *v4l2_dev)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun 	return container_of(v4l2_dev, struct hdpvr_device, v4l2_dev);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun /* buffer one bulk urb of data */
133*4882a593Smuzhiyun struct hdpvr_buffer {
134*4882a593Smuzhiyun 	struct list_head	buff_list;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	struct urb		*urb;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	struct hdpvr_device	*dev;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	uint			pos;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	__u8			status;
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun /* */
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun struct hdpvr_video_info {
148*4882a593Smuzhiyun 	u16	width;
149*4882a593Smuzhiyun 	u16	height;
150*4882a593Smuzhiyun 	u8	fps;
151*4882a593Smuzhiyun 	bool	valid;
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun enum {
155*4882a593Smuzhiyun 	STATUS_UNINITIALIZED	= 0,
156*4882a593Smuzhiyun 	STATUS_IDLE,
157*4882a593Smuzhiyun 	STATUS_STARTING,
158*4882a593Smuzhiyun 	STATUS_SHUTTING_DOWN,
159*4882a593Smuzhiyun 	STATUS_STREAMING,
160*4882a593Smuzhiyun 	STATUS_ERROR,
161*4882a593Smuzhiyun 	STATUS_DISCONNECTED,
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun enum {
165*4882a593Smuzhiyun 	HDPVR_FLAG_AC3_CAP = 1,
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun enum {
169*4882a593Smuzhiyun 	BUFSTAT_UNINITIALIZED = 0,
170*4882a593Smuzhiyun 	BUFSTAT_AVAILABLE,
171*4882a593Smuzhiyun 	BUFSTAT_INPROGRESS,
172*4882a593Smuzhiyun 	BUFSTAT_READY,
173*4882a593Smuzhiyun };
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun #define CTRL_START_STREAMING_VALUE	0x0700
176*4882a593Smuzhiyun #define CTRL_STOP_STREAMING_VALUE	0x0800
177*4882a593Smuzhiyun #define CTRL_BITRATE_VALUE		0x1000
178*4882a593Smuzhiyun #define CTRL_BITRATE_MODE_VALUE		0x1200
179*4882a593Smuzhiyun #define CTRL_GOP_MODE_VALUE		0x1300
180*4882a593Smuzhiyun #define CTRL_VIDEO_INPUT_VALUE		0x1500
181*4882a593Smuzhiyun #define CTRL_VIDEO_STD_TYPE		0x1700
182*4882a593Smuzhiyun #define CTRL_AUDIO_INPUT_VALUE		0x2500
183*4882a593Smuzhiyun #define CTRL_BRIGHTNESS			0x2900
184*4882a593Smuzhiyun #define CTRL_CONTRAST			0x2a00
185*4882a593Smuzhiyun #define CTRL_HUE			0x2b00
186*4882a593Smuzhiyun #define CTRL_SATURATION			0x2c00
187*4882a593Smuzhiyun #define CTRL_SHARPNESS			0x2d00
188*4882a593Smuzhiyun #define CTRL_LOW_PASS_FILTER_VALUE	0x3100
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun #define CTRL_DEFAULT_INDEX		0x0003
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	/* :0 s 38 01 1000 0003 0004 4 = 0a00ca00
194*4882a593Smuzhiyun 	 * BITRATE SETTING
195*4882a593Smuzhiyun 	 *   1st and 2nd byte (little endian): average bitrate in 100 000 bit/s
196*4882a593Smuzhiyun 	 *                                     min: 1 mbit/s, max: 13.5 mbit/s
197*4882a593Smuzhiyun 	 *   3rd and 4th byte (little endian): peak bitrate in 100 000 bit/s
198*4882a593Smuzhiyun 	 *                                     min: average + 100kbit/s,
199*4882a593Smuzhiyun 	 *                                      max: 20.2 mbit/s
200*4882a593Smuzhiyun 	 */
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	/* :0 s 38 01 1200 0003 0001 1 = 02
203*4882a593Smuzhiyun 	 * BIT RATE MODE
204*4882a593Smuzhiyun 	 *  constant = 1, variable (peak) = 2, variable (average) = 3
205*4882a593Smuzhiyun 	 */
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	/* :0 s 38 01 1300 0003 0001 1 = 03
208*4882a593Smuzhiyun 	 * GOP MODE (2 bit)
209*4882a593Smuzhiyun 	 *    low bit 0/1: advanced/simple GOP
210*4882a593Smuzhiyun 	 *   high bit 0/1: IDR(4/32/128) / no IDR (4/32/0)
211*4882a593Smuzhiyun 	 */
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	/* :0 s 38 01 1700 0003 0001 1 = 00
214*4882a593Smuzhiyun 	 * VIDEO STANDARD or FREQUENCY 0 = 60hz, 1 = 50hz
215*4882a593Smuzhiyun 	 */
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	/* :0 s 38 01 3100 0003 0004 4 = 03030000
218*4882a593Smuzhiyun 	 * FILTER CONTROL
219*4882a593Smuzhiyun 	 *   1st byte luma low pass filter strength,
220*4882a593Smuzhiyun 	 *   2nd byte chroma low pass filter strength,
221*4882a593Smuzhiyun 	 *   3rd byte MF enable chroma, min=0, max=1
222*4882a593Smuzhiyun 	 *   4th byte n
223*4882a593Smuzhiyun 	 */
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	/* :0 s 38 b9 0001 0000 0000 0 */
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun /* :0 s 38 d3 0000 0000 0001 1 = 00 */
231*4882a593Smuzhiyun /*		ret = usb_control_msg(dev->udev, */
232*4882a593Smuzhiyun /*				      usb_sndctrlpipe(dev->udev, 0), */
233*4882a593Smuzhiyun /*				      0xd3, 0x38, */
234*4882a593Smuzhiyun /*				      0, 0, */
235*4882a593Smuzhiyun /*				      "\0", 1, */
236*4882a593Smuzhiyun /*				      1000); */
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun /*		info("control request returned %d", ret); */
239*4882a593Smuzhiyun /*		msleep(5000); */
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	/* :0 s b8 81 1400 0003 0005 5 <
243*4882a593Smuzhiyun 	 * :0 0 5 = d0024002 19
244*4882a593Smuzhiyun 	 * QUERY FRAME SIZE AND RATE
245*4882a593Smuzhiyun 	 *   1st and 2nd byte (little endian): horizontal resolution
246*4882a593Smuzhiyun 	 *   3rd and 4th byte (little endian): vertical resolution
247*4882a593Smuzhiyun 	 *   5th byte: frame rate
248*4882a593Smuzhiyun 	 */
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	/* :0 s b8 81 1800 0003 0003 3 <
251*4882a593Smuzhiyun 	 * :0 0 3 = 030104
252*4882a593Smuzhiyun 	 * QUERY SIGNAL AND DETECTED LINES, maybe INPUT
253*4882a593Smuzhiyun 	 */
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun enum hdpvr_video_std {
256*4882a593Smuzhiyun 	HDPVR_60HZ = 0,
257*4882a593Smuzhiyun 	HDPVR_50HZ,
258*4882a593Smuzhiyun };
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun enum hdpvr_video_input {
261*4882a593Smuzhiyun 	HDPVR_COMPONENT = 0,
262*4882a593Smuzhiyun 	HDPVR_SVIDEO,
263*4882a593Smuzhiyun 	HDPVR_COMPOSITE,
264*4882a593Smuzhiyun 	HDPVR_VIDEO_INPUTS
265*4882a593Smuzhiyun };
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun enum hdpvr_audio_inputs {
268*4882a593Smuzhiyun 	HDPVR_RCA_BACK = 0,
269*4882a593Smuzhiyun 	HDPVR_RCA_FRONT,
270*4882a593Smuzhiyun 	HDPVR_SPDIF,
271*4882a593Smuzhiyun 	HDPVR_AUDIO_INPUTS
272*4882a593Smuzhiyun };
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun enum hdpvr_bitrate_mode {
275*4882a593Smuzhiyun 	HDPVR_CONSTANT = 1,
276*4882a593Smuzhiyun 	HDPVR_VARIABLE_PEAK,
277*4882a593Smuzhiyun 	HDPVR_VARIABLE_AVERAGE,
278*4882a593Smuzhiyun };
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun enum hdpvr_gop_mode {
281*4882a593Smuzhiyun 	HDPVR_ADVANCED_IDR_GOP = 0,
282*4882a593Smuzhiyun 	HDPVR_SIMPLE_IDR_GOP,
283*4882a593Smuzhiyun 	HDPVR_ADVANCED_NOIDR_GOP,
284*4882a593Smuzhiyun 	HDPVR_SIMPLE_NOIDR_GOP,
285*4882a593Smuzhiyun };
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun void hdpvr_delete(struct hdpvr_device *dev);
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun /*========================================================================*/
290*4882a593Smuzhiyun /* hardware control functions */
291*4882a593Smuzhiyun int hdpvr_set_options(struct hdpvr_device *dev);
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun int hdpvr_set_bitrate(struct hdpvr_device *dev);
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun int hdpvr_set_audio(struct hdpvr_device *dev, u8 input,
296*4882a593Smuzhiyun 		    enum v4l2_mpeg_audio_encoding codec);
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun int hdpvr_config_call(struct hdpvr_device *dev, uint value,
299*4882a593Smuzhiyun 		      unsigned char valbuf);
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun int get_video_info(struct hdpvr_device *dev, struct hdpvr_video_info *vid_info);
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun /* :0 s b8 81 1800 0003 0003 3 < */
304*4882a593Smuzhiyun /* :0 0 3 = 0301ff */
305*4882a593Smuzhiyun int get_input_lines_info(struct hdpvr_device *dev);
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun /*========================================================================*/
309*4882a593Smuzhiyun /* v4l2 registration */
310*4882a593Smuzhiyun int hdpvr_register_videodev(struct hdpvr_device *dev, struct device *parent,
311*4882a593Smuzhiyun 			    int devnumber);
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun int hdpvr_cancel_queue(struct hdpvr_device *dev);
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun /*========================================================================*/
316*4882a593Smuzhiyun /* i2c adapter registration */
317*4882a593Smuzhiyun int hdpvr_register_i2c_adapter(struct hdpvr_device *dev);
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun struct i2c_client *hdpvr_register_ir_i2c(struct hdpvr_device *dev);
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun /*========================================================================*/
322*4882a593Smuzhiyun /* buffer management */
323*4882a593Smuzhiyun int hdpvr_free_buffers(struct hdpvr_device *dev);
324*4882a593Smuzhiyun int hdpvr_alloc_buffers(struct hdpvr_device *dev, uint count);
325