1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /**
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * GSPCA sub driver for W996[78]CF JPEG USB Dual Mode Camera Chip.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2009 Hans de Goede <hdegoede@redhat.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This module is adapted from the in kernel v4l1 w9968cf driver:
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Copyright (C) 2002-2004 by Luca Risolia <luca.risolia@studio.unibo.it>
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /* Note this is not a stand alone driver, it gets included in ov519.c, this
14*4882a593Smuzhiyun is a bit of a hack, but it needs the driver code for a lot of different
15*4882a593Smuzhiyun ov sensors which is already present in ov519.c (the old v4l1 driver used
16*4882a593Smuzhiyun the ovchipcam framework). When we have the time we really should move
17*4882a593Smuzhiyun the sensor drivers to v4l2 sub drivers, and properly split of this
18*4882a593Smuzhiyun driver from ov519.c */
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define W9968CF_I2C_BUS_DELAY 4 /* delay in us for I2C bit r/w operations */
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define Y_QUANTABLE (&sd->jpeg_hdr[JPEG_QT0_OFFSET])
25*4882a593Smuzhiyun #define UV_QUANTABLE (&sd->jpeg_hdr[JPEG_QT1_OFFSET])
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun static const struct v4l2_pix_format w9968cf_vga_mode[] = {
28*4882a593Smuzhiyun {160, 120, V4L2_PIX_FMT_UYVY, V4L2_FIELD_NONE,
29*4882a593Smuzhiyun .bytesperline = 160 * 2,
30*4882a593Smuzhiyun .sizeimage = 160 * 120 * 2,
31*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG},
32*4882a593Smuzhiyun {176, 144, V4L2_PIX_FMT_UYVY, V4L2_FIELD_NONE,
33*4882a593Smuzhiyun .bytesperline = 176 * 2,
34*4882a593Smuzhiyun .sizeimage = 176 * 144 * 2,
35*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG},
36*4882a593Smuzhiyun {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
37*4882a593Smuzhiyun .bytesperline = 320 * 2,
38*4882a593Smuzhiyun .sizeimage = 320 * 240 * 2,
39*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG},
40*4882a593Smuzhiyun {352, 288, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
41*4882a593Smuzhiyun .bytesperline = 352 * 2,
42*4882a593Smuzhiyun .sizeimage = 352 * 288 * 2,
43*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG},
44*4882a593Smuzhiyun {640, 480, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
45*4882a593Smuzhiyun .bytesperline = 640 * 2,
46*4882a593Smuzhiyun .sizeimage = 640 * 480 * 2,
47*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG},
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static void reg_w(struct sd *sd, u16 index, u16 value);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /*--------------------------------------------------------------------------
53*4882a593Smuzhiyun Write 64-bit data to the fast serial bus registers.
54*4882a593Smuzhiyun Return 0 on success, -1 otherwise.
55*4882a593Smuzhiyun --------------------------------------------------------------------------*/
w9968cf_write_fsb(struct sd * sd,u16 * data)56*4882a593Smuzhiyun static void w9968cf_write_fsb(struct sd *sd, u16* data)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun struct usb_device *udev = sd->gspca_dev.dev;
59*4882a593Smuzhiyun u16 value;
60*4882a593Smuzhiyun int ret;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun if (sd->gspca_dev.usb_err < 0)
63*4882a593Smuzhiyun return;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun value = *data++;
66*4882a593Smuzhiyun memcpy(sd->gspca_dev.usb_buf, data, 6);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* Avoid things going to fast for the bridge with a xhci host */
69*4882a593Smuzhiyun udelay(150);
70*4882a593Smuzhiyun ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 0,
71*4882a593Smuzhiyun USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE,
72*4882a593Smuzhiyun value, 0x06, sd->gspca_dev.usb_buf, 6, 500);
73*4882a593Smuzhiyun if (ret < 0) {
74*4882a593Smuzhiyun pr_err("Write FSB registers failed (%d)\n", ret);
75*4882a593Smuzhiyun sd->gspca_dev.usb_err = ret;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /*--------------------------------------------------------------------------
80*4882a593Smuzhiyun Write data to the serial bus control register.
81*4882a593Smuzhiyun Return 0 on success, a negative number otherwise.
82*4882a593Smuzhiyun --------------------------------------------------------------------------*/
w9968cf_write_sb(struct sd * sd,u16 value)83*4882a593Smuzhiyun static void w9968cf_write_sb(struct sd *sd, u16 value)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun int ret;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun if (sd->gspca_dev.usb_err < 0)
88*4882a593Smuzhiyun return;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* Avoid things going to fast for the bridge with a xhci host */
91*4882a593Smuzhiyun udelay(150);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /* We don't use reg_w here, as that would cause all writes when
94*4882a593Smuzhiyun bitbanging i2c to be logged, making the logs impossible to read */
95*4882a593Smuzhiyun ret = usb_control_msg(sd->gspca_dev.dev,
96*4882a593Smuzhiyun usb_sndctrlpipe(sd->gspca_dev.dev, 0),
97*4882a593Smuzhiyun 0,
98*4882a593Smuzhiyun USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
99*4882a593Smuzhiyun value, 0x01, NULL, 0, 500);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun udelay(W9968CF_I2C_BUS_DELAY);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun if (ret < 0) {
104*4882a593Smuzhiyun pr_err("Write SB reg [01] %04x failed\n", value);
105*4882a593Smuzhiyun sd->gspca_dev.usb_err = ret;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /*--------------------------------------------------------------------------
110*4882a593Smuzhiyun Read data from the serial bus control register.
111*4882a593Smuzhiyun Return 0 on success, a negative number otherwise.
112*4882a593Smuzhiyun --------------------------------------------------------------------------*/
w9968cf_read_sb(struct sd * sd)113*4882a593Smuzhiyun static int w9968cf_read_sb(struct sd *sd)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun int ret;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun if (sd->gspca_dev.usb_err < 0)
118*4882a593Smuzhiyun return -1;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* Avoid things going to fast for the bridge with a xhci host */
121*4882a593Smuzhiyun udelay(150);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /* We don't use reg_r here, as the w9968cf is special and has 16
124*4882a593Smuzhiyun bit registers instead of 8 bit */
125*4882a593Smuzhiyun ret = usb_control_msg(sd->gspca_dev.dev,
126*4882a593Smuzhiyun usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
127*4882a593Smuzhiyun 1,
128*4882a593Smuzhiyun USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
129*4882a593Smuzhiyun 0, 0x01, sd->gspca_dev.usb_buf, 2, 500);
130*4882a593Smuzhiyun if (ret >= 0) {
131*4882a593Smuzhiyun ret = sd->gspca_dev.usb_buf[0] |
132*4882a593Smuzhiyun (sd->gspca_dev.usb_buf[1] << 8);
133*4882a593Smuzhiyun } else {
134*4882a593Smuzhiyun pr_err("Read SB reg [01] failed\n");
135*4882a593Smuzhiyun sd->gspca_dev.usb_err = ret;
136*4882a593Smuzhiyun /*
137*4882a593Smuzhiyun * Make sure the buffer is zeroed to avoid uninitialized
138*4882a593Smuzhiyun * values.
139*4882a593Smuzhiyun */
140*4882a593Smuzhiyun memset(sd->gspca_dev.usb_buf, 0, 2);
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun udelay(W9968CF_I2C_BUS_DELAY);
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun return ret;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun /*--------------------------------------------------------------------------
149*4882a593Smuzhiyun Upload quantization tables for the JPEG compression.
150*4882a593Smuzhiyun This function is called by w9968cf_start_transfer().
151*4882a593Smuzhiyun Return 0 on success, a negative number otherwise.
152*4882a593Smuzhiyun --------------------------------------------------------------------------*/
w9968cf_upload_quantizationtables(struct sd * sd)153*4882a593Smuzhiyun static void w9968cf_upload_quantizationtables(struct sd *sd)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun u16 a, b;
156*4882a593Smuzhiyun int i, j;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun reg_w(sd, 0x39, 0x0010); /* JPEG clock enable */
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun for (i = 0, j = 0; i < 32; i++, j += 2) {
161*4882a593Smuzhiyun a = Y_QUANTABLE[j] | ((unsigned)(Y_QUANTABLE[j + 1]) << 8);
162*4882a593Smuzhiyun b = UV_QUANTABLE[j] | ((unsigned)(UV_QUANTABLE[j + 1]) << 8);
163*4882a593Smuzhiyun reg_w(sd, 0x40 + i, a);
164*4882a593Smuzhiyun reg_w(sd, 0x60 + i, b);
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun reg_w(sd, 0x39, 0x0012); /* JPEG encoder enable */
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun /****************************************************************************
170*4882a593Smuzhiyun * Low-level I2C I/O functions. *
171*4882a593Smuzhiyun * The adapter supports the following I2C transfer functions: *
172*4882a593Smuzhiyun * i2c_adap_fastwrite_byte_data() (at 400 kHz bit frequency only) *
173*4882a593Smuzhiyun * i2c_adap_read_byte_data() *
174*4882a593Smuzhiyun * i2c_adap_read_byte() *
175*4882a593Smuzhiyun ****************************************************************************/
176*4882a593Smuzhiyun
w9968cf_smbus_start(struct sd * sd)177*4882a593Smuzhiyun static void w9968cf_smbus_start(struct sd *sd)
178*4882a593Smuzhiyun {
179*4882a593Smuzhiyun w9968cf_write_sb(sd, 0x0011); /* SDE=1, SDA=0, SCL=1 */
180*4882a593Smuzhiyun w9968cf_write_sb(sd, 0x0010); /* SDE=1, SDA=0, SCL=0 */
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun
w9968cf_smbus_stop(struct sd * sd)183*4882a593Smuzhiyun static void w9968cf_smbus_stop(struct sd *sd)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun w9968cf_write_sb(sd, 0x0010); /* SDE=1, SDA=0, SCL=0 */
186*4882a593Smuzhiyun w9968cf_write_sb(sd, 0x0011); /* SDE=1, SDA=0, SCL=1 */
187*4882a593Smuzhiyun w9968cf_write_sb(sd, 0x0013); /* SDE=1, SDA=1, SCL=1 */
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
w9968cf_smbus_write_byte(struct sd * sd,u8 v)190*4882a593Smuzhiyun static void w9968cf_smbus_write_byte(struct sd *sd, u8 v)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun u8 bit;
193*4882a593Smuzhiyun int sda;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun for (bit = 0 ; bit < 8 ; bit++) {
196*4882a593Smuzhiyun sda = (v & 0x80) ? 2 : 0;
197*4882a593Smuzhiyun v <<= 1;
198*4882a593Smuzhiyun /* SDE=1, SDA=sda, SCL=0 */
199*4882a593Smuzhiyun w9968cf_write_sb(sd, 0x10 | sda);
200*4882a593Smuzhiyun /* SDE=1, SDA=sda, SCL=1 */
201*4882a593Smuzhiyun w9968cf_write_sb(sd, 0x11 | sda);
202*4882a593Smuzhiyun /* SDE=1, SDA=sda, SCL=0 */
203*4882a593Smuzhiyun w9968cf_write_sb(sd, 0x10 | sda);
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
w9968cf_smbus_read_byte(struct sd * sd,u8 * v)207*4882a593Smuzhiyun static void w9968cf_smbus_read_byte(struct sd *sd, u8 *v)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun u8 bit;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun /* No need to ensure SDA is high as we are always called after
212*4882a593Smuzhiyun read_ack which ends with SDA high */
213*4882a593Smuzhiyun *v = 0;
214*4882a593Smuzhiyun for (bit = 0 ; bit < 8 ; bit++) {
215*4882a593Smuzhiyun *v <<= 1;
216*4882a593Smuzhiyun /* SDE=1, SDA=1, SCL=1 */
217*4882a593Smuzhiyun w9968cf_write_sb(sd, 0x0013);
218*4882a593Smuzhiyun *v |= (w9968cf_read_sb(sd) & 0x0008) ? 1 : 0;
219*4882a593Smuzhiyun /* SDE=1, SDA=1, SCL=0 */
220*4882a593Smuzhiyun w9968cf_write_sb(sd, 0x0012);
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun
w9968cf_smbus_write_nack(struct sd * sd)224*4882a593Smuzhiyun static void w9968cf_smbus_write_nack(struct sd *sd)
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun /* No need to ensure SDA is high as we are always called after
227*4882a593Smuzhiyun read_byte which ends with SDA high */
228*4882a593Smuzhiyun w9968cf_write_sb(sd, 0x0013); /* SDE=1, SDA=1, SCL=1 */
229*4882a593Smuzhiyun w9968cf_write_sb(sd, 0x0012); /* SDE=1, SDA=1, SCL=0 */
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
w9968cf_smbus_read_ack(struct sd * sd)232*4882a593Smuzhiyun static void w9968cf_smbus_read_ack(struct sd *sd)
233*4882a593Smuzhiyun {
234*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
235*4882a593Smuzhiyun int sda;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun /* Ensure SDA is high before raising clock to avoid a spurious stop */
238*4882a593Smuzhiyun w9968cf_write_sb(sd, 0x0012); /* SDE=1, SDA=1, SCL=0 */
239*4882a593Smuzhiyun w9968cf_write_sb(sd, 0x0013); /* SDE=1, SDA=1, SCL=1 */
240*4882a593Smuzhiyun sda = w9968cf_read_sb(sd);
241*4882a593Smuzhiyun w9968cf_write_sb(sd, 0x0012); /* SDE=1, SDA=1, SCL=0 */
242*4882a593Smuzhiyun if (sda >= 0 && (sda & 0x08)) {
243*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_USBI, "Did not receive i2c ACK\n");
244*4882a593Smuzhiyun sd->gspca_dev.usb_err = -EIO;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun /* SMBus protocol: S Addr Wr [A] Subaddr [A] Value [A] P */
w9968cf_i2c_w(struct sd * sd,u8 reg,u8 value)249*4882a593Smuzhiyun static void w9968cf_i2c_w(struct sd *sd, u8 reg, u8 value)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
252*4882a593Smuzhiyun u16* data = (u16 *)sd->gspca_dev.usb_buf;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun data[0] = 0x082f | ((sd->sensor_addr & 0x80) ? 0x1500 : 0x0);
255*4882a593Smuzhiyun data[0] |= (sd->sensor_addr & 0x40) ? 0x4000 : 0x0;
256*4882a593Smuzhiyun data[1] = 0x2082 | ((sd->sensor_addr & 0x40) ? 0x0005 : 0x0);
257*4882a593Smuzhiyun data[1] |= (sd->sensor_addr & 0x20) ? 0x0150 : 0x0;
258*4882a593Smuzhiyun data[1] |= (sd->sensor_addr & 0x10) ? 0x5400 : 0x0;
259*4882a593Smuzhiyun data[2] = 0x8208 | ((sd->sensor_addr & 0x08) ? 0x0015 : 0x0);
260*4882a593Smuzhiyun data[2] |= (sd->sensor_addr & 0x04) ? 0x0540 : 0x0;
261*4882a593Smuzhiyun data[2] |= (sd->sensor_addr & 0x02) ? 0x5000 : 0x0;
262*4882a593Smuzhiyun data[3] = 0x1d20 | ((sd->sensor_addr & 0x02) ? 0x0001 : 0x0);
263*4882a593Smuzhiyun data[3] |= (sd->sensor_addr & 0x01) ? 0x0054 : 0x0;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun w9968cf_write_fsb(sd, data);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun data[0] = 0x8208 | ((reg & 0x80) ? 0x0015 : 0x0);
268*4882a593Smuzhiyun data[0] |= (reg & 0x40) ? 0x0540 : 0x0;
269*4882a593Smuzhiyun data[0] |= (reg & 0x20) ? 0x5000 : 0x0;
270*4882a593Smuzhiyun data[1] = 0x0820 | ((reg & 0x20) ? 0x0001 : 0x0);
271*4882a593Smuzhiyun data[1] |= (reg & 0x10) ? 0x0054 : 0x0;
272*4882a593Smuzhiyun data[1] |= (reg & 0x08) ? 0x1500 : 0x0;
273*4882a593Smuzhiyun data[1] |= (reg & 0x04) ? 0x4000 : 0x0;
274*4882a593Smuzhiyun data[2] = 0x2082 | ((reg & 0x04) ? 0x0005 : 0x0);
275*4882a593Smuzhiyun data[2] |= (reg & 0x02) ? 0x0150 : 0x0;
276*4882a593Smuzhiyun data[2] |= (reg & 0x01) ? 0x5400 : 0x0;
277*4882a593Smuzhiyun data[3] = 0x001d;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun w9968cf_write_fsb(sd, data);
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun data[0] = 0x8208 | ((value & 0x80) ? 0x0015 : 0x0);
282*4882a593Smuzhiyun data[0] |= (value & 0x40) ? 0x0540 : 0x0;
283*4882a593Smuzhiyun data[0] |= (value & 0x20) ? 0x5000 : 0x0;
284*4882a593Smuzhiyun data[1] = 0x0820 | ((value & 0x20) ? 0x0001 : 0x0);
285*4882a593Smuzhiyun data[1] |= (value & 0x10) ? 0x0054 : 0x0;
286*4882a593Smuzhiyun data[1] |= (value & 0x08) ? 0x1500 : 0x0;
287*4882a593Smuzhiyun data[1] |= (value & 0x04) ? 0x4000 : 0x0;
288*4882a593Smuzhiyun data[2] = 0x2082 | ((value & 0x04) ? 0x0005 : 0x0);
289*4882a593Smuzhiyun data[2] |= (value & 0x02) ? 0x0150 : 0x0;
290*4882a593Smuzhiyun data[2] |= (value & 0x01) ? 0x5400 : 0x0;
291*4882a593Smuzhiyun data[3] = 0xfe1d;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun w9968cf_write_fsb(sd, data);
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_USBO, "i2c 0x%02x -> [0x%02x]\n", value, reg);
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun /* SMBus protocol: S Addr Wr [A] Subaddr [A] P S Addr+1 Rd [A] [Value] NA P */
w9968cf_i2c_r(struct sd * sd,u8 reg)299*4882a593Smuzhiyun static int w9968cf_i2c_r(struct sd *sd, u8 reg)
300*4882a593Smuzhiyun {
301*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
302*4882a593Smuzhiyun int ret = 0;
303*4882a593Smuzhiyun u8 value;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun /* Fast serial bus data control disable */
306*4882a593Smuzhiyun w9968cf_write_sb(sd, 0x0013); /* don't change ! */
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun w9968cf_smbus_start(sd);
309*4882a593Smuzhiyun w9968cf_smbus_write_byte(sd, sd->sensor_addr);
310*4882a593Smuzhiyun w9968cf_smbus_read_ack(sd);
311*4882a593Smuzhiyun w9968cf_smbus_write_byte(sd, reg);
312*4882a593Smuzhiyun w9968cf_smbus_read_ack(sd);
313*4882a593Smuzhiyun w9968cf_smbus_stop(sd);
314*4882a593Smuzhiyun w9968cf_smbus_start(sd);
315*4882a593Smuzhiyun w9968cf_smbus_write_byte(sd, sd->sensor_addr + 1);
316*4882a593Smuzhiyun w9968cf_smbus_read_ack(sd);
317*4882a593Smuzhiyun w9968cf_smbus_read_byte(sd, &value);
318*4882a593Smuzhiyun /* signal we don't want to read anymore, the v4l1 driver used to
319*4882a593Smuzhiyun send an ack here which is very wrong! (and then fixed
320*4882a593Smuzhiyun the issues this gave by retrying reads) */
321*4882a593Smuzhiyun w9968cf_smbus_write_nack(sd);
322*4882a593Smuzhiyun w9968cf_smbus_stop(sd);
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun /* Fast serial bus data control re-enable */
325*4882a593Smuzhiyun w9968cf_write_sb(sd, 0x0030);
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun if (sd->gspca_dev.usb_err >= 0) {
328*4882a593Smuzhiyun ret = value;
329*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_USBI, "i2c [0x%02X] -> 0x%02X\n",
330*4882a593Smuzhiyun reg, value);
331*4882a593Smuzhiyun } else
332*4882a593Smuzhiyun gspca_err(gspca_dev, "i2c read [0x%02x] failed\n", reg);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun return ret;
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun /*--------------------------------------------------------------------------
338*4882a593Smuzhiyun Turn on the LED on some webcams. A beep should be heard too.
339*4882a593Smuzhiyun Return 0 on success, a negative number otherwise.
340*4882a593Smuzhiyun --------------------------------------------------------------------------*/
w9968cf_configure(struct sd * sd)341*4882a593Smuzhiyun static void w9968cf_configure(struct sd *sd)
342*4882a593Smuzhiyun {
343*4882a593Smuzhiyun reg_w(sd, 0x00, 0xff00); /* power-down */
344*4882a593Smuzhiyun reg_w(sd, 0x00, 0xbf17); /* reset everything */
345*4882a593Smuzhiyun reg_w(sd, 0x00, 0xbf10); /* normal operation */
346*4882a593Smuzhiyun reg_w(sd, 0x01, 0x0010); /* serial bus, SDS high */
347*4882a593Smuzhiyun reg_w(sd, 0x01, 0x0000); /* serial bus, SDS low */
348*4882a593Smuzhiyun reg_w(sd, 0x01, 0x0010); /* ..high 'beep-beep' */
349*4882a593Smuzhiyun reg_w(sd, 0x01, 0x0030); /* Set sda scl to FSB mode */
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun sd->stopped = 1;
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
w9968cf_init(struct sd * sd)354*4882a593Smuzhiyun static void w9968cf_init(struct sd *sd)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun unsigned long hw_bufsize = sd->sif ? (352 * 288 * 2) : (640 * 480 * 2),
357*4882a593Smuzhiyun y0 = 0x0000,
358*4882a593Smuzhiyun u0 = y0 + hw_bufsize / 2,
359*4882a593Smuzhiyun v0 = u0 + hw_bufsize / 4,
360*4882a593Smuzhiyun y1 = v0 + hw_bufsize / 4,
361*4882a593Smuzhiyun u1 = y1 + hw_bufsize / 2,
362*4882a593Smuzhiyun v1 = u1 + hw_bufsize / 4;
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun reg_w(sd, 0x00, 0xff00); /* power off */
365*4882a593Smuzhiyun reg_w(sd, 0x00, 0xbf10); /* power on */
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun reg_w(sd, 0x03, 0x405d); /* DRAM timings */
368*4882a593Smuzhiyun reg_w(sd, 0x04, 0x0030); /* SDRAM timings */
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun reg_w(sd, 0x20, y0 & 0xffff); /* Y buf.0, low */
371*4882a593Smuzhiyun reg_w(sd, 0x21, y0 >> 16); /* Y buf.0, high */
372*4882a593Smuzhiyun reg_w(sd, 0x24, u0 & 0xffff); /* U buf.0, low */
373*4882a593Smuzhiyun reg_w(sd, 0x25, u0 >> 16); /* U buf.0, high */
374*4882a593Smuzhiyun reg_w(sd, 0x28, v0 & 0xffff); /* V buf.0, low */
375*4882a593Smuzhiyun reg_w(sd, 0x29, v0 >> 16); /* V buf.0, high */
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun reg_w(sd, 0x22, y1 & 0xffff); /* Y buf.1, low */
378*4882a593Smuzhiyun reg_w(sd, 0x23, y1 >> 16); /* Y buf.1, high */
379*4882a593Smuzhiyun reg_w(sd, 0x26, u1 & 0xffff); /* U buf.1, low */
380*4882a593Smuzhiyun reg_w(sd, 0x27, u1 >> 16); /* U buf.1, high */
381*4882a593Smuzhiyun reg_w(sd, 0x2a, v1 & 0xffff); /* V buf.1, low */
382*4882a593Smuzhiyun reg_w(sd, 0x2b, v1 >> 16); /* V buf.1, high */
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun reg_w(sd, 0x32, y1 & 0xffff); /* JPEG buf 0 low */
385*4882a593Smuzhiyun reg_w(sd, 0x33, y1 >> 16); /* JPEG buf 0 high */
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun reg_w(sd, 0x34, y1 & 0xffff); /* JPEG buf 1 low */
388*4882a593Smuzhiyun reg_w(sd, 0x35, y1 >> 16); /* JPEG bug 1 high */
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun reg_w(sd, 0x36, 0x0000);/* JPEG restart interval */
391*4882a593Smuzhiyun reg_w(sd, 0x37, 0x0804);/*JPEG VLE FIFO threshold*/
392*4882a593Smuzhiyun reg_w(sd, 0x38, 0x0000);/* disable hw up-scaling */
393*4882a593Smuzhiyun reg_w(sd, 0x3f, 0x0000); /* JPEG/MCTL test data */
394*4882a593Smuzhiyun }
395*4882a593Smuzhiyun
w9968cf_set_crop_window(struct sd * sd)396*4882a593Smuzhiyun static void w9968cf_set_crop_window(struct sd *sd)
397*4882a593Smuzhiyun {
398*4882a593Smuzhiyun int start_cropx, start_cropy, x, y, fw, fh, cw, ch,
399*4882a593Smuzhiyun max_width, max_height;
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun if (sd->sif) {
402*4882a593Smuzhiyun max_width = 352;
403*4882a593Smuzhiyun max_height = 288;
404*4882a593Smuzhiyun } else {
405*4882a593Smuzhiyun max_width = 640;
406*4882a593Smuzhiyun max_height = 480;
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun if (sd->sensor == SEN_OV7620) {
410*4882a593Smuzhiyun /*
411*4882a593Smuzhiyun * Sigh, this is dependend on the clock / framerate changes
412*4882a593Smuzhiyun * made by the frequency control, sick.
413*4882a593Smuzhiyun *
414*4882a593Smuzhiyun * Note we cannot use v4l2_ctrl_g_ctrl here, as we get called
415*4882a593Smuzhiyun * from ov519.c:setfreq() with the ctrl lock held!
416*4882a593Smuzhiyun */
417*4882a593Smuzhiyun if (sd->freq->val == 1) {
418*4882a593Smuzhiyun start_cropx = 277;
419*4882a593Smuzhiyun start_cropy = 37;
420*4882a593Smuzhiyun } else {
421*4882a593Smuzhiyun start_cropx = 105;
422*4882a593Smuzhiyun start_cropy = 37;
423*4882a593Smuzhiyun }
424*4882a593Smuzhiyun } else {
425*4882a593Smuzhiyun start_cropx = 320;
426*4882a593Smuzhiyun start_cropy = 35;
427*4882a593Smuzhiyun }
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun /* Work around to avoid FP arithmetic */
430*4882a593Smuzhiyun #define SC(x) ((x) << 10)
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun /* Scaling factors */
433*4882a593Smuzhiyun fw = SC(sd->gspca_dev.pixfmt.width) / max_width;
434*4882a593Smuzhiyun fh = SC(sd->gspca_dev.pixfmt.height) / max_height;
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun cw = (fw >= fh) ? max_width : SC(sd->gspca_dev.pixfmt.width) / fh;
437*4882a593Smuzhiyun ch = (fw >= fh) ? SC(sd->gspca_dev.pixfmt.height) / fw : max_height;
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun sd->sensor_width = max_width;
440*4882a593Smuzhiyun sd->sensor_height = max_height;
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun x = (max_width - cw) / 2;
443*4882a593Smuzhiyun y = (max_height - ch) / 2;
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun reg_w(sd, 0x10, start_cropx + x);
446*4882a593Smuzhiyun reg_w(sd, 0x11, start_cropy + y);
447*4882a593Smuzhiyun reg_w(sd, 0x12, start_cropx + x + cw);
448*4882a593Smuzhiyun reg_w(sd, 0x13, start_cropy + y + ch);
449*4882a593Smuzhiyun }
450*4882a593Smuzhiyun
w9968cf_mode_init_regs(struct sd * sd)451*4882a593Smuzhiyun static void w9968cf_mode_init_regs(struct sd *sd)
452*4882a593Smuzhiyun {
453*4882a593Smuzhiyun int val, vs_polarity, hs_polarity;
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun w9968cf_set_crop_window(sd);
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun reg_w(sd, 0x14, sd->gspca_dev.pixfmt.width);
458*4882a593Smuzhiyun reg_w(sd, 0x15, sd->gspca_dev.pixfmt.height);
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun /* JPEG width & height */
461*4882a593Smuzhiyun reg_w(sd, 0x30, sd->gspca_dev.pixfmt.width);
462*4882a593Smuzhiyun reg_w(sd, 0x31, sd->gspca_dev.pixfmt.height);
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun /* Y & UV frame buffer strides (in WORD) */
465*4882a593Smuzhiyun if (w9968cf_vga_mode[sd->gspca_dev.curr_mode].pixelformat ==
466*4882a593Smuzhiyun V4L2_PIX_FMT_JPEG) {
467*4882a593Smuzhiyun reg_w(sd, 0x2c, sd->gspca_dev.pixfmt.width / 2);
468*4882a593Smuzhiyun reg_w(sd, 0x2d, sd->gspca_dev.pixfmt.width / 4);
469*4882a593Smuzhiyun } else
470*4882a593Smuzhiyun reg_w(sd, 0x2c, sd->gspca_dev.pixfmt.width);
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun reg_w(sd, 0x00, 0xbf17); /* reset everything */
473*4882a593Smuzhiyun reg_w(sd, 0x00, 0xbf10); /* normal operation */
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun /* Transfer size in WORDS (for UYVY format only) */
476*4882a593Smuzhiyun val = sd->gspca_dev.pixfmt.width * sd->gspca_dev.pixfmt.height;
477*4882a593Smuzhiyun reg_w(sd, 0x3d, val & 0xffff); /* low bits */
478*4882a593Smuzhiyun reg_w(sd, 0x3e, val >> 16); /* high bits */
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun if (w9968cf_vga_mode[sd->gspca_dev.curr_mode].pixelformat ==
481*4882a593Smuzhiyun V4L2_PIX_FMT_JPEG) {
482*4882a593Smuzhiyun /* We may get called multiple times (usb isoc bw negotiat.) */
483*4882a593Smuzhiyun jpeg_define(sd->jpeg_hdr, sd->gspca_dev.pixfmt.height,
484*4882a593Smuzhiyun sd->gspca_dev.pixfmt.width, 0x22); /* JPEG 420 */
485*4882a593Smuzhiyun jpeg_set_qual(sd->jpeg_hdr, v4l2_ctrl_g_ctrl(sd->jpegqual));
486*4882a593Smuzhiyun w9968cf_upload_quantizationtables(sd);
487*4882a593Smuzhiyun v4l2_ctrl_grab(sd->jpegqual, true);
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun /* Video Capture Control Register */
491*4882a593Smuzhiyun if (sd->sensor == SEN_OV7620) {
492*4882a593Smuzhiyun /* Seems to work around a bug in the image sensor */
493*4882a593Smuzhiyun vs_polarity = 1;
494*4882a593Smuzhiyun hs_polarity = 1;
495*4882a593Smuzhiyun } else {
496*4882a593Smuzhiyun vs_polarity = 1;
497*4882a593Smuzhiyun hs_polarity = 0;
498*4882a593Smuzhiyun }
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun val = (vs_polarity << 12) | (hs_polarity << 11);
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun /* NOTE: We may not have enough memory to do double buffering while
503*4882a593Smuzhiyun doing compression (amount of memory differs per model cam).
504*4882a593Smuzhiyun So we use the second image buffer also as jpeg stream buffer
505*4882a593Smuzhiyun (see w9968cf_init), and disable double buffering. */
506*4882a593Smuzhiyun if (w9968cf_vga_mode[sd->gspca_dev.curr_mode].pixelformat ==
507*4882a593Smuzhiyun V4L2_PIX_FMT_JPEG) {
508*4882a593Smuzhiyun /* val |= 0x0002; YUV422P */
509*4882a593Smuzhiyun val |= 0x0003; /* YUV420P */
510*4882a593Smuzhiyun } else
511*4882a593Smuzhiyun val |= 0x0080; /* Enable HW double buffering */
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun /* val |= 0x0020; enable clamping */
514*4882a593Smuzhiyun /* val |= 0x0008; enable (1-2-1) filter */
515*4882a593Smuzhiyun /* val |= 0x000c; enable (2-3-6-3-2) filter */
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun val |= 0x8000; /* capt. enable */
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun reg_w(sd, 0x16, val);
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun sd->gspca_dev.empty_packet = 0;
522*4882a593Smuzhiyun }
523*4882a593Smuzhiyun
w9968cf_stop0(struct sd * sd)524*4882a593Smuzhiyun static void w9968cf_stop0(struct sd *sd)
525*4882a593Smuzhiyun {
526*4882a593Smuzhiyun v4l2_ctrl_grab(sd->jpegqual, false);
527*4882a593Smuzhiyun reg_w(sd, 0x39, 0x0000); /* disable JPEG encoder */
528*4882a593Smuzhiyun reg_w(sd, 0x16, 0x0000); /* stop video capture */
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun /* The w9968cf docs say that a 0 sized packet means EOF (and also SOF
532*4882a593Smuzhiyun for the next frame). This seems to simply not be true when operating
533*4882a593Smuzhiyun in JPEG mode, in this case there may be empty packets within the
534*4882a593Smuzhiyun frame. So in JPEG mode use the JPEG SOI marker to detect SOF.
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun Note to make things even more interesting the w9968cf sends *PLANAR* jpeg,
537*4882a593Smuzhiyun to be precise it sends: SOI, SOF, DRI, SOS, Y-data, SOS, U-data, SOS,
538*4882a593Smuzhiyun V-data, EOI. */
w9968cf_pkt_scan(struct gspca_dev * gspca_dev,u8 * data,int len)539*4882a593Smuzhiyun static void w9968cf_pkt_scan(struct gspca_dev *gspca_dev,
540*4882a593Smuzhiyun u8 *data, /* isoc packet */
541*4882a593Smuzhiyun int len) /* iso packet length */
542*4882a593Smuzhiyun {
543*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun if (w9968cf_vga_mode[gspca_dev->curr_mode].pixelformat ==
546*4882a593Smuzhiyun V4L2_PIX_FMT_JPEG) {
547*4882a593Smuzhiyun if (len >= 2 &&
548*4882a593Smuzhiyun data[0] == 0xff &&
549*4882a593Smuzhiyun data[1] == 0xd8) {
550*4882a593Smuzhiyun gspca_frame_add(gspca_dev, LAST_PACKET,
551*4882a593Smuzhiyun NULL, 0);
552*4882a593Smuzhiyun gspca_frame_add(gspca_dev, FIRST_PACKET,
553*4882a593Smuzhiyun sd->jpeg_hdr, JPEG_HDR_SZ);
554*4882a593Smuzhiyun /* Strip the ff d8, our own header (which adds
555*4882a593Smuzhiyun huffman and quantization tables) already has this */
556*4882a593Smuzhiyun len -= 2;
557*4882a593Smuzhiyun data += 2;
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun } else {
560*4882a593Smuzhiyun /* In UYVY mode an empty packet signals EOF */
561*4882a593Smuzhiyun if (gspca_dev->empty_packet) {
562*4882a593Smuzhiyun gspca_frame_add(gspca_dev, LAST_PACKET,
563*4882a593Smuzhiyun NULL, 0);
564*4882a593Smuzhiyun gspca_frame_add(gspca_dev, FIRST_PACKET,
565*4882a593Smuzhiyun NULL, 0);
566*4882a593Smuzhiyun gspca_dev->empty_packet = 0;
567*4882a593Smuzhiyun }
568*4882a593Smuzhiyun }
569*4882a593Smuzhiyun gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
570*4882a593Smuzhiyun }
571