1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * OV519 driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2008-2011 Jean-François Moine <moinejf@free.fr>
6*4882a593Smuzhiyun * Copyright (C) 2009 Hans de Goede <hdegoede@redhat.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This module is adapted from the ov51x-jpeg package, which itself
9*4882a593Smuzhiyun * was adapted from the ov511 driver.
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Original copyright for the ov511 driver is:
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * Copyright (c) 1999-2006 Mark W. McClelland
14*4882a593Smuzhiyun * Support for OV519, OV8610 Copyright (c) 2003 Joerg Heckenbach
15*4882a593Smuzhiyun * Many improvements by Bret Wallach <bwallac1@san.rr.com>
16*4882a593Smuzhiyun * Color fixes by by Orion Sky Lawlor <olawlor@acm.org> (2/26/2000)
17*4882a593Smuzhiyun * OV7620 fixes by Charl P. Botha <cpbotha@ieee.org>
18*4882a593Smuzhiyun * Changes by Claudio Matsuoka <claudio@conectiva.com>
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * ov51x-jpeg original copyright is:
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * Copyright (c) 2004-2007 Romain Beauxis <toots@rastageeks.org>
23*4882a593Smuzhiyun * Support for OV7670 sensors was contributed by Sam Skipsey <aoanla@yahoo.com>
24*4882a593Smuzhiyun */
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define MODULE_NAME "ov519"
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #include <linux/input.h>
31*4882a593Smuzhiyun #include "gspca.h"
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* The jpeg_hdr is used by w996Xcf only */
34*4882a593Smuzhiyun /* The CONEX_CAM define for jpeg.h needs renaming, now its used here too */
35*4882a593Smuzhiyun #define CONEX_CAM
36*4882a593Smuzhiyun #include "jpeg.h"
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun MODULE_AUTHOR("Jean-Francois Moine <http://moinejf.free.fr>");
39*4882a593Smuzhiyun MODULE_DESCRIPTION("OV519 USB Camera Driver");
40*4882a593Smuzhiyun MODULE_LICENSE("GPL");
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* global parameters */
43*4882a593Smuzhiyun static int frame_rate;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* Number of times to retry a failed I2C transaction. Increase this if you
46*4882a593Smuzhiyun * are getting "Failed to read sensor ID..." */
47*4882a593Smuzhiyun static int i2c_detect_tries = 10;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* ov519 device descriptor */
50*4882a593Smuzhiyun struct sd {
51*4882a593Smuzhiyun struct gspca_dev gspca_dev; /* !! must be the first item */
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun struct v4l2_ctrl *jpegqual;
54*4882a593Smuzhiyun struct v4l2_ctrl *freq;
55*4882a593Smuzhiyun struct { /* h/vflip control cluster */
56*4882a593Smuzhiyun struct v4l2_ctrl *hflip;
57*4882a593Smuzhiyun struct v4l2_ctrl *vflip;
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun struct { /* autobrightness/brightness control cluster */
60*4882a593Smuzhiyun struct v4l2_ctrl *autobright;
61*4882a593Smuzhiyun struct v4l2_ctrl *brightness;
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun u8 revision;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun u8 packet_nr;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun char bridge;
69*4882a593Smuzhiyun #define BRIDGE_OV511 0
70*4882a593Smuzhiyun #define BRIDGE_OV511PLUS 1
71*4882a593Smuzhiyun #define BRIDGE_OV518 2
72*4882a593Smuzhiyun #define BRIDGE_OV518PLUS 3
73*4882a593Smuzhiyun #define BRIDGE_OV519 4 /* = ov530 */
74*4882a593Smuzhiyun #define BRIDGE_OVFX2 5
75*4882a593Smuzhiyun #define BRIDGE_W9968CF 6
76*4882a593Smuzhiyun #define BRIDGE_MASK 7
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun char invert_led;
79*4882a593Smuzhiyun #define BRIDGE_INVERT_LED 8
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun char snapshot_pressed;
82*4882a593Smuzhiyun char snapshot_needs_reset;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* Determined by sensor type */
85*4882a593Smuzhiyun u8 sif;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun #define QUALITY_MIN 50
88*4882a593Smuzhiyun #define QUALITY_MAX 70
89*4882a593Smuzhiyun #define QUALITY_DEF 50
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun u8 stopped; /* Streaming is temporarily paused */
92*4882a593Smuzhiyun u8 first_frame;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun u8 frame_rate; /* current Framerate */
95*4882a593Smuzhiyun u8 clockdiv; /* clockdiv override */
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun s8 sensor; /* Type of image sensor chip (SEN_*) */
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun u8 sensor_addr;
100*4882a593Smuzhiyun u16 sensor_width;
101*4882a593Smuzhiyun u16 sensor_height;
102*4882a593Smuzhiyun s16 sensor_reg_cache[256];
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun u8 jpeg_hdr[JPEG_HDR_SZ];
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun enum sensors {
107*4882a593Smuzhiyun SEN_OV2610,
108*4882a593Smuzhiyun SEN_OV2610AE,
109*4882a593Smuzhiyun SEN_OV3610,
110*4882a593Smuzhiyun SEN_OV6620,
111*4882a593Smuzhiyun SEN_OV6630,
112*4882a593Smuzhiyun SEN_OV66308AF,
113*4882a593Smuzhiyun SEN_OV7610,
114*4882a593Smuzhiyun SEN_OV7620,
115*4882a593Smuzhiyun SEN_OV7620AE,
116*4882a593Smuzhiyun SEN_OV7640,
117*4882a593Smuzhiyun SEN_OV7648,
118*4882a593Smuzhiyun SEN_OV7660,
119*4882a593Smuzhiyun SEN_OV7670,
120*4882a593Smuzhiyun SEN_OV76BE,
121*4882a593Smuzhiyun SEN_OV8610,
122*4882a593Smuzhiyun SEN_OV9600,
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* Note this is a bit of a hack, but the w9968cf driver needs the code for all
126*4882a593Smuzhiyun the ov sensors which is already present here. When we have the time we
127*4882a593Smuzhiyun really should move the sensor drivers to v4l2 sub drivers. */
128*4882a593Smuzhiyun #include "w996Xcf.c"
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun /* table of the disabled controls */
131*4882a593Smuzhiyun struct ctrl_valid {
132*4882a593Smuzhiyun unsigned int has_brightness:1;
133*4882a593Smuzhiyun unsigned int has_contrast:1;
134*4882a593Smuzhiyun unsigned int has_exposure:1;
135*4882a593Smuzhiyun unsigned int has_autogain:1;
136*4882a593Smuzhiyun unsigned int has_sat:1;
137*4882a593Smuzhiyun unsigned int has_hvflip:1;
138*4882a593Smuzhiyun unsigned int has_autobright:1;
139*4882a593Smuzhiyun unsigned int has_freq:1;
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun static const struct ctrl_valid valid_controls[] = {
143*4882a593Smuzhiyun [SEN_OV2610] = {
144*4882a593Smuzhiyun .has_exposure = 1,
145*4882a593Smuzhiyun .has_autogain = 1,
146*4882a593Smuzhiyun },
147*4882a593Smuzhiyun [SEN_OV2610AE] = {
148*4882a593Smuzhiyun .has_exposure = 1,
149*4882a593Smuzhiyun .has_autogain = 1,
150*4882a593Smuzhiyun },
151*4882a593Smuzhiyun [SEN_OV3610] = {
152*4882a593Smuzhiyun /* No controls */
153*4882a593Smuzhiyun },
154*4882a593Smuzhiyun [SEN_OV6620] = {
155*4882a593Smuzhiyun .has_brightness = 1,
156*4882a593Smuzhiyun .has_contrast = 1,
157*4882a593Smuzhiyun .has_sat = 1,
158*4882a593Smuzhiyun .has_autobright = 1,
159*4882a593Smuzhiyun .has_freq = 1,
160*4882a593Smuzhiyun },
161*4882a593Smuzhiyun [SEN_OV6630] = {
162*4882a593Smuzhiyun .has_brightness = 1,
163*4882a593Smuzhiyun .has_contrast = 1,
164*4882a593Smuzhiyun .has_sat = 1,
165*4882a593Smuzhiyun .has_autobright = 1,
166*4882a593Smuzhiyun .has_freq = 1,
167*4882a593Smuzhiyun },
168*4882a593Smuzhiyun [SEN_OV66308AF] = {
169*4882a593Smuzhiyun .has_brightness = 1,
170*4882a593Smuzhiyun .has_contrast = 1,
171*4882a593Smuzhiyun .has_sat = 1,
172*4882a593Smuzhiyun .has_autobright = 1,
173*4882a593Smuzhiyun .has_freq = 1,
174*4882a593Smuzhiyun },
175*4882a593Smuzhiyun [SEN_OV7610] = {
176*4882a593Smuzhiyun .has_brightness = 1,
177*4882a593Smuzhiyun .has_contrast = 1,
178*4882a593Smuzhiyun .has_sat = 1,
179*4882a593Smuzhiyun .has_autobright = 1,
180*4882a593Smuzhiyun .has_freq = 1,
181*4882a593Smuzhiyun },
182*4882a593Smuzhiyun [SEN_OV7620] = {
183*4882a593Smuzhiyun .has_brightness = 1,
184*4882a593Smuzhiyun .has_contrast = 1,
185*4882a593Smuzhiyun .has_sat = 1,
186*4882a593Smuzhiyun .has_autobright = 1,
187*4882a593Smuzhiyun .has_freq = 1,
188*4882a593Smuzhiyun },
189*4882a593Smuzhiyun [SEN_OV7620AE] = {
190*4882a593Smuzhiyun .has_brightness = 1,
191*4882a593Smuzhiyun .has_contrast = 1,
192*4882a593Smuzhiyun .has_sat = 1,
193*4882a593Smuzhiyun .has_autobright = 1,
194*4882a593Smuzhiyun .has_freq = 1,
195*4882a593Smuzhiyun },
196*4882a593Smuzhiyun [SEN_OV7640] = {
197*4882a593Smuzhiyun .has_brightness = 1,
198*4882a593Smuzhiyun .has_sat = 1,
199*4882a593Smuzhiyun .has_freq = 1,
200*4882a593Smuzhiyun },
201*4882a593Smuzhiyun [SEN_OV7648] = {
202*4882a593Smuzhiyun .has_brightness = 1,
203*4882a593Smuzhiyun .has_sat = 1,
204*4882a593Smuzhiyun .has_freq = 1,
205*4882a593Smuzhiyun },
206*4882a593Smuzhiyun [SEN_OV7660] = {
207*4882a593Smuzhiyun .has_brightness = 1,
208*4882a593Smuzhiyun .has_contrast = 1,
209*4882a593Smuzhiyun .has_sat = 1,
210*4882a593Smuzhiyun .has_hvflip = 1,
211*4882a593Smuzhiyun .has_freq = 1,
212*4882a593Smuzhiyun },
213*4882a593Smuzhiyun [SEN_OV7670] = {
214*4882a593Smuzhiyun .has_brightness = 1,
215*4882a593Smuzhiyun .has_contrast = 1,
216*4882a593Smuzhiyun .has_hvflip = 1,
217*4882a593Smuzhiyun .has_freq = 1,
218*4882a593Smuzhiyun },
219*4882a593Smuzhiyun [SEN_OV76BE] = {
220*4882a593Smuzhiyun .has_brightness = 1,
221*4882a593Smuzhiyun .has_contrast = 1,
222*4882a593Smuzhiyun .has_sat = 1,
223*4882a593Smuzhiyun .has_autobright = 1,
224*4882a593Smuzhiyun .has_freq = 1,
225*4882a593Smuzhiyun },
226*4882a593Smuzhiyun [SEN_OV8610] = {
227*4882a593Smuzhiyun .has_brightness = 1,
228*4882a593Smuzhiyun .has_contrast = 1,
229*4882a593Smuzhiyun .has_sat = 1,
230*4882a593Smuzhiyun .has_autobright = 1,
231*4882a593Smuzhiyun },
232*4882a593Smuzhiyun [SEN_OV9600] = {
233*4882a593Smuzhiyun .has_exposure = 1,
234*4882a593Smuzhiyun .has_autogain = 1,
235*4882a593Smuzhiyun },
236*4882a593Smuzhiyun };
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun static const struct v4l2_pix_format ov519_vga_mode[] = {
239*4882a593Smuzhiyun {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
240*4882a593Smuzhiyun .bytesperline = 320,
241*4882a593Smuzhiyun .sizeimage = 320 * 240 * 3 / 8 + 590,
242*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG,
243*4882a593Smuzhiyun .priv = 1},
244*4882a593Smuzhiyun {640, 480, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
245*4882a593Smuzhiyun .bytesperline = 640,
246*4882a593Smuzhiyun .sizeimage = 640 * 480 * 3 / 8 + 590,
247*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG,
248*4882a593Smuzhiyun .priv = 0},
249*4882a593Smuzhiyun };
250*4882a593Smuzhiyun static const struct v4l2_pix_format ov519_sif_mode[] = {
251*4882a593Smuzhiyun {160, 120, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
252*4882a593Smuzhiyun .bytesperline = 160,
253*4882a593Smuzhiyun .sizeimage = 160 * 120 * 3 / 8 + 590,
254*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG,
255*4882a593Smuzhiyun .priv = 3},
256*4882a593Smuzhiyun {176, 144, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
257*4882a593Smuzhiyun .bytesperline = 176,
258*4882a593Smuzhiyun .sizeimage = 176 * 144 * 3 / 8 + 590,
259*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG,
260*4882a593Smuzhiyun .priv = 1},
261*4882a593Smuzhiyun {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
262*4882a593Smuzhiyun .bytesperline = 320,
263*4882a593Smuzhiyun .sizeimage = 320 * 240 * 3 / 8 + 590,
264*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG,
265*4882a593Smuzhiyun .priv = 2},
266*4882a593Smuzhiyun {352, 288, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
267*4882a593Smuzhiyun .bytesperline = 352,
268*4882a593Smuzhiyun .sizeimage = 352 * 288 * 3 / 8 + 590,
269*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG,
270*4882a593Smuzhiyun .priv = 0},
271*4882a593Smuzhiyun };
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun /* Note some of the sizeimage values for the ov511 / ov518 may seem
274*4882a593Smuzhiyun larger then necessary, however they need to be this big as the ov511 /
275*4882a593Smuzhiyun ov518 always fills the entire isoc frame, using 0 padding bytes when
276*4882a593Smuzhiyun it doesn't have any data. So with low framerates the amount of data
277*4882a593Smuzhiyun transferred can become quite large (libv4l will remove all the 0 padding
278*4882a593Smuzhiyun in userspace). */
279*4882a593Smuzhiyun static const struct v4l2_pix_format ov518_vga_mode[] = {
280*4882a593Smuzhiyun {320, 240, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
281*4882a593Smuzhiyun .bytesperline = 320,
282*4882a593Smuzhiyun .sizeimage = 320 * 240 * 3,
283*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG,
284*4882a593Smuzhiyun .priv = 1},
285*4882a593Smuzhiyun {640, 480, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
286*4882a593Smuzhiyun .bytesperline = 640,
287*4882a593Smuzhiyun .sizeimage = 640 * 480 * 2,
288*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG,
289*4882a593Smuzhiyun .priv = 0},
290*4882a593Smuzhiyun };
291*4882a593Smuzhiyun static const struct v4l2_pix_format ov518_sif_mode[] = {
292*4882a593Smuzhiyun {160, 120, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
293*4882a593Smuzhiyun .bytesperline = 160,
294*4882a593Smuzhiyun .sizeimage = 70000,
295*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG,
296*4882a593Smuzhiyun .priv = 3},
297*4882a593Smuzhiyun {176, 144, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
298*4882a593Smuzhiyun .bytesperline = 176,
299*4882a593Smuzhiyun .sizeimage = 70000,
300*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG,
301*4882a593Smuzhiyun .priv = 1},
302*4882a593Smuzhiyun {320, 240, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
303*4882a593Smuzhiyun .bytesperline = 320,
304*4882a593Smuzhiyun .sizeimage = 320 * 240 * 3,
305*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG,
306*4882a593Smuzhiyun .priv = 2},
307*4882a593Smuzhiyun {352, 288, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
308*4882a593Smuzhiyun .bytesperline = 352,
309*4882a593Smuzhiyun .sizeimage = 352 * 288 * 3,
310*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG,
311*4882a593Smuzhiyun .priv = 0},
312*4882a593Smuzhiyun };
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun static const struct v4l2_pix_format ov511_vga_mode[] = {
315*4882a593Smuzhiyun {320, 240, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
316*4882a593Smuzhiyun .bytesperline = 320,
317*4882a593Smuzhiyun .sizeimage = 320 * 240 * 3,
318*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG,
319*4882a593Smuzhiyun .priv = 1},
320*4882a593Smuzhiyun {640, 480, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
321*4882a593Smuzhiyun .bytesperline = 640,
322*4882a593Smuzhiyun .sizeimage = 640 * 480 * 2,
323*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG,
324*4882a593Smuzhiyun .priv = 0},
325*4882a593Smuzhiyun };
326*4882a593Smuzhiyun static const struct v4l2_pix_format ov511_sif_mode[] = {
327*4882a593Smuzhiyun {160, 120, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
328*4882a593Smuzhiyun .bytesperline = 160,
329*4882a593Smuzhiyun .sizeimage = 70000,
330*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG,
331*4882a593Smuzhiyun .priv = 3},
332*4882a593Smuzhiyun {176, 144, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
333*4882a593Smuzhiyun .bytesperline = 176,
334*4882a593Smuzhiyun .sizeimage = 70000,
335*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG,
336*4882a593Smuzhiyun .priv = 1},
337*4882a593Smuzhiyun {320, 240, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
338*4882a593Smuzhiyun .bytesperline = 320,
339*4882a593Smuzhiyun .sizeimage = 320 * 240 * 3,
340*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG,
341*4882a593Smuzhiyun .priv = 2},
342*4882a593Smuzhiyun {352, 288, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
343*4882a593Smuzhiyun .bytesperline = 352,
344*4882a593Smuzhiyun .sizeimage = 352 * 288 * 3,
345*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_JPEG,
346*4882a593Smuzhiyun .priv = 0},
347*4882a593Smuzhiyun };
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun static const struct v4l2_pix_format ovfx2_ov2610_mode[] = {
350*4882a593Smuzhiyun {800, 600, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
351*4882a593Smuzhiyun .bytesperline = 800,
352*4882a593Smuzhiyun .sizeimage = 800 * 600,
353*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_SRGB,
354*4882a593Smuzhiyun .priv = 1},
355*4882a593Smuzhiyun {1600, 1200, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
356*4882a593Smuzhiyun .bytesperline = 1600,
357*4882a593Smuzhiyun .sizeimage = 1600 * 1200,
358*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_SRGB},
359*4882a593Smuzhiyun };
360*4882a593Smuzhiyun static const struct v4l2_pix_format ovfx2_ov3610_mode[] = {
361*4882a593Smuzhiyun {640, 480, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
362*4882a593Smuzhiyun .bytesperline = 640,
363*4882a593Smuzhiyun .sizeimage = 640 * 480,
364*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_SRGB,
365*4882a593Smuzhiyun .priv = 1},
366*4882a593Smuzhiyun {800, 600, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
367*4882a593Smuzhiyun .bytesperline = 800,
368*4882a593Smuzhiyun .sizeimage = 800 * 600,
369*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_SRGB,
370*4882a593Smuzhiyun .priv = 1},
371*4882a593Smuzhiyun {1024, 768, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
372*4882a593Smuzhiyun .bytesperline = 1024,
373*4882a593Smuzhiyun .sizeimage = 1024 * 768,
374*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_SRGB,
375*4882a593Smuzhiyun .priv = 1},
376*4882a593Smuzhiyun {1600, 1200, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
377*4882a593Smuzhiyun .bytesperline = 1600,
378*4882a593Smuzhiyun .sizeimage = 1600 * 1200,
379*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_SRGB,
380*4882a593Smuzhiyun .priv = 0},
381*4882a593Smuzhiyun {2048, 1536, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
382*4882a593Smuzhiyun .bytesperline = 2048,
383*4882a593Smuzhiyun .sizeimage = 2048 * 1536,
384*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_SRGB,
385*4882a593Smuzhiyun .priv = 0},
386*4882a593Smuzhiyun };
387*4882a593Smuzhiyun static const struct v4l2_pix_format ovfx2_ov9600_mode[] = {
388*4882a593Smuzhiyun {640, 480, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
389*4882a593Smuzhiyun .bytesperline = 640,
390*4882a593Smuzhiyun .sizeimage = 640 * 480,
391*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_SRGB,
392*4882a593Smuzhiyun .priv = 1},
393*4882a593Smuzhiyun {1280, 1024, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
394*4882a593Smuzhiyun .bytesperline = 1280,
395*4882a593Smuzhiyun .sizeimage = 1280 * 1024,
396*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_SRGB},
397*4882a593Smuzhiyun };
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun /* Registers common to OV511 / OV518 */
400*4882a593Smuzhiyun #define R51x_FIFO_PSIZE 0x30 /* 2 bytes wide w/ OV518(+) */
401*4882a593Smuzhiyun #define R51x_SYS_RESET 0x50
402*4882a593Smuzhiyun /* Reset type flags */
403*4882a593Smuzhiyun #define OV511_RESET_OMNICE 0x08
404*4882a593Smuzhiyun #define R51x_SYS_INIT 0x53
405*4882a593Smuzhiyun #define R51x_SYS_SNAP 0x52
406*4882a593Smuzhiyun #define R51x_SYS_CUST_ID 0x5f
407*4882a593Smuzhiyun #define R51x_COMP_LUT_BEGIN 0x80
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun /* OV511 Camera interface register numbers */
410*4882a593Smuzhiyun #define R511_CAM_DELAY 0x10
411*4882a593Smuzhiyun #define R511_CAM_EDGE 0x11
412*4882a593Smuzhiyun #define R511_CAM_PXCNT 0x12
413*4882a593Smuzhiyun #define R511_CAM_LNCNT 0x13
414*4882a593Smuzhiyun #define R511_CAM_PXDIV 0x14
415*4882a593Smuzhiyun #define R511_CAM_LNDIV 0x15
416*4882a593Smuzhiyun #define R511_CAM_UV_EN 0x16
417*4882a593Smuzhiyun #define R511_CAM_LINE_MODE 0x17
418*4882a593Smuzhiyun #define R511_CAM_OPTS 0x18
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun #define R511_SNAP_FRAME 0x19
421*4882a593Smuzhiyun #define R511_SNAP_PXCNT 0x1a
422*4882a593Smuzhiyun #define R511_SNAP_LNCNT 0x1b
423*4882a593Smuzhiyun #define R511_SNAP_PXDIV 0x1c
424*4882a593Smuzhiyun #define R511_SNAP_LNDIV 0x1d
425*4882a593Smuzhiyun #define R511_SNAP_UV_EN 0x1e
426*4882a593Smuzhiyun #define R511_SNAP_OPTS 0x1f
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun #define R511_DRAM_FLOW_CTL 0x20
429*4882a593Smuzhiyun #define R511_FIFO_OPTS 0x31
430*4882a593Smuzhiyun #define R511_I2C_CTL 0x40
431*4882a593Smuzhiyun #define R511_SYS_LED_CTL 0x55 /* OV511+ only */
432*4882a593Smuzhiyun #define R511_COMP_EN 0x78
433*4882a593Smuzhiyun #define R511_COMP_LUT_EN 0x79
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun /* OV518 Camera interface register numbers */
436*4882a593Smuzhiyun #define R518_GPIO_OUT 0x56 /* OV518(+) only */
437*4882a593Smuzhiyun #define R518_GPIO_CTL 0x57 /* OV518(+) only */
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun /* OV519 Camera interface register numbers */
440*4882a593Smuzhiyun #define OV519_R10_H_SIZE 0x10
441*4882a593Smuzhiyun #define OV519_R11_V_SIZE 0x11
442*4882a593Smuzhiyun #define OV519_R12_X_OFFSETL 0x12
443*4882a593Smuzhiyun #define OV519_R13_X_OFFSETH 0x13
444*4882a593Smuzhiyun #define OV519_R14_Y_OFFSETL 0x14
445*4882a593Smuzhiyun #define OV519_R15_Y_OFFSETH 0x15
446*4882a593Smuzhiyun #define OV519_R16_DIVIDER 0x16
447*4882a593Smuzhiyun #define OV519_R20_DFR 0x20
448*4882a593Smuzhiyun #define OV519_R25_FORMAT 0x25
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun /* OV519 System Controller register numbers */
451*4882a593Smuzhiyun #define OV519_R51_RESET1 0x51
452*4882a593Smuzhiyun #define OV519_R54_EN_CLK1 0x54
453*4882a593Smuzhiyun #define OV519_R57_SNAPSHOT 0x57
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun #define OV519_GPIO_DATA_OUT0 0x71
456*4882a593Smuzhiyun #define OV519_GPIO_IO_CTRL0 0x72
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun /*#define OV511_ENDPOINT_ADDRESS 1 * Isoc endpoint number */
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun /*
461*4882a593Smuzhiyun * The FX2 chip does not give us a zero length read at end of frame.
462*4882a593Smuzhiyun * It does, however, give a short read at the end of a frame, if
463*4882a593Smuzhiyun * necessary, rather than run two frames together.
464*4882a593Smuzhiyun *
465*4882a593Smuzhiyun * By choosing the right bulk transfer size, we are guaranteed to always
466*4882a593Smuzhiyun * get a short read for the last read of each frame. Frame sizes are
467*4882a593Smuzhiyun * always a composite number (width * height, or a multiple) so if we
468*4882a593Smuzhiyun * choose a prime number, we are guaranteed that the last read of a
469*4882a593Smuzhiyun * frame will be short.
470*4882a593Smuzhiyun *
471*4882a593Smuzhiyun * But it isn't that easy: the 2.6 kernel requires a multiple of 4KB,
472*4882a593Smuzhiyun * otherwise EOVERFLOW "babbling" errors occur. I have not been able
473*4882a593Smuzhiyun * to figure out why. [PMiller]
474*4882a593Smuzhiyun *
475*4882a593Smuzhiyun * The constant (13 * 4096) is the largest "prime enough" number less than 64KB.
476*4882a593Smuzhiyun *
477*4882a593Smuzhiyun * It isn't enough to know the number of bytes per frame, in case we
478*4882a593Smuzhiyun * have data dropouts or buffer overruns (even though the FX2 double
479*4882a593Smuzhiyun * buffers, there are some pretty strict real time constraints for
480*4882a593Smuzhiyun * isochronous transfer for larger frame sizes).
481*4882a593Smuzhiyun */
482*4882a593Smuzhiyun /*jfm: this value does not work for 800x600 - see isoc_init */
483*4882a593Smuzhiyun #define OVFX2_BULK_SIZE (13 * 4096)
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun /* I2C registers */
486*4882a593Smuzhiyun #define R51x_I2C_W_SID 0x41
487*4882a593Smuzhiyun #define R51x_I2C_SADDR_3 0x42
488*4882a593Smuzhiyun #define R51x_I2C_SADDR_2 0x43
489*4882a593Smuzhiyun #define R51x_I2C_R_SID 0x44
490*4882a593Smuzhiyun #define R51x_I2C_DATA 0x45
491*4882a593Smuzhiyun #define R518_I2C_CTL 0x47 /* OV518(+) only */
492*4882a593Smuzhiyun #define OVFX2_I2C_ADDR 0x00
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun /* I2C ADDRESSES */
495*4882a593Smuzhiyun #define OV7xx0_SID 0x42
496*4882a593Smuzhiyun #define OV_HIRES_SID 0x60 /* OV9xxx / OV2xxx / OV3xxx */
497*4882a593Smuzhiyun #define OV8xx0_SID 0xa0
498*4882a593Smuzhiyun #define OV6xx0_SID 0xc0
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun /* OV7610 registers */
501*4882a593Smuzhiyun #define OV7610_REG_GAIN 0x00 /* gain setting (5:0) */
502*4882a593Smuzhiyun #define OV7610_REG_BLUE 0x01 /* blue channel balance */
503*4882a593Smuzhiyun #define OV7610_REG_RED 0x02 /* red channel balance */
504*4882a593Smuzhiyun #define OV7610_REG_SAT 0x03 /* saturation */
505*4882a593Smuzhiyun #define OV8610_REG_HUE 0x04 /* 04 reserved */
506*4882a593Smuzhiyun #define OV7610_REG_CNT 0x05 /* Y contrast */
507*4882a593Smuzhiyun #define OV7610_REG_BRT 0x06 /* Y brightness */
508*4882a593Smuzhiyun #define OV7610_REG_COM_C 0x14 /* misc common regs */
509*4882a593Smuzhiyun #define OV7610_REG_ID_HIGH 0x1c /* manufacturer ID MSB */
510*4882a593Smuzhiyun #define OV7610_REG_ID_LOW 0x1d /* manufacturer ID LSB */
511*4882a593Smuzhiyun #define OV7610_REG_COM_I 0x29 /* misc settings */
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun /* OV7660 and OV7670 registers */
514*4882a593Smuzhiyun #define OV7670_R00_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
515*4882a593Smuzhiyun #define OV7670_R01_BLUE 0x01 /* blue gain */
516*4882a593Smuzhiyun #define OV7670_R02_RED 0x02 /* red gain */
517*4882a593Smuzhiyun #define OV7670_R03_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
518*4882a593Smuzhiyun #define OV7670_R04_COM1 0x04 /* Control 1 */
519*4882a593Smuzhiyun /*#define OV7670_R07_AECHH 0x07 * AEC MS 5 bits */
520*4882a593Smuzhiyun #define OV7670_R0C_COM3 0x0c /* Control 3 */
521*4882a593Smuzhiyun #define OV7670_R0D_COM4 0x0d /* Control 4 */
522*4882a593Smuzhiyun #define OV7670_R0E_COM5 0x0e /* All "reserved" */
523*4882a593Smuzhiyun #define OV7670_R0F_COM6 0x0f /* Control 6 */
524*4882a593Smuzhiyun #define OV7670_R10_AECH 0x10 /* More bits of AEC value */
525*4882a593Smuzhiyun #define OV7670_R11_CLKRC 0x11 /* Clock control */
526*4882a593Smuzhiyun #define OV7670_R12_COM7 0x12 /* Control 7 */
527*4882a593Smuzhiyun #define OV7670_COM7_FMT_VGA 0x00
528*4882a593Smuzhiyun /*#define OV7670_COM7_YUV 0x00 * YUV */
529*4882a593Smuzhiyun #define OV7670_COM7_FMT_QVGA 0x10 /* QVGA format */
530*4882a593Smuzhiyun #define OV7670_COM7_FMT_MASK 0x38
531*4882a593Smuzhiyun #define OV7670_COM7_RESET 0x80 /* Register reset */
532*4882a593Smuzhiyun #define OV7670_R13_COM8 0x13 /* Control 8 */
533*4882a593Smuzhiyun #define OV7670_COM8_AEC 0x01 /* Auto exposure enable */
534*4882a593Smuzhiyun #define OV7670_COM8_AWB 0x02 /* White balance enable */
535*4882a593Smuzhiyun #define OV7670_COM8_AGC 0x04 /* Auto gain enable */
536*4882a593Smuzhiyun #define OV7670_COM8_BFILT 0x20 /* Band filter enable */
537*4882a593Smuzhiyun #define OV7670_COM8_AECSTEP 0x40 /* Unlimited AEC step size */
538*4882a593Smuzhiyun #define OV7670_COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
539*4882a593Smuzhiyun #define OV7670_R14_COM9 0x14 /* Control 9 - gain ceiling */
540*4882a593Smuzhiyun #define OV7670_R15_COM10 0x15 /* Control 10 */
541*4882a593Smuzhiyun #define OV7670_R17_HSTART 0x17 /* Horiz start high bits */
542*4882a593Smuzhiyun #define OV7670_R18_HSTOP 0x18 /* Horiz stop high bits */
543*4882a593Smuzhiyun #define OV7670_R19_VSTART 0x19 /* Vert start high bits */
544*4882a593Smuzhiyun #define OV7670_R1A_VSTOP 0x1a /* Vert stop high bits */
545*4882a593Smuzhiyun #define OV7670_R1E_MVFP 0x1e /* Mirror / vflip */
546*4882a593Smuzhiyun #define OV7670_MVFP_VFLIP 0x10 /* vertical flip */
547*4882a593Smuzhiyun #define OV7670_MVFP_MIRROR 0x20 /* Mirror image */
548*4882a593Smuzhiyun #define OV7670_R24_AEW 0x24 /* AGC upper limit */
549*4882a593Smuzhiyun #define OV7670_R25_AEB 0x25 /* AGC lower limit */
550*4882a593Smuzhiyun #define OV7670_R26_VPT 0x26 /* AGC/AEC fast mode op region */
551*4882a593Smuzhiyun #define OV7670_R32_HREF 0x32 /* HREF pieces */
552*4882a593Smuzhiyun #define OV7670_R3A_TSLB 0x3a /* lots of stuff */
553*4882a593Smuzhiyun #define OV7670_R3B_COM11 0x3b /* Control 11 */
554*4882a593Smuzhiyun #define OV7670_COM11_EXP 0x02
555*4882a593Smuzhiyun #define OV7670_COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
556*4882a593Smuzhiyun #define OV7670_R3C_COM12 0x3c /* Control 12 */
557*4882a593Smuzhiyun #define OV7670_R3D_COM13 0x3d /* Control 13 */
558*4882a593Smuzhiyun #define OV7670_COM13_GAMMA 0x80 /* Gamma enable */
559*4882a593Smuzhiyun #define OV7670_COM13_UVSAT 0x40 /* UV saturation auto adjustment */
560*4882a593Smuzhiyun #define OV7670_R3E_COM14 0x3e /* Control 14 */
561*4882a593Smuzhiyun #define OV7670_R3F_EDGE 0x3f /* Edge enhancement factor */
562*4882a593Smuzhiyun #define OV7670_R40_COM15 0x40 /* Control 15 */
563*4882a593Smuzhiyun /*#define OV7670_COM15_R00FF 0xc0 * 00 to FF */
564*4882a593Smuzhiyun #define OV7670_R41_COM16 0x41 /* Control 16 */
565*4882a593Smuzhiyun #define OV7670_COM16_AWBGAIN 0x08 /* AWB gain enable */
566*4882a593Smuzhiyun /* end of ov7660 common registers */
567*4882a593Smuzhiyun #define OV7670_R55_BRIGHT 0x55 /* Brightness */
568*4882a593Smuzhiyun #define OV7670_R56_CONTRAS 0x56 /* Contrast control */
569*4882a593Smuzhiyun #define OV7670_R69_GFIX 0x69 /* Fix gain control */
570*4882a593Smuzhiyun /*#define OV7670_R8C_RGB444 0x8c * RGB 444 control */
571*4882a593Smuzhiyun #define OV7670_R9F_HAECC1 0x9f /* Hist AEC/AGC control 1 */
572*4882a593Smuzhiyun #define OV7670_RA0_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
573*4882a593Smuzhiyun #define OV7670_RA5_BD50MAX 0xa5 /* 50hz banding step limit */
574*4882a593Smuzhiyun #define OV7670_RA6_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
575*4882a593Smuzhiyun #define OV7670_RA7_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
576*4882a593Smuzhiyun #define OV7670_RA8_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
577*4882a593Smuzhiyun #define OV7670_RA9_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
578*4882a593Smuzhiyun #define OV7670_RAA_HAECC7 0xaa /* Hist AEC/AGC control 7 */
579*4882a593Smuzhiyun #define OV7670_RAB_BD60MAX 0xab /* 60hz banding step limit */
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun struct ov_regvals {
582*4882a593Smuzhiyun u8 reg;
583*4882a593Smuzhiyun u8 val;
584*4882a593Smuzhiyun };
585*4882a593Smuzhiyun struct ov_i2c_regvals {
586*4882a593Smuzhiyun u8 reg;
587*4882a593Smuzhiyun u8 val;
588*4882a593Smuzhiyun };
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun /* Settings for OV2610 camera chip */
591*4882a593Smuzhiyun static const struct ov_i2c_regvals norm_2610[] = {
592*4882a593Smuzhiyun { 0x12, 0x80 }, /* reset */
593*4882a593Smuzhiyun };
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun static const struct ov_i2c_regvals norm_2610ae[] = {
596*4882a593Smuzhiyun {0x12, 0x80}, /* reset */
597*4882a593Smuzhiyun {0x13, 0xcd},
598*4882a593Smuzhiyun {0x09, 0x01},
599*4882a593Smuzhiyun {0x0d, 0x00},
600*4882a593Smuzhiyun {0x11, 0x80},
601*4882a593Smuzhiyun {0x12, 0x20}, /* 1600x1200 */
602*4882a593Smuzhiyun {0x33, 0x0c},
603*4882a593Smuzhiyun {0x35, 0x90},
604*4882a593Smuzhiyun {0x36, 0x37},
605*4882a593Smuzhiyun /* ms-win traces */
606*4882a593Smuzhiyun {0x11, 0x83}, /* clock / 3 ? */
607*4882a593Smuzhiyun {0x2d, 0x00}, /* 60 Hz filter */
608*4882a593Smuzhiyun {0x24, 0xb0}, /* normal colors */
609*4882a593Smuzhiyun {0x25, 0x90},
610*4882a593Smuzhiyun {0x10, 0x43},
611*4882a593Smuzhiyun };
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun static const struct ov_i2c_regvals norm_3620b[] = {
614*4882a593Smuzhiyun /*
615*4882a593Smuzhiyun * From the datasheet: "Note that after writing to register COMH
616*4882a593Smuzhiyun * (0x12) to change the sensor mode, registers related to the
617*4882a593Smuzhiyun * sensor’s cropping window will be reset back to their default
618*4882a593Smuzhiyun * values."
619*4882a593Smuzhiyun *
620*4882a593Smuzhiyun * "wait 4096 external clock ... to make sure the sensor is
621*4882a593Smuzhiyun * stable and ready to access registers" i.e. 160us at 24MHz
622*4882a593Smuzhiyun */
623*4882a593Smuzhiyun { 0x12, 0x80 }, /* COMH reset */
624*4882a593Smuzhiyun { 0x12, 0x00 }, /* QXGA, master */
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun /*
627*4882a593Smuzhiyun * 11 CLKRC "Clock Rate Control"
628*4882a593Smuzhiyun * [7] internal frequency doublers: on
629*4882a593Smuzhiyun * [6] video port mode: master
630*4882a593Smuzhiyun * [5:0] clock divider: 1
631*4882a593Smuzhiyun */
632*4882a593Smuzhiyun { 0x11, 0x80 },
633*4882a593Smuzhiyun
634*4882a593Smuzhiyun /*
635*4882a593Smuzhiyun * 13 COMI "Common Control I"
636*4882a593Smuzhiyun * = 192 (0xC0) 11000000
637*4882a593Smuzhiyun * COMI[7] "AEC speed selection"
638*4882a593Smuzhiyun * = 1 (0x01) 1....... "Faster AEC correction"
639*4882a593Smuzhiyun * COMI[6] "AEC speed step selection"
640*4882a593Smuzhiyun * = 1 (0x01) .1...... "Big steps, fast"
641*4882a593Smuzhiyun * COMI[5] "Banding filter on off"
642*4882a593Smuzhiyun * = 0 (0x00) ..0..... "Off"
643*4882a593Smuzhiyun * COMI[4] "Banding filter option"
644*4882a593Smuzhiyun * = 0 (0x00) ...0.... "Main clock is 48 MHz and
645*4882a593Smuzhiyun * the PLL is ON"
646*4882a593Smuzhiyun * COMI[3] "Reserved"
647*4882a593Smuzhiyun * = 0 (0x00) ....0...
648*4882a593Smuzhiyun * COMI[2] "AGC auto manual control selection"
649*4882a593Smuzhiyun * = 0 (0x00) .....0.. "Manual"
650*4882a593Smuzhiyun * COMI[1] "AWB auto manual control selection"
651*4882a593Smuzhiyun * = 0 (0x00) ......0. "Manual"
652*4882a593Smuzhiyun * COMI[0] "Exposure control"
653*4882a593Smuzhiyun * = 0 (0x00) .......0 "Manual"
654*4882a593Smuzhiyun */
655*4882a593Smuzhiyun { 0x13, 0xc0 },
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun /*
658*4882a593Smuzhiyun * 09 COMC "Common Control C"
659*4882a593Smuzhiyun * = 8 (0x08) 00001000
660*4882a593Smuzhiyun * COMC[7:5] "Reserved"
661*4882a593Smuzhiyun * = 0 (0x00) 000.....
662*4882a593Smuzhiyun * COMC[4] "Sleep Mode Enable"
663*4882a593Smuzhiyun * = 0 (0x00) ...0.... "Normal mode"
664*4882a593Smuzhiyun * COMC[3:2] "Sensor sampling reset timing selection"
665*4882a593Smuzhiyun * = 2 (0x02) ....10.. "Longer reset time"
666*4882a593Smuzhiyun * COMC[1:0] "Output drive current select"
667*4882a593Smuzhiyun * = 0 (0x00) ......00 "Weakest"
668*4882a593Smuzhiyun */
669*4882a593Smuzhiyun { 0x09, 0x08 },
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun /*
672*4882a593Smuzhiyun * 0C COMD "Common Control D"
673*4882a593Smuzhiyun * = 8 (0x08) 00001000
674*4882a593Smuzhiyun * COMD[7] "Reserved"
675*4882a593Smuzhiyun * = 0 (0x00) 0.......
676*4882a593Smuzhiyun * COMD[6] "Swap MSB and LSB at the output port"
677*4882a593Smuzhiyun * = 0 (0x00) .0...... "False"
678*4882a593Smuzhiyun * COMD[5:3] "Reserved"
679*4882a593Smuzhiyun * = 1 (0x01) ..001...
680*4882a593Smuzhiyun * COMD[2] "Output Average On Off"
681*4882a593Smuzhiyun * = 0 (0x00) .....0.. "Output Normal"
682*4882a593Smuzhiyun * COMD[1] "Sensor precharge voltage selection"
683*4882a593Smuzhiyun * = 0 (0x00) ......0. "Selects internal
684*4882a593Smuzhiyun * reference precharge
685*4882a593Smuzhiyun * voltage"
686*4882a593Smuzhiyun * COMD[0] "Snapshot option"
687*4882a593Smuzhiyun * = 0 (0x00) .......0 "Enable live video output
688*4882a593Smuzhiyun * after snapshot sequence"
689*4882a593Smuzhiyun */
690*4882a593Smuzhiyun { 0x0c, 0x08 },
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun /*
693*4882a593Smuzhiyun * 0D COME "Common Control E"
694*4882a593Smuzhiyun * = 161 (0xA1) 10100001
695*4882a593Smuzhiyun * COME[7] "Output average option"
696*4882a593Smuzhiyun * = 1 (0x01) 1....... "Output average of 4 pixels"
697*4882a593Smuzhiyun * COME[6] "Anti-blooming control"
698*4882a593Smuzhiyun * = 0 (0x00) .0...... "Off"
699*4882a593Smuzhiyun * COME[5:3] "Reserved"
700*4882a593Smuzhiyun * = 4 (0x04) ..100...
701*4882a593Smuzhiyun * COME[2] "Clock output power down pin status"
702*4882a593Smuzhiyun * = 0 (0x00) .....0.. "Tri-state data output pin
703*4882a593Smuzhiyun * on power down"
704*4882a593Smuzhiyun * COME[1] "Data output pin status selection at power down"
705*4882a593Smuzhiyun * = 0 (0x00) ......0. "Tri-state VSYNC, PCLK,
706*4882a593Smuzhiyun * HREF, and CHSYNC pins on
707*4882a593Smuzhiyun * power down"
708*4882a593Smuzhiyun * COME[0] "Auto zero circuit select"
709*4882a593Smuzhiyun * = 1 (0x01) .......1 "On"
710*4882a593Smuzhiyun */
711*4882a593Smuzhiyun { 0x0d, 0xa1 },
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun /*
714*4882a593Smuzhiyun * 0E COMF "Common Control F"
715*4882a593Smuzhiyun * = 112 (0x70) 01110000
716*4882a593Smuzhiyun * COMF[7] "System clock selection"
717*4882a593Smuzhiyun * = 0 (0x00) 0....... "Use 24 MHz system clock"
718*4882a593Smuzhiyun * COMF[6:4] "Reserved"
719*4882a593Smuzhiyun * = 7 (0x07) .111....
720*4882a593Smuzhiyun * COMF[3] "Manual auto negative offset canceling selection"
721*4882a593Smuzhiyun * = 0 (0x00) ....0... "Auto detect negative
722*4882a593Smuzhiyun * offset and cancel it"
723*4882a593Smuzhiyun * COMF[2:0] "Reserved"
724*4882a593Smuzhiyun * = 0 (0x00) .....000
725*4882a593Smuzhiyun */
726*4882a593Smuzhiyun { 0x0e, 0x70 },
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun /*
729*4882a593Smuzhiyun * 0F COMG "Common Control G"
730*4882a593Smuzhiyun * = 66 (0x42) 01000010
731*4882a593Smuzhiyun * COMG[7] "Optical black output selection"
732*4882a593Smuzhiyun * = 0 (0x00) 0....... "Disable"
733*4882a593Smuzhiyun * COMG[6] "Black level calibrate selection"
734*4882a593Smuzhiyun * = 1 (0x01) .1...... "Use optical black pixels
735*4882a593Smuzhiyun * to calibrate"
736*4882a593Smuzhiyun * COMG[5:4] "Reserved"
737*4882a593Smuzhiyun * = 0 (0x00) ..00....
738*4882a593Smuzhiyun * COMG[3] "Channel offset adjustment"
739*4882a593Smuzhiyun * = 0 (0x00) ....0... "Disable offset adjustment"
740*4882a593Smuzhiyun * COMG[2] "ADC black level calibration option"
741*4882a593Smuzhiyun * = 0 (0x00) .....0.. "Use B/G line and G/R
742*4882a593Smuzhiyun * line to calibrate each
743*4882a593Smuzhiyun * channel's black level"
744*4882a593Smuzhiyun * COMG[1] "Reserved"
745*4882a593Smuzhiyun * = 1 (0x01) ......1.
746*4882a593Smuzhiyun * COMG[0] "ADC black level calibration enable"
747*4882a593Smuzhiyun * = 0 (0x00) .......0 "Disable"
748*4882a593Smuzhiyun */
749*4882a593Smuzhiyun { 0x0f, 0x42 },
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun /*
752*4882a593Smuzhiyun * 14 COMJ "Common Control J"
753*4882a593Smuzhiyun * = 198 (0xC6) 11000110
754*4882a593Smuzhiyun * COMJ[7:6] "AGC gain ceiling"
755*4882a593Smuzhiyun * = 3 (0x03) 11...... "8x"
756*4882a593Smuzhiyun * COMJ[5:4] "Reserved"
757*4882a593Smuzhiyun * = 0 (0x00) ..00....
758*4882a593Smuzhiyun * COMJ[3] "Auto banding filter"
759*4882a593Smuzhiyun * = 0 (0x00) ....0... "Banding filter is always
760*4882a593Smuzhiyun * on off depending on
761*4882a593Smuzhiyun * COMI[5] setting"
762*4882a593Smuzhiyun * COMJ[2] "VSYNC drop option"
763*4882a593Smuzhiyun * = 1 (0x01) .....1.. "SYNC is dropped if frame
764*4882a593Smuzhiyun * data is dropped"
765*4882a593Smuzhiyun * COMJ[1] "Frame data drop"
766*4882a593Smuzhiyun * = 1 (0x01) ......1. "Drop frame data if
767*4882a593Smuzhiyun * exposure is not within
768*4882a593Smuzhiyun * tolerance. In AEC mode,
769*4882a593Smuzhiyun * data is normally dropped
770*4882a593Smuzhiyun * when data is out of
771*4882a593Smuzhiyun * range."
772*4882a593Smuzhiyun * COMJ[0] "Reserved"
773*4882a593Smuzhiyun * = 0 (0x00) .......0
774*4882a593Smuzhiyun */
775*4882a593Smuzhiyun { 0x14, 0xc6 },
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun /*
778*4882a593Smuzhiyun * 15 COMK "Common Control K"
779*4882a593Smuzhiyun * = 2 (0x02) 00000010
780*4882a593Smuzhiyun * COMK[7] "CHSYNC pin output swap"
781*4882a593Smuzhiyun * = 0 (0x00) 0....... "CHSYNC"
782*4882a593Smuzhiyun * COMK[6] "HREF pin output swap"
783*4882a593Smuzhiyun * = 0 (0x00) .0...... "HREF"
784*4882a593Smuzhiyun * COMK[5] "PCLK output selection"
785*4882a593Smuzhiyun * = 0 (0x00) ..0..... "PCLK always output"
786*4882a593Smuzhiyun * COMK[4] "PCLK edge selection"
787*4882a593Smuzhiyun * = 0 (0x00) ...0.... "Data valid on falling edge"
788*4882a593Smuzhiyun * COMK[3] "HREF output polarity"
789*4882a593Smuzhiyun * = 0 (0x00) ....0... "positive"
790*4882a593Smuzhiyun * COMK[2] "Reserved"
791*4882a593Smuzhiyun * = 0 (0x00) .....0..
792*4882a593Smuzhiyun * COMK[1] "VSYNC polarity"
793*4882a593Smuzhiyun * = 1 (0x01) ......1. "negative"
794*4882a593Smuzhiyun * COMK[0] "HSYNC polarity"
795*4882a593Smuzhiyun * = 0 (0x00) .......0 "positive"
796*4882a593Smuzhiyun */
797*4882a593Smuzhiyun { 0x15, 0x02 },
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun /*
800*4882a593Smuzhiyun * 33 CHLF "Current Control"
801*4882a593Smuzhiyun * = 9 (0x09) 00001001
802*4882a593Smuzhiyun * CHLF[7:6] "Sensor current control"
803*4882a593Smuzhiyun * = 0 (0x00) 00......
804*4882a593Smuzhiyun * CHLF[5] "Sensor current range control"
805*4882a593Smuzhiyun * = 0 (0x00) ..0..... "normal range"
806*4882a593Smuzhiyun * CHLF[4] "Sensor current"
807*4882a593Smuzhiyun * = 0 (0x00) ...0.... "normal current"
808*4882a593Smuzhiyun * CHLF[3] "Sensor buffer current control"
809*4882a593Smuzhiyun * = 1 (0x01) ....1... "half current"
810*4882a593Smuzhiyun * CHLF[2] "Column buffer current control"
811*4882a593Smuzhiyun * = 0 (0x00) .....0.. "normal current"
812*4882a593Smuzhiyun * CHLF[1] "Analog DSP current control"
813*4882a593Smuzhiyun * = 0 (0x00) ......0. "normal current"
814*4882a593Smuzhiyun * CHLF[1] "ADC current control"
815*4882a593Smuzhiyun * = 0 (0x00) ......0. "normal current"
816*4882a593Smuzhiyun */
817*4882a593Smuzhiyun { 0x33, 0x09 },
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun /*
820*4882a593Smuzhiyun * 34 VBLM "Blooming Control"
821*4882a593Smuzhiyun * = 80 (0x50) 01010000
822*4882a593Smuzhiyun * VBLM[7] "Hard soft reset switch"
823*4882a593Smuzhiyun * = 0 (0x00) 0....... "Hard reset"
824*4882a593Smuzhiyun * VBLM[6:4] "Blooming voltage selection"
825*4882a593Smuzhiyun * = 5 (0x05) .101....
826*4882a593Smuzhiyun * VBLM[3:0] "Sensor current control"
827*4882a593Smuzhiyun * = 0 (0x00) ....0000
828*4882a593Smuzhiyun */
829*4882a593Smuzhiyun { 0x34, 0x50 },
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun /*
832*4882a593Smuzhiyun * 36 VCHG "Sensor Precharge Voltage Control"
833*4882a593Smuzhiyun * = 0 (0x00) 00000000
834*4882a593Smuzhiyun * VCHG[7] "Reserved"
835*4882a593Smuzhiyun * = 0 (0x00) 0.......
836*4882a593Smuzhiyun * VCHG[6:4] "Sensor precharge voltage control"
837*4882a593Smuzhiyun * = 0 (0x00) .000....
838*4882a593Smuzhiyun * VCHG[3:0] "Sensor array common reference"
839*4882a593Smuzhiyun * = 0 (0x00) ....0000
840*4882a593Smuzhiyun */
841*4882a593Smuzhiyun { 0x36, 0x00 },
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun /*
844*4882a593Smuzhiyun * 37 ADC "ADC Reference Control"
845*4882a593Smuzhiyun * = 4 (0x04) 00000100
846*4882a593Smuzhiyun * ADC[7:4] "Reserved"
847*4882a593Smuzhiyun * = 0 (0x00) 0000....
848*4882a593Smuzhiyun * ADC[3] "ADC input signal range"
849*4882a593Smuzhiyun * = 0 (0x00) ....0... "Input signal 1.0x"
850*4882a593Smuzhiyun * ADC[2:0] "ADC range control"
851*4882a593Smuzhiyun * = 4 (0x04) .....100
852*4882a593Smuzhiyun */
853*4882a593Smuzhiyun { 0x37, 0x04 },
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun /*
856*4882a593Smuzhiyun * 38 ACOM "Analog Common Ground"
857*4882a593Smuzhiyun * = 82 (0x52) 01010010
858*4882a593Smuzhiyun * ACOM[7] "Analog gain control"
859*4882a593Smuzhiyun * = 0 (0x00) 0....... "Gain 1x"
860*4882a593Smuzhiyun * ACOM[6] "Analog black level calibration"
861*4882a593Smuzhiyun * = 1 (0x01) .1...... "On"
862*4882a593Smuzhiyun * ACOM[5:0] "Reserved"
863*4882a593Smuzhiyun * = 18 (0x12) ..010010
864*4882a593Smuzhiyun */
865*4882a593Smuzhiyun { 0x38, 0x52 },
866*4882a593Smuzhiyun
867*4882a593Smuzhiyun /*
868*4882a593Smuzhiyun * 3A FREFA "Internal Reference Adjustment"
869*4882a593Smuzhiyun * = 0 (0x00) 00000000
870*4882a593Smuzhiyun * FREFA[7:0] "Range"
871*4882a593Smuzhiyun * = 0 (0x00) 00000000
872*4882a593Smuzhiyun */
873*4882a593Smuzhiyun { 0x3a, 0x00 },
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun /*
876*4882a593Smuzhiyun * 3C FVOPT "Internal Reference Adjustment"
877*4882a593Smuzhiyun * = 31 (0x1F) 00011111
878*4882a593Smuzhiyun * FVOPT[7:0] "Range"
879*4882a593Smuzhiyun * = 31 (0x1F) 00011111
880*4882a593Smuzhiyun */
881*4882a593Smuzhiyun { 0x3c, 0x1f },
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun /*
884*4882a593Smuzhiyun * 44 Undocumented = 0 (0x00) 00000000
885*4882a593Smuzhiyun * 44[7:0] "It's a secret"
886*4882a593Smuzhiyun * = 0 (0x00) 00000000
887*4882a593Smuzhiyun */
888*4882a593Smuzhiyun { 0x44, 0x00 },
889*4882a593Smuzhiyun
890*4882a593Smuzhiyun /*
891*4882a593Smuzhiyun * 40 Undocumented = 0 (0x00) 00000000
892*4882a593Smuzhiyun * 40[7:0] "It's a secret"
893*4882a593Smuzhiyun * = 0 (0x00) 00000000
894*4882a593Smuzhiyun */
895*4882a593Smuzhiyun { 0x40, 0x00 },
896*4882a593Smuzhiyun
897*4882a593Smuzhiyun /*
898*4882a593Smuzhiyun * 41 Undocumented = 0 (0x00) 00000000
899*4882a593Smuzhiyun * 41[7:0] "It's a secret"
900*4882a593Smuzhiyun * = 0 (0x00) 00000000
901*4882a593Smuzhiyun */
902*4882a593Smuzhiyun { 0x41, 0x00 },
903*4882a593Smuzhiyun
904*4882a593Smuzhiyun /*
905*4882a593Smuzhiyun * 42 Undocumented = 0 (0x00) 00000000
906*4882a593Smuzhiyun * 42[7:0] "It's a secret"
907*4882a593Smuzhiyun * = 0 (0x00) 00000000
908*4882a593Smuzhiyun */
909*4882a593Smuzhiyun { 0x42, 0x00 },
910*4882a593Smuzhiyun
911*4882a593Smuzhiyun /*
912*4882a593Smuzhiyun * 43 Undocumented = 0 (0x00) 00000000
913*4882a593Smuzhiyun * 43[7:0] "It's a secret"
914*4882a593Smuzhiyun * = 0 (0x00) 00000000
915*4882a593Smuzhiyun */
916*4882a593Smuzhiyun { 0x43, 0x00 },
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun /*
919*4882a593Smuzhiyun * 45 Undocumented = 128 (0x80) 10000000
920*4882a593Smuzhiyun * 45[7:0] "It's a secret"
921*4882a593Smuzhiyun * = 128 (0x80) 10000000
922*4882a593Smuzhiyun */
923*4882a593Smuzhiyun { 0x45, 0x80 },
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun /*
926*4882a593Smuzhiyun * 48 Undocumented = 192 (0xC0) 11000000
927*4882a593Smuzhiyun * 48[7:0] "It's a secret"
928*4882a593Smuzhiyun * = 192 (0xC0) 11000000
929*4882a593Smuzhiyun */
930*4882a593Smuzhiyun { 0x48, 0xc0 },
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun /*
933*4882a593Smuzhiyun * 49 Undocumented = 25 (0x19) 00011001
934*4882a593Smuzhiyun * 49[7:0] "It's a secret"
935*4882a593Smuzhiyun * = 25 (0x19) 00011001
936*4882a593Smuzhiyun */
937*4882a593Smuzhiyun { 0x49, 0x19 },
938*4882a593Smuzhiyun
939*4882a593Smuzhiyun /*
940*4882a593Smuzhiyun * 4B Undocumented = 128 (0x80) 10000000
941*4882a593Smuzhiyun * 4B[7:0] "It's a secret"
942*4882a593Smuzhiyun * = 128 (0x80) 10000000
943*4882a593Smuzhiyun */
944*4882a593Smuzhiyun { 0x4b, 0x80 },
945*4882a593Smuzhiyun
946*4882a593Smuzhiyun /*
947*4882a593Smuzhiyun * 4D Undocumented = 196 (0xC4) 11000100
948*4882a593Smuzhiyun * 4D[7:0] "It's a secret"
949*4882a593Smuzhiyun * = 196 (0xC4) 11000100
950*4882a593Smuzhiyun */
951*4882a593Smuzhiyun { 0x4d, 0xc4 },
952*4882a593Smuzhiyun
953*4882a593Smuzhiyun /*
954*4882a593Smuzhiyun * 35 VREF "Reference Voltage Control"
955*4882a593Smuzhiyun * = 76 (0x4c) 01001100
956*4882a593Smuzhiyun * VREF[7:5] "Column high reference control"
957*4882a593Smuzhiyun * = 2 (0x02) 010..... "higher voltage"
958*4882a593Smuzhiyun * VREF[4:2] "Column low reference control"
959*4882a593Smuzhiyun * = 3 (0x03) ...011.. "Highest voltage"
960*4882a593Smuzhiyun * VREF[1:0] "Reserved"
961*4882a593Smuzhiyun * = 0 (0x00) ......00
962*4882a593Smuzhiyun */
963*4882a593Smuzhiyun { 0x35, 0x4c },
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun /*
966*4882a593Smuzhiyun * 3D Undocumented = 0 (0x00) 00000000
967*4882a593Smuzhiyun * 3D[7:0] "It's a secret"
968*4882a593Smuzhiyun * = 0 (0x00) 00000000
969*4882a593Smuzhiyun */
970*4882a593Smuzhiyun { 0x3d, 0x00 },
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun /*
973*4882a593Smuzhiyun * 3E Undocumented = 0 (0x00) 00000000
974*4882a593Smuzhiyun * 3E[7:0] "It's a secret"
975*4882a593Smuzhiyun * = 0 (0x00) 00000000
976*4882a593Smuzhiyun */
977*4882a593Smuzhiyun { 0x3e, 0x00 },
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun /*
980*4882a593Smuzhiyun * 3B FREFB "Internal Reference Adjustment"
981*4882a593Smuzhiyun * = 24 (0x18) 00011000
982*4882a593Smuzhiyun * FREFB[7:0] "Range"
983*4882a593Smuzhiyun * = 24 (0x18) 00011000
984*4882a593Smuzhiyun */
985*4882a593Smuzhiyun { 0x3b, 0x18 },
986*4882a593Smuzhiyun
987*4882a593Smuzhiyun /*
988*4882a593Smuzhiyun * 33 CHLF "Current Control"
989*4882a593Smuzhiyun * = 25 (0x19) 00011001
990*4882a593Smuzhiyun * CHLF[7:6] "Sensor current control"
991*4882a593Smuzhiyun * = 0 (0x00) 00......
992*4882a593Smuzhiyun * CHLF[5] "Sensor current range control"
993*4882a593Smuzhiyun * = 0 (0x00) ..0..... "normal range"
994*4882a593Smuzhiyun * CHLF[4] "Sensor current"
995*4882a593Smuzhiyun * = 1 (0x01) ...1.... "double current"
996*4882a593Smuzhiyun * CHLF[3] "Sensor buffer current control"
997*4882a593Smuzhiyun * = 1 (0x01) ....1... "half current"
998*4882a593Smuzhiyun * CHLF[2] "Column buffer current control"
999*4882a593Smuzhiyun * = 0 (0x00) .....0.. "normal current"
1000*4882a593Smuzhiyun * CHLF[1] "Analog DSP current control"
1001*4882a593Smuzhiyun * = 0 (0x00) ......0. "normal current"
1002*4882a593Smuzhiyun * CHLF[1] "ADC current control"
1003*4882a593Smuzhiyun * = 0 (0x00) ......0. "normal current"
1004*4882a593Smuzhiyun */
1005*4882a593Smuzhiyun { 0x33, 0x19 },
1006*4882a593Smuzhiyun
1007*4882a593Smuzhiyun /*
1008*4882a593Smuzhiyun * 34 VBLM "Blooming Control"
1009*4882a593Smuzhiyun * = 90 (0x5A) 01011010
1010*4882a593Smuzhiyun * VBLM[7] "Hard soft reset switch"
1011*4882a593Smuzhiyun * = 0 (0x00) 0....... "Hard reset"
1012*4882a593Smuzhiyun * VBLM[6:4] "Blooming voltage selection"
1013*4882a593Smuzhiyun * = 5 (0x05) .101....
1014*4882a593Smuzhiyun * VBLM[3:0] "Sensor current control"
1015*4882a593Smuzhiyun * = 10 (0x0A) ....1010
1016*4882a593Smuzhiyun */
1017*4882a593Smuzhiyun { 0x34, 0x5a },
1018*4882a593Smuzhiyun
1019*4882a593Smuzhiyun /*
1020*4882a593Smuzhiyun * 3B FREFB "Internal Reference Adjustment"
1021*4882a593Smuzhiyun * = 0 (0x00) 00000000
1022*4882a593Smuzhiyun * FREFB[7:0] "Range"
1023*4882a593Smuzhiyun * = 0 (0x00) 00000000
1024*4882a593Smuzhiyun */
1025*4882a593Smuzhiyun { 0x3b, 0x00 },
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun /*
1028*4882a593Smuzhiyun * 33 CHLF "Current Control"
1029*4882a593Smuzhiyun * = 9 (0x09) 00001001
1030*4882a593Smuzhiyun * CHLF[7:6] "Sensor current control"
1031*4882a593Smuzhiyun * = 0 (0x00) 00......
1032*4882a593Smuzhiyun * CHLF[5] "Sensor current range control"
1033*4882a593Smuzhiyun * = 0 (0x00) ..0..... "normal range"
1034*4882a593Smuzhiyun * CHLF[4] "Sensor current"
1035*4882a593Smuzhiyun * = 0 (0x00) ...0.... "normal current"
1036*4882a593Smuzhiyun * CHLF[3] "Sensor buffer current control"
1037*4882a593Smuzhiyun * = 1 (0x01) ....1... "half current"
1038*4882a593Smuzhiyun * CHLF[2] "Column buffer current control"
1039*4882a593Smuzhiyun * = 0 (0x00) .....0.. "normal current"
1040*4882a593Smuzhiyun * CHLF[1] "Analog DSP current control"
1041*4882a593Smuzhiyun * = 0 (0x00) ......0. "normal current"
1042*4882a593Smuzhiyun * CHLF[1] "ADC current control"
1043*4882a593Smuzhiyun * = 0 (0x00) ......0. "normal current"
1044*4882a593Smuzhiyun */
1045*4882a593Smuzhiyun { 0x33, 0x09 },
1046*4882a593Smuzhiyun
1047*4882a593Smuzhiyun /*
1048*4882a593Smuzhiyun * 34 VBLM "Blooming Control"
1049*4882a593Smuzhiyun * = 80 (0x50) 01010000
1050*4882a593Smuzhiyun * VBLM[7] "Hard soft reset switch"
1051*4882a593Smuzhiyun * = 0 (0x00) 0....... "Hard reset"
1052*4882a593Smuzhiyun * VBLM[6:4] "Blooming voltage selection"
1053*4882a593Smuzhiyun * = 5 (0x05) .101....
1054*4882a593Smuzhiyun * VBLM[3:0] "Sensor current control"
1055*4882a593Smuzhiyun * = 0 (0x00) ....0000
1056*4882a593Smuzhiyun */
1057*4882a593Smuzhiyun { 0x34, 0x50 },
1058*4882a593Smuzhiyun
1059*4882a593Smuzhiyun /*
1060*4882a593Smuzhiyun * 12 COMH "Common Control H"
1061*4882a593Smuzhiyun * = 64 (0x40) 01000000
1062*4882a593Smuzhiyun * COMH[7] "SRST"
1063*4882a593Smuzhiyun * = 0 (0x00) 0....... "No-op"
1064*4882a593Smuzhiyun * COMH[6:4] "Resolution selection"
1065*4882a593Smuzhiyun * = 4 (0x04) .100.... "XGA"
1066*4882a593Smuzhiyun * COMH[3] "Master slave selection"
1067*4882a593Smuzhiyun * = 0 (0x00) ....0... "Master mode"
1068*4882a593Smuzhiyun * COMH[2] "Internal B/R channel option"
1069*4882a593Smuzhiyun * = 0 (0x00) .....0.. "B/R use same channel"
1070*4882a593Smuzhiyun * COMH[1] "Color bar test pattern"
1071*4882a593Smuzhiyun * = 0 (0x00) ......0. "Off"
1072*4882a593Smuzhiyun * COMH[0] "Reserved"
1073*4882a593Smuzhiyun * = 0 (0x00) .......0
1074*4882a593Smuzhiyun */
1075*4882a593Smuzhiyun { 0x12, 0x40 },
1076*4882a593Smuzhiyun
1077*4882a593Smuzhiyun /*
1078*4882a593Smuzhiyun * 17 HREFST "Horizontal window start"
1079*4882a593Smuzhiyun * = 31 (0x1F) 00011111
1080*4882a593Smuzhiyun * HREFST[7:0] "Horizontal window start, 8 MSBs"
1081*4882a593Smuzhiyun * = 31 (0x1F) 00011111
1082*4882a593Smuzhiyun */
1083*4882a593Smuzhiyun { 0x17, 0x1f },
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun /*
1086*4882a593Smuzhiyun * 18 HREFEND "Horizontal window end"
1087*4882a593Smuzhiyun * = 95 (0x5F) 01011111
1088*4882a593Smuzhiyun * HREFEND[7:0] "Horizontal Window End, 8 MSBs"
1089*4882a593Smuzhiyun * = 95 (0x5F) 01011111
1090*4882a593Smuzhiyun */
1091*4882a593Smuzhiyun { 0x18, 0x5f },
1092*4882a593Smuzhiyun
1093*4882a593Smuzhiyun /*
1094*4882a593Smuzhiyun * 19 VSTRT "Vertical window start"
1095*4882a593Smuzhiyun * = 0 (0x00) 00000000
1096*4882a593Smuzhiyun * VSTRT[7:0] "Vertical Window Start, 8 MSBs"
1097*4882a593Smuzhiyun * = 0 (0x00) 00000000
1098*4882a593Smuzhiyun */
1099*4882a593Smuzhiyun { 0x19, 0x00 },
1100*4882a593Smuzhiyun
1101*4882a593Smuzhiyun /*
1102*4882a593Smuzhiyun * 1A VEND "Vertical window end"
1103*4882a593Smuzhiyun * = 96 (0x60) 01100000
1104*4882a593Smuzhiyun * VEND[7:0] "Vertical Window End, 8 MSBs"
1105*4882a593Smuzhiyun * = 96 (0x60) 01100000
1106*4882a593Smuzhiyun */
1107*4882a593Smuzhiyun { 0x1a, 0x60 },
1108*4882a593Smuzhiyun
1109*4882a593Smuzhiyun /*
1110*4882a593Smuzhiyun * 32 COMM "Common Control M"
1111*4882a593Smuzhiyun * = 18 (0x12) 00010010
1112*4882a593Smuzhiyun * COMM[7:6] "Pixel clock divide option"
1113*4882a593Smuzhiyun * = 0 (0x00) 00...... "/1"
1114*4882a593Smuzhiyun * COMM[5:3] "Horizontal window end position, 3 LSBs"
1115*4882a593Smuzhiyun * = 2 (0x02) ..010...
1116*4882a593Smuzhiyun * COMM[2:0] "Horizontal window start position, 3 LSBs"
1117*4882a593Smuzhiyun * = 2 (0x02) .....010
1118*4882a593Smuzhiyun */
1119*4882a593Smuzhiyun { 0x32, 0x12 },
1120*4882a593Smuzhiyun
1121*4882a593Smuzhiyun /*
1122*4882a593Smuzhiyun * 03 COMA "Common Control A"
1123*4882a593Smuzhiyun * = 74 (0x4A) 01001010
1124*4882a593Smuzhiyun * COMA[7:4] "AWB Update Threshold"
1125*4882a593Smuzhiyun * = 4 (0x04) 0100....
1126*4882a593Smuzhiyun * COMA[3:2] "Vertical window end line control 2 LSBs"
1127*4882a593Smuzhiyun * = 2 (0x02) ....10..
1128*4882a593Smuzhiyun * COMA[1:0] "Vertical window start line control 2 LSBs"
1129*4882a593Smuzhiyun * = 2 (0x02) ......10
1130*4882a593Smuzhiyun */
1131*4882a593Smuzhiyun { 0x03, 0x4a },
1132*4882a593Smuzhiyun
1133*4882a593Smuzhiyun /*
1134*4882a593Smuzhiyun * 11 CLKRC "Clock Rate Control"
1135*4882a593Smuzhiyun * = 128 (0x80) 10000000
1136*4882a593Smuzhiyun * CLKRC[7] "Internal frequency doublers on off seclection"
1137*4882a593Smuzhiyun * = 1 (0x01) 1....... "On"
1138*4882a593Smuzhiyun * CLKRC[6] "Digital video master slave selection"
1139*4882a593Smuzhiyun * = 0 (0x00) .0...... "Master mode, sensor
1140*4882a593Smuzhiyun * provides PCLK"
1141*4882a593Smuzhiyun * CLKRC[5:0] "Clock divider { CLK = PCLK/(1+CLKRC[5:0]) }"
1142*4882a593Smuzhiyun * = 0 (0x00) ..000000
1143*4882a593Smuzhiyun */
1144*4882a593Smuzhiyun { 0x11, 0x80 },
1145*4882a593Smuzhiyun
1146*4882a593Smuzhiyun /*
1147*4882a593Smuzhiyun * 12 COMH "Common Control H"
1148*4882a593Smuzhiyun * = 0 (0x00) 00000000
1149*4882a593Smuzhiyun * COMH[7] "SRST"
1150*4882a593Smuzhiyun * = 0 (0x00) 0....... "No-op"
1151*4882a593Smuzhiyun * COMH[6:4] "Resolution selection"
1152*4882a593Smuzhiyun * = 0 (0x00) .000.... "QXGA"
1153*4882a593Smuzhiyun * COMH[3] "Master slave selection"
1154*4882a593Smuzhiyun * = 0 (0x00) ....0... "Master mode"
1155*4882a593Smuzhiyun * COMH[2] "Internal B/R channel option"
1156*4882a593Smuzhiyun * = 0 (0x00) .....0.. "B/R use same channel"
1157*4882a593Smuzhiyun * COMH[1] "Color bar test pattern"
1158*4882a593Smuzhiyun * = 0 (0x00) ......0. "Off"
1159*4882a593Smuzhiyun * COMH[0] "Reserved"
1160*4882a593Smuzhiyun * = 0 (0x00) .......0
1161*4882a593Smuzhiyun */
1162*4882a593Smuzhiyun { 0x12, 0x00 },
1163*4882a593Smuzhiyun
1164*4882a593Smuzhiyun /*
1165*4882a593Smuzhiyun * 12 COMH "Common Control H"
1166*4882a593Smuzhiyun * = 64 (0x40) 01000000
1167*4882a593Smuzhiyun * COMH[7] "SRST"
1168*4882a593Smuzhiyun * = 0 (0x00) 0....... "No-op"
1169*4882a593Smuzhiyun * COMH[6:4] "Resolution selection"
1170*4882a593Smuzhiyun * = 4 (0x04) .100.... "XGA"
1171*4882a593Smuzhiyun * COMH[3] "Master slave selection"
1172*4882a593Smuzhiyun * = 0 (0x00) ....0... "Master mode"
1173*4882a593Smuzhiyun * COMH[2] "Internal B/R channel option"
1174*4882a593Smuzhiyun * = 0 (0x00) .....0.. "B/R use same channel"
1175*4882a593Smuzhiyun * COMH[1] "Color bar test pattern"
1176*4882a593Smuzhiyun * = 0 (0x00) ......0. "Off"
1177*4882a593Smuzhiyun * COMH[0] "Reserved"
1178*4882a593Smuzhiyun * = 0 (0x00) .......0
1179*4882a593Smuzhiyun */
1180*4882a593Smuzhiyun { 0x12, 0x40 },
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun /*
1183*4882a593Smuzhiyun * 17 HREFST "Horizontal window start"
1184*4882a593Smuzhiyun * = 31 (0x1F) 00011111
1185*4882a593Smuzhiyun * HREFST[7:0] "Horizontal window start, 8 MSBs"
1186*4882a593Smuzhiyun * = 31 (0x1F) 00011111
1187*4882a593Smuzhiyun */
1188*4882a593Smuzhiyun { 0x17, 0x1f },
1189*4882a593Smuzhiyun
1190*4882a593Smuzhiyun /*
1191*4882a593Smuzhiyun * 18 HREFEND "Horizontal window end"
1192*4882a593Smuzhiyun * = 95 (0x5F) 01011111
1193*4882a593Smuzhiyun * HREFEND[7:0] "Horizontal Window End, 8 MSBs"
1194*4882a593Smuzhiyun * = 95 (0x5F) 01011111
1195*4882a593Smuzhiyun */
1196*4882a593Smuzhiyun { 0x18, 0x5f },
1197*4882a593Smuzhiyun
1198*4882a593Smuzhiyun /*
1199*4882a593Smuzhiyun * 19 VSTRT "Vertical window start"
1200*4882a593Smuzhiyun * = 0 (0x00) 00000000
1201*4882a593Smuzhiyun * VSTRT[7:0] "Vertical Window Start, 8 MSBs"
1202*4882a593Smuzhiyun * = 0 (0x00) 00000000
1203*4882a593Smuzhiyun */
1204*4882a593Smuzhiyun { 0x19, 0x00 },
1205*4882a593Smuzhiyun
1206*4882a593Smuzhiyun /*
1207*4882a593Smuzhiyun * 1A VEND "Vertical window end"
1208*4882a593Smuzhiyun * = 96 (0x60) 01100000
1209*4882a593Smuzhiyun * VEND[7:0] "Vertical Window End, 8 MSBs"
1210*4882a593Smuzhiyun * = 96 (0x60) 01100000
1211*4882a593Smuzhiyun */
1212*4882a593Smuzhiyun { 0x1a, 0x60 },
1213*4882a593Smuzhiyun
1214*4882a593Smuzhiyun /*
1215*4882a593Smuzhiyun * 32 COMM "Common Control M"
1216*4882a593Smuzhiyun * = 18 (0x12) 00010010
1217*4882a593Smuzhiyun * COMM[7:6] "Pixel clock divide option"
1218*4882a593Smuzhiyun * = 0 (0x00) 00...... "/1"
1219*4882a593Smuzhiyun * COMM[5:3] "Horizontal window end position, 3 LSBs"
1220*4882a593Smuzhiyun * = 2 (0x02) ..010...
1221*4882a593Smuzhiyun * COMM[2:0] "Horizontal window start position, 3 LSBs"
1222*4882a593Smuzhiyun * = 2 (0x02) .....010
1223*4882a593Smuzhiyun */
1224*4882a593Smuzhiyun { 0x32, 0x12 },
1225*4882a593Smuzhiyun
1226*4882a593Smuzhiyun /*
1227*4882a593Smuzhiyun * 03 COMA "Common Control A"
1228*4882a593Smuzhiyun * = 74 (0x4A) 01001010
1229*4882a593Smuzhiyun * COMA[7:4] "AWB Update Threshold"
1230*4882a593Smuzhiyun * = 4 (0x04) 0100....
1231*4882a593Smuzhiyun * COMA[3:2] "Vertical window end line control 2 LSBs"
1232*4882a593Smuzhiyun * = 2 (0x02) ....10..
1233*4882a593Smuzhiyun * COMA[1:0] "Vertical window start line control 2 LSBs"
1234*4882a593Smuzhiyun * = 2 (0x02) ......10
1235*4882a593Smuzhiyun */
1236*4882a593Smuzhiyun { 0x03, 0x4a },
1237*4882a593Smuzhiyun
1238*4882a593Smuzhiyun /*
1239*4882a593Smuzhiyun * 02 RED "Red Gain Control"
1240*4882a593Smuzhiyun * = 175 (0xAF) 10101111
1241*4882a593Smuzhiyun * RED[7] "Action"
1242*4882a593Smuzhiyun * = 1 (0x01) 1....... "gain = 1/(1+bitrev([6:0]))"
1243*4882a593Smuzhiyun * RED[6:0] "Value"
1244*4882a593Smuzhiyun * = 47 (0x2F) .0101111
1245*4882a593Smuzhiyun */
1246*4882a593Smuzhiyun { 0x02, 0xaf },
1247*4882a593Smuzhiyun
1248*4882a593Smuzhiyun /*
1249*4882a593Smuzhiyun * 2D ADDVSL "VSYNC Pulse Width"
1250*4882a593Smuzhiyun * = 210 (0xD2) 11010010
1251*4882a593Smuzhiyun * ADDVSL[7:0] "VSYNC pulse width, LSB"
1252*4882a593Smuzhiyun * = 210 (0xD2) 11010010
1253*4882a593Smuzhiyun */
1254*4882a593Smuzhiyun { 0x2d, 0xd2 },
1255*4882a593Smuzhiyun
1256*4882a593Smuzhiyun /*
1257*4882a593Smuzhiyun * 00 GAIN = 24 (0x18) 00011000
1258*4882a593Smuzhiyun * GAIN[7:6] "Reserved"
1259*4882a593Smuzhiyun * = 0 (0x00) 00......
1260*4882a593Smuzhiyun * GAIN[5] "Double"
1261*4882a593Smuzhiyun * = 0 (0x00) ..0..... "False"
1262*4882a593Smuzhiyun * GAIN[4] "Double"
1263*4882a593Smuzhiyun * = 1 (0x01) ...1.... "True"
1264*4882a593Smuzhiyun * GAIN[3:0] "Range"
1265*4882a593Smuzhiyun * = 8 (0x08) ....1000
1266*4882a593Smuzhiyun */
1267*4882a593Smuzhiyun { 0x00, 0x18 },
1268*4882a593Smuzhiyun
1269*4882a593Smuzhiyun /*
1270*4882a593Smuzhiyun * 01 BLUE "Blue Gain Control"
1271*4882a593Smuzhiyun * = 240 (0xF0) 11110000
1272*4882a593Smuzhiyun * BLUE[7] "Action"
1273*4882a593Smuzhiyun * = 1 (0x01) 1....... "gain = 1/(1+bitrev([6:0]))"
1274*4882a593Smuzhiyun * BLUE[6:0] "Value"
1275*4882a593Smuzhiyun * = 112 (0x70) .1110000
1276*4882a593Smuzhiyun */
1277*4882a593Smuzhiyun { 0x01, 0xf0 },
1278*4882a593Smuzhiyun
1279*4882a593Smuzhiyun /*
1280*4882a593Smuzhiyun * 10 AEC "Automatic Exposure Control"
1281*4882a593Smuzhiyun * = 10 (0x0A) 00001010
1282*4882a593Smuzhiyun * AEC[7:0] "Automatic Exposure Control, 8 MSBs"
1283*4882a593Smuzhiyun * = 10 (0x0A) 00001010
1284*4882a593Smuzhiyun */
1285*4882a593Smuzhiyun { 0x10, 0x0a },
1286*4882a593Smuzhiyun
1287*4882a593Smuzhiyun { 0xe1, 0x67 },
1288*4882a593Smuzhiyun { 0xe3, 0x03 },
1289*4882a593Smuzhiyun { 0xe4, 0x26 },
1290*4882a593Smuzhiyun { 0xe5, 0x3e },
1291*4882a593Smuzhiyun { 0xf8, 0x01 },
1292*4882a593Smuzhiyun { 0xff, 0x01 },
1293*4882a593Smuzhiyun };
1294*4882a593Smuzhiyun
1295*4882a593Smuzhiyun static const struct ov_i2c_regvals norm_6x20[] = {
1296*4882a593Smuzhiyun { 0x12, 0x80 }, /* reset */
1297*4882a593Smuzhiyun { 0x11, 0x01 },
1298*4882a593Smuzhiyun { 0x03, 0x60 },
1299*4882a593Smuzhiyun { 0x05, 0x7f }, /* For when autoadjust is off */
1300*4882a593Smuzhiyun { 0x07, 0xa8 },
1301*4882a593Smuzhiyun /* The ratio of 0x0c and 0x0d controls the white point */
1302*4882a593Smuzhiyun { 0x0c, 0x24 },
1303*4882a593Smuzhiyun { 0x0d, 0x24 },
1304*4882a593Smuzhiyun { 0x0f, 0x15 }, /* COMS */
1305*4882a593Smuzhiyun { 0x10, 0x75 }, /* AEC Exposure time */
1306*4882a593Smuzhiyun { 0x12, 0x24 }, /* Enable AGC */
1307*4882a593Smuzhiyun { 0x14, 0x04 },
1308*4882a593Smuzhiyun /* 0x16: 0x06 helps frame stability with moving objects */
1309*4882a593Smuzhiyun { 0x16, 0x06 },
1310*4882a593Smuzhiyun /* { 0x20, 0x30 }, * Aperture correction enable */
1311*4882a593Smuzhiyun { 0x26, 0xb2 }, /* BLC enable */
1312*4882a593Smuzhiyun /* 0x28: 0x05 Selects RGB format if RGB on */
1313*4882a593Smuzhiyun { 0x28, 0x05 },
1314*4882a593Smuzhiyun { 0x2a, 0x04 }, /* Disable framerate adjust */
1315*4882a593Smuzhiyun /* { 0x2b, 0xac }, * Framerate; Set 2a[7] first */
1316*4882a593Smuzhiyun { 0x2d, 0x85 },
1317*4882a593Smuzhiyun { 0x33, 0xa0 }, /* Color Processing Parameter */
1318*4882a593Smuzhiyun { 0x34, 0xd2 }, /* Max A/D range */
1319*4882a593Smuzhiyun { 0x38, 0x8b },
1320*4882a593Smuzhiyun { 0x39, 0x40 },
1321*4882a593Smuzhiyun
1322*4882a593Smuzhiyun { 0x3c, 0x39 }, /* Enable AEC mode changing */
1323*4882a593Smuzhiyun { 0x3c, 0x3c }, /* Change AEC mode */
1324*4882a593Smuzhiyun { 0x3c, 0x24 }, /* Disable AEC mode changing */
1325*4882a593Smuzhiyun
1326*4882a593Smuzhiyun { 0x3d, 0x80 },
1327*4882a593Smuzhiyun /* These next two registers (0x4a, 0x4b) are undocumented.
1328*4882a593Smuzhiyun * They control the color balance */
1329*4882a593Smuzhiyun { 0x4a, 0x80 },
1330*4882a593Smuzhiyun { 0x4b, 0x80 },
1331*4882a593Smuzhiyun { 0x4d, 0xd2 }, /* This reduces noise a bit */
1332*4882a593Smuzhiyun { 0x4e, 0xc1 },
1333*4882a593Smuzhiyun { 0x4f, 0x04 },
1334*4882a593Smuzhiyun /* Do 50-53 have any effect? */
1335*4882a593Smuzhiyun /* Toggle 0x12[2] off and on here? */
1336*4882a593Smuzhiyun };
1337*4882a593Smuzhiyun
1338*4882a593Smuzhiyun static const struct ov_i2c_regvals norm_6x30[] = {
1339*4882a593Smuzhiyun { 0x12, 0x80 }, /* Reset */
1340*4882a593Smuzhiyun { 0x00, 0x1f }, /* Gain */
1341*4882a593Smuzhiyun { 0x01, 0x99 }, /* Blue gain */
1342*4882a593Smuzhiyun { 0x02, 0x7c }, /* Red gain */
1343*4882a593Smuzhiyun { 0x03, 0xc0 }, /* Saturation */
1344*4882a593Smuzhiyun { 0x05, 0x0a }, /* Contrast */
1345*4882a593Smuzhiyun { 0x06, 0x95 }, /* Brightness */
1346*4882a593Smuzhiyun { 0x07, 0x2d }, /* Sharpness */
1347*4882a593Smuzhiyun { 0x0c, 0x20 },
1348*4882a593Smuzhiyun { 0x0d, 0x20 },
1349*4882a593Smuzhiyun { 0x0e, 0xa0 }, /* Was 0x20, bit7 enables a 2x gain which we need */
1350*4882a593Smuzhiyun { 0x0f, 0x05 },
1351*4882a593Smuzhiyun { 0x10, 0x9a },
1352*4882a593Smuzhiyun { 0x11, 0x00 }, /* Pixel clock = fastest */
1353*4882a593Smuzhiyun { 0x12, 0x24 }, /* Enable AGC and AWB */
1354*4882a593Smuzhiyun { 0x13, 0x21 },
1355*4882a593Smuzhiyun { 0x14, 0x80 },
1356*4882a593Smuzhiyun { 0x15, 0x01 },
1357*4882a593Smuzhiyun { 0x16, 0x03 },
1358*4882a593Smuzhiyun { 0x17, 0x38 },
1359*4882a593Smuzhiyun { 0x18, 0xea },
1360*4882a593Smuzhiyun { 0x19, 0x04 },
1361*4882a593Smuzhiyun { 0x1a, 0x93 },
1362*4882a593Smuzhiyun { 0x1b, 0x00 },
1363*4882a593Smuzhiyun { 0x1e, 0xc4 },
1364*4882a593Smuzhiyun { 0x1f, 0x04 },
1365*4882a593Smuzhiyun { 0x20, 0x20 },
1366*4882a593Smuzhiyun { 0x21, 0x10 },
1367*4882a593Smuzhiyun { 0x22, 0x88 },
1368*4882a593Smuzhiyun { 0x23, 0xc0 }, /* Crystal circuit power level */
1369*4882a593Smuzhiyun { 0x25, 0x9a }, /* Increase AEC black ratio */
1370*4882a593Smuzhiyun { 0x26, 0xb2 }, /* BLC enable */
1371*4882a593Smuzhiyun { 0x27, 0xa2 },
1372*4882a593Smuzhiyun { 0x28, 0x00 },
1373*4882a593Smuzhiyun { 0x29, 0x00 },
1374*4882a593Smuzhiyun { 0x2a, 0x84 }, /* 60 Hz power */
1375*4882a593Smuzhiyun { 0x2b, 0xa8 }, /* 60 Hz power */
1376*4882a593Smuzhiyun { 0x2c, 0xa0 },
1377*4882a593Smuzhiyun { 0x2d, 0x95 }, /* Enable auto-brightness */
1378*4882a593Smuzhiyun { 0x2e, 0x88 },
1379*4882a593Smuzhiyun { 0x33, 0x26 },
1380*4882a593Smuzhiyun { 0x34, 0x03 },
1381*4882a593Smuzhiyun { 0x36, 0x8f },
1382*4882a593Smuzhiyun { 0x37, 0x80 },
1383*4882a593Smuzhiyun { 0x38, 0x83 },
1384*4882a593Smuzhiyun { 0x39, 0x80 },
1385*4882a593Smuzhiyun { 0x3a, 0x0f },
1386*4882a593Smuzhiyun { 0x3b, 0x3c },
1387*4882a593Smuzhiyun { 0x3c, 0x1a },
1388*4882a593Smuzhiyun { 0x3d, 0x80 },
1389*4882a593Smuzhiyun { 0x3e, 0x80 },
1390*4882a593Smuzhiyun { 0x3f, 0x0e },
1391*4882a593Smuzhiyun { 0x40, 0x00 }, /* White bal */
1392*4882a593Smuzhiyun { 0x41, 0x00 }, /* White bal */
1393*4882a593Smuzhiyun { 0x42, 0x80 },
1394*4882a593Smuzhiyun { 0x43, 0x3f }, /* White bal */
1395*4882a593Smuzhiyun { 0x44, 0x80 },
1396*4882a593Smuzhiyun { 0x45, 0x20 },
1397*4882a593Smuzhiyun { 0x46, 0x20 },
1398*4882a593Smuzhiyun { 0x47, 0x80 },
1399*4882a593Smuzhiyun { 0x48, 0x7f },
1400*4882a593Smuzhiyun { 0x49, 0x00 },
1401*4882a593Smuzhiyun { 0x4a, 0x00 },
1402*4882a593Smuzhiyun { 0x4b, 0x80 },
1403*4882a593Smuzhiyun { 0x4c, 0xd0 },
1404*4882a593Smuzhiyun { 0x4d, 0x10 }, /* U = 0.563u, V = 0.714v */
1405*4882a593Smuzhiyun { 0x4e, 0x40 },
1406*4882a593Smuzhiyun { 0x4f, 0x07 }, /* UV avg., col. killer: max */
1407*4882a593Smuzhiyun { 0x50, 0xff },
1408*4882a593Smuzhiyun { 0x54, 0x23 }, /* Max AGC gain: 18dB */
1409*4882a593Smuzhiyun { 0x55, 0xff },
1410*4882a593Smuzhiyun { 0x56, 0x12 },
1411*4882a593Smuzhiyun { 0x57, 0x81 },
1412*4882a593Smuzhiyun { 0x58, 0x75 },
1413*4882a593Smuzhiyun { 0x59, 0x01 }, /* AGC dark current comp.: +1 */
1414*4882a593Smuzhiyun { 0x5a, 0x2c },
1415*4882a593Smuzhiyun { 0x5b, 0x0f }, /* AWB chrominance levels */
1416*4882a593Smuzhiyun { 0x5c, 0x10 },
1417*4882a593Smuzhiyun { 0x3d, 0x80 },
1418*4882a593Smuzhiyun { 0x27, 0xa6 },
1419*4882a593Smuzhiyun { 0x12, 0x20 }, /* Toggle AWB */
1420*4882a593Smuzhiyun { 0x12, 0x24 },
1421*4882a593Smuzhiyun };
1422*4882a593Smuzhiyun
1423*4882a593Smuzhiyun /* Lawrence Glaister <lg@jfm.bc.ca> reports:
1424*4882a593Smuzhiyun *
1425*4882a593Smuzhiyun * Register 0x0f in the 7610 has the following effects:
1426*4882a593Smuzhiyun *
1427*4882a593Smuzhiyun * 0x85 (AEC method 1): Best overall, good contrast range
1428*4882a593Smuzhiyun * 0x45 (AEC method 2): Very overexposed
1429*4882a593Smuzhiyun * 0xa5 (spec sheet default): Ok, but the black level is
1430*4882a593Smuzhiyun * shifted resulting in loss of contrast
1431*4882a593Smuzhiyun * 0x05 (old driver setting): very overexposed, too much
1432*4882a593Smuzhiyun * contrast
1433*4882a593Smuzhiyun */
1434*4882a593Smuzhiyun static const struct ov_i2c_regvals norm_7610[] = {
1435*4882a593Smuzhiyun { 0x10, 0xff },
1436*4882a593Smuzhiyun { 0x16, 0x06 },
1437*4882a593Smuzhiyun { 0x28, 0x24 },
1438*4882a593Smuzhiyun { 0x2b, 0xac },
1439*4882a593Smuzhiyun { 0x12, 0x00 },
1440*4882a593Smuzhiyun { 0x38, 0x81 },
1441*4882a593Smuzhiyun { 0x28, 0x24 }, /* 0c */
1442*4882a593Smuzhiyun { 0x0f, 0x85 }, /* lg's setting */
1443*4882a593Smuzhiyun { 0x15, 0x01 },
1444*4882a593Smuzhiyun { 0x20, 0x1c },
1445*4882a593Smuzhiyun { 0x23, 0x2a },
1446*4882a593Smuzhiyun { 0x24, 0x10 },
1447*4882a593Smuzhiyun { 0x25, 0x8a },
1448*4882a593Smuzhiyun { 0x26, 0xa2 },
1449*4882a593Smuzhiyun { 0x27, 0xc2 },
1450*4882a593Smuzhiyun { 0x2a, 0x04 },
1451*4882a593Smuzhiyun { 0x2c, 0xfe },
1452*4882a593Smuzhiyun { 0x2d, 0x93 },
1453*4882a593Smuzhiyun { 0x30, 0x71 },
1454*4882a593Smuzhiyun { 0x31, 0x60 },
1455*4882a593Smuzhiyun { 0x32, 0x26 },
1456*4882a593Smuzhiyun { 0x33, 0x20 },
1457*4882a593Smuzhiyun { 0x34, 0x48 },
1458*4882a593Smuzhiyun { 0x12, 0x24 },
1459*4882a593Smuzhiyun { 0x11, 0x01 },
1460*4882a593Smuzhiyun { 0x0c, 0x24 },
1461*4882a593Smuzhiyun { 0x0d, 0x24 },
1462*4882a593Smuzhiyun };
1463*4882a593Smuzhiyun
1464*4882a593Smuzhiyun static const struct ov_i2c_regvals norm_7620[] = {
1465*4882a593Smuzhiyun { 0x12, 0x80 }, /* reset */
1466*4882a593Smuzhiyun { 0x00, 0x00 }, /* gain */
1467*4882a593Smuzhiyun { 0x01, 0x80 }, /* blue gain */
1468*4882a593Smuzhiyun { 0x02, 0x80 }, /* red gain */
1469*4882a593Smuzhiyun { 0x03, 0xc0 }, /* OV7670_R03_VREF */
1470*4882a593Smuzhiyun { 0x06, 0x60 },
1471*4882a593Smuzhiyun { 0x07, 0x00 },
1472*4882a593Smuzhiyun { 0x0c, 0x24 },
1473*4882a593Smuzhiyun { 0x0c, 0x24 },
1474*4882a593Smuzhiyun { 0x0d, 0x24 },
1475*4882a593Smuzhiyun { 0x11, 0x01 },
1476*4882a593Smuzhiyun { 0x12, 0x24 },
1477*4882a593Smuzhiyun { 0x13, 0x01 },
1478*4882a593Smuzhiyun { 0x14, 0x84 },
1479*4882a593Smuzhiyun { 0x15, 0x01 },
1480*4882a593Smuzhiyun { 0x16, 0x03 },
1481*4882a593Smuzhiyun { 0x17, 0x2f },
1482*4882a593Smuzhiyun { 0x18, 0xcf },
1483*4882a593Smuzhiyun { 0x19, 0x06 },
1484*4882a593Smuzhiyun { 0x1a, 0xf5 },
1485*4882a593Smuzhiyun { 0x1b, 0x00 },
1486*4882a593Smuzhiyun { 0x20, 0x18 },
1487*4882a593Smuzhiyun { 0x21, 0x80 },
1488*4882a593Smuzhiyun { 0x22, 0x80 },
1489*4882a593Smuzhiyun { 0x23, 0x00 },
1490*4882a593Smuzhiyun { 0x26, 0xa2 },
1491*4882a593Smuzhiyun { 0x27, 0xea },
1492*4882a593Smuzhiyun { 0x28, 0x22 }, /* Was 0x20, bit1 enables a 2x gain which we need */
1493*4882a593Smuzhiyun { 0x29, 0x00 },
1494*4882a593Smuzhiyun { 0x2a, 0x10 },
1495*4882a593Smuzhiyun { 0x2b, 0x00 },
1496*4882a593Smuzhiyun { 0x2c, 0x88 },
1497*4882a593Smuzhiyun { 0x2d, 0x91 },
1498*4882a593Smuzhiyun { 0x2e, 0x80 },
1499*4882a593Smuzhiyun { 0x2f, 0x44 },
1500*4882a593Smuzhiyun { 0x60, 0x27 },
1501*4882a593Smuzhiyun { 0x61, 0x02 },
1502*4882a593Smuzhiyun { 0x62, 0x5f },
1503*4882a593Smuzhiyun { 0x63, 0xd5 },
1504*4882a593Smuzhiyun { 0x64, 0x57 },
1505*4882a593Smuzhiyun { 0x65, 0x83 },
1506*4882a593Smuzhiyun { 0x66, 0x55 },
1507*4882a593Smuzhiyun { 0x67, 0x92 },
1508*4882a593Smuzhiyun { 0x68, 0xcf },
1509*4882a593Smuzhiyun { 0x69, 0x76 },
1510*4882a593Smuzhiyun { 0x6a, 0x22 },
1511*4882a593Smuzhiyun { 0x6b, 0x00 },
1512*4882a593Smuzhiyun { 0x6c, 0x02 },
1513*4882a593Smuzhiyun { 0x6d, 0x44 },
1514*4882a593Smuzhiyun { 0x6e, 0x80 },
1515*4882a593Smuzhiyun { 0x6f, 0x1d },
1516*4882a593Smuzhiyun { 0x70, 0x8b },
1517*4882a593Smuzhiyun { 0x71, 0x00 },
1518*4882a593Smuzhiyun { 0x72, 0x14 },
1519*4882a593Smuzhiyun { 0x73, 0x54 },
1520*4882a593Smuzhiyun { 0x74, 0x00 },
1521*4882a593Smuzhiyun { 0x75, 0x8e },
1522*4882a593Smuzhiyun { 0x76, 0x00 },
1523*4882a593Smuzhiyun { 0x77, 0xff },
1524*4882a593Smuzhiyun { 0x78, 0x80 },
1525*4882a593Smuzhiyun { 0x79, 0x80 },
1526*4882a593Smuzhiyun { 0x7a, 0x80 },
1527*4882a593Smuzhiyun { 0x7b, 0xe2 },
1528*4882a593Smuzhiyun { 0x7c, 0x00 },
1529*4882a593Smuzhiyun };
1530*4882a593Smuzhiyun
1531*4882a593Smuzhiyun /* 7640 and 7648. The defaults should be OK for most registers. */
1532*4882a593Smuzhiyun static const struct ov_i2c_regvals norm_7640[] = {
1533*4882a593Smuzhiyun { 0x12, 0x80 },
1534*4882a593Smuzhiyun { 0x12, 0x14 },
1535*4882a593Smuzhiyun };
1536*4882a593Smuzhiyun
1537*4882a593Smuzhiyun static const struct ov_regvals init_519_ov7660[] = {
1538*4882a593Smuzhiyun { 0x5d, 0x03 }, /* Turn off suspend mode */
1539*4882a593Smuzhiyun { 0x53, 0x9b }, /* 0x9f enables the (unused) microcontroller */
1540*4882a593Smuzhiyun { 0x54, 0x0f }, /* bit2 (jpeg enable) */
1541*4882a593Smuzhiyun { 0xa2, 0x20 }, /* a2-a5 are undocumented */
1542*4882a593Smuzhiyun { 0xa3, 0x18 },
1543*4882a593Smuzhiyun { 0xa4, 0x04 },
1544*4882a593Smuzhiyun { 0xa5, 0x28 },
1545*4882a593Smuzhiyun { 0x37, 0x00 }, /* SetUsbInit */
1546*4882a593Smuzhiyun { 0x55, 0x02 }, /* 4.096 Mhz audio clock */
1547*4882a593Smuzhiyun /* Enable both fields, YUV Input, disable defect comp (why?) */
1548*4882a593Smuzhiyun { 0x20, 0x0c }, /* 0x0d does U <-> V swap */
1549*4882a593Smuzhiyun { 0x21, 0x38 },
1550*4882a593Smuzhiyun { 0x22, 0x1d },
1551*4882a593Smuzhiyun { 0x17, 0x50 }, /* undocumented */
1552*4882a593Smuzhiyun { 0x37, 0x00 }, /* undocumented */
1553*4882a593Smuzhiyun { 0x40, 0xff }, /* I2C timeout counter */
1554*4882a593Smuzhiyun { 0x46, 0x00 }, /* I2C clock prescaler */
1555*4882a593Smuzhiyun };
1556*4882a593Smuzhiyun static const struct ov_i2c_regvals norm_7660[] = {
1557*4882a593Smuzhiyun {OV7670_R12_COM7, OV7670_COM7_RESET},
1558*4882a593Smuzhiyun {OV7670_R11_CLKRC, 0x81},
1559*4882a593Smuzhiyun {0x92, 0x00}, /* DM_LNL */
1560*4882a593Smuzhiyun {0x93, 0x00}, /* DM_LNH */
1561*4882a593Smuzhiyun {0x9d, 0x4c}, /* BD50ST */
1562*4882a593Smuzhiyun {0x9e, 0x3f}, /* BD60ST */
1563*4882a593Smuzhiyun {OV7670_R3B_COM11, 0x02},
1564*4882a593Smuzhiyun {OV7670_R13_COM8, 0xf5},
1565*4882a593Smuzhiyun {OV7670_R10_AECH, 0x00},
1566*4882a593Smuzhiyun {OV7670_R00_GAIN, 0x00},
1567*4882a593Smuzhiyun {OV7670_R01_BLUE, 0x7c},
1568*4882a593Smuzhiyun {OV7670_R02_RED, 0x9d},
1569*4882a593Smuzhiyun {OV7670_R12_COM7, 0x00},
1570*4882a593Smuzhiyun {OV7670_R04_COM1, 00},
1571*4882a593Smuzhiyun {OV7670_R18_HSTOP, 0x01},
1572*4882a593Smuzhiyun {OV7670_R17_HSTART, 0x13},
1573*4882a593Smuzhiyun {OV7670_R32_HREF, 0x92},
1574*4882a593Smuzhiyun {OV7670_R19_VSTART, 0x02},
1575*4882a593Smuzhiyun {OV7670_R1A_VSTOP, 0x7a},
1576*4882a593Smuzhiyun {OV7670_R03_VREF, 0x00},
1577*4882a593Smuzhiyun {OV7670_R0E_COM5, 0x04},
1578*4882a593Smuzhiyun {OV7670_R0F_COM6, 0x62},
1579*4882a593Smuzhiyun {OV7670_R15_COM10, 0x00},
1580*4882a593Smuzhiyun {0x16, 0x02}, /* RSVD */
1581*4882a593Smuzhiyun {0x1b, 0x00}, /* PSHFT */
1582*4882a593Smuzhiyun {OV7670_R1E_MVFP, 0x01},
1583*4882a593Smuzhiyun {0x29, 0x3c}, /* RSVD */
1584*4882a593Smuzhiyun {0x33, 0x00}, /* CHLF */
1585*4882a593Smuzhiyun {0x34, 0x07}, /* ARBLM */
1586*4882a593Smuzhiyun {0x35, 0x84}, /* RSVD */
1587*4882a593Smuzhiyun {0x36, 0x00}, /* RSVD */
1588*4882a593Smuzhiyun {0x37, 0x04}, /* ADC */
1589*4882a593Smuzhiyun {0x39, 0x43}, /* OFON */
1590*4882a593Smuzhiyun {OV7670_R3A_TSLB, 0x00},
1591*4882a593Smuzhiyun {OV7670_R3C_COM12, 0x6c},
1592*4882a593Smuzhiyun {OV7670_R3D_COM13, 0x98},
1593*4882a593Smuzhiyun {OV7670_R3F_EDGE, 0x23},
1594*4882a593Smuzhiyun {OV7670_R40_COM15, 0xc1},
1595*4882a593Smuzhiyun {OV7670_R41_COM16, 0x22},
1596*4882a593Smuzhiyun {0x6b, 0x0a}, /* DBLV */
1597*4882a593Smuzhiyun {0xa1, 0x08}, /* RSVD */
1598*4882a593Smuzhiyun {0x69, 0x80}, /* HV */
1599*4882a593Smuzhiyun {0x43, 0xf0}, /* RSVD.. */
1600*4882a593Smuzhiyun {0x44, 0x10},
1601*4882a593Smuzhiyun {0x45, 0x78},
1602*4882a593Smuzhiyun {0x46, 0xa8},
1603*4882a593Smuzhiyun {0x47, 0x60},
1604*4882a593Smuzhiyun {0x48, 0x80},
1605*4882a593Smuzhiyun {0x59, 0xba},
1606*4882a593Smuzhiyun {0x5a, 0x9a},
1607*4882a593Smuzhiyun {0x5b, 0x22},
1608*4882a593Smuzhiyun {0x5c, 0xb9},
1609*4882a593Smuzhiyun {0x5d, 0x9b},
1610*4882a593Smuzhiyun {0x5e, 0x10},
1611*4882a593Smuzhiyun {0x5f, 0xe0},
1612*4882a593Smuzhiyun {0x60, 0x85},
1613*4882a593Smuzhiyun {0x61, 0x60},
1614*4882a593Smuzhiyun {0x9f, 0x9d}, /* RSVD */
1615*4882a593Smuzhiyun {0xa0, 0xa0}, /* DSPC2 */
1616*4882a593Smuzhiyun {0x4f, 0x60}, /* matrix */
1617*4882a593Smuzhiyun {0x50, 0x64},
1618*4882a593Smuzhiyun {0x51, 0x04},
1619*4882a593Smuzhiyun {0x52, 0x18},
1620*4882a593Smuzhiyun {0x53, 0x3c},
1621*4882a593Smuzhiyun {0x54, 0x54},
1622*4882a593Smuzhiyun {0x55, 0x40},
1623*4882a593Smuzhiyun {0x56, 0x40},
1624*4882a593Smuzhiyun {0x57, 0x40},
1625*4882a593Smuzhiyun {0x58, 0x0d}, /* matrix sign */
1626*4882a593Smuzhiyun {0x8b, 0xcc}, /* RSVD */
1627*4882a593Smuzhiyun {0x8c, 0xcc},
1628*4882a593Smuzhiyun {0x8d, 0xcf},
1629*4882a593Smuzhiyun {0x6c, 0x40}, /* gamma curve */
1630*4882a593Smuzhiyun {0x6d, 0xe0},
1631*4882a593Smuzhiyun {0x6e, 0xa0},
1632*4882a593Smuzhiyun {0x6f, 0x80},
1633*4882a593Smuzhiyun {0x70, 0x70},
1634*4882a593Smuzhiyun {0x71, 0x80},
1635*4882a593Smuzhiyun {0x72, 0x60},
1636*4882a593Smuzhiyun {0x73, 0x60},
1637*4882a593Smuzhiyun {0x74, 0x50},
1638*4882a593Smuzhiyun {0x75, 0x40},
1639*4882a593Smuzhiyun {0x76, 0x38},
1640*4882a593Smuzhiyun {0x77, 0x3c},
1641*4882a593Smuzhiyun {0x78, 0x32},
1642*4882a593Smuzhiyun {0x79, 0x1a},
1643*4882a593Smuzhiyun {0x7a, 0x28},
1644*4882a593Smuzhiyun {0x7b, 0x24},
1645*4882a593Smuzhiyun {0x7c, 0x04}, /* gamma curve */
1646*4882a593Smuzhiyun {0x7d, 0x12},
1647*4882a593Smuzhiyun {0x7e, 0x26},
1648*4882a593Smuzhiyun {0x7f, 0x46},
1649*4882a593Smuzhiyun {0x80, 0x54},
1650*4882a593Smuzhiyun {0x81, 0x64},
1651*4882a593Smuzhiyun {0x82, 0x70},
1652*4882a593Smuzhiyun {0x83, 0x7c},
1653*4882a593Smuzhiyun {0x84, 0x86},
1654*4882a593Smuzhiyun {0x85, 0x8e},
1655*4882a593Smuzhiyun {0x86, 0x9c},
1656*4882a593Smuzhiyun {0x87, 0xab},
1657*4882a593Smuzhiyun {0x88, 0xc4},
1658*4882a593Smuzhiyun {0x89, 0xd1},
1659*4882a593Smuzhiyun {0x8a, 0xe5},
1660*4882a593Smuzhiyun {OV7670_R14_COM9, 0x1e},
1661*4882a593Smuzhiyun {OV7670_R24_AEW, 0x80},
1662*4882a593Smuzhiyun {OV7670_R25_AEB, 0x72},
1663*4882a593Smuzhiyun {OV7670_R26_VPT, 0xb3},
1664*4882a593Smuzhiyun {0x62, 0x80}, /* LCC1 */
1665*4882a593Smuzhiyun {0x63, 0x80}, /* LCC2 */
1666*4882a593Smuzhiyun {0x64, 0x06}, /* LCC3 */
1667*4882a593Smuzhiyun {0x65, 0x00}, /* LCC4 */
1668*4882a593Smuzhiyun {0x66, 0x01}, /* LCC5 */
1669*4882a593Smuzhiyun {0x94, 0x0e}, /* RSVD.. */
1670*4882a593Smuzhiyun {0x95, 0x14},
1671*4882a593Smuzhiyun {OV7670_R13_COM8, OV7670_COM8_FASTAEC
1672*4882a593Smuzhiyun | OV7670_COM8_AECSTEP
1673*4882a593Smuzhiyun | OV7670_COM8_BFILT
1674*4882a593Smuzhiyun | 0x10
1675*4882a593Smuzhiyun | OV7670_COM8_AGC
1676*4882a593Smuzhiyun | OV7670_COM8_AWB
1677*4882a593Smuzhiyun | OV7670_COM8_AEC},
1678*4882a593Smuzhiyun {0xa1, 0xc8}
1679*4882a593Smuzhiyun };
1680*4882a593Smuzhiyun static const struct ov_i2c_regvals norm_9600[] = {
1681*4882a593Smuzhiyun {0x12, 0x80},
1682*4882a593Smuzhiyun {0x0c, 0x28},
1683*4882a593Smuzhiyun {0x11, 0x80},
1684*4882a593Smuzhiyun {0x13, 0xb5},
1685*4882a593Smuzhiyun {0x14, 0x3e},
1686*4882a593Smuzhiyun {0x1b, 0x04},
1687*4882a593Smuzhiyun {0x24, 0xb0},
1688*4882a593Smuzhiyun {0x25, 0x90},
1689*4882a593Smuzhiyun {0x26, 0x94},
1690*4882a593Smuzhiyun {0x35, 0x90},
1691*4882a593Smuzhiyun {0x37, 0x07},
1692*4882a593Smuzhiyun {0x38, 0x08},
1693*4882a593Smuzhiyun {0x01, 0x8e},
1694*4882a593Smuzhiyun {0x02, 0x85}
1695*4882a593Smuzhiyun };
1696*4882a593Smuzhiyun
1697*4882a593Smuzhiyun /* 7670. Defaults taken from OmniVision provided data,
1698*4882a593Smuzhiyun * as provided by Jonathan Corbet of OLPC */
1699*4882a593Smuzhiyun static const struct ov_i2c_regvals norm_7670[] = {
1700*4882a593Smuzhiyun { OV7670_R12_COM7, OV7670_COM7_RESET },
1701*4882a593Smuzhiyun { OV7670_R3A_TSLB, 0x04 }, /* OV */
1702*4882a593Smuzhiyun { OV7670_R12_COM7, OV7670_COM7_FMT_VGA }, /* VGA */
1703*4882a593Smuzhiyun { OV7670_R11_CLKRC, 0x01 },
1704*4882a593Smuzhiyun /*
1705*4882a593Smuzhiyun * Set the hardware window. These values from OV don't entirely
1706*4882a593Smuzhiyun * make sense - hstop is less than hstart. But they work...
1707*4882a593Smuzhiyun */
1708*4882a593Smuzhiyun { OV7670_R17_HSTART, 0x13 },
1709*4882a593Smuzhiyun { OV7670_R18_HSTOP, 0x01 },
1710*4882a593Smuzhiyun { OV7670_R32_HREF, 0xb6 },
1711*4882a593Smuzhiyun { OV7670_R19_VSTART, 0x02 },
1712*4882a593Smuzhiyun { OV7670_R1A_VSTOP, 0x7a },
1713*4882a593Smuzhiyun { OV7670_R03_VREF, 0x0a },
1714*4882a593Smuzhiyun
1715*4882a593Smuzhiyun { OV7670_R0C_COM3, 0x00 },
1716*4882a593Smuzhiyun { OV7670_R3E_COM14, 0x00 },
1717*4882a593Smuzhiyun /* Mystery scaling numbers */
1718*4882a593Smuzhiyun { 0x70, 0x3a },
1719*4882a593Smuzhiyun { 0x71, 0x35 },
1720*4882a593Smuzhiyun { 0x72, 0x11 },
1721*4882a593Smuzhiyun { 0x73, 0xf0 },
1722*4882a593Smuzhiyun { 0xa2, 0x02 },
1723*4882a593Smuzhiyun /* { OV7670_R15_COM10, 0x0 }, */
1724*4882a593Smuzhiyun
1725*4882a593Smuzhiyun /* Gamma curve values */
1726*4882a593Smuzhiyun { 0x7a, 0x20 },
1727*4882a593Smuzhiyun { 0x7b, 0x10 },
1728*4882a593Smuzhiyun { 0x7c, 0x1e },
1729*4882a593Smuzhiyun { 0x7d, 0x35 },
1730*4882a593Smuzhiyun { 0x7e, 0x5a },
1731*4882a593Smuzhiyun { 0x7f, 0x69 },
1732*4882a593Smuzhiyun { 0x80, 0x76 },
1733*4882a593Smuzhiyun { 0x81, 0x80 },
1734*4882a593Smuzhiyun { 0x82, 0x88 },
1735*4882a593Smuzhiyun { 0x83, 0x8f },
1736*4882a593Smuzhiyun { 0x84, 0x96 },
1737*4882a593Smuzhiyun { 0x85, 0xa3 },
1738*4882a593Smuzhiyun { 0x86, 0xaf },
1739*4882a593Smuzhiyun { 0x87, 0xc4 },
1740*4882a593Smuzhiyun { 0x88, 0xd7 },
1741*4882a593Smuzhiyun { 0x89, 0xe8 },
1742*4882a593Smuzhiyun
1743*4882a593Smuzhiyun /* AGC and AEC parameters. Note we start by disabling those features,
1744*4882a593Smuzhiyun then turn them only after tweaking the values. */
1745*4882a593Smuzhiyun { OV7670_R13_COM8, OV7670_COM8_FASTAEC
1746*4882a593Smuzhiyun | OV7670_COM8_AECSTEP
1747*4882a593Smuzhiyun | OV7670_COM8_BFILT },
1748*4882a593Smuzhiyun { OV7670_R00_GAIN, 0x00 },
1749*4882a593Smuzhiyun { OV7670_R10_AECH, 0x00 },
1750*4882a593Smuzhiyun { OV7670_R0D_COM4, 0x40 }, /* magic reserved bit */
1751*4882a593Smuzhiyun { OV7670_R14_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
1752*4882a593Smuzhiyun { OV7670_RA5_BD50MAX, 0x05 },
1753*4882a593Smuzhiyun { OV7670_RAB_BD60MAX, 0x07 },
1754*4882a593Smuzhiyun { OV7670_R24_AEW, 0x95 },
1755*4882a593Smuzhiyun { OV7670_R25_AEB, 0x33 },
1756*4882a593Smuzhiyun { OV7670_R26_VPT, 0xe3 },
1757*4882a593Smuzhiyun { OV7670_R9F_HAECC1, 0x78 },
1758*4882a593Smuzhiyun { OV7670_RA0_HAECC2, 0x68 },
1759*4882a593Smuzhiyun { 0xa1, 0x03 }, /* magic */
1760*4882a593Smuzhiyun { OV7670_RA6_HAECC3, 0xd8 },
1761*4882a593Smuzhiyun { OV7670_RA7_HAECC4, 0xd8 },
1762*4882a593Smuzhiyun { OV7670_RA8_HAECC5, 0xf0 },
1763*4882a593Smuzhiyun { OV7670_RA9_HAECC6, 0x90 },
1764*4882a593Smuzhiyun { OV7670_RAA_HAECC7, 0x94 },
1765*4882a593Smuzhiyun { OV7670_R13_COM8, OV7670_COM8_FASTAEC
1766*4882a593Smuzhiyun | OV7670_COM8_AECSTEP
1767*4882a593Smuzhiyun | OV7670_COM8_BFILT
1768*4882a593Smuzhiyun | OV7670_COM8_AGC
1769*4882a593Smuzhiyun | OV7670_COM8_AEC },
1770*4882a593Smuzhiyun
1771*4882a593Smuzhiyun /* Almost all of these are magic "reserved" values. */
1772*4882a593Smuzhiyun { OV7670_R0E_COM5, 0x61 },
1773*4882a593Smuzhiyun { OV7670_R0F_COM6, 0x4b },
1774*4882a593Smuzhiyun { 0x16, 0x02 },
1775*4882a593Smuzhiyun { OV7670_R1E_MVFP, 0x07 },
1776*4882a593Smuzhiyun { 0x21, 0x02 },
1777*4882a593Smuzhiyun { 0x22, 0x91 },
1778*4882a593Smuzhiyun { 0x29, 0x07 },
1779*4882a593Smuzhiyun { 0x33, 0x0b },
1780*4882a593Smuzhiyun { 0x35, 0x0b },
1781*4882a593Smuzhiyun { 0x37, 0x1d },
1782*4882a593Smuzhiyun { 0x38, 0x71 },
1783*4882a593Smuzhiyun { 0x39, 0x2a },
1784*4882a593Smuzhiyun { OV7670_R3C_COM12, 0x78 },
1785*4882a593Smuzhiyun { 0x4d, 0x40 },
1786*4882a593Smuzhiyun { 0x4e, 0x20 },
1787*4882a593Smuzhiyun { OV7670_R69_GFIX, 0x00 },
1788*4882a593Smuzhiyun { 0x6b, 0x4a },
1789*4882a593Smuzhiyun { 0x74, 0x10 },
1790*4882a593Smuzhiyun { 0x8d, 0x4f },
1791*4882a593Smuzhiyun { 0x8e, 0x00 },
1792*4882a593Smuzhiyun { 0x8f, 0x00 },
1793*4882a593Smuzhiyun { 0x90, 0x00 },
1794*4882a593Smuzhiyun { 0x91, 0x00 },
1795*4882a593Smuzhiyun { 0x96, 0x00 },
1796*4882a593Smuzhiyun { 0x9a, 0x00 },
1797*4882a593Smuzhiyun { 0xb0, 0x84 },
1798*4882a593Smuzhiyun { 0xb1, 0x0c },
1799*4882a593Smuzhiyun { 0xb2, 0x0e },
1800*4882a593Smuzhiyun { 0xb3, 0x82 },
1801*4882a593Smuzhiyun { 0xb8, 0x0a },
1802*4882a593Smuzhiyun
1803*4882a593Smuzhiyun /* More reserved magic, some of which tweaks white balance */
1804*4882a593Smuzhiyun { 0x43, 0x0a },
1805*4882a593Smuzhiyun { 0x44, 0xf0 },
1806*4882a593Smuzhiyun { 0x45, 0x34 },
1807*4882a593Smuzhiyun { 0x46, 0x58 },
1808*4882a593Smuzhiyun { 0x47, 0x28 },
1809*4882a593Smuzhiyun { 0x48, 0x3a },
1810*4882a593Smuzhiyun { 0x59, 0x88 },
1811*4882a593Smuzhiyun { 0x5a, 0x88 },
1812*4882a593Smuzhiyun { 0x5b, 0x44 },
1813*4882a593Smuzhiyun { 0x5c, 0x67 },
1814*4882a593Smuzhiyun { 0x5d, 0x49 },
1815*4882a593Smuzhiyun { 0x5e, 0x0e },
1816*4882a593Smuzhiyun { 0x6c, 0x0a },
1817*4882a593Smuzhiyun { 0x6d, 0x55 },
1818*4882a593Smuzhiyun { 0x6e, 0x11 },
1819*4882a593Smuzhiyun { 0x6f, 0x9f }, /* "9e for advance AWB" */
1820*4882a593Smuzhiyun { 0x6a, 0x40 },
1821*4882a593Smuzhiyun { OV7670_R01_BLUE, 0x40 },
1822*4882a593Smuzhiyun { OV7670_R02_RED, 0x60 },
1823*4882a593Smuzhiyun { OV7670_R13_COM8, OV7670_COM8_FASTAEC
1824*4882a593Smuzhiyun | OV7670_COM8_AECSTEP
1825*4882a593Smuzhiyun | OV7670_COM8_BFILT
1826*4882a593Smuzhiyun | OV7670_COM8_AGC
1827*4882a593Smuzhiyun | OV7670_COM8_AEC
1828*4882a593Smuzhiyun | OV7670_COM8_AWB },
1829*4882a593Smuzhiyun
1830*4882a593Smuzhiyun /* Matrix coefficients */
1831*4882a593Smuzhiyun { 0x4f, 0x80 },
1832*4882a593Smuzhiyun { 0x50, 0x80 },
1833*4882a593Smuzhiyun { 0x51, 0x00 },
1834*4882a593Smuzhiyun { 0x52, 0x22 },
1835*4882a593Smuzhiyun { 0x53, 0x5e },
1836*4882a593Smuzhiyun { 0x54, 0x80 },
1837*4882a593Smuzhiyun { 0x58, 0x9e },
1838*4882a593Smuzhiyun
1839*4882a593Smuzhiyun { OV7670_R41_COM16, OV7670_COM16_AWBGAIN },
1840*4882a593Smuzhiyun { OV7670_R3F_EDGE, 0x00 },
1841*4882a593Smuzhiyun { 0x75, 0x05 },
1842*4882a593Smuzhiyun { 0x76, 0xe1 },
1843*4882a593Smuzhiyun { 0x4c, 0x00 },
1844*4882a593Smuzhiyun { 0x77, 0x01 },
1845*4882a593Smuzhiyun { OV7670_R3D_COM13, OV7670_COM13_GAMMA
1846*4882a593Smuzhiyun | OV7670_COM13_UVSAT
1847*4882a593Smuzhiyun | 2}, /* was 3 */
1848*4882a593Smuzhiyun { 0x4b, 0x09 },
1849*4882a593Smuzhiyun { 0xc9, 0x60 },
1850*4882a593Smuzhiyun { OV7670_R41_COM16, 0x38 },
1851*4882a593Smuzhiyun { 0x56, 0x40 },
1852*4882a593Smuzhiyun
1853*4882a593Smuzhiyun { 0x34, 0x11 },
1854*4882a593Smuzhiyun { OV7670_R3B_COM11, OV7670_COM11_EXP|OV7670_COM11_HZAUTO },
1855*4882a593Smuzhiyun { 0xa4, 0x88 },
1856*4882a593Smuzhiyun { 0x96, 0x00 },
1857*4882a593Smuzhiyun { 0x97, 0x30 },
1858*4882a593Smuzhiyun { 0x98, 0x20 },
1859*4882a593Smuzhiyun { 0x99, 0x30 },
1860*4882a593Smuzhiyun { 0x9a, 0x84 },
1861*4882a593Smuzhiyun { 0x9b, 0x29 },
1862*4882a593Smuzhiyun { 0x9c, 0x03 },
1863*4882a593Smuzhiyun { 0x9d, 0x4c },
1864*4882a593Smuzhiyun { 0x9e, 0x3f },
1865*4882a593Smuzhiyun { 0x78, 0x04 },
1866*4882a593Smuzhiyun
1867*4882a593Smuzhiyun /* Extra-weird stuff. Some sort of multiplexor register */
1868*4882a593Smuzhiyun { 0x79, 0x01 },
1869*4882a593Smuzhiyun { 0xc8, 0xf0 },
1870*4882a593Smuzhiyun { 0x79, 0x0f },
1871*4882a593Smuzhiyun { 0xc8, 0x00 },
1872*4882a593Smuzhiyun { 0x79, 0x10 },
1873*4882a593Smuzhiyun { 0xc8, 0x7e },
1874*4882a593Smuzhiyun { 0x79, 0x0a },
1875*4882a593Smuzhiyun { 0xc8, 0x80 },
1876*4882a593Smuzhiyun { 0x79, 0x0b },
1877*4882a593Smuzhiyun { 0xc8, 0x01 },
1878*4882a593Smuzhiyun { 0x79, 0x0c },
1879*4882a593Smuzhiyun { 0xc8, 0x0f },
1880*4882a593Smuzhiyun { 0x79, 0x0d },
1881*4882a593Smuzhiyun { 0xc8, 0x20 },
1882*4882a593Smuzhiyun { 0x79, 0x09 },
1883*4882a593Smuzhiyun { 0xc8, 0x80 },
1884*4882a593Smuzhiyun { 0x79, 0x02 },
1885*4882a593Smuzhiyun { 0xc8, 0xc0 },
1886*4882a593Smuzhiyun { 0x79, 0x03 },
1887*4882a593Smuzhiyun { 0xc8, 0x40 },
1888*4882a593Smuzhiyun { 0x79, 0x05 },
1889*4882a593Smuzhiyun { 0xc8, 0x30 },
1890*4882a593Smuzhiyun { 0x79, 0x26 },
1891*4882a593Smuzhiyun };
1892*4882a593Smuzhiyun
1893*4882a593Smuzhiyun static const struct ov_i2c_regvals norm_8610[] = {
1894*4882a593Smuzhiyun { 0x12, 0x80 },
1895*4882a593Smuzhiyun { 0x00, 0x00 },
1896*4882a593Smuzhiyun { 0x01, 0x80 },
1897*4882a593Smuzhiyun { 0x02, 0x80 },
1898*4882a593Smuzhiyun { 0x03, 0xc0 },
1899*4882a593Smuzhiyun { 0x04, 0x30 },
1900*4882a593Smuzhiyun { 0x05, 0x30 }, /* was 0x10, new from windrv 090403 */
1901*4882a593Smuzhiyun { 0x06, 0x70 }, /* was 0x80, new from windrv 090403 */
1902*4882a593Smuzhiyun { 0x0a, 0x86 },
1903*4882a593Smuzhiyun { 0x0b, 0xb0 },
1904*4882a593Smuzhiyun { 0x0c, 0x20 },
1905*4882a593Smuzhiyun { 0x0d, 0x20 },
1906*4882a593Smuzhiyun { 0x11, 0x01 },
1907*4882a593Smuzhiyun { 0x12, 0x25 },
1908*4882a593Smuzhiyun { 0x13, 0x01 },
1909*4882a593Smuzhiyun { 0x14, 0x04 },
1910*4882a593Smuzhiyun { 0x15, 0x01 }, /* Lin and Win think different about UV order */
1911*4882a593Smuzhiyun { 0x16, 0x03 },
1912*4882a593Smuzhiyun { 0x17, 0x38 }, /* was 0x2f, new from windrv 090403 */
1913*4882a593Smuzhiyun { 0x18, 0xea }, /* was 0xcf, new from windrv 090403 */
1914*4882a593Smuzhiyun { 0x19, 0x02 }, /* was 0x06, new from windrv 090403 */
1915*4882a593Smuzhiyun { 0x1a, 0xf5 },
1916*4882a593Smuzhiyun { 0x1b, 0x00 },
1917*4882a593Smuzhiyun { 0x20, 0xd0 }, /* was 0x90, new from windrv 090403 */
1918*4882a593Smuzhiyun { 0x23, 0xc0 }, /* was 0x00, new from windrv 090403 */
1919*4882a593Smuzhiyun { 0x24, 0x30 }, /* was 0x1d, new from windrv 090403 */
1920*4882a593Smuzhiyun { 0x25, 0x50 }, /* was 0x57, new from windrv 090403 */
1921*4882a593Smuzhiyun { 0x26, 0xa2 },
1922*4882a593Smuzhiyun { 0x27, 0xea },
1923*4882a593Smuzhiyun { 0x28, 0x00 },
1924*4882a593Smuzhiyun { 0x29, 0x00 },
1925*4882a593Smuzhiyun { 0x2a, 0x80 },
1926*4882a593Smuzhiyun { 0x2b, 0xc8 }, /* was 0xcc, new from windrv 090403 */
1927*4882a593Smuzhiyun { 0x2c, 0xac },
1928*4882a593Smuzhiyun { 0x2d, 0x45 }, /* was 0xd5, new from windrv 090403 */
1929*4882a593Smuzhiyun { 0x2e, 0x80 },
1930*4882a593Smuzhiyun { 0x2f, 0x14 }, /* was 0x01, new from windrv 090403 */
1931*4882a593Smuzhiyun { 0x4c, 0x00 },
1932*4882a593Smuzhiyun { 0x4d, 0x30 }, /* was 0x10, new from windrv 090403 */
1933*4882a593Smuzhiyun { 0x60, 0x02 }, /* was 0x01, new from windrv 090403 */
1934*4882a593Smuzhiyun { 0x61, 0x00 }, /* was 0x09, new from windrv 090403 */
1935*4882a593Smuzhiyun { 0x62, 0x5f }, /* was 0xd7, new from windrv 090403 */
1936*4882a593Smuzhiyun { 0x63, 0xff },
1937*4882a593Smuzhiyun { 0x64, 0x53 }, /* new windrv 090403 says 0x57,
1938*4882a593Smuzhiyun * maybe that's wrong */
1939*4882a593Smuzhiyun { 0x65, 0x00 },
1940*4882a593Smuzhiyun { 0x66, 0x55 },
1941*4882a593Smuzhiyun { 0x67, 0xb0 },
1942*4882a593Smuzhiyun { 0x68, 0xc0 }, /* was 0xaf, new from windrv 090403 */
1943*4882a593Smuzhiyun { 0x69, 0x02 },
1944*4882a593Smuzhiyun { 0x6a, 0x22 },
1945*4882a593Smuzhiyun { 0x6b, 0x00 },
1946*4882a593Smuzhiyun { 0x6c, 0x99 }, /* was 0x80, old windrv says 0x00, but
1947*4882a593Smuzhiyun * deleting bit7 colors the first images red */
1948*4882a593Smuzhiyun { 0x6d, 0x11 }, /* was 0x00, new from windrv 090403 */
1949*4882a593Smuzhiyun { 0x6e, 0x11 }, /* was 0x00, new from windrv 090403 */
1950*4882a593Smuzhiyun { 0x6f, 0x01 },
1951*4882a593Smuzhiyun { 0x70, 0x8b },
1952*4882a593Smuzhiyun { 0x71, 0x00 },
1953*4882a593Smuzhiyun { 0x72, 0x14 },
1954*4882a593Smuzhiyun { 0x73, 0x54 },
1955*4882a593Smuzhiyun { 0x74, 0x00 },/* 0x60? - was 0x00, new from windrv 090403 */
1956*4882a593Smuzhiyun { 0x75, 0x0e },
1957*4882a593Smuzhiyun { 0x76, 0x02 }, /* was 0x02, new from windrv 090403 */
1958*4882a593Smuzhiyun { 0x77, 0xff },
1959*4882a593Smuzhiyun { 0x78, 0x80 },
1960*4882a593Smuzhiyun { 0x79, 0x80 },
1961*4882a593Smuzhiyun { 0x7a, 0x80 },
1962*4882a593Smuzhiyun { 0x7b, 0x10 }, /* was 0x13, new from windrv 090403 */
1963*4882a593Smuzhiyun { 0x7c, 0x00 },
1964*4882a593Smuzhiyun { 0x7d, 0x08 }, /* was 0x09, new from windrv 090403 */
1965*4882a593Smuzhiyun { 0x7e, 0x08 }, /* was 0xc0, new from windrv 090403 */
1966*4882a593Smuzhiyun { 0x7f, 0xfb },
1967*4882a593Smuzhiyun { 0x80, 0x28 },
1968*4882a593Smuzhiyun { 0x81, 0x00 },
1969*4882a593Smuzhiyun { 0x82, 0x23 },
1970*4882a593Smuzhiyun { 0x83, 0x0b },
1971*4882a593Smuzhiyun { 0x84, 0x00 },
1972*4882a593Smuzhiyun { 0x85, 0x62 }, /* was 0x61, new from windrv 090403 */
1973*4882a593Smuzhiyun { 0x86, 0xc9 },
1974*4882a593Smuzhiyun { 0x87, 0x00 },
1975*4882a593Smuzhiyun { 0x88, 0x00 },
1976*4882a593Smuzhiyun { 0x89, 0x01 },
1977*4882a593Smuzhiyun { 0x12, 0x20 },
1978*4882a593Smuzhiyun { 0x12, 0x25 }, /* was 0x24, new from windrv 090403 */
1979*4882a593Smuzhiyun };
1980*4882a593Smuzhiyun
ov7670_abs_to_sm(unsigned char v)1981*4882a593Smuzhiyun static unsigned char ov7670_abs_to_sm(unsigned char v)
1982*4882a593Smuzhiyun {
1983*4882a593Smuzhiyun if (v > 127)
1984*4882a593Smuzhiyun return v & 0x7f;
1985*4882a593Smuzhiyun return (128 - v) | 0x80;
1986*4882a593Smuzhiyun }
1987*4882a593Smuzhiyun
1988*4882a593Smuzhiyun /* Write a OV519 register */
reg_w(struct sd * sd,u16 index,u16 value)1989*4882a593Smuzhiyun static void reg_w(struct sd *sd, u16 index, u16 value)
1990*4882a593Smuzhiyun {
1991*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
1992*4882a593Smuzhiyun int ret, req = 0;
1993*4882a593Smuzhiyun
1994*4882a593Smuzhiyun if (sd->gspca_dev.usb_err < 0)
1995*4882a593Smuzhiyun return;
1996*4882a593Smuzhiyun
1997*4882a593Smuzhiyun /* Avoid things going to fast for the bridge with a xhci host */
1998*4882a593Smuzhiyun udelay(150);
1999*4882a593Smuzhiyun
2000*4882a593Smuzhiyun switch (sd->bridge) {
2001*4882a593Smuzhiyun case BRIDGE_OV511:
2002*4882a593Smuzhiyun case BRIDGE_OV511PLUS:
2003*4882a593Smuzhiyun req = 2;
2004*4882a593Smuzhiyun break;
2005*4882a593Smuzhiyun case BRIDGE_OVFX2:
2006*4882a593Smuzhiyun req = 0x0a;
2007*4882a593Smuzhiyun fallthrough;
2008*4882a593Smuzhiyun case BRIDGE_W9968CF:
2009*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_USBO, "SET %02x %04x %04x\n",
2010*4882a593Smuzhiyun req, value, index);
2011*4882a593Smuzhiyun ret = usb_control_msg(sd->gspca_dev.dev,
2012*4882a593Smuzhiyun usb_sndctrlpipe(sd->gspca_dev.dev, 0),
2013*4882a593Smuzhiyun req,
2014*4882a593Smuzhiyun USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
2015*4882a593Smuzhiyun value, index, NULL, 0, 500);
2016*4882a593Smuzhiyun goto leave;
2017*4882a593Smuzhiyun default:
2018*4882a593Smuzhiyun req = 1;
2019*4882a593Smuzhiyun }
2020*4882a593Smuzhiyun
2021*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_USBO, "SET %02x 0000 %04x %02x\n",
2022*4882a593Smuzhiyun req, index, value);
2023*4882a593Smuzhiyun sd->gspca_dev.usb_buf[0] = value;
2024*4882a593Smuzhiyun ret = usb_control_msg(sd->gspca_dev.dev,
2025*4882a593Smuzhiyun usb_sndctrlpipe(sd->gspca_dev.dev, 0),
2026*4882a593Smuzhiyun req,
2027*4882a593Smuzhiyun USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
2028*4882a593Smuzhiyun 0, index,
2029*4882a593Smuzhiyun sd->gspca_dev.usb_buf, 1, 500);
2030*4882a593Smuzhiyun leave:
2031*4882a593Smuzhiyun if (ret < 0) {
2032*4882a593Smuzhiyun gspca_err(gspca_dev, "reg_w %02x failed %d\n", index, ret);
2033*4882a593Smuzhiyun sd->gspca_dev.usb_err = ret;
2034*4882a593Smuzhiyun return;
2035*4882a593Smuzhiyun }
2036*4882a593Smuzhiyun }
2037*4882a593Smuzhiyun
2038*4882a593Smuzhiyun /* Read from a OV519 register, note not valid for the w9968cf!! */
2039*4882a593Smuzhiyun /* returns: negative is error, pos or zero is data */
reg_r(struct sd * sd,u16 index)2040*4882a593Smuzhiyun static int reg_r(struct sd *sd, u16 index)
2041*4882a593Smuzhiyun {
2042*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
2043*4882a593Smuzhiyun int ret;
2044*4882a593Smuzhiyun int req;
2045*4882a593Smuzhiyun
2046*4882a593Smuzhiyun if (sd->gspca_dev.usb_err < 0)
2047*4882a593Smuzhiyun return -1;
2048*4882a593Smuzhiyun
2049*4882a593Smuzhiyun switch (sd->bridge) {
2050*4882a593Smuzhiyun case BRIDGE_OV511:
2051*4882a593Smuzhiyun case BRIDGE_OV511PLUS:
2052*4882a593Smuzhiyun req = 3;
2053*4882a593Smuzhiyun break;
2054*4882a593Smuzhiyun case BRIDGE_OVFX2:
2055*4882a593Smuzhiyun req = 0x0b;
2056*4882a593Smuzhiyun break;
2057*4882a593Smuzhiyun default:
2058*4882a593Smuzhiyun req = 1;
2059*4882a593Smuzhiyun }
2060*4882a593Smuzhiyun
2061*4882a593Smuzhiyun /* Avoid things going to fast for the bridge with a xhci host */
2062*4882a593Smuzhiyun udelay(150);
2063*4882a593Smuzhiyun ret = usb_control_msg(sd->gspca_dev.dev,
2064*4882a593Smuzhiyun usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
2065*4882a593Smuzhiyun req,
2066*4882a593Smuzhiyun USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
2067*4882a593Smuzhiyun 0, index, sd->gspca_dev.usb_buf, 1, 500);
2068*4882a593Smuzhiyun
2069*4882a593Smuzhiyun if (ret >= 0) {
2070*4882a593Smuzhiyun ret = sd->gspca_dev.usb_buf[0];
2071*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_USBI, "GET %02x 0000 %04x %02x\n",
2072*4882a593Smuzhiyun req, index, ret);
2073*4882a593Smuzhiyun } else {
2074*4882a593Smuzhiyun gspca_err(gspca_dev, "reg_r %02x failed %d\n", index, ret);
2075*4882a593Smuzhiyun sd->gspca_dev.usb_err = ret;
2076*4882a593Smuzhiyun /*
2077*4882a593Smuzhiyun * Make sure the result is zeroed to avoid uninitialized
2078*4882a593Smuzhiyun * values.
2079*4882a593Smuzhiyun */
2080*4882a593Smuzhiyun gspca_dev->usb_buf[0] = 0;
2081*4882a593Smuzhiyun }
2082*4882a593Smuzhiyun
2083*4882a593Smuzhiyun return ret;
2084*4882a593Smuzhiyun }
2085*4882a593Smuzhiyun
2086*4882a593Smuzhiyun /* Read 8 values from a OV519 register */
reg_r8(struct sd * sd,u16 index)2087*4882a593Smuzhiyun static int reg_r8(struct sd *sd,
2088*4882a593Smuzhiyun u16 index)
2089*4882a593Smuzhiyun {
2090*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
2091*4882a593Smuzhiyun int ret;
2092*4882a593Smuzhiyun
2093*4882a593Smuzhiyun if (sd->gspca_dev.usb_err < 0)
2094*4882a593Smuzhiyun return -1;
2095*4882a593Smuzhiyun
2096*4882a593Smuzhiyun /* Avoid things going to fast for the bridge with a xhci host */
2097*4882a593Smuzhiyun udelay(150);
2098*4882a593Smuzhiyun ret = usb_control_msg(sd->gspca_dev.dev,
2099*4882a593Smuzhiyun usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
2100*4882a593Smuzhiyun 1, /* REQ_IO */
2101*4882a593Smuzhiyun USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
2102*4882a593Smuzhiyun 0, index, sd->gspca_dev.usb_buf, 8, 500);
2103*4882a593Smuzhiyun
2104*4882a593Smuzhiyun if (ret >= 0) {
2105*4882a593Smuzhiyun ret = sd->gspca_dev.usb_buf[0];
2106*4882a593Smuzhiyun } else {
2107*4882a593Smuzhiyun gspca_err(gspca_dev, "reg_r8 %02x failed %d\n", index, ret);
2108*4882a593Smuzhiyun sd->gspca_dev.usb_err = ret;
2109*4882a593Smuzhiyun /*
2110*4882a593Smuzhiyun * Make sure the buffer is zeroed to avoid uninitialized
2111*4882a593Smuzhiyun * values.
2112*4882a593Smuzhiyun */
2113*4882a593Smuzhiyun memset(gspca_dev->usb_buf, 0, 8);
2114*4882a593Smuzhiyun }
2115*4882a593Smuzhiyun
2116*4882a593Smuzhiyun return ret;
2117*4882a593Smuzhiyun }
2118*4882a593Smuzhiyun
2119*4882a593Smuzhiyun /*
2120*4882a593Smuzhiyun * Writes bits at positions specified by mask to an OV51x reg. Bits that are in
2121*4882a593Smuzhiyun * the same position as 1's in "mask" are cleared and set to "value". Bits
2122*4882a593Smuzhiyun * that are in the same position as 0's in "mask" are preserved, regardless
2123*4882a593Smuzhiyun * of their respective state in "value".
2124*4882a593Smuzhiyun */
reg_w_mask(struct sd * sd,u16 index,u8 value,u8 mask)2125*4882a593Smuzhiyun static void reg_w_mask(struct sd *sd,
2126*4882a593Smuzhiyun u16 index,
2127*4882a593Smuzhiyun u8 value,
2128*4882a593Smuzhiyun u8 mask)
2129*4882a593Smuzhiyun {
2130*4882a593Smuzhiyun int ret;
2131*4882a593Smuzhiyun u8 oldval;
2132*4882a593Smuzhiyun
2133*4882a593Smuzhiyun if (mask != 0xff) {
2134*4882a593Smuzhiyun value &= mask; /* Enforce mask on value */
2135*4882a593Smuzhiyun ret = reg_r(sd, index);
2136*4882a593Smuzhiyun if (ret < 0)
2137*4882a593Smuzhiyun return;
2138*4882a593Smuzhiyun
2139*4882a593Smuzhiyun oldval = ret & ~mask; /* Clear the masked bits */
2140*4882a593Smuzhiyun value |= oldval; /* Set the desired bits */
2141*4882a593Smuzhiyun }
2142*4882a593Smuzhiyun reg_w(sd, index, value);
2143*4882a593Smuzhiyun }
2144*4882a593Smuzhiyun
2145*4882a593Smuzhiyun /*
2146*4882a593Smuzhiyun * Writes multiple (n) byte value to a single register. Only valid with certain
2147*4882a593Smuzhiyun * registers (0x30 and 0xc4 - 0xce).
2148*4882a593Smuzhiyun */
ov518_reg_w32(struct sd * sd,u16 index,u32 value,int n)2149*4882a593Smuzhiyun static void ov518_reg_w32(struct sd *sd, u16 index, u32 value, int n)
2150*4882a593Smuzhiyun {
2151*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
2152*4882a593Smuzhiyun int ret;
2153*4882a593Smuzhiyun
2154*4882a593Smuzhiyun if (sd->gspca_dev.usb_err < 0)
2155*4882a593Smuzhiyun return;
2156*4882a593Smuzhiyun
2157*4882a593Smuzhiyun *((__le32 *) sd->gspca_dev.usb_buf) = __cpu_to_le32(value);
2158*4882a593Smuzhiyun
2159*4882a593Smuzhiyun /* Avoid things going to fast for the bridge with a xhci host */
2160*4882a593Smuzhiyun udelay(150);
2161*4882a593Smuzhiyun ret = usb_control_msg(sd->gspca_dev.dev,
2162*4882a593Smuzhiyun usb_sndctrlpipe(sd->gspca_dev.dev, 0),
2163*4882a593Smuzhiyun 1 /* REG_IO */,
2164*4882a593Smuzhiyun USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
2165*4882a593Smuzhiyun 0, index,
2166*4882a593Smuzhiyun sd->gspca_dev.usb_buf, n, 500);
2167*4882a593Smuzhiyun if (ret < 0) {
2168*4882a593Smuzhiyun gspca_err(gspca_dev, "reg_w32 %02x failed %d\n", index, ret);
2169*4882a593Smuzhiyun sd->gspca_dev.usb_err = ret;
2170*4882a593Smuzhiyun }
2171*4882a593Smuzhiyun }
2172*4882a593Smuzhiyun
ov511_i2c_w(struct sd * sd,u8 reg,u8 value)2173*4882a593Smuzhiyun static void ov511_i2c_w(struct sd *sd, u8 reg, u8 value)
2174*4882a593Smuzhiyun {
2175*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
2176*4882a593Smuzhiyun int rc, retries;
2177*4882a593Smuzhiyun
2178*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_USBO, "ov511_i2c_w %02x %02x\n", reg, value);
2179*4882a593Smuzhiyun
2180*4882a593Smuzhiyun /* Three byte write cycle */
2181*4882a593Smuzhiyun for (retries = 6; ; ) {
2182*4882a593Smuzhiyun /* Select camera register */
2183*4882a593Smuzhiyun reg_w(sd, R51x_I2C_SADDR_3, reg);
2184*4882a593Smuzhiyun
2185*4882a593Smuzhiyun /* Write "value" to I2C data port of OV511 */
2186*4882a593Smuzhiyun reg_w(sd, R51x_I2C_DATA, value);
2187*4882a593Smuzhiyun
2188*4882a593Smuzhiyun /* Initiate 3-byte write cycle */
2189*4882a593Smuzhiyun reg_w(sd, R511_I2C_CTL, 0x01);
2190*4882a593Smuzhiyun
2191*4882a593Smuzhiyun do {
2192*4882a593Smuzhiyun rc = reg_r(sd, R511_I2C_CTL);
2193*4882a593Smuzhiyun } while (rc > 0 && ((rc & 1) == 0)); /* Retry until idle */
2194*4882a593Smuzhiyun
2195*4882a593Smuzhiyun if (rc < 0)
2196*4882a593Smuzhiyun return;
2197*4882a593Smuzhiyun
2198*4882a593Smuzhiyun if ((rc & 2) == 0) /* Ack? */
2199*4882a593Smuzhiyun break;
2200*4882a593Smuzhiyun if (--retries < 0) {
2201*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_USBO, "i2c write retries exhausted\n");
2202*4882a593Smuzhiyun return;
2203*4882a593Smuzhiyun }
2204*4882a593Smuzhiyun }
2205*4882a593Smuzhiyun }
2206*4882a593Smuzhiyun
ov511_i2c_r(struct sd * sd,u8 reg)2207*4882a593Smuzhiyun static int ov511_i2c_r(struct sd *sd, u8 reg)
2208*4882a593Smuzhiyun {
2209*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
2210*4882a593Smuzhiyun int rc, value, retries;
2211*4882a593Smuzhiyun
2212*4882a593Smuzhiyun /* Two byte write cycle */
2213*4882a593Smuzhiyun for (retries = 6; ; ) {
2214*4882a593Smuzhiyun /* Select camera register */
2215*4882a593Smuzhiyun reg_w(sd, R51x_I2C_SADDR_2, reg);
2216*4882a593Smuzhiyun
2217*4882a593Smuzhiyun /* Initiate 2-byte write cycle */
2218*4882a593Smuzhiyun reg_w(sd, R511_I2C_CTL, 0x03);
2219*4882a593Smuzhiyun
2220*4882a593Smuzhiyun do {
2221*4882a593Smuzhiyun rc = reg_r(sd, R511_I2C_CTL);
2222*4882a593Smuzhiyun } while (rc > 0 && ((rc & 1) == 0)); /* Retry until idle */
2223*4882a593Smuzhiyun
2224*4882a593Smuzhiyun if (rc < 0)
2225*4882a593Smuzhiyun return rc;
2226*4882a593Smuzhiyun
2227*4882a593Smuzhiyun if ((rc & 2) == 0) /* Ack? */
2228*4882a593Smuzhiyun break;
2229*4882a593Smuzhiyun
2230*4882a593Smuzhiyun /* I2C abort */
2231*4882a593Smuzhiyun reg_w(sd, R511_I2C_CTL, 0x10);
2232*4882a593Smuzhiyun
2233*4882a593Smuzhiyun if (--retries < 0) {
2234*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_USBI, "i2c write retries exhausted\n");
2235*4882a593Smuzhiyun return -1;
2236*4882a593Smuzhiyun }
2237*4882a593Smuzhiyun }
2238*4882a593Smuzhiyun
2239*4882a593Smuzhiyun /* Two byte read cycle */
2240*4882a593Smuzhiyun for (retries = 6; ; ) {
2241*4882a593Smuzhiyun /* Initiate 2-byte read cycle */
2242*4882a593Smuzhiyun reg_w(sd, R511_I2C_CTL, 0x05);
2243*4882a593Smuzhiyun
2244*4882a593Smuzhiyun do {
2245*4882a593Smuzhiyun rc = reg_r(sd, R511_I2C_CTL);
2246*4882a593Smuzhiyun } while (rc > 0 && ((rc & 1) == 0)); /* Retry until idle */
2247*4882a593Smuzhiyun
2248*4882a593Smuzhiyun if (rc < 0)
2249*4882a593Smuzhiyun return rc;
2250*4882a593Smuzhiyun
2251*4882a593Smuzhiyun if ((rc & 2) == 0) /* Ack? */
2252*4882a593Smuzhiyun break;
2253*4882a593Smuzhiyun
2254*4882a593Smuzhiyun /* I2C abort */
2255*4882a593Smuzhiyun reg_w(sd, R511_I2C_CTL, 0x10);
2256*4882a593Smuzhiyun
2257*4882a593Smuzhiyun if (--retries < 0) {
2258*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_USBI, "i2c read retries exhausted\n");
2259*4882a593Smuzhiyun return -1;
2260*4882a593Smuzhiyun }
2261*4882a593Smuzhiyun }
2262*4882a593Smuzhiyun
2263*4882a593Smuzhiyun value = reg_r(sd, R51x_I2C_DATA);
2264*4882a593Smuzhiyun
2265*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_USBI, "ov511_i2c_r %02x %02x\n", reg, value);
2266*4882a593Smuzhiyun
2267*4882a593Smuzhiyun /* This is needed to make i2c_w() work */
2268*4882a593Smuzhiyun reg_w(sd, R511_I2C_CTL, 0x05);
2269*4882a593Smuzhiyun
2270*4882a593Smuzhiyun return value;
2271*4882a593Smuzhiyun }
2272*4882a593Smuzhiyun
2273*4882a593Smuzhiyun /*
2274*4882a593Smuzhiyun * The OV518 I2C I/O procedure is different, hence, this function.
2275*4882a593Smuzhiyun * This is normally only called from i2c_w(). Note that this function
2276*4882a593Smuzhiyun * always succeeds regardless of whether the sensor is present and working.
2277*4882a593Smuzhiyun */
ov518_i2c_w(struct sd * sd,u8 reg,u8 value)2278*4882a593Smuzhiyun static void ov518_i2c_w(struct sd *sd,
2279*4882a593Smuzhiyun u8 reg,
2280*4882a593Smuzhiyun u8 value)
2281*4882a593Smuzhiyun {
2282*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
2283*4882a593Smuzhiyun
2284*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_USBO, "ov518_i2c_w %02x %02x\n", reg, value);
2285*4882a593Smuzhiyun
2286*4882a593Smuzhiyun /* Select camera register */
2287*4882a593Smuzhiyun reg_w(sd, R51x_I2C_SADDR_3, reg);
2288*4882a593Smuzhiyun
2289*4882a593Smuzhiyun /* Write "value" to I2C data port of OV511 */
2290*4882a593Smuzhiyun reg_w(sd, R51x_I2C_DATA, value);
2291*4882a593Smuzhiyun
2292*4882a593Smuzhiyun /* Initiate 3-byte write cycle */
2293*4882a593Smuzhiyun reg_w(sd, R518_I2C_CTL, 0x01);
2294*4882a593Smuzhiyun
2295*4882a593Smuzhiyun /* wait for write complete */
2296*4882a593Smuzhiyun msleep(4);
2297*4882a593Smuzhiyun reg_r8(sd, R518_I2C_CTL);
2298*4882a593Smuzhiyun }
2299*4882a593Smuzhiyun
2300*4882a593Smuzhiyun /*
2301*4882a593Smuzhiyun * returns: negative is error, pos or zero is data
2302*4882a593Smuzhiyun *
2303*4882a593Smuzhiyun * The OV518 I2C I/O procedure is different, hence, this function.
2304*4882a593Smuzhiyun * This is normally only called from i2c_r(). Note that this function
2305*4882a593Smuzhiyun * always succeeds regardless of whether the sensor is present and working.
2306*4882a593Smuzhiyun */
ov518_i2c_r(struct sd * sd,u8 reg)2307*4882a593Smuzhiyun static int ov518_i2c_r(struct sd *sd, u8 reg)
2308*4882a593Smuzhiyun {
2309*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
2310*4882a593Smuzhiyun int value;
2311*4882a593Smuzhiyun
2312*4882a593Smuzhiyun /* Select camera register */
2313*4882a593Smuzhiyun reg_w(sd, R51x_I2C_SADDR_2, reg);
2314*4882a593Smuzhiyun
2315*4882a593Smuzhiyun /* Initiate 2-byte write cycle */
2316*4882a593Smuzhiyun reg_w(sd, R518_I2C_CTL, 0x03);
2317*4882a593Smuzhiyun reg_r8(sd, R518_I2C_CTL);
2318*4882a593Smuzhiyun
2319*4882a593Smuzhiyun /* Initiate 2-byte read cycle */
2320*4882a593Smuzhiyun reg_w(sd, R518_I2C_CTL, 0x05);
2321*4882a593Smuzhiyun reg_r8(sd, R518_I2C_CTL);
2322*4882a593Smuzhiyun
2323*4882a593Smuzhiyun value = reg_r(sd, R51x_I2C_DATA);
2324*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_USBI, "ov518_i2c_r %02x %02x\n", reg, value);
2325*4882a593Smuzhiyun return value;
2326*4882a593Smuzhiyun }
2327*4882a593Smuzhiyun
ovfx2_i2c_w(struct sd * sd,u8 reg,u8 value)2328*4882a593Smuzhiyun static void ovfx2_i2c_w(struct sd *sd, u8 reg, u8 value)
2329*4882a593Smuzhiyun {
2330*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
2331*4882a593Smuzhiyun int ret;
2332*4882a593Smuzhiyun
2333*4882a593Smuzhiyun if (sd->gspca_dev.usb_err < 0)
2334*4882a593Smuzhiyun return;
2335*4882a593Smuzhiyun
2336*4882a593Smuzhiyun ret = usb_control_msg(sd->gspca_dev.dev,
2337*4882a593Smuzhiyun usb_sndctrlpipe(sd->gspca_dev.dev, 0),
2338*4882a593Smuzhiyun 0x02,
2339*4882a593Smuzhiyun USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
2340*4882a593Smuzhiyun (u16) value, (u16) reg, NULL, 0, 500);
2341*4882a593Smuzhiyun
2342*4882a593Smuzhiyun if (ret < 0) {
2343*4882a593Smuzhiyun gspca_err(gspca_dev, "ovfx2_i2c_w %02x failed %d\n", reg, ret);
2344*4882a593Smuzhiyun sd->gspca_dev.usb_err = ret;
2345*4882a593Smuzhiyun }
2346*4882a593Smuzhiyun
2347*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_USBO, "ovfx2_i2c_w %02x %02x\n", reg, value);
2348*4882a593Smuzhiyun }
2349*4882a593Smuzhiyun
ovfx2_i2c_r(struct sd * sd,u8 reg)2350*4882a593Smuzhiyun static int ovfx2_i2c_r(struct sd *sd, u8 reg)
2351*4882a593Smuzhiyun {
2352*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
2353*4882a593Smuzhiyun int ret;
2354*4882a593Smuzhiyun
2355*4882a593Smuzhiyun if (sd->gspca_dev.usb_err < 0)
2356*4882a593Smuzhiyun return -1;
2357*4882a593Smuzhiyun
2358*4882a593Smuzhiyun ret = usb_control_msg(sd->gspca_dev.dev,
2359*4882a593Smuzhiyun usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
2360*4882a593Smuzhiyun 0x03,
2361*4882a593Smuzhiyun USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
2362*4882a593Smuzhiyun 0, (u16) reg, sd->gspca_dev.usb_buf, 1, 500);
2363*4882a593Smuzhiyun
2364*4882a593Smuzhiyun if (ret >= 0) {
2365*4882a593Smuzhiyun ret = sd->gspca_dev.usb_buf[0];
2366*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_USBI, "ovfx2_i2c_r %02x %02x\n",
2367*4882a593Smuzhiyun reg, ret);
2368*4882a593Smuzhiyun } else {
2369*4882a593Smuzhiyun gspca_err(gspca_dev, "ovfx2_i2c_r %02x failed %d\n", reg, ret);
2370*4882a593Smuzhiyun sd->gspca_dev.usb_err = ret;
2371*4882a593Smuzhiyun }
2372*4882a593Smuzhiyun
2373*4882a593Smuzhiyun return ret;
2374*4882a593Smuzhiyun }
2375*4882a593Smuzhiyun
i2c_w(struct sd * sd,u8 reg,u8 value)2376*4882a593Smuzhiyun static void i2c_w(struct sd *sd, u8 reg, u8 value)
2377*4882a593Smuzhiyun {
2378*4882a593Smuzhiyun if (sd->sensor_reg_cache[reg] == value)
2379*4882a593Smuzhiyun return;
2380*4882a593Smuzhiyun
2381*4882a593Smuzhiyun switch (sd->bridge) {
2382*4882a593Smuzhiyun case BRIDGE_OV511:
2383*4882a593Smuzhiyun case BRIDGE_OV511PLUS:
2384*4882a593Smuzhiyun ov511_i2c_w(sd, reg, value);
2385*4882a593Smuzhiyun break;
2386*4882a593Smuzhiyun case BRIDGE_OV518:
2387*4882a593Smuzhiyun case BRIDGE_OV518PLUS:
2388*4882a593Smuzhiyun case BRIDGE_OV519:
2389*4882a593Smuzhiyun ov518_i2c_w(sd, reg, value);
2390*4882a593Smuzhiyun break;
2391*4882a593Smuzhiyun case BRIDGE_OVFX2:
2392*4882a593Smuzhiyun ovfx2_i2c_w(sd, reg, value);
2393*4882a593Smuzhiyun break;
2394*4882a593Smuzhiyun case BRIDGE_W9968CF:
2395*4882a593Smuzhiyun w9968cf_i2c_w(sd, reg, value);
2396*4882a593Smuzhiyun break;
2397*4882a593Smuzhiyun }
2398*4882a593Smuzhiyun
2399*4882a593Smuzhiyun if (sd->gspca_dev.usb_err >= 0) {
2400*4882a593Smuzhiyun /* Up on sensor reset empty the register cache */
2401*4882a593Smuzhiyun if (reg == 0x12 && (value & 0x80))
2402*4882a593Smuzhiyun memset(sd->sensor_reg_cache, -1,
2403*4882a593Smuzhiyun sizeof(sd->sensor_reg_cache));
2404*4882a593Smuzhiyun else
2405*4882a593Smuzhiyun sd->sensor_reg_cache[reg] = value;
2406*4882a593Smuzhiyun }
2407*4882a593Smuzhiyun }
2408*4882a593Smuzhiyun
i2c_r(struct sd * sd,u8 reg)2409*4882a593Smuzhiyun static int i2c_r(struct sd *sd, u8 reg)
2410*4882a593Smuzhiyun {
2411*4882a593Smuzhiyun int ret = -1;
2412*4882a593Smuzhiyun
2413*4882a593Smuzhiyun if (sd->sensor_reg_cache[reg] != -1)
2414*4882a593Smuzhiyun return sd->sensor_reg_cache[reg];
2415*4882a593Smuzhiyun
2416*4882a593Smuzhiyun switch (sd->bridge) {
2417*4882a593Smuzhiyun case BRIDGE_OV511:
2418*4882a593Smuzhiyun case BRIDGE_OV511PLUS:
2419*4882a593Smuzhiyun ret = ov511_i2c_r(sd, reg);
2420*4882a593Smuzhiyun break;
2421*4882a593Smuzhiyun case BRIDGE_OV518:
2422*4882a593Smuzhiyun case BRIDGE_OV518PLUS:
2423*4882a593Smuzhiyun case BRIDGE_OV519:
2424*4882a593Smuzhiyun ret = ov518_i2c_r(sd, reg);
2425*4882a593Smuzhiyun break;
2426*4882a593Smuzhiyun case BRIDGE_OVFX2:
2427*4882a593Smuzhiyun ret = ovfx2_i2c_r(sd, reg);
2428*4882a593Smuzhiyun break;
2429*4882a593Smuzhiyun case BRIDGE_W9968CF:
2430*4882a593Smuzhiyun ret = w9968cf_i2c_r(sd, reg);
2431*4882a593Smuzhiyun break;
2432*4882a593Smuzhiyun }
2433*4882a593Smuzhiyun
2434*4882a593Smuzhiyun if (ret >= 0)
2435*4882a593Smuzhiyun sd->sensor_reg_cache[reg] = ret;
2436*4882a593Smuzhiyun
2437*4882a593Smuzhiyun return ret;
2438*4882a593Smuzhiyun }
2439*4882a593Smuzhiyun
2440*4882a593Smuzhiyun /* Writes bits at positions specified by mask to an I2C reg. Bits that are in
2441*4882a593Smuzhiyun * the same position as 1's in "mask" are cleared and set to "value". Bits
2442*4882a593Smuzhiyun * that are in the same position as 0's in "mask" are preserved, regardless
2443*4882a593Smuzhiyun * of their respective state in "value".
2444*4882a593Smuzhiyun */
i2c_w_mask(struct sd * sd,u8 reg,u8 value,u8 mask)2445*4882a593Smuzhiyun static void i2c_w_mask(struct sd *sd,
2446*4882a593Smuzhiyun u8 reg,
2447*4882a593Smuzhiyun u8 value,
2448*4882a593Smuzhiyun u8 mask)
2449*4882a593Smuzhiyun {
2450*4882a593Smuzhiyun int rc;
2451*4882a593Smuzhiyun u8 oldval;
2452*4882a593Smuzhiyun
2453*4882a593Smuzhiyun value &= mask; /* Enforce mask on value */
2454*4882a593Smuzhiyun rc = i2c_r(sd, reg);
2455*4882a593Smuzhiyun if (rc < 0)
2456*4882a593Smuzhiyun return;
2457*4882a593Smuzhiyun oldval = rc & ~mask; /* Clear the masked bits */
2458*4882a593Smuzhiyun value |= oldval; /* Set the desired bits */
2459*4882a593Smuzhiyun i2c_w(sd, reg, value);
2460*4882a593Smuzhiyun }
2461*4882a593Smuzhiyun
2462*4882a593Smuzhiyun /* Temporarily stops OV511 from functioning. Must do this before changing
2463*4882a593Smuzhiyun * registers while the camera is streaming */
ov51x_stop(struct sd * sd)2464*4882a593Smuzhiyun static inline void ov51x_stop(struct sd *sd)
2465*4882a593Smuzhiyun {
2466*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
2467*4882a593Smuzhiyun
2468*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_STREAM, "stopping\n");
2469*4882a593Smuzhiyun sd->stopped = 1;
2470*4882a593Smuzhiyun switch (sd->bridge) {
2471*4882a593Smuzhiyun case BRIDGE_OV511:
2472*4882a593Smuzhiyun case BRIDGE_OV511PLUS:
2473*4882a593Smuzhiyun reg_w(sd, R51x_SYS_RESET, 0x3d);
2474*4882a593Smuzhiyun break;
2475*4882a593Smuzhiyun case BRIDGE_OV518:
2476*4882a593Smuzhiyun case BRIDGE_OV518PLUS:
2477*4882a593Smuzhiyun reg_w_mask(sd, R51x_SYS_RESET, 0x3a, 0x3a);
2478*4882a593Smuzhiyun break;
2479*4882a593Smuzhiyun case BRIDGE_OV519:
2480*4882a593Smuzhiyun reg_w(sd, OV519_R51_RESET1, 0x0f);
2481*4882a593Smuzhiyun reg_w(sd, OV519_R51_RESET1, 0x00);
2482*4882a593Smuzhiyun reg_w(sd, 0x22, 0x00); /* FRAR */
2483*4882a593Smuzhiyun break;
2484*4882a593Smuzhiyun case BRIDGE_OVFX2:
2485*4882a593Smuzhiyun reg_w_mask(sd, 0x0f, 0x00, 0x02);
2486*4882a593Smuzhiyun break;
2487*4882a593Smuzhiyun case BRIDGE_W9968CF:
2488*4882a593Smuzhiyun reg_w(sd, 0x3c, 0x0a05); /* stop USB transfer */
2489*4882a593Smuzhiyun break;
2490*4882a593Smuzhiyun }
2491*4882a593Smuzhiyun }
2492*4882a593Smuzhiyun
2493*4882a593Smuzhiyun /* Restarts OV511 after ov511_stop() is called. Has no effect if it is not
2494*4882a593Smuzhiyun * actually stopped (for performance). */
ov51x_restart(struct sd * sd)2495*4882a593Smuzhiyun static inline void ov51x_restart(struct sd *sd)
2496*4882a593Smuzhiyun {
2497*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
2498*4882a593Smuzhiyun
2499*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_STREAM, "restarting\n");
2500*4882a593Smuzhiyun if (!sd->stopped)
2501*4882a593Smuzhiyun return;
2502*4882a593Smuzhiyun sd->stopped = 0;
2503*4882a593Smuzhiyun
2504*4882a593Smuzhiyun /* Reinitialize the stream */
2505*4882a593Smuzhiyun switch (sd->bridge) {
2506*4882a593Smuzhiyun case BRIDGE_OV511:
2507*4882a593Smuzhiyun case BRIDGE_OV511PLUS:
2508*4882a593Smuzhiyun reg_w(sd, R51x_SYS_RESET, 0x00);
2509*4882a593Smuzhiyun break;
2510*4882a593Smuzhiyun case BRIDGE_OV518:
2511*4882a593Smuzhiyun case BRIDGE_OV518PLUS:
2512*4882a593Smuzhiyun reg_w(sd, 0x2f, 0x80);
2513*4882a593Smuzhiyun reg_w(sd, R51x_SYS_RESET, 0x00);
2514*4882a593Smuzhiyun break;
2515*4882a593Smuzhiyun case BRIDGE_OV519:
2516*4882a593Smuzhiyun reg_w(sd, OV519_R51_RESET1, 0x0f);
2517*4882a593Smuzhiyun reg_w(sd, OV519_R51_RESET1, 0x00);
2518*4882a593Smuzhiyun reg_w(sd, 0x22, 0x1d); /* FRAR */
2519*4882a593Smuzhiyun break;
2520*4882a593Smuzhiyun case BRIDGE_OVFX2:
2521*4882a593Smuzhiyun reg_w_mask(sd, 0x0f, 0x02, 0x02);
2522*4882a593Smuzhiyun break;
2523*4882a593Smuzhiyun case BRIDGE_W9968CF:
2524*4882a593Smuzhiyun reg_w(sd, 0x3c, 0x8a05); /* USB FIFO enable */
2525*4882a593Smuzhiyun break;
2526*4882a593Smuzhiyun }
2527*4882a593Smuzhiyun }
2528*4882a593Smuzhiyun
2529*4882a593Smuzhiyun static void ov51x_set_slave_ids(struct sd *sd, u8 slave);
2530*4882a593Smuzhiyun
2531*4882a593Smuzhiyun /* This does an initial reset of an OmniVision sensor and ensures that I2C
2532*4882a593Smuzhiyun * is synchronized. Returns <0 on failure.
2533*4882a593Smuzhiyun */
init_ov_sensor(struct sd * sd,u8 slave)2534*4882a593Smuzhiyun static int init_ov_sensor(struct sd *sd, u8 slave)
2535*4882a593Smuzhiyun {
2536*4882a593Smuzhiyun int i;
2537*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
2538*4882a593Smuzhiyun
2539*4882a593Smuzhiyun ov51x_set_slave_ids(sd, slave);
2540*4882a593Smuzhiyun
2541*4882a593Smuzhiyun /* Reset the sensor */
2542*4882a593Smuzhiyun i2c_w(sd, 0x12, 0x80);
2543*4882a593Smuzhiyun
2544*4882a593Smuzhiyun /* Wait for it to initialize */
2545*4882a593Smuzhiyun msleep(150);
2546*4882a593Smuzhiyun
2547*4882a593Smuzhiyun for (i = 0; i < i2c_detect_tries; i++) {
2548*4882a593Smuzhiyun if (i2c_r(sd, OV7610_REG_ID_HIGH) == 0x7f &&
2549*4882a593Smuzhiyun i2c_r(sd, OV7610_REG_ID_LOW) == 0xa2) {
2550*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "I2C synced in %d attempt(s)\n",
2551*4882a593Smuzhiyun i);
2552*4882a593Smuzhiyun return 0;
2553*4882a593Smuzhiyun }
2554*4882a593Smuzhiyun
2555*4882a593Smuzhiyun /* Reset the sensor */
2556*4882a593Smuzhiyun i2c_w(sd, 0x12, 0x80);
2557*4882a593Smuzhiyun
2558*4882a593Smuzhiyun /* Wait for it to initialize */
2559*4882a593Smuzhiyun msleep(150);
2560*4882a593Smuzhiyun
2561*4882a593Smuzhiyun /* Dummy read to sync I2C */
2562*4882a593Smuzhiyun if (i2c_r(sd, 0x00) < 0)
2563*4882a593Smuzhiyun return -1;
2564*4882a593Smuzhiyun }
2565*4882a593Smuzhiyun return -1;
2566*4882a593Smuzhiyun }
2567*4882a593Smuzhiyun
2568*4882a593Smuzhiyun /* Set the read and write slave IDs. The "slave" argument is the write slave,
2569*4882a593Smuzhiyun * and the read slave will be set to (slave + 1).
2570*4882a593Smuzhiyun * This should not be called from outside the i2c I/O functions.
2571*4882a593Smuzhiyun * Sets I2C read and write slave IDs. Returns <0 for error
2572*4882a593Smuzhiyun */
ov51x_set_slave_ids(struct sd * sd,u8 slave)2573*4882a593Smuzhiyun static void ov51x_set_slave_ids(struct sd *sd,
2574*4882a593Smuzhiyun u8 slave)
2575*4882a593Smuzhiyun {
2576*4882a593Smuzhiyun switch (sd->bridge) {
2577*4882a593Smuzhiyun case BRIDGE_OVFX2:
2578*4882a593Smuzhiyun reg_w(sd, OVFX2_I2C_ADDR, slave);
2579*4882a593Smuzhiyun return;
2580*4882a593Smuzhiyun case BRIDGE_W9968CF:
2581*4882a593Smuzhiyun sd->sensor_addr = slave;
2582*4882a593Smuzhiyun return;
2583*4882a593Smuzhiyun }
2584*4882a593Smuzhiyun
2585*4882a593Smuzhiyun reg_w(sd, R51x_I2C_W_SID, slave);
2586*4882a593Smuzhiyun reg_w(sd, R51x_I2C_R_SID, slave + 1);
2587*4882a593Smuzhiyun }
2588*4882a593Smuzhiyun
write_regvals(struct sd * sd,const struct ov_regvals * regvals,int n)2589*4882a593Smuzhiyun static void write_regvals(struct sd *sd,
2590*4882a593Smuzhiyun const struct ov_regvals *regvals,
2591*4882a593Smuzhiyun int n)
2592*4882a593Smuzhiyun {
2593*4882a593Smuzhiyun while (--n >= 0) {
2594*4882a593Smuzhiyun reg_w(sd, regvals->reg, regvals->val);
2595*4882a593Smuzhiyun regvals++;
2596*4882a593Smuzhiyun }
2597*4882a593Smuzhiyun }
2598*4882a593Smuzhiyun
write_i2c_regvals(struct sd * sd,const struct ov_i2c_regvals * regvals,int n)2599*4882a593Smuzhiyun static void write_i2c_regvals(struct sd *sd,
2600*4882a593Smuzhiyun const struct ov_i2c_regvals *regvals,
2601*4882a593Smuzhiyun int n)
2602*4882a593Smuzhiyun {
2603*4882a593Smuzhiyun while (--n >= 0) {
2604*4882a593Smuzhiyun i2c_w(sd, regvals->reg, regvals->val);
2605*4882a593Smuzhiyun regvals++;
2606*4882a593Smuzhiyun }
2607*4882a593Smuzhiyun }
2608*4882a593Smuzhiyun
2609*4882a593Smuzhiyun /****************************************************************************
2610*4882a593Smuzhiyun *
2611*4882a593Smuzhiyun * OV511 and sensor configuration
2612*4882a593Smuzhiyun *
2613*4882a593Smuzhiyun ***************************************************************************/
2614*4882a593Smuzhiyun
2615*4882a593Smuzhiyun /* This initializes the OV2x10 / OV3610 / OV3620 / OV9600 */
ov_hires_configure(struct sd * sd)2616*4882a593Smuzhiyun static void ov_hires_configure(struct sd *sd)
2617*4882a593Smuzhiyun {
2618*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
2619*4882a593Smuzhiyun int high, low;
2620*4882a593Smuzhiyun
2621*4882a593Smuzhiyun if (sd->bridge != BRIDGE_OVFX2) {
2622*4882a593Smuzhiyun gspca_err(gspca_dev, "error hires sensors only supported with ovfx2\n");
2623*4882a593Smuzhiyun return;
2624*4882a593Smuzhiyun }
2625*4882a593Smuzhiyun
2626*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "starting ov hires configuration\n");
2627*4882a593Smuzhiyun
2628*4882a593Smuzhiyun /* Detect sensor (sub)type */
2629*4882a593Smuzhiyun high = i2c_r(sd, 0x0a);
2630*4882a593Smuzhiyun low = i2c_r(sd, 0x0b);
2631*4882a593Smuzhiyun /* info("%x, %x", high, low); */
2632*4882a593Smuzhiyun switch (high) {
2633*4882a593Smuzhiyun case 0x96:
2634*4882a593Smuzhiyun switch (low) {
2635*4882a593Smuzhiyun case 0x40:
2636*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Sensor is a OV2610\n");
2637*4882a593Smuzhiyun sd->sensor = SEN_OV2610;
2638*4882a593Smuzhiyun return;
2639*4882a593Smuzhiyun case 0x41:
2640*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Sensor is a OV2610AE\n");
2641*4882a593Smuzhiyun sd->sensor = SEN_OV2610AE;
2642*4882a593Smuzhiyun return;
2643*4882a593Smuzhiyun case 0xb1:
2644*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Sensor is a OV9600\n");
2645*4882a593Smuzhiyun sd->sensor = SEN_OV9600;
2646*4882a593Smuzhiyun return;
2647*4882a593Smuzhiyun }
2648*4882a593Smuzhiyun break;
2649*4882a593Smuzhiyun case 0x36:
2650*4882a593Smuzhiyun if ((low & 0x0f) == 0x00) {
2651*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Sensor is a OV3610\n");
2652*4882a593Smuzhiyun sd->sensor = SEN_OV3610;
2653*4882a593Smuzhiyun return;
2654*4882a593Smuzhiyun }
2655*4882a593Smuzhiyun break;
2656*4882a593Smuzhiyun }
2657*4882a593Smuzhiyun gspca_err(gspca_dev, "Error unknown sensor type: %02x%02x\n",
2658*4882a593Smuzhiyun high, low);
2659*4882a593Smuzhiyun }
2660*4882a593Smuzhiyun
2661*4882a593Smuzhiyun /* This initializes the OV8110, OV8610 sensor. The OV8110 uses
2662*4882a593Smuzhiyun * the same register settings as the OV8610, since they are very similar.
2663*4882a593Smuzhiyun */
ov8xx0_configure(struct sd * sd)2664*4882a593Smuzhiyun static void ov8xx0_configure(struct sd *sd)
2665*4882a593Smuzhiyun {
2666*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
2667*4882a593Smuzhiyun int rc;
2668*4882a593Smuzhiyun
2669*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "starting ov8xx0 configuration\n");
2670*4882a593Smuzhiyun
2671*4882a593Smuzhiyun /* Detect sensor (sub)type */
2672*4882a593Smuzhiyun rc = i2c_r(sd, OV7610_REG_COM_I);
2673*4882a593Smuzhiyun if (rc < 0) {
2674*4882a593Smuzhiyun gspca_err(gspca_dev, "Error detecting sensor type\n");
2675*4882a593Smuzhiyun return;
2676*4882a593Smuzhiyun }
2677*4882a593Smuzhiyun if ((rc & 3) == 1)
2678*4882a593Smuzhiyun sd->sensor = SEN_OV8610;
2679*4882a593Smuzhiyun else
2680*4882a593Smuzhiyun gspca_err(gspca_dev, "Unknown image sensor version: %d\n",
2681*4882a593Smuzhiyun rc & 3);
2682*4882a593Smuzhiyun }
2683*4882a593Smuzhiyun
2684*4882a593Smuzhiyun /* This initializes the OV7610, OV7620, or OV76BE sensor. The OV76BE uses
2685*4882a593Smuzhiyun * the same register settings as the OV7610, since they are very similar.
2686*4882a593Smuzhiyun */
ov7xx0_configure(struct sd * sd)2687*4882a593Smuzhiyun static void ov7xx0_configure(struct sd *sd)
2688*4882a593Smuzhiyun {
2689*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
2690*4882a593Smuzhiyun int rc, high, low;
2691*4882a593Smuzhiyun
2692*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "starting OV7xx0 configuration\n");
2693*4882a593Smuzhiyun
2694*4882a593Smuzhiyun /* Detect sensor (sub)type */
2695*4882a593Smuzhiyun rc = i2c_r(sd, OV7610_REG_COM_I);
2696*4882a593Smuzhiyun
2697*4882a593Smuzhiyun /* add OV7670 here
2698*4882a593Smuzhiyun * it appears to be wrongly detected as a 7610 by default */
2699*4882a593Smuzhiyun if (rc < 0) {
2700*4882a593Smuzhiyun gspca_err(gspca_dev, "Error detecting sensor type\n");
2701*4882a593Smuzhiyun return;
2702*4882a593Smuzhiyun }
2703*4882a593Smuzhiyun if ((rc & 3) == 3) {
2704*4882a593Smuzhiyun /* quick hack to make OV7670s work */
2705*4882a593Smuzhiyun high = i2c_r(sd, 0x0a);
2706*4882a593Smuzhiyun low = i2c_r(sd, 0x0b);
2707*4882a593Smuzhiyun /* info("%x, %x", high, low); */
2708*4882a593Smuzhiyun if (high == 0x76 && (low & 0xf0) == 0x70) {
2709*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV76%02x\n",
2710*4882a593Smuzhiyun low);
2711*4882a593Smuzhiyun sd->sensor = SEN_OV7670;
2712*4882a593Smuzhiyun } else {
2713*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV7610\n");
2714*4882a593Smuzhiyun sd->sensor = SEN_OV7610;
2715*4882a593Smuzhiyun }
2716*4882a593Smuzhiyun } else if ((rc & 3) == 1) {
2717*4882a593Smuzhiyun /* I don't know what's different about the 76BE yet. */
2718*4882a593Smuzhiyun if (i2c_r(sd, 0x15) & 1) {
2719*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV7620AE\n");
2720*4882a593Smuzhiyun sd->sensor = SEN_OV7620AE;
2721*4882a593Smuzhiyun } else {
2722*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV76BE\n");
2723*4882a593Smuzhiyun sd->sensor = SEN_OV76BE;
2724*4882a593Smuzhiyun }
2725*4882a593Smuzhiyun } else if ((rc & 3) == 0) {
2726*4882a593Smuzhiyun /* try to read product id registers */
2727*4882a593Smuzhiyun high = i2c_r(sd, 0x0a);
2728*4882a593Smuzhiyun if (high < 0) {
2729*4882a593Smuzhiyun gspca_err(gspca_dev, "Error detecting camera chip PID\n");
2730*4882a593Smuzhiyun return;
2731*4882a593Smuzhiyun }
2732*4882a593Smuzhiyun low = i2c_r(sd, 0x0b);
2733*4882a593Smuzhiyun if (low < 0) {
2734*4882a593Smuzhiyun gspca_err(gspca_dev, "Error detecting camera chip VER\n");
2735*4882a593Smuzhiyun return;
2736*4882a593Smuzhiyun }
2737*4882a593Smuzhiyun if (high == 0x76) {
2738*4882a593Smuzhiyun switch (low) {
2739*4882a593Smuzhiyun case 0x30:
2740*4882a593Smuzhiyun gspca_err(gspca_dev, "Sensor is an OV7630/OV7635\n");
2741*4882a593Smuzhiyun gspca_err(gspca_dev, "7630 is not supported by this driver\n");
2742*4882a593Smuzhiyun return;
2743*4882a593Smuzhiyun case 0x40:
2744*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV7645\n");
2745*4882a593Smuzhiyun sd->sensor = SEN_OV7640; /* FIXME */
2746*4882a593Smuzhiyun break;
2747*4882a593Smuzhiyun case 0x45:
2748*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV7645B\n");
2749*4882a593Smuzhiyun sd->sensor = SEN_OV7640; /* FIXME */
2750*4882a593Smuzhiyun break;
2751*4882a593Smuzhiyun case 0x48:
2752*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV7648\n");
2753*4882a593Smuzhiyun sd->sensor = SEN_OV7648;
2754*4882a593Smuzhiyun break;
2755*4882a593Smuzhiyun case 0x60:
2756*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Sensor is a OV7660\n");
2757*4882a593Smuzhiyun sd->sensor = SEN_OV7660;
2758*4882a593Smuzhiyun break;
2759*4882a593Smuzhiyun default:
2760*4882a593Smuzhiyun gspca_err(gspca_dev, "Unknown sensor: 0x76%02x\n",
2761*4882a593Smuzhiyun low);
2762*4882a593Smuzhiyun return;
2763*4882a593Smuzhiyun }
2764*4882a593Smuzhiyun } else {
2765*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV7620\n");
2766*4882a593Smuzhiyun sd->sensor = SEN_OV7620;
2767*4882a593Smuzhiyun }
2768*4882a593Smuzhiyun } else {
2769*4882a593Smuzhiyun gspca_err(gspca_dev, "Unknown image sensor version: %d\n",
2770*4882a593Smuzhiyun rc & 3);
2771*4882a593Smuzhiyun }
2772*4882a593Smuzhiyun }
2773*4882a593Smuzhiyun
2774*4882a593Smuzhiyun /* This initializes the OV6620, OV6630, OV6630AE, or OV6630AF sensor. */
ov6xx0_configure(struct sd * sd)2775*4882a593Smuzhiyun static void ov6xx0_configure(struct sd *sd)
2776*4882a593Smuzhiyun {
2777*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
2778*4882a593Smuzhiyun int rc;
2779*4882a593Smuzhiyun
2780*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "starting OV6xx0 configuration\n");
2781*4882a593Smuzhiyun
2782*4882a593Smuzhiyun /* Detect sensor (sub)type */
2783*4882a593Smuzhiyun rc = i2c_r(sd, OV7610_REG_COM_I);
2784*4882a593Smuzhiyun if (rc < 0) {
2785*4882a593Smuzhiyun gspca_err(gspca_dev, "Error detecting sensor type\n");
2786*4882a593Smuzhiyun return;
2787*4882a593Smuzhiyun }
2788*4882a593Smuzhiyun
2789*4882a593Smuzhiyun /* Ugh. The first two bits are the version bits, but
2790*4882a593Smuzhiyun * the entire register value must be used. I guess OVT
2791*4882a593Smuzhiyun * underestimated how many variants they would make. */
2792*4882a593Smuzhiyun switch (rc) {
2793*4882a593Smuzhiyun case 0x00:
2794*4882a593Smuzhiyun sd->sensor = SEN_OV6630;
2795*4882a593Smuzhiyun pr_warn("WARNING: Sensor is an OV66308. Your camera may have been misdetected in previous driver versions.\n");
2796*4882a593Smuzhiyun break;
2797*4882a593Smuzhiyun case 0x01:
2798*4882a593Smuzhiyun sd->sensor = SEN_OV6620;
2799*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV6620\n");
2800*4882a593Smuzhiyun break;
2801*4882a593Smuzhiyun case 0x02:
2802*4882a593Smuzhiyun sd->sensor = SEN_OV6630;
2803*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV66308AE\n");
2804*4882a593Smuzhiyun break;
2805*4882a593Smuzhiyun case 0x03:
2806*4882a593Smuzhiyun sd->sensor = SEN_OV66308AF;
2807*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV66308AF\n");
2808*4882a593Smuzhiyun break;
2809*4882a593Smuzhiyun case 0x90:
2810*4882a593Smuzhiyun sd->sensor = SEN_OV6630;
2811*4882a593Smuzhiyun pr_warn("WARNING: Sensor is an OV66307. Your camera may have been misdetected in previous driver versions.\n");
2812*4882a593Smuzhiyun break;
2813*4882a593Smuzhiyun default:
2814*4882a593Smuzhiyun gspca_err(gspca_dev, "FATAL: Unknown sensor version: 0x%02x\n",
2815*4882a593Smuzhiyun rc);
2816*4882a593Smuzhiyun return;
2817*4882a593Smuzhiyun }
2818*4882a593Smuzhiyun
2819*4882a593Smuzhiyun /* Set sensor-specific vars */
2820*4882a593Smuzhiyun sd->sif = 1;
2821*4882a593Smuzhiyun }
2822*4882a593Smuzhiyun
2823*4882a593Smuzhiyun /* Turns on or off the LED. Only has an effect with OV511+/OV518(+)/OV519 */
ov51x_led_control(struct sd * sd,int on)2824*4882a593Smuzhiyun static void ov51x_led_control(struct sd *sd, int on)
2825*4882a593Smuzhiyun {
2826*4882a593Smuzhiyun if (sd->invert_led)
2827*4882a593Smuzhiyun on = !on;
2828*4882a593Smuzhiyun
2829*4882a593Smuzhiyun switch (sd->bridge) {
2830*4882a593Smuzhiyun /* OV511 has no LED control */
2831*4882a593Smuzhiyun case BRIDGE_OV511PLUS:
2832*4882a593Smuzhiyun reg_w(sd, R511_SYS_LED_CTL, on);
2833*4882a593Smuzhiyun break;
2834*4882a593Smuzhiyun case BRIDGE_OV518:
2835*4882a593Smuzhiyun case BRIDGE_OV518PLUS:
2836*4882a593Smuzhiyun reg_w_mask(sd, R518_GPIO_OUT, 0x02 * on, 0x02);
2837*4882a593Smuzhiyun break;
2838*4882a593Smuzhiyun case BRIDGE_OV519:
2839*4882a593Smuzhiyun reg_w_mask(sd, OV519_GPIO_DATA_OUT0, on, 1);
2840*4882a593Smuzhiyun break;
2841*4882a593Smuzhiyun }
2842*4882a593Smuzhiyun }
2843*4882a593Smuzhiyun
sd_reset_snapshot(struct gspca_dev * gspca_dev)2844*4882a593Smuzhiyun static void sd_reset_snapshot(struct gspca_dev *gspca_dev)
2845*4882a593Smuzhiyun {
2846*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
2847*4882a593Smuzhiyun
2848*4882a593Smuzhiyun if (!sd->snapshot_needs_reset)
2849*4882a593Smuzhiyun return;
2850*4882a593Smuzhiyun
2851*4882a593Smuzhiyun /* Note it is important that we clear sd->snapshot_needs_reset,
2852*4882a593Smuzhiyun before actually clearing the snapshot state in the bridge
2853*4882a593Smuzhiyun otherwise we might race with the pkt_scan interrupt handler */
2854*4882a593Smuzhiyun sd->snapshot_needs_reset = 0;
2855*4882a593Smuzhiyun
2856*4882a593Smuzhiyun switch (sd->bridge) {
2857*4882a593Smuzhiyun case BRIDGE_OV511:
2858*4882a593Smuzhiyun case BRIDGE_OV511PLUS:
2859*4882a593Smuzhiyun reg_w(sd, R51x_SYS_SNAP, 0x02);
2860*4882a593Smuzhiyun reg_w(sd, R51x_SYS_SNAP, 0x00);
2861*4882a593Smuzhiyun break;
2862*4882a593Smuzhiyun case BRIDGE_OV518:
2863*4882a593Smuzhiyun case BRIDGE_OV518PLUS:
2864*4882a593Smuzhiyun reg_w(sd, R51x_SYS_SNAP, 0x02); /* Reset */
2865*4882a593Smuzhiyun reg_w(sd, R51x_SYS_SNAP, 0x01); /* Enable */
2866*4882a593Smuzhiyun break;
2867*4882a593Smuzhiyun case BRIDGE_OV519:
2868*4882a593Smuzhiyun reg_w(sd, R51x_SYS_RESET, 0x40);
2869*4882a593Smuzhiyun reg_w(sd, R51x_SYS_RESET, 0x00);
2870*4882a593Smuzhiyun break;
2871*4882a593Smuzhiyun }
2872*4882a593Smuzhiyun }
2873*4882a593Smuzhiyun
ov51x_upload_quan_tables(struct sd * sd)2874*4882a593Smuzhiyun static void ov51x_upload_quan_tables(struct sd *sd)
2875*4882a593Smuzhiyun {
2876*4882a593Smuzhiyun static const unsigned char yQuanTable511[] = {
2877*4882a593Smuzhiyun 0, 1, 1, 2, 2, 3, 3, 4,
2878*4882a593Smuzhiyun 1, 1, 1, 2, 2, 3, 4, 4,
2879*4882a593Smuzhiyun 1, 1, 2, 2, 3, 4, 4, 4,
2880*4882a593Smuzhiyun 2, 2, 2, 3, 4, 4, 4, 4,
2881*4882a593Smuzhiyun 2, 2, 3, 4, 4, 5, 5, 5,
2882*4882a593Smuzhiyun 3, 3, 4, 4, 5, 5, 5, 5,
2883*4882a593Smuzhiyun 3, 4, 4, 4, 5, 5, 5, 5,
2884*4882a593Smuzhiyun 4, 4, 4, 4, 5, 5, 5, 5
2885*4882a593Smuzhiyun };
2886*4882a593Smuzhiyun
2887*4882a593Smuzhiyun static const unsigned char uvQuanTable511[] = {
2888*4882a593Smuzhiyun 0, 2, 2, 3, 4, 4, 4, 4,
2889*4882a593Smuzhiyun 2, 2, 2, 4, 4, 4, 4, 4,
2890*4882a593Smuzhiyun 2, 2, 3, 4, 4, 4, 4, 4,
2891*4882a593Smuzhiyun 3, 4, 4, 4, 4, 4, 4, 4,
2892*4882a593Smuzhiyun 4, 4, 4, 4, 4, 4, 4, 4,
2893*4882a593Smuzhiyun 4, 4, 4, 4, 4, 4, 4, 4,
2894*4882a593Smuzhiyun 4, 4, 4, 4, 4, 4, 4, 4,
2895*4882a593Smuzhiyun 4, 4, 4, 4, 4, 4, 4, 4
2896*4882a593Smuzhiyun };
2897*4882a593Smuzhiyun
2898*4882a593Smuzhiyun /* OV518 quantization tables are 8x4 (instead of 8x8) */
2899*4882a593Smuzhiyun static const unsigned char yQuanTable518[] = {
2900*4882a593Smuzhiyun 5, 4, 5, 6, 6, 7, 7, 7,
2901*4882a593Smuzhiyun 5, 5, 5, 5, 6, 7, 7, 7,
2902*4882a593Smuzhiyun 6, 6, 6, 6, 7, 7, 7, 8,
2903*4882a593Smuzhiyun 7, 7, 6, 7, 7, 7, 8, 8
2904*4882a593Smuzhiyun };
2905*4882a593Smuzhiyun static const unsigned char uvQuanTable518[] = {
2906*4882a593Smuzhiyun 6, 6, 6, 7, 7, 7, 7, 7,
2907*4882a593Smuzhiyun 6, 6, 6, 7, 7, 7, 7, 7,
2908*4882a593Smuzhiyun 6, 6, 6, 7, 7, 7, 7, 8,
2909*4882a593Smuzhiyun 7, 7, 7, 7, 7, 7, 8, 8
2910*4882a593Smuzhiyun };
2911*4882a593Smuzhiyun
2912*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
2913*4882a593Smuzhiyun const unsigned char *pYTable, *pUVTable;
2914*4882a593Smuzhiyun unsigned char val0, val1;
2915*4882a593Smuzhiyun int i, size, reg = R51x_COMP_LUT_BEGIN;
2916*4882a593Smuzhiyun
2917*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Uploading quantization tables\n");
2918*4882a593Smuzhiyun
2919*4882a593Smuzhiyun if (sd->bridge == BRIDGE_OV511 || sd->bridge == BRIDGE_OV511PLUS) {
2920*4882a593Smuzhiyun pYTable = yQuanTable511;
2921*4882a593Smuzhiyun pUVTable = uvQuanTable511;
2922*4882a593Smuzhiyun size = 32;
2923*4882a593Smuzhiyun } else {
2924*4882a593Smuzhiyun pYTable = yQuanTable518;
2925*4882a593Smuzhiyun pUVTable = uvQuanTable518;
2926*4882a593Smuzhiyun size = 16;
2927*4882a593Smuzhiyun }
2928*4882a593Smuzhiyun
2929*4882a593Smuzhiyun for (i = 0; i < size; i++) {
2930*4882a593Smuzhiyun val0 = *pYTable++;
2931*4882a593Smuzhiyun val1 = *pYTable++;
2932*4882a593Smuzhiyun val0 &= 0x0f;
2933*4882a593Smuzhiyun val1 &= 0x0f;
2934*4882a593Smuzhiyun val0 |= val1 << 4;
2935*4882a593Smuzhiyun reg_w(sd, reg, val0);
2936*4882a593Smuzhiyun
2937*4882a593Smuzhiyun val0 = *pUVTable++;
2938*4882a593Smuzhiyun val1 = *pUVTable++;
2939*4882a593Smuzhiyun val0 &= 0x0f;
2940*4882a593Smuzhiyun val1 &= 0x0f;
2941*4882a593Smuzhiyun val0 |= val1 << 4;
2942*4882a593Smuzhiyun reg_w(sd, reg + size, val0);
2943*4882a593Smuzhiyun
2944*4882a593Smuzhiyun reg++;
2945*4882a593Smuzhiyun }
2946*4882a593Smuzhiyun }
2947*4882a593Smuzhiyun
2948*4882a593Smuzhiyun /* This initializes the OV511/OV511+ and the sensor */
ov511_configure(struct gspca_dev * gspca_dev)2949*4882a593Smuzhiyun static void ov511_configure(struct gspca_dev *gspca_dev)
2950*4882a593Smuzhiyun {
2951*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
2952*4882a593Smuzhiyun
2953*4882a593Smuzhiyun /* For 511 and 511+ */
2954*4882a593Smuzhiyun static const struct ov_regvals init_511[] = {
2955*4882a593Smuzhiyun { R51x_SYS_RESET, 0x7f },
2956*4882a593Smuzhiyun { R51x_SYS_INIT, 0x01 },
2957*4882a593Smuzhiyun { R51x_SYS_RESET, 0x7f },
2958*4882a593Smuzhiyun { R51x_SYS_INIT, 0x01 },
2959*4882a593Smuzhiyun { R51x_SYS_RESET, 0x3f },
2960*4882a593Smuzhiyun { R51x_SYS_INIT, 0x01 },
2961*4882a593Smuzhiyun { R51x_SYS_RESET, 0x3d },
2962*4882a593Smuzhiyun };
2963*4882a593Smuzhiyun
2964*4882a593Smuzhiyun static const struct ov_regvals norm_511[] = {
2965*4882a593Smuzhiyun { R511_DRAM_FLOW_CTL, 0x01 },
2966*4882a593Smuzhiyun { R51x_SYS_SNAP, 0x00 },
2967*4882a593Smuzhiyun { R51x_SYS_SNAP, 0x02 },
2968*4882a593Smuzhiyun { R51x_SYS_SNAP, 0x00 },
2969*4882a593Smuzhiyun { R511_FIFO_OPTS, 0x1f },
2970*4882a593Smuzhiyun { R511_COMP_EN, 0x00 },
2971*4882a593Smuzhiyun { R511_COMP_LUT_EN, 0x03 },
2972*4882a593Smuzhiyun };
2973*4882a593Smuzhiyun
2974*4882a593Smuzhiyun static const struct ov_regvals norm_511_p[] = {
2975*4882a593Smuzhiyun { R511_DRAM_FLOW_CTL, 0xff },
2976*4882a593Smuzhiyun { R51x_SYS_SNAP, 0x00 },
2977*4882a593Smuzhiyun { R51x_SYS_SNAP, 0x02 },
2978*4882a593Smuzhiyun { R51x_SYS_SNAP, 0x00 },
2979*4882a593Smuzhiyun { R511_FIFO_OPTS, 0xff },
2980*4882a593Smuzhiyun { R511_COMP_EN, 0x00 },
2981*4882a593Smuzhiyun { R511_COMP_LUT_EN, 0x03 },
2982*4882a593Smuzhiyun };
2983*4882a593Smuzhiyun
2984*4882a593Smuzhiyun static const struct ov_regvals compress_511[] = {
2985*4882a593Smuzhiyun { 0x70, 0x1f },
2986*4882a593Smuzhiyun { 0x71, 0x05 },
2987*4882a593Smuzhiyun { 0x72, 0x06 },
2988*4882a593Smuzhiyun { 0x73, 0x06 },
2989*4882a593Smuzhiyun { 0x74, 0x14 },
2990*4882a593Smuzhiyun { 0x75, 0x03 },
2991*4882a593Smuzhiyun { 0x76, 0x04 },
2992*4882a593Smuzhiyun { 0x77, 0x04 },
2993*4882a593Smuzhiyun };
2994*4882a593Smuzhiyun
2995*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Device custom id %x\n",
2996*4882a593Smuzhiyun reg_r(sd, R51x_SYS_CUST_ID));
2997*4882a593Smuzhiyun
2998*4882a593Smuzhiyun write_regvals(sd, init_511, ARRAY_SIZE(init_511));
2999*4882a593Smuzhiyun
3000*4882a593Smuzhiyun switch (sd->bridge) {
3001*4882a593Smuzhiyun case BRIDGE_OV511:
3002*4882a593Smuzhiyun write_regvals(sd, norm_511, ARRAY_SIZE(norm_511));
3003*4882a593Smuzhiyun break;
3004*4882a593Smuzhiyun case BRIDGE_OV511PLUS:
3005*4882a593Smuzhiyun write_regvals(sd, norm_511_p, ARRAY_SIZE(norm_511_p));
3006*4882a593Smuzhiyun break;
3007*4882a593Smuzhiyun }
3008*4882a593Smuzhiyun
3009*4882a593Smuzhiyun /* Init compression */
3010*4882a593Smuzhiyun write_regvals(sd, compress_511, ARRAY_SIZE(compress_511));
3011*4882a593Smuzhiyun
3012*4882a593Smuzhiyun ov51x_upload_quan_tables(sd);
3013*4882a593Smuzhiyun }
3014*4882a593Smuzhiyun
3015*4882a593Smuzhiyun /* This initializes the OV518/OV518+ and the sensor */
ov518_configure(struct gspca_dev * gspca_dev)3016*4882a593Smuzhiyun static void ov518_configure(struct gspca_dev *gspca_dev)
3017*4882a593Smuzhiyun {
3018*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
3019*4882a593Smuzhiyun
3020*4882a593Smuzhiyun /* For 518 and 518+ */
3021*4882a593Smuzhiyun static const struct ov_regvals init_518[] = {
3022*4882a593Smuzhiyun { R51x_SYS_RESET, 0x40 },
3023*4882a593Smuzhiyun { R51x_SYS_INIT, 0xe1 },
3024*4882a593Smuzhiyun { R51x_SYS_RESET, 0x3e },
3025*4882a593Smuzhiyun { R51x_SYS_INIT, 0xe1 },
3026*4882a593Smuzhiyun { R51x_SYS_RESET, 0x00 },
3027*4882a593Smuzhiyun { R51x_SYS_INIT, 0xe1 },
3028*4882a593Smuzhiyun { 0x46, 0x00 },
3029*4882a593Smuzhiyun { 0x5d, 0x03 },
3030*4882a593Smuzhiyun };
3031*4882a593Smuzhiyun
3032*4882a593Smuzhiyun static const struct ov_regvals norm_518[] = {
3033*4882a593Smuzhiyun { R51x_SYS_SNAP, 0x02 }, /* Reset */
3034*4882a593Smuzhiyun { R51x_SYS_SNAP, 0x01 }, /* Enable */
3035*4882a593Smuzhiyun { 0x31, 0x0f },
3036*4882a593Smuzhiyun { 0x5d, 0x03 },
3037*4882a593Smuzhiyun { 0x24, 0x9f },
3038*4882a593Smuzhiyun { 0x25, 0x90 },
3039*4882a593Smuzhiyun { 0x20, 0x00 },
3040*4882a593Smuzhiyun { 0x51, 0x04 },
3041*4882a593Smuzhiyun { 0x71, 0x19 },
3042*4882a593Smuzhiyun { 0x2f, 0x80 },
3043*4882a593Smuzhiyun };
3044*4882a593Smuzhiyun
3045*4882a593Smuzhiyun static const struct ov_regvals norm_518_p[] = {
3046*4882a593Smuzhiyun { R51x_SYS_SNAP, 0x02 }, /* Reset */
3047*4882a593Smuzhiyun { R51x_SYS_SNAP, 0x01 }, /* Enable */
3048*4882a593Smuzhiyun { 0x31, 0x0f },
3049*4882a593Smuzhiyun { 0x5d, 0x03 },
3050*4882a593Smuzhiyun { 0x24, 0x9f },
3051*4882a593Smuzhiyun { 0x25, 0x90 },
3052*4882a593Smuzhiyun { 0x20, 0x60 },
3053*4882a593Smuzhiyun { 0x51, 0x02 },
3054*4882a593Smuzhiyun { 0x71, 0x19 },
3055*4882a593Smuzhiyun { 0x40, 0xff },
3056*4882a593Smuzhiyun { 0x41, 0x42 },
3057*4882a593Smuzhiyun { 0x46, 0x00 },
3058*4882a593Smuzhiyun { 0x33, 0x04 },
3059*4882a593Smuzhiyun { 0x21, 0x19 },
3060*4882a593Smuzhiyun { 0x3f, 0x10 },
3061*4882a593Smuzhiyun { 0x2f, 0x80 },
3062*4882a593Smuzhiyun };
3063*4882a593Smuzhiyun
3064*4882a593Smuzhiyun /* First 5 bits of custom ID reg are a revision ID on OV518 */
3065*4882a593Smuzhiyun sd->revision = reg_r(sd, R51x_SYS_CUST_ID) & 0x1f;
3066*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Device revision %d\n", sd->revision);
3067*4882a593Smuzhiyun
3068*4882a593Smuzhiyun write_regvals(sd, init_518, ARRAY_SIZE(init_518));
3069*4882a593Smuzhiyun
3070*4882a593Smuzhiyun /* Set LED GPIO pin to output mode */
3071*4882a593Smuzhiyun reg_w_mask(sd, R518_GPIO_CTL, 0x00, 0x02);
3072*4882a593Smuzhiyun
3073*4882a593Smuzhiyun switch (sd->bridge) {
3074*4882a593Smuzhiyun case BRIDGE_OV518:
3075*4882a593Smuzhiyun write_regvals(sd, norm_518, ARRAY_SIZE(norm_518));
3076*4882a593Smuzhiyun break;
3077*4882a593Smuzhiyun case BRIDGE_OV518PLUS:
3078*4882a593Smuzhiyun write_regvals(sd, norm_518_p, ARRAY_SIZE(norm_518_p));
3079*4882a593Smuzhiyun break;
3080*4882a593Smuzhiyun }
3081*4882a593Smuzhiyun
3082*4882a593Smuzhiyun ov51x_upload_quan_tables(sd);
3083*4882a593Smuzhiyun
3084*4882a593Smuzhiyun reg_w(sd, 0x2f, 0x80);
3085*4882a593Smuzhiyun }
3086*4882a593Smuzhiyun
ov519_configure(struct sd * sd)3087*4882a593Smuzhiyun static void ov519_configure(struct sd *sd)
3088*4882a593Smuzhiyun {
3089*4882a593Smuzhiyun static const struct ov_regvals init_519[] = {
3090*4882a593Smuzhiyun { 0x5a, 0x6d }, /* EnableSystem */
3091*4882a593Smuzhiyun { 0x53, 0x9b }, /* don't enable the microcontroller */
3092*4882a593Smuzhiyun { OV519_R54_EN_CLK1, 0xff }, /* set bit2 to enable jpeg */
3093*4882a593Smuzhiyun { 0x5d, 0x03 },
3094*4882a593Smuzhiyun { 0x49, 0x01 },
3095*4882a593Smuzhiyun { 0x48, 0x00 },
3096*4882a593Smuzhiyun /* Set LED pin to output mode. Bit 4 must be cleared or sensor
3097*4882a593Smuzhiyun * detection will fail. This deserves further investigation. */
3098*4882a593Smuzhiyun { OV519_GPIO_IO_CTRL0, 0xee },
3099*4882a593Smuzhiyun { OV519_R51_RESET1, 0x0f },
3100*4882a593Smuzhiyun { OV519_R51_RESET1, 0x00 },
3101*4882a593Smuzhiyun { 0x22, 0x00 },
3102*4882a593Smuzhiyun /* windows reads 0x55 at this point*/
3103*4882a593Smuzhiyun };
3104*4882a593Smuzhiyun
3105*4882a593Smuzhiyun write_regvals(sd, init_519, ARRAY_SIZE(init_519));
3106*4882a593Smuzhiyun }
3107*4882a593Smuzhiyun
ovfx2_configure(struct sd * sd)3108*4882a593Smuzhiyun static void ovfx2_configure(struct sd *sd)
3109*4882a593Smuzhiyun {
3110*4882a593Smuzhiyun static const struct ov_regvals init_fx2[] = {
3111*4882a593Smuzhiyun { 0x00, 0x60 },
3112*4882a593Smuzhiyun { 0x02, 0x01 },
3113*4882a593Smuzhiyun { 0x0f, 0x1d },
3114*4882a593Smuzhiyun { 0xe9, 0x82 },
3115*4882a593Smuzhiyun { 0xea, 0xc7 },
3116*4882a593Smuzhiyun { 0xeb, 0x10 },
3117*4882a593Smuzhiyun { 0xec, 0xf6 },
3118*4882a593Smuzhiyun };
3119*4882a593Smuzhiyun
3120*4882a593Smuzhiyun sd->stopped = 1;
3121*4882a593Smuzhiyun
3122*4882a593Smuzhiyun write_regvals(sd, init_fx2, ARRAY_SIZE(init_fx2));
3123*4882a593Smuzhiyun }
3124*4882a593Smuzhiyun
3125*4882a593Smuzhiyun /* set the mode */
3126*4882a593Smuzhiyun /* This function works for ov7660 only */
ov519_set_mode(struct sd * sd)3127*4882a593Smuzhiyun static void ov519_set_mode(struct sd *sd)
3128*4882a593Smuzhiyun {
3129*4882a593Smuzhiyun static const struct ov_regvals bridge_ov7660[2][10] = {
3130*4882a593Smuzhiyun {{0x10, 0x14}, {0x11, 0x1e}, {0x12, 0x00}, {0x13, 0x00},
3131*4882a593Smuzhiyun {0x14, 0x00}, {0x15, 0x00}, {0x16, 0x00}, {0x20, 0x0c},
3132*4882a593Smuzhiyun {0x25, 0x01}, {0x26, 0x00}},
3133*4882a593Smuzhiyun {{0x10, 0x28}, {0x11, 0x3c}, {0x12, 0x00}, {0x13, 0x00},
3134*4882a593Smuzhiyun {0x14, 0x00}, {0x15, 0x00}, {0x16, 0x00}, {0x20, 0x0c},
3135*4882a593Smuzhiyun {0x25, 0x03}, {0x26, 0x00}}
3136*4882a593Smuzhiyun };
3137*4882a593Smuzhiyun static const struct ov_i2c_regvals sensor_ov7660[2][3] = {
3138*4882a593Smuzhiyun {{0x12, 0x00}, {0x24, 0x00}, {0x0c, 0x0c}},
3139*4882a593Smuzhiyun {{0x12, 0x00}, {0x04, 0x00}, {0x0c, 0x00}}
3140*4882a593Smuzhiyun };
3141*4882a593Smuzhiyun static const struct ov_i2c_regvals sensor_ov7660_2[] = {
3142*4882a593Smuzhiyun {OV7670_R17_HSTART, 0x13},
3143*4882a593Smuzhiyun {OV7670_R18_HSTOP, 0x01},
3144*4882a593Smuzhiyun {OV7670_R32_HREF, 0x92},
3145*4882a593Smuzhiyun {OV7670_R19_VSTART, 0x02},
3146*4882a593Smuzhiyun {OV7670_R1A_VSTOP, 0x7a},
3147*4882a593Smuzhiyun {OV7670_R03_VREF, 0x00},
3148*4882a593Smuzhiyun /* {0x33, 0x00}, */
3149*4882a593Smuzhiyun /* {0x34, 0x07}, */
3150*4882a593Smuzhiyun /* {0x36, 0x00}, */
3151*4882a593Smuzhiyun /* {0x6b, 0x0a}, */
3152*4882a593Smuzhiyun };
3153*4882a593Smuzhiyun
3154*4882a593Smuzhiyun write_regvals(sd, bridge_ov7660[sd->gspca_dev.curr_mode],
3155*4882a593Smuzhiyun ARRAY_SIZE(bridge_ov7660[0]));
3156*4882a593Smuzhiyun write_i2c_regvals(sd, sensor_ov7660[sd->gspca_dev.curr_mode],
3157*4882a593Smuzhiyun ARRAY_SIZE(sensor_ov7660[0]));
3158*4882a593Smuzhiyun write_i2c_regvals(sd, sensor_ov7660_2,
3159*4882a593Smuzhiyun ARRAY_SIZE(sensor_ov7660_2));
3160*4882a593Smuzhiyun }
3161*4882a593Smuzhiyun
3162*4882a593Smuzhiyun /* set the frame rate */
3163*4882a593Smuzhiyun /* This function works for sensors ov7640, ov7648 ov7660 and ov7670 only */
ov519_set_fr(struct sd * sd)3164*4882a593Smuzhiyun static void ov519_set_fr(struct sd *sd)
3165*4882a593Smuzhiyun {
3166*4882a593Smuzhiyun int fr;
3167*4882a593Smuzhiyun u8 clock;
3168*4882a593Smuzhiyun /* frame rate table with indices:
3169*4882a593Smuzhiyun * - mode = 0: 320x240, 1: 640x480
3170*4882a593Smuzhiyun * - fr rate = 0: 30, 1: 25, 2: 20, 3: 15, 4: 10, 5: 5
3171*4882a593Smuzhiyun * - reg = 0: bridge a4, 1: bridge 23, 2: sensor 11 (clock)
3172*4882a593Smuzhiyun */
3173*4882a593Smuzhiyun static const u8 fr_tb[2][6][3] = {
3174*4882a593Smuzhiyun {{0x04, 0xff, 0x00},
3175*4882a593Smuzhiyun {0x04, 0x1f, 0x00},
3176*4882a593Smuzhiyun {0x04, 0x1b, 0x00},
3177*4882a593Smuzhiyun {0x04, 0x15, 0x00},
3178*4882a593Smuzhiyun {0x04, 0x09, 0x00},
3179*4882a593Smuzhiyun {0x04, 0x01, 0x00}},
3180*4882a593Smuzhiyun {{0x0c, 0xff, 0x00},
3181*4882a593Smuzhiyun {0x0c, 0x1f, 0x00},
3182*4882a593Smuzhiyun {0x0c, 0x1b, 0x00},
3183*4882a593Smuzhiyun {0x04, 0xff, 0x01},
3184*4882a593Smuzhiyun {0x04, 0x1f, 0x01},
3185*4882a593Smuzhiyun {0x04, 0x1b, 0x01}},
3186*4882a593Smuzhiyun };
3187*4882a593Smuzhiyun
3188*4882a593Smuzhiyun if (frame_rate > 0)
3189*4882a593Smuzhiyun sd->frame_rate = frame_rate;
3190*4882a593Smuzhiyun if (sd->frame_rate >= 30)
3191*4882a593Smuzhiyun fr = 0;
3192*4882a593Smuzhiyun else if (sd->frame_rate >= 25)
3193*4882a593Smuzhiyun fr = 1;
3194*4882a593Smuzhiyun else if (sd->frame_rate >= 20)
3195*4882a593Smuzhiyun fr = 2;
3196*4882a593Smuzhiyun else if (sd->frame_rate >= 15)
3197*4882a593Smuzhiyun fr = 3;
3198*4882a593Smuzhiyun else if (sd->frame_rate >= 10)
3199*4882a593Smuzhiyun fr = 4;
3200*4882a593Smuzhiyun else
3201*4882a593Smuzhiyun fr = 5;
3202*4882a593Smuzhiyun reg_w(sd, 0xa4, fr_tb[sd->gspca_dev.curr_mode][fr][0]);
3203*4882a593Smuzhiyun reg_w(sd, 0x23, fr_tb[sd->gspca_dev.curr_mode][fr][1]);
3204*4882a593Smuzhiyun clock = fr_tb[sd->gspca_dev.curr_mode][fr][2];
3205*4882a593Smuzhiyun if (sd->sensor == SEN_OV7660)
3206*4882a593Smuzhiyun clock |= 0x80; /* enable double clock */
3207*4882a593Smuzhiyun ov518_i2c_w(sd, OV7670_R11_CLKRC, clock);
3208*4882a593Smuzhiyun }
3209*4882a593Smuzhiyun
setautogain(struct gspca_dev * gspca_dev,s32 val)3210*4882a593Smuzhiyun static void setautogain(struct gspca_dev *gspca_dev, s32 val)
3211*4882a593Smuzhiyun {
3212*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
3213*4882a593Smuzhiyun
3214*4882a593Smuzhiyun i2c_w_mask(sd, 0x13, val ? 0x05 : 0x00, 0x05);
3215*4882a593Smuzhiyun }
3216*4882a593Smuzhiyun
3217*4882a593Smuzhiyun /* this function is called at probe time */
sd_config(struct gspca_dev * gspca_dev,const struct usb_device_id * id)3218*4882a593Smuzhiyun static int sd_config(struct gspca_dev *gspca_dev,
3219*4882a593Smuzhiyun const struct usb_device_id *id)
3220*4882a593Smuzhiyun {
3221*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
3222*4882a593Smuzhiyun struct cam *cam = &gspca_dev->cam;
3223*4882a593Smuzhiyun
3224*4882a593Smuzhiyun sd->bridge = id->driver_info & BRIDGE_MASK;
3225*4882a593Smuzhiyun sd->invert_led = (id->driver_info & BRIDGE_INVERT_LED) != 0;
3226*4882a593Smuzhiyun
3227*4882a593Smuzhiyun switch (sd->bridge) {
3228*4882a593Smuzhiyun case BRIDGE_OV511:
3229*4882a593Smuzhiyun case BRIDGE_OV511PLUS:
3230*4882a593Smuzhiyun cam->cam_mode = ov511_vga_mode;
3231*4882a593Smuzhiyun cam->nmodes = ARRAY_SIZE(ov511_vga_mode);
3232*4882a593Smuzhiyun break;
3233*4882a593Smuzhiyun case BRIDGE_OV518:
3234*4882a593Smuzhiyun case BRIDGE_OV518PLUS:
3235*4882a593Smuzhiyun cam->cam_mode = ov518_vga_mode;
3236*4882a593Smuzhiyun cam->nmodes = ARRAY_SIZE(ov518_vga_mode);
3237*4882a593Smuzhiyun break;
3238*4882a593Smuzhiyun case BRIDGE_OV519:
3239*4882a593Smuzhiyun cam->cam_mode = ov519_vga_mode;
3240*4882a593Smuzhiyun cam->nmodes = ARRAY_SIZE(ov519_vga_mode);
3241*4882a593Smuzhiyun break;
3242*4882a593Smuzhiyun case BRIDGE_OVFX2:
3243*4882a593Smuzhiyun cam->cam_mode = ov519_vga_mode;
3244*4882a593Smuzhiyun cam->nmodes = ARRAY_SIZE(ov519_vga_mode);
3245*4882a593Smuzhiyun cam->bulk_size = OVFX2_BULK_SIZE;
3246*4882a593Smuzhiyun cam->bulk_nurbs = MAX_NURBS;
3247*4882a593Smuzhiyun cam->bulk = 1;
3248*4882a593Smuzhiyun break;
3249*4882a593Smuzhiyun case BRIDGE_W9968CF:
3250*4882a593Smuzhiyun cam->cam_mode = w9968cf_vga_mode;
3251*4882a593Smuzhiyun cam->nmodes = ARRAY_SIZE(w9968cf_vga_mode);
3252*4882a593Smuzhiyun break;
3253*4882a593Smuzhiyun }
3254*4882a593Smuzhiyun
3255*4882a593Smuzhiyun sd->frame_rate = 15;
3256*4882a593Smuzhiyun
3257*4882a593Smuzhiyun return 0;
3258*4882a593Smuzhiyun }
3259*4882a593Smuzhiyun
3260*4882a593Smuzhiyun /* this function is called at probe and resume time */
sd_init(struct gspca_dev * gspca_dev)3261*4882a593Smuzhiyun static int sd_init(struct gspca_dev *gspca_dev)
3262*4882a593Smuzhiyun {
3263*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
3264*4882a593Smuzhiyun struct cam *cam = &gspca_dev->cam;
3265*4882a593Smuzhiyun
3266*4882a593Smuzhiyun switch (sd->bridge) {
3267*4882a593Smuzhiyun case BRIDGE_OV511:
3268*4882a593Smuzhiyun case BRIDGE_OV511PLUS:
3269*4882a593Smuzhiyun ov511_configure(gspca_dev);
3270*4882a593Smuzhiyun break;
3271*4882a593Smuzhiyun case BRIDGE_OV518:
3272*4882a593Smuzhiyun case BRIDGE_OV518PLUS:
3273*4882a593Smuzhiyun ov518_configure(gspca_dev);
3274*4882a593Smuzhiyun break;
3275*4882a593Smuzhiyun case BRIDGE_OV519:
3276*4882a593Smuzhiyun ov519_configure(sd);
3277*4882a593Smuzhiyun break;
3278*4882a593Smuzhiyun case BRIDGE_OVFX2:
3279*4882a593Smuzhiyun ovfx2_configure(sd);
3280*4882a593Smuzhiyun break;
3281*4882a593Smuzhiyun case BRIDGE_W9968CF:
3282*4882a593Smuzhiyun w9968cf_configure(sd);
3283*4882a593Smuzhiyun break;
3284*4882a593Smuzhiyun }
3285*4882a593Smuzhiyun
3286*4882a593Smuzhiyun /* The OV519 must be more aggressive about sensor detection since
3287*4882a593Smuzhiyun * I2C write will never fail if the sensor is not present. We have
3288*4882a593Smuzhiyun * to try to initialize the sensor to detect its presence */
3289*4882a593Smuzhiyun sd->sensor = -1;
3290*4882a593Smuzhiyun
3291*4882a593Smuzhiyun /* Test for 76xx */
3292*4882a593Smuzhiyun if (init_ov_sensor(sd, OV7xx0_SID) >= 0) {
3293*4882a593Smuzhiyun ov7xx0_configure(sd);
3294*4882a593Smuzhiyun
3295*4882a593Smuzhiyun /* Test for 6xx0 */
3296*4882a593Smuzhiyun } else if (init_ov_sensor(sd, OV6xx0_SID) >= 0) {
3297*4882a593Smuzhiyun ov6xx0_configure(sd);
3298*4882a593Smuzhiyun
3299*4882a593Smuzhiyun /* Test for 8xx0 */
3300*4882a593Smuzhiyun } else if (init_ov_sensor(sd, OV8xx0_SID) >= 0) {
3301*4882a593Smuzhiyun ov8xx0_configure(sd);
3302*4882a593Smuzhiyun
3303*4882a593Smuzhiyun /* Test for 3xxx / 2xxx */
3304*4882a593Smuzhiyun } else if (init_ov_sensor(sd, OV_HIRES_SID) >= 0) {
3305*4882a593Smuzhiyun ov_hires_configure(sd);
3306*4882a593Smuzhiyun } else {
3307*4882a593Smuzhiyun gspca_err(gspca_dev, "Can't determine sensor slave IDs\n");
3308*4882a593Smuzhiyun goto error;
3309*4882a593Smuzhiyun }
3310*4882a593Smuzhiyun
3311*4882a593Smuzhiyun if (sd->sensor < 0)
3312*4882a593Smuzhiyun goto error;
3313*4882a593Smuzhiyun
3314*4882a593Smuzhiyun ov51x_led_control(sd, 0); /* turn LED off */
3315*4882a593Smuzhiyun
3316*4882a593Smuzhiyun switch (sd->bridge) {
3317*4882a593Smuzhiyun case BRIDGE_OV511:
3318*4882a593Smuzhiyun case BRIDGE_OV511PLUS:
3319*4882a593Smuzhiyun if (sd->sif) {
3320*4882a593Smuzhiyun cam->cam_mode = ov511_sif_mode;
3321*4882a593Smuzhiyun cam->nmodes = ARRAY_SIZE(ov511_sif_mode);
3322*4882a593Smuzhiyun }
3323*4882a593Smuzhiyun break;
3324*4882a593Smuzhiyun case BRIDGE_OV518:
3325*4882a593Smuzhiyun case BRIDGE_OV518PLUS:
3326*4882a593Smuzhiyun if (sd->sif) {
3327*4882a593Smuzhiyun cam->cam_mode = ov518_sif_mode;
3328*4882a593Smuzhiyun cam->nmodes = ARRAY_SIZE(ov518_sif_mode);
3329*4882a593Smuzhiyun }
3330*4882a593Smuzhiyun break;
3331*4882a593Smuzhiyun case BRIDGE_OV519:
3332*4882a593Smuzhiyun if (sd->sif) {
3333*4882a593Smuzhiyun cam->cam_mode = ov519_sif_mode;
3334*4882a593Smuzhiyun cam->nmodes = ARRAY_SIZE(ov519_sif_mode);
3335*4882a593Smuzhiyun }
3336*4882a593Smuzhiyun break;
3337*4882a593Smuzhiyun case BRIDGE_OVFX2:
3338*4882a593Smuzhiyun switch (sd->sensor) {
3339*4882a593Smuzhiyun case SEN_OV2610:
3340*4882a593Smuzhiyun case SEN_OV2610AE:
3341*4882a593Smuzhiyun cam->cam_mode = ovfx2_ov2610_mode;
3342*4882a593Smuzhiyun cam->nmodes = ARRAY_SIZE(ovfx2_ov2610_mode);
3343*4882a593Smuzhiyun break;
3344*4882a593Smuzhiyun case SEN_OV3610:
3345*4882a593Smuzhiyun cam->cam_mode = ovfx2_ov3610_mode;
3346*4882a593Smuzhiyun cam->nmodes = ARRAY_SIZE(ovfx2_ov3610_mode);
3347*4882a593Smuzhiyun break;
3348*4882a593Smuzhiyun case SEN_OV9600:
3349*4882a593Smuzhiyun cam->cam_mode = ovfx2_ov9600_mode;
3350*4882a593Smuzhiyun cam->nmodes = ARRAY_SIZE(ovfx2_ov9600_mode);
3351*4882a593Smuzhiyun break;
3352*4882a593Smuzhiyun default:
3353*4882a593Smuzhiyun if (sd->sif) {
3354*4882a593Smuzhiyun cam->cam_mode = ov519_sif_mode;
3355*4882a593Smuzhiyun cam->nmodes = ARRAY_SIZE(ov519_sif_mode);
3356*4882a593Smuzhiyun }
3357*4882a593Smuzhiyun break;
3358*4882a593Smuzhiyun }
3359*4882a593Smuzhiyun break;
3360*4882a593Smuzhiyun case BRIDGE_W9968CF:
3361*4882a593Smuzhiyun if (sd->sif)
3362*4882a593Smuzhiyun cam->nmodes = ARRAY_SIZE(w9968cf_vga_mode) - 1;
3363*4882a593Smuzhiyun
3364*4882a593Smuzhiyun /* w9968cf needs initialisation once the sensor is known */
3365*4882a593Smuzhiyun w9968cf_init(sd);
3366*4882a593Smuzhiyun break;
3367*4882a593Smuzhiyun }
3368*4882a593Smuzhiyun
3369*4882a593Smuzhiyun /* initialize the sensor */
3370*4882a593Smuzhiyun switch (sd->sensor) {
3371*4882a593Smuzhiyun case SEN_OV2610:
3372*4882a593Smuzhiyun write_i2c_regvals(sd, norm_2610, ARRAY_SIZE(norm_2610));
3373*4882a593Smuzhiyun
3374*4882a593Smuzhiyun /* Enable autogain, autoexpo, awb, bandfilter */
3375*4882a593Smuzhiyun i2c_w_mask(sd, 0x13, 0x27, 0x27);
3376*4882a593Smuzhiyun break;
3377*4882a593Smuzhiyun case SEN_OV2610AE:
3378*4882a593Smuzhiyun write_i2c_regvals(sd, norm_2610ae, ARRAY_SIZE(norm_2610ae));
3379*4882a593Smuzhiyun
3380*4882a593Smuzhiyun /* enable autoexpo */
3381*4882a593Smuzhiyun i2c_w_mask(sd, 0x13, 0x05, 0x05);
3382*4882a593Smuzhiyun break;
3383*4882a593Smuzhiyun case SEN_OV3610:
3384*4882a593Smuzhiyun write_i2c_regvals(sd, norm_3620b, ARRAY_SIZE(norm_3620b));
3385*4882a593Smuzhiyun
3386*4882a593Smuzhiyun /* Enable autogain, autoexpo, awb, bandfilter */
3387*4882a593Smuzhiyun i2c_w_mask(sd, 0x13, 0x27, 0x27);
3388*4882a593Smuzhiyun break;
3389*4882a593Smuzhiyun case SEN_OV6620:
3390*4882a593Smuzhiyun write_i2c_regvals(sd, norm_6x20, ARRAY_SIZE(norm_6x20));
3391*4882a593Smuzhiyun break;
3392*4882a593Smuzhiyun case SEN_OV6630:
3393*4882a593Smuzhiyun case SEN_OV66308AF:
3394*4882a593Smuzhiyun write_i2c_regvals(sd, norm_6x30, ARRAY_SIZE(norm_6x30));
3395*4882a593Smuzhiyun break;
3396*4882a593Smuzhiyun default:
3397*4882a593Smuzhiyun /* case SEN_OV7610: */
3398*4882a593Smuzhiyun /* case SEN_OV76BE: */
3399*4882a593Smuzhiyun write_i2c_regvals(sd, norm_7610, ARRAY_SIZE(norm_7610));
3400*4882a593Smuzhiyun i2c_w_mask(sd, 0x0e, 0x00, 0x40);
3401*4882a593Smuzhiyun break;
3402*4882a593Smuzhiyun case SEN_OV7620:
3403*4882a593Smuzhiyun case SEN_OV7620AE:
3404*4882a593Smuzhiyun write_i2c_regvals(sd, norm_7620, ARRAY_SIZE(norm_7620));
3405*4882a593Smuzhiyun break;
3406*4882a593Smuzhiyun case SEN_OV7640:
3407*4882a593Smuzhiyun case SEN_OV7648:
3408*4882a593Smuzhiyun write_i2c_regvals(sd, norm_7640, ARRAY_SIZE(norm_7640));
3409*4882a593Smuzhiyun break;
3410*4882a593Smuzhiyun case SEN_OV7660:
3411*4882a593Smuzhiyun i2c_w(sd, OV7670_R12_COM7, OV7670_COM7_RESET);
3412*4882a593Smuzhiyun msleep(14);
3413*4882a593Smuzhiyun reg_w(sd, OV519_R57_SNAPSHOT, 0x23);
3414*4882a593Smuzhiyun write_regvals(sd, init_519_ov7660,
3415*4882a593Smuzhiyun ARRAY_SIZE(init_519_ov7660));
3416*4882a593Smuzhiyun write_i2c_regvals(sd, norm_7660, ARRAY_SIZE(norm_7660));
3417*4882a593Smuzhiyun sd->gspca_dev.curr_mode = 1; /* 640x480 */
3418*4882a593Smuzhiyun ov519_set_mode(sd);
3419*4882a593Smuzhiyun ov519_set_fr(sd);
3420*4882a593Smuzhiyun sd_reset_snapshot(gspca_dev);
3421*4882a593Smuzhiyun ov51x_restart(sd);
3422*4882a593Smuzhiyun ov51x_stop(sd); /* not in win traces */
3423*4882a593Smuzhiyun ov51x_led_control(sd, 0);
3424*4882a593Smuzhiyun break;
3425*4882a593Smuzhiyun case SEN_OV7670:
3426*4882a593Smuzhiyun write_i2c_regvals(sd, norm_7670, ARRAY_SIZE(norm_7670));
3427*4882a593Smuzhiyun break;
3428*4882a593Smuzhiyun case SEN_OV8610:
3429*4882a593Smuzhiyun write_i2c_regvals(sd, norm_8610, ARRAY_SIZE(norm_8610));
3430*4882a593Smuzhiyun break;
3431*4882a593Smuzhiyun case SEN_OV9600:
3432*4882a593Smuzhiyun write_i2c_regvals(sd, norm_9600, ARRAY_SIZE(norm_9600));
3433*4882a593Smuzhiyun
3434*4882a593Smuzhiyun /* enable autoexpo */
3435*4882a593Smuzhiyun /* i2c_w_mask(sd, 0x13, 0x05, 0x05); */
3436*4882a593Smuzhiyun break;
3437*4882a593Smuzhiyun }
3438*4882a593Smuzhiyun return gspca_dev->usb_err;
3439*4882a593Smuzhiyun error:
3440*4882a593Smuzhiyun gspca_err(gspca_dev, "OV519 Config failed\n");
3441*4882a593Smuzhiyun return -EINVAL;
3442*4882a593Smuzhiyun }
3443*4882a593Smuzhiyun
3444*4882a593Smuzhiyun /* function called at start time before URB creation */
sd_isoc_init(struct gspca_dev * gspca_dev)3445*4882a593Smuzhiyun static int sd_isoc_init(struct gspca_dev *gspca_dev)
3446*4882a593Smuzhiyun {
3447*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
3448*4882a593Smuzhiyun
3449*4882a593Smuzhiyun switch (sd->bridge) {
3450*4882a593Smuzhiyun case BRIDGE_OVFX2:
3451*4882a593Smuzhiyun if (gspca_dev->pixfmt.width != 800)
3452*4882a593Smuzhiyun gspca_dev->cam.bulk_size = OVFX2_BULK_SIZE;
3453*4882a593Smuzhiyun else
3454*4882a593Smuzhiyun gspca_dev->cam.bulk_size = 7 * 4096;
3455*4882a593Smuzhiyun break;
3456*4882a593Smuzhiyun }
3457*4882a593Smuzhiyun return 0;
3458*4882a593Smuzhiyun }
3459*4882a593Smuzhiyun
3460*4882a593Smuzhiyun /* Set up the OV511/OV511+ with the given image parameters.
3461*4882a593Smuzhiyun *
3462*4882a593Smuzhiyun * Do not put any sensor-specific code in here (including I2C I/O functions)
3463*4882a593Smuzhiyun */
ov511_mode_init_regs(struct sd * sd)3464*4882a593Smuzhiyun static void ov511_mode_init_regs(struct sd *sd)
3465*4882a593Smuzhiyun {
3466*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
3467*4882a593Smuzhiyun int hsegs, vsegs, packet_size, fps, needed;
3468*4882a593Smuzhiyun int interlaced = 0;
3469*4882a593Smuzhiyun struct usb_host_interface *alt;
3470*4882a593Smuzhiyun struct usb_interface *intf;
3471*4882a593Smuzhiyun
3472*4882a593Smuzhiyun intf = usb_ifnum_to_if(sd->gspca_dev.dev, sd->gspca_dev.iface);
3473*4882a593Smuzhiyun alt = usb_altnum_to_altsetting(intf, sd->gspca_dev.alt);
3474*4882a593Smuzhiyun if (!alt) {
3475*4882a593Smuzhiyun gspca_err(gspca_dev, "Couldn't get altsetting\n");
3476*4882a593Smuzhiyun sd->gspca_dev.usb_err = -EIO;
3477*4882a593Smuzhiyun return;
3478*4882a593Smuzhiyun }
3479*4882a593Smuzhiyun
3480*4882a593Smuzhiyun if (alt->desc.bNumEndpoints < 1) {
3481*4882a593Smuzhiyun sd->gspca_dev.usb_err = -ENODEV;
3482*4882a593Smuzhiyun return;
3483*4882a593Smuzhiyun }
3484*4882a593Smuzhiyun
3485*4882a593Smuzhiyun packet_size = le16_to_cpu(alt->endpoint[0].desc.wMaxPacketSize);
3486*4882a593Smuzhiyun reg_w(sd, R51x_FIFO_PSIZE, packet_size >> 5);
3487*4882a593Smuzhiyun
3488*4882a593Smuzhiyun reg_w(sd, R511_CAM_UV_EN, 0x01);
3489*4882a593Smuzhiyun reg_w(sd, R511_SNAP_UV_EN, 0x01);
3490*4882a593Smuzhiyun reg_w(sd, R511_SNAP_OPTS, 0x03);
3491*4882a593Smuzhiyun
3492*4882a593Smuzhiyun /* Here I'm assuming that snapshot size == image size.
3493*4882a593Smuzhiyun * I hope that's always true. --claudio
3494*4882a593Smuzhiyun */
3495*4882a593Smuzhiyun hsegs = (sd->gspca_dev.pixfmt.width >> 3) - 1;
3496*4882a593Smuzhiyun vsegs = (sd->gspca_dev.pixfmt.height >> 3) - 1;
3497*4882a593Smuzhiyun
3498*4882a593Smuzhiyun reg_w(sd, R511_CAM_PXCNT, hsegs);
3499*4882a593Smuzhiyun reg_w(sd, R511_CAM_LNCNT, vsegs);
3500*4882a593Smuzhiyun reg_w(sd, R511_CAM_PXDIV, 0x00);
3501*4882a593Smuzhiyun reg_w(sd, R511_CAM_LNDIV, 0x00);
3502*4882a593Smuzhiyun
3503*4882a593Smuzhiyun /* YUV420, low pass filter on */
3504*4882a593Smuzhiyun reg_w(sd, R511_CAM_OPTS, 0x03);
3505*4882a593Smuzhiyun
3506*4882a593Smuzhiyun /* Snapshot additions */
3507*4882a593Smuzhiyun reg_w(sd, R511_SNAP_PXCNT, hsegs);
3508*4882a593Smuzhiyun reg_w(sd, R511_SNAP_LNCNT, vsegs);
3509*4882a593Smuzhiyun reg_w(sd, R511_SNAP_PXDIV, 0x00);
3510*4882a593Smuzhiyun reg_w(sd, R511_SNAP_LNDIV, 0x00);
3511*4882a593Smuzhiyun
3512*4882a593Smuzhiyun /******** Set the framerate ********/
3513*4882a593Smuzhiyun if (frame_rate > 0)
3514*4882a593Smuzhiyun sd->frame_rate = frame_rate;
3515*4882a593Smuzhiyun
3516*4882a593Smuzhiyun switch (sd->sensor) {
3517*4882a593Smuzhiyun case SEN_OV6620:
3518*4882a593Smuzhiyun /* No framerate control, doesn't like higher rates yet */
3519*4882a593Smuzhiyun sd->clockdiv = 3;
3520*4882a593Smuzhiyun break;
3521*4882a593Smuzhiyun
3522*4882a593Smuzhiyun /* Note once the FIXME's in mode_init_ov_sensor_regs() are fixed
3523*4882a593Smuzhiyun for more sensors we need to do this for them too */
3524*4882a593Smuzhiyun case SEN_OV7620:
3525*4882a593Smuzhiyun case SEN_OV7620AE:
3526*4882a593Smuzhiyun case SEN_OV7640:
3527*4882a593Smuzhiyun case SEN_OV7648:
3528*4882a593Smuzhiyun case SEN_OV76BE:
3529*4882a593Smuzhiyun if (sd->gspca_dev.pixfmt.width == 320)
3530*4882a593Smuzhiyun interlaced = 1;
3531*4882a593Smuzhiyun fallthrough;
3532*4882a593Smuzhiyun case SEN_OV6630:
3533*4882a593Smuzhiyun case SEN_OV7610:
3534*4882a593Smuzhiyun case SEN_OV7670:
3535*4882a593Smuzhiyun switch (sd->frame_rate) {
3536*4882a593Smuzhiyun case 30:
3537*4882a593Smuzhiyun case 25:
3538*4882a593Smuzhiyun /* Not enough bandwidth to do 640x480 @ 30 fps */
3539*4882a593Smuzhiyun if (sd->gspca_dev.pixfmt.width != 640) {
3540*4882a593Smuzhiyun sd->clockdiv = 0;
3541*4882a593Smuzhiyun break;
3542*4882a593Smuzhiyun }
3543*4882a593Smuzhiyun /* For 640x480 case */
3544*4882a593Smuzhiyun fallthrough;
3545*4882a593Smuzhiyun default:
3546*4882a593Smuzhiyun /* case 20: */
3547*4882a593Smuzhiyun /* case 15: */
3548*4882a593Smuzhiyun sd->clockdiv = 1;
3549*4882a593Smuzhiyun break;
3550*4882a593Smuzhiyun case 10:
3551*4882a593Smuzhiyun sd->clockdiv = 2;
3552*4882a593Smuzhiyun break;
3553*4882a593Smuzhiyun case 5:
3554*4882a593Smuzhiyun sd->clockdiv = 5;
3555*4882a593Smuzhiyun break;
3556*4882a593Smuzhiyun }
3557*4882a593Smuzhiyun if (interlaced) {
3558*4882a593Smuzhiyun sd->clockdiv = (sd->clockdiv + 1) * 2 - 1;
3559*4882a593Smuzhiyun /* Higher then 10 does not work */
3560*4882a593Smuzhiyun if (sd->clockdiv > 10)
3561*4882a593Smuzhiyun sd->clockdiv = 10;
3562*4882a593Smuzhiyun }
3563*4882a593Smuzhiyun break;
3564*4882a593Smuzhiyun
3565*4882a593Smuzhiyun case SEN_OV8610:
3566*4882a593Smuzhiyun /* No framerate control ?? */
3567*4882a593Smuzhiyun sd->clockdiv = 0;
3568*4882a593Smuzhiyun break;
3569*4882a593Smuzhiyun }
3570*4882a593Smuzhiyun
3571*4882a593Smuzhiyun /* Check if we have enough bandwidth to disable compression */
3572*4882a593Smuzhiyun fps = (interlaced ? 60 : 30) / (sd->clockdiv + 1) + 1;
3573*4882a593Smuzhiyun needed = fps * sd->gspca_dev.pixfmt.width *
3574*4882a593Smuzhiyun sd->gspca_dev.pixfmt.height * 3 / 2;
3575*4882a593Smuzhiyun /* 1000 isoc packets/sec */
3576*4882a593Smuzhiyun if (needed > 1000 * packet_size) {
3577*4882a593Smuzhiyun /* Enable Y and UV quantization and compression */
3578*4882a593Smuzhiyun reg_w(sd, R511_COMP_EN, 0x07);
3579*4882a593Smuzhiyun reg_w(sd, R511_COMP_LUT_EN, 0x03);
3580*4882a593Smuzhiyun } else {
3581*4882a593Smuzhiyun reg_w(sd, R511_COMP_EN, 0x06);
3582*4882a593Smuzhiyun reg_w(sd, R511_COMP_LUT_EN, 0x00);
3583*4882a593Smuzhiyun }
3584*4882a593Smuzhiyun
3585*4882a593Smuzhiyun reg_w(sd, R51x_SYS_RESET, OV511_RESET_OMNICE);
3586*4882a593Smuzhiyun reg_w(sd, R51x_SYS_RESET, 0);
3587*4882a593Smuzhiyun }
3588*4882a593Smuzhiyun
3589*4882a593Smuzhiyun /* Sets up the OV518/OV518+ with the given image parameters
3590*4882a593Smuzhiyun *
3591*4882a593Smuzhiyun * OV518 needs a completely different approach, until we can figure out what
3592*4882a593Smuzhiyun * the individual registers do. Also, only 15 FPS is supported now.
3593*4882a593Smuzhiyun *
3594*4882a593Smuzhiyun * Do not put any sensor-specific code in here (including I2C I/O functions)
3595*4882a593Smuzhiyun */
ov518_mode_init_regs(struct sd * sd)3596*4882a593Smuzhiyun static void ov518_mode_init_regs(struct sd *sd)
3597*4882a593Smuzhiyun {
3598*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
3599*4882a593Smuzhiyun int hsegs, vsegs, packet_size;
3600*4882a593Smuzhiyun struct usb_host_interface *alt;
3601*4882a593Smuzhiyun struct usb_interface *intf;
3602*4882a593Smuzhiyun
3603*4882a593Smuzhiyun intf = usb_ifnum_to_if(sd->gspca_dev.dev, sd->gspca_dev.iface);
3604*4882a593Smuzhiyun alt = usb_altnum_to_altsetting(intf, sd->gspca_dev.alt);
3605*4882a593Smuzhiyun if (!alt) {
3606*4882a593Smuzhiyun gspca_err(gspca_dev, "Couldn't get altsetting\n");
3607*4882a593Smuzhiyun sd->gspca_dev.usb_err = -EIO;
3608*4882a593Smuzhiyun return;
3609*4882a593Smuzhiyun }
3610*4882a593Smuzhiyun
3611*4882a593Smuzhiyun if (alt->desc.bNumEndpoints < 1) {
3612*4882a593Smuzhiyun sd->gspca_dev.usb_err = -ENODEV;
3613*4882a593Smuzhiyun return;
3614*4882a593Smuzhiyun }
3615*4882a593Smuzhiyun
3616*4882a593Smuzhiyun packet_size = le16_to_cpu(alt->endpoint[0].desc.wMaxPacketSize);
3617*4882a593Smuzhiyun ov518_reg_w32(sd, R51x_FIFO_PSIZE, packet_size & ~7, 2);
3618*4882a593Smuzhiyun
3619*4882a593Smuzhiyun /******** Set the mode ********/
3620*4882a593Smuzhiyun reg_w(sd, 0x2b, 0);
3621*4882a593Smuzhiyun reg_w(sd, 0x2c, 0);
3622*4882a593Smuzhiyun reg_w(sd, 0x2d, 0);
3623*4882a593Smuzhiyun reg_w(sd, 0x2e, 0);
3624*4882a593Smuzhiyun reg_w(sd, 0x3b, 0);
3625*4882a593Smuzhiyun reg_w(sd, 0x3c, 0);
3626*4882a593Smuzhiyun reg_w(sd, 0x3d, 0);
3627*4882a593Smuzhiyun reg_w(sd, 0x3e, 0);
3628*4882a593Smuzhiyun
3629*4882a593Smuzhiyun if (sd->bridge == BRIDGE_OV518) {
3630*4882a593Smuzhiyun /* Set 8-bit (YVYU) input format */
3631*4882a593Smuzhiyun reg_w_mask(sd, 0x20, 0x08, 0x08);
3632*4882a593Smuzhiyun
3633*4882a593Smuzhiyun /* Set 12-bit (4:2:0) output format */
3634*4882a593Smuzhiyun reg_w_mask(sd, 0x28, 0x80, 0xf0);
3635*4882a593Smuzhiyun reg_w_mask(sd, 0x38, 0x80, 0xf0);
3636*4882a593Smuzhiyun } else {
3637*4882a593Smuzhiyun reg_w(sd, 0x28, 0x80);
3638*4882a593Smuzhiyun reg_w(sd, 0x38, 0x80);
3639*4882a593Smuzhiyun }
3640*4882a593Smuzhiyun
3641*4882a593Smuzhiyun hsegs = sd->gspca_dev.pixfmt.width / 16;
3642*4882a593Smuzhiyun vsegs = sd->gspca_dev.pixfmt.height / 4;
3643*4882a593Smuzhiyun
3644*4882a593Smuzhiyun reg_w(sd, 0x29, hsegs);
3645*4882a593Smuzhiyun reg_w(sd, 0x2a, vsegs);
3646*4882a593Smuzhiyun
3647*4882a593Smuzhiyun reg_w(sd, 0x39, hsegs);
3648*4882a593Smuzhiyun reg_w(sd, 0x3a, vsegs);
3649*4882a593Smuzhiyun
3650*4882a593Smuzhiyun /* Windows driver does this here; who knows why */
3651*4882a593Smuzhiyun reg_w(sd, 0x2f, 0x80);
3652*4882a593Smuzhiyun
3653*4882a593Smuzhiyun /******** Set the framerate ********/
3654*4882a593Smuzhiyun if (sd->bridge == BRIDGE_OV518PLUS && sd->revision == 0 &&
3655*4882a593Smuzhiyun sd->sensor == SEN_OV7620AE)
3656*4882a593Smuzhiyun sd->clockdiv = 0;
3657*4882a593Smuzhiyun else
3658*4882a593Smuzhiyun sd->clockdiv = 1;
3659*4882a593Smuzhiyun
3660*4882a593Smuzhiyun /* Mode independent, but framerate dependent, regs */
3661*4882a593Smuzhiyun /* 0x51: Clock divider; Only works on some cams which use 2 crystals */
3662*4882a593Smuzhiyun reg_w(sd, 0x51, 0x04);
3663*4882a593Smuzhiyun reg_w(sd, 0x22, 0x18);
3664*4882a593Smuzhiyun reg_w(sd, 0x23, 0xff);
3665*4882a593Smuzhiyun
3666*4882a593Smuzhiyun if (sd->bridge == BRIDGE_OV518PLUS) {
3667*4882a593Smuzhiyun switch (sd->sensor) {
3668*4882a593Smuzhiyun case SEN_OV7620AE:
3669*4882a593Smuzhiyun /*
3670*4882a593Smuzhiyun * HdG: 640x480 needs special handling on device
3671*4882a593Smuzhiyun * revision 2, we check for device revision > 0 to
3672*4882a593Smuzhiyun * avoid regressions, as we don't know the correct
3673*4882a593Smuzhiyun * thing todo for revision 1.
3674*4882a593Smuzhiyun *
3675*4882a593Smuzhiyun * Also this likely means we don't need to
3676*4882a593Smuzhiyun * differentiate between the OV7620 and OV7620AE,
3677*4882a593Smuzhiyun * earlier testing hitting this same problem likely
3678*4882a593Smuzhiyun * happened to be with revision < 2 cams using an
3679*4882a593Smuzhiyun * OV7620 and revision 2 cams using an OV7620AE.
3680*4882a593Smuzhiyun */
3681*4882a593Smuzhiyun if (sd->revision > 0 &&
3682*4882a593Smuzhiyun sd->gspca_dev.pixfmt.width == 640) {
3683*4882a593Smuzhiyun reg_w(sd, 0x20, 0x60);
3684*4882a593Smuzhiyun reg_w(sd, 0x21, 0x1f);
3685*4882a593Smuzhiyun } else {
3686*4882a593Smuzhiyun reg_w(sd, 0x20, 0x00);
3687*4882a593Smuzhiyun reg_w(sd, 0x21, 0x19);
3688*4882a593Smuzhiyun }
3689*4882a593Smuzhiyun break;
3690*4882a593Smuzhiyun case SEN_OV7620:
3691*4882a593Smuzhiyun reg_w(sd, 0x20, 0x00);
3692*4882a593Smuzhiyun reg_w(sd, 0x21, 0x19);
3693*4882a593Smuzhiyun break;
3694*4882a593Smuzhiyun default:
3695*4882a593Smuzhiyun reg_w(sd, 0x21, 0x19);
3696*4882a593Smuzhiyun }
3697*4882a593Smuzhiyun } else
3698*4882a593Smuzhiyun reg_w(sd, 0x71, 0x17); /* Compression-related? */
3699*4882a593Smuzhiyun
3700*4882a593Smuzhiyun /* FIXME: Sensor-specific */
3701*4882a593Smuzhiyun /* Bit 5 is what matters here. Of course, it is "reserved" */
3702*4882a593Smuzhiyun i2c_w(sd, 0x54, 0x23);
3703*4882a593Smuzhiyun
3704*4882a593Smuzhiyun reg_w(sd, 0x2f, 0x80);
3705*4882a593Smuzhiyun
3706*4882a593Smuzhiyun if (sd->bridge == BRIDGE_OV518PLUS) {
3707*4882a593Smuzhiyun reg_w(sd, 0x24, 0x94);
3708*4882a593Smuzhiyun reg_w(sd, 0x25, 0x90);
3709*4882a593Smuzhiyun ov518_reg_w32(sd, 0xc4, 400, 2); /* 190h */
3710*4882a593Smuzhiyun ov518_reg_w32(sd, 0xc6, 540, 2); /* 21ch */
3711*4882a593Smuzhiyun ov518_reg_w32(sd, 0xc7, 540, 2); /* 21ch */
3712*4882a593Smuzhiyun ov518_reg_w32(sd, 0xc8, 108, 2); /* 6ch */
3713*4882a593Smuzhiyun ov518_reg_w32(sd, 0xca, 131098, 3); /* 2001ah */
3714*4882a593Smuzhiyun ov518_reg_w32(sd, 0xcb, 532, 2); /* 214h */
3715*4882a593Smuzhiyun ov518_reg_w32(sd, 0xcc, 2400, 2); /* 960h */
3716*4882a593Smuzhiyun ov518_reg_w32(sd, 0xcd, 32, 2); /* 20h */
3717*4882a593Smuzhiyun ov518_reg_w32(sd, 0xce, 608, 2); /* 260h */
3718*4882a593Smuzhiyun } else {
3719*4882a593Smuzhiyun reg_w(sd, 0x24, 0x9f);
3720*4882a593Smuzhiyun reg_w(sd, 0x25, 0x90);
3721*4882a593Smuzhiyun ov518_reg_w32(sd, 0xc4, 400, 2); /* 190h */
3722*4882a593Smuzhiyun ov518_reg_w32(sd, 0xc6, 381, 2); /* 17dh */
3723*4882a593Smuzhiyun ov518_reg_w32(sd, 0xc7, 381, 2); /* 17dh */
3724*4882a593Smuzhiyun ov518_reg_w32(sd, 0xc8, 128, 2); /* 80h */
3725*4882a593Smuzhiyun ov518_reg_w32(sd, 0xca, 183331, 3); /* 2cc23h */
3726*4882a593Smuzhiyun ov518_reg_w32(sd, 0xcb, 746, 2); /* 2eah */
3727*4882a593Smuzhiyun ov518_reg_w32(sd, 0xcc, 1750, 2); /* 6d6h */
3728*4882a593Smuzhiyun ov518_reg_w32(sd, 0xcd, 45, 2); /* 2dh */
3729*4882a593Smuzhiyun ov518_reg_w32(sd, 0xce, 851, 2); /* 353h */
3730*4882a593Smuzhiyun }
3731*4882a593Smuzhiyun
3732*4882a593Smuzhiyun reg_w(sd, 0x2f, 0x80);
3733*4882a593Smuzhiyun }
3734*4882a593Smuzhiyun
3735*4882a593Smuzhiyun /* Sets up the OV519 with the given image parameters
3736*4882a593Smuzhiyun *
3737*4882a593Smuzhiyun * OV519 needs a completely different approach, until we can figure out what
3738*4882a593Smuzhiyun * the individual registers do.
3739*4882a593Smuzhiyun *
3740*4882a593Smuzhiyun * Do not put any sensor-specific code in here (including I2C I/O functions)
3741*4882a593Smuzhiyun */
ov519_mode_init_regs(struct sd * sd)3742*4882a593Smuzhiyun static void ov519_mode_init_regs(struct sd *sd)
3743*4882a593Smuzhiyun {
3744*4882a593Smuzhiyun static const struct ov_regvals mode_init_519_ov7670[] = {
3745*4882a593Smuzhiyun { 0x5d, 0x03 }, /* Turn off suspend mode */
3746*4882a593Smuzhiyun { 0x53, 0x9f }, /* was 9b in 1.65-1.08 */
3747*4882a593Smuzhiyun { OV519_R54_EN_CLK1, 0x0f }, /* bit2 (jpeg enable) */
3748*4882a593Smuzhiyun { 0xa2, 0x20 }, /* a2-a5 are undocumented */
3749*4882a593Smuzhiyun { 0xa3, 0x18 },
3750*4882a593Smuzhiyun { 0xa4, 0x04 },
3751*4882a593Smuzhiyun { 0xa5, 0x28 },
3752*4882a593Smuzhiyun { 0x37, 0x00 }, /* SetUsbInit */
3753*4882a593Smuzhiyun { 0x55, 0x02 }, /* 4.096 Mhz audio clock */
3754*4882a593Smuzhiyun /* Enable both fields, YUV Input, disable defect comp (why?) */
3755*4882a593Smuzhiyun { 0x20, 0x0c },
3756*4882a593Smuzhiyun { 0x21, 0x38 },
3757*4882a593Smuzhiyun { 0x22, 0x1d },
3758*4882a593Smuzhiyun { 0x17, 0x50 }, /* undocumented */
3759*4882a593Smuzhiyun { 0x37, 0x00 }, /* undocumented */
3760*4882a593Smuzhiyun { 0x40, 0xff }, /* I2C timeout counter */
3761*4882a593Smuzhiyun { 0x46, 0x00 }, /* I2C clock prescaler */
3762*4882a593Smuzhiyun { 0x59, 0x04 }, /* new from windrv 090403 */
3763*4882a593Smuzhiyun { 0xff, 0x00 }, /* undocumented */
3764*4882a593Smuzhiyun /* windows reads 0x55 at this point, why? */
3765*4882a593Smuzhiyun };
3766*4882a593Smuzhiyun
3767*4882a593Smuzhiyun static const struct ov_regvals mode_init_519[] = {
3768*4882a593Smuzhiyun { 0x5d, 0x03 }, /* Turn off suspend mode */
3769*4882a593Smuzhiyun { 0x53, 0x9f }, /* was 9b in 1.65-1.08 */
3770*4882a593Smuzhiyun { OV519_R54_EN_CLK1, 0x0f }, /* bit2 (jpeg enable) */
3771*4882a593Smuzhiyun { 0xa2, 0x20 }, /* a2-a5 are undocumented */
3772*4882a593Smuzhiyun { 0xa3, 0x18 },
3773*4882a593Smuzhiyun { 0xa4, 0x04 },
3774*4882a593Smuzhiyun { 0xa5, 0x28 },
3775*4882a593Smuzhiyun { 0x37, 0x00 }, /* SetUsbInit */
3776*4882a593Smuzhiyun { 0x55, 0x02 }, /* 4.096 Mhz audio clock */
3777*4882a593Smuzhiyun /* Enable both fields, YUV Input, disable defect comp (why?) */
3778*4882a593Smuzhiyun { 0x22, 0x1d },
3779*4882a593Smuzhiyun { 0x17, 0x50 }, /* undocumented */
3780*4882a593Smuzhiyun { 0x37, 0x00 }, /* undocumented */
3781*4882a593Smuzhiyun { 0x40, 0xff }, /* I2C timeout counter */
3782*4882a593Smuzhiyun { 0x46, 0x00 }, /* I2C clock prescaler */
3783*4882a593Smuzhiyun { 0x59, 0x04 }, /* new from windrv 090403 */
3784*4882a593Smuzhiyun { 0xff, 0x00 }, /* undocumented */
3785*4882a593Smuzhiyun /* windows reads 0x55 at this point, why? */
3786*4882a593Smuzhiyun };
3787*4882a593Smuzhiyun
3788*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
3789*4882a593Smuzhiyun
3790*4882a593Smuzhiyun /******** Set the mode ********/
3791*4882a593Smuzhiyun switch (sd->sensor) {
3792*4882a593Smuzhiyun default:
3793*4882a593Smuzhiyun write_regvals(sd, mode_init_519, ARRAY_SIZE(mode_init_519));
3794*4882a593Smuzhiyun if (sd->sensor == SEN_OV7640 ||
3795*4882a593Smuzhiyun sd->sensor == SEN_OV7648) {
3796*4882a593Smuzhiyun /* Select 8-bit input mode */
3797*4882a593Smuzhiyun reg_w_mask(sd, OV519_R20_DFR, 0x10, 0x10);
3798*4882a593Smuzhiyun }
3799*4882a593Smuzhiyun break;
3800*4882a593Smuzhiyun case SEN_OV7660:
3801*4882a593Smuzhiyun return; /* done by ov519_set_mode/fr() */
3802*4882a593Smuzhiyun case SEN_OV7670:
3803*4882a593Smuzhiyun write_regvals(sd, mode_init_519_ov7670,
3804*4882a593Smuzhiyun ARRAY_SIZE(mode_init_519_ov7670));
3805*4882a593Smuzhiyun break;
3806*4882a593Smuzhiyun }
3807*4882a593Smuzhiyun
3808*4882a593Smuzhiyun reg_w(sd, OV519_R10_H_SIZE, sd->gspca_dev.pixfmt.width >> 4);
3809*4882a593Smuzhiyun reg_w(sd, OV519_R11_V_SIZE, sd->gspca_dev.pixfmt.height >> 3);
3810*4882a593Smuzhiyun if (sd->sensor == SEN_OV7670 &&
3811*4882a593Smuzhiyun sd->gspca_dev.cam.cam_mode[sd->gspca_dev.curr_mode].priv)
3812*4882a593Smuzhiyun reg_w(sd, OV519_R12_X_OFFSETL, 0x04);
3813*4882a593Smuzhiyun else if (sd->sensor == SEN_OV7648 &&
3814*4882a593Smuzhiyun sd->gspca_dev.cam.cam_mode[sd->gspca_dev.curr_mode].priv)
3815*4882a593Smuzhiyun reg_w(sd, OV519_R12_X_OFFSETL, 0x01);
3816*4882a593Smuzhiyun else
3817*4882a593Smuzhiyun reg_w(sd, OV519_R12_X_OFFSETL, 0x00);
3818*4882a593Smuzhiyun reg_w(sd, OV519_R13_X_OFFSETH, 0x00);
3819*4882a593Smuzhiyun reg_w(sd, OV519_R14_Y_OFFSETL, 0x00);
3820*4882a593Smuzhiyun reg_w(sd, OV519_R15_Y_OFFSETH, 0x00);
3821*4882a593Smuzhiyun reg_w(sd, OV519_R16_DIVIDER, 0x00);
3822*4882a593Smuzhiyun reg_w(sd, OV519_R25_FORMAT, 0x03); /* YUV422 */
3823*4882a593Smuzhiyun reg_w(sd, 0x26, 0x00); /* Undocumented */
3824*4882a593Smuzhiyun
3825*4882a593Smuzhiyun /******** Set the framerate ********/
3826*4882a593Smuzhiyun if (frame_rate > 0)
3827*4882a593Smuzhiyun sd->frame_rate = frame_rate;
3828*4882a593Smuzhiyun
3829*4882a593Smuzhiyun /* FIXME: These are only valid at the max resolution. */
3830*4882a593Smuzhiyun sd->clockdiv = 0;
3831*4882a593Smuzhiyun switch (sd->sensor) {
3832*4882a593Smuzhiyun case SEN_OV7640:
3833*4882a593Smuzhiyun case SEN_OV7648:
3834*4882a593Smuzhiyun switch (sd->frame_rate) {
3835*4882a593Smuzhiyun default:
3836*4882a593Smuzhiyun /* case 30: */
3837*4882a593Smuzhiyun reg_w(sd, 0xa4, 0x0c);
3838*4882a593Smuzhiyun reg_w(sd, 0x23, 0xff);
3839*4882a593Smuzhiyun break;
3840*4882a593Smuzhiyun case 25:
3841*4882a593Smuzhiyun reg_w(sd, 0xa4, 0x0c);
3842*4882a593Smuzhiyun reg_w(sd, 0x23, 0x1f);
3843*4882a593Smuzhiyun break;
3844*4882a593Smuzhiyun case 20:
3845*4882a593Smuzhiyun reg_w(sd, 0xa4, 0x0c);
3846*4882a593Smuzhiyun reg_w(sd, 0x23, 0x1b);
3847*4882a593Smuzhiyun break;
3848*4882a593Smuzhiyun case 15:
3849*4882a593Smuzhiyun reg_w(sd, 0xa4, 0x04);
3850*4882a593Smuzhiyun reg_w(sd, 0x23, 0xff);
3851*4882a593Smuzhiyun sd->clockdiv = 1;
3852*4882a593Smuzhiyun break;
3853*4882a593Smuzhiyun case 10:
3854*4882a593Smuzhiyun reg_w(sd, 0xa4, 0x04);
3855*4882a593Smuzhiyun reg_w(sd, 0x23, 0x1f);
3856*4882a593Smuzhiyun sd->clockdiv = 1;
3857*4882a593Smuzhiyun break;
3858*4882a593Smuzhiyun case 5:
3859*4882a593Smuzhiyun reg_w(sd, 0xa4, 0x04);
3860*4882a593Smuzhiyun reg_w(sd, 0x23, 0x1b);
3861*4882a593Smuzhiyun sd->clockdiv = 1;
3862*4882a593Smuzhiyun break;
3863*4882a593Smuzhiyun }
3864*4882a593Smuzhiyun break;
3865*4882a593Smuzhiyun case SEN_OV8610:
3866*4882a593Smuzhiyun switch (sd->frame_rate) {
3867*4882a593Smuzhiyun default: /* 15 fps */
3868*4882a593Smuzhiyun /* case 15: */
3869*4882a593Smuzhiyun reg_w(sd, 0xa4, 0x06);
3870*4882a593Smuzhiyun reg_w(sd, 0x23, 0xff);
3871*4882a593Smuzhiyun break;
3872*4882a593Smuzhiyun case 10:
3873*4882a593Smuzhiyun reg_w(sd, 0xa4, 0x06);
3874*4882a593Smuzhiyun reg_w(sd, 0x23, 0x1f);
3875*4882a593Smuzhiyun break;
3876*4882a593Smuzhiyun case 5:
3877*4882a593Smuzhiyun reg_w(sd, 0xa4, 0x06);
3878*4882a593Smuzhiyun reg_w(sd, 0x23, 0x1b);
3879*4882a593Smuzhiyun break;
3880*4882a593Smuzhiyun }
3881*4882a593Smuzhiyun break;
3882*4882a593Smuzhiyun case SEN_OV7670: /* guesses, based on 7640 */
3883*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_STREAM, "Setting framerate to %d fps\n",
3884*4882a593Smuzhiyun (sd->frame_rate == 0) ? 15 : sd->frame_rate);
3885*4882a593Smuzhiyun reg_w(sd, 0xa4, 0x10);
3886*4882a593Smuzhiyun switch (sd->frame_rate) {
3887*4882a593Smuzhiyun case 30:
3888*4882a593Smuzhiyun reg_w(sd, 0x23, 0xff);
3889*4882a593Smuzhiyun break;
3890*4882a593Smuzhiyun case 20:
3891*4882a593Smuzhiyun reg_w(sd, 0x23, 0x1b);
3892*4882a593Smuzhiyun break;
3893*4882a593Smuzhiyun default:
3894*4882a593Smuzhiyun /* case 15: */
3895*4882a593Smuzhiyun reg_w(sd, 0x23, 0xff);
3896*4882a593Smuzhiyun sd->clockdiv = 1;
3897*4882a593Smuzhiyun break;
3898*4882a593Smuzhiyun }
3899*4882a593Smuzhiyun break;
3900*4882a593Smuzhiyun }
3901*4882a593Smuzhiyun }
3902*4882a593Smuzhiyun
mode_init_ov_sensor_regs(struct sd * sd)3903*4882a593Smuzhiyun static void mode_init_ov_sensor_regs(struct sd *sd)
3904*4882a593Smuzhiyun {
3905*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
3906*4882a593Smuzhiyun int qvga, xstart, xend, ystart, yend;
3907*4882a593Smuzhiyun u8 v;
3908*4882a593Smuzhiyun
3909*4882a593Smuzhiyun qvga = gspca_dev->cam.cam_mode[gspca_dev->curr_mode].priv & 1;
3910*4882a593Smuzhiyun
3911*4882a593Smuzhiyun /******** Mode (VGA/QVGA) and sensor specific regs ********/
3912*4882a593Smuzhiyun switch (sd->sensor) {
3913*4882a593Smuzhiyun case SEN_OV2610:
3914*4882a593Smuzhiyun i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3915*4882a593Smuzhiyun i2c_w_mask(sd, 0x28, qvga ? 0x00 : 0x20, 0x20);
3916*4882a593Smuzhiyun i2c_w(sd, 0x24, qvga ? 0x20 : 0x3a);
3917*4882a593Smuzhiyun i2c_w(sd, 0x25, qvga ? 0x30 : 0x60);
3918*4882a593Smuzhiyun i2c_w_mask(sd, 0x2d, qvga ? 0x40 : 0x00, 0x40);
3919*4882a593Smuzhiyun i2c_w_mask(sd, 0x67, qvga ? 0xf0 : 0x90, 0xf0);
3920*4882a593Smuzhiyun i2c_w_mask(sd, 0x74, qvga ? 0x20 : 0x00, 0x20);
3921*4882a593Smuzhiyun return;
3922*4882a593Smuzhiyun case SEN_OV2610AE: {
3923*4882a593Smuzhiyun u8 v;
3924*4882a593Smuzhiyun
3925*4882a593Smuzhiyun /* frame rates:
3926*4882a593Smuzhiyun * 10fps / 5 fps for 1600x1200
3927*4882a593Smuzhiyun * 40fps / 20fps for 800x600
3928*4882a593Smuzhiyun */
3929*4882a593Smuzhiyun v = 80;
3930*4882a593Smuzhiyun if (qvga) {
3931*4882a593Smuzhiyun if (sd->frame_rate < 25)
3932*4882a593Smuzhiyun v = 0x81;
3933*4882a593Smuzhiyun } else {
3934*4882a593Smuzhiyun if (sd->frame_rate < 10)
3935*4882a593Smuzhiyun v = 0x81;
3936*4882a593Smuzhiyun }
3937*4882a593Smuzhiyun i2c_w(sd, 0x11, v);
3938*4882a593Smuzhiyun i2c_w(sd, 0x12, qvga ? 0x60 : 0x20);
3939*4882a593Smuzhiyun return;
3940*4882a593Smuzhiyun }
3941*4882a593Smuzhiyun case SEN_OV3610:
3942*4882a593Smuzhiyun if (qvga) {
3943*4882a593Smuzhiyun xstart = (1040 - gspca_dev->pixfmt.width) / 2 +
3944*4882a593Smuzhiyun (0x1f << 4);
3945*4882a593Smuzhiyun ystart = (776 - gspca_dev->pixfmt.height) / 2;
3946*4882a593Smuzhiyun } else {
3947*4882a593Smuzhiyun xstart = (2076 - gspca_dev->pixfmt.width) / 2 +
3948*4882a593Smuzhiyun (0x10 << 4);
3949*4882a593Smuzhiyun ystart = (1544 - gspca_dev->pixfmt.height) / 2;
3950*4882a593Smuzhiyun }
3951*4882a593Smuzhiyun xend = xstart + gspca_dev->pixfmt.width;
3952*4882a593Smuzhiyun yend = ystart + gspca_dev->pixfmt.height;
3953*4882a593Smuzhiyun /* Writing to the COMH register resets the other windowing regs
3954*4882a593Smuzhiyun to their default values, so we must do this first. */
3955*4882a593Smuzhiyun i2c_w_mask(sd, 0x12, qvga ? 0x40 : 0x00, 0xf0);
3956*4882a593Smuzhiyun i2c_w_mask(sd, 0x32,
3957*4882a593Smuzhiyun (((xend >> 1) & 7) << 3) | ((xstart >> 1) & 7),
3958*4882a593Smuzhiyun 0x3f);
3959*4882a593Smuzhiyun i2c_w_mask(sd, 0x03,
3960*4882a593Smuzhiyun (((yend >> 1) & 3) << 2) | ((ystart >> 1) & 3),
3961*4882a593Smuzhiyun 0x0f);
3962*4882a593Smuzhiyun i2c_w(sd, 0x17, xstart >> 4);
3963*4882a593Smuzhiyun i2c_w(sd, 0x18, xend >> 4);
3964*4882a593Smuzhiyun i2c_w(sd, 0x19, ystart >> 3);
3965*4882a593Smuzhiyun i2c_w(sd, 0x1a, yend >> 3);
3966*4882a593Smuzhiyun return;
3967*4882a593Smuzhiyun case SEN_OV8610:
3968*4882a593Smuzhiyun /* For OV8610 qvga means qsvga */
3969*4882a593Smuzhiyun i2c_w_mask(sd, OV7610_REG_COM_C, qvga ? (1 << 5) : 0, 1 << 5);
3970*4882a593Smuzhiyun i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3971*4882a593Smuzhiyun i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
3972*4882a593Smuzhiyun i2c_w_mask(sd, 0x2d, 0x00, 0x40); /* from windrv 090403 */
3973*4882a593Smuzhiyun i2c_w_mask(sd, 0x28, 0x20, 0x20); /* progressive mode on */
3974*4882a593Smuzhiyun break;
3975*4882a593Smuzhiyun case SEN_OV7610:
3976*4882a593Smuzhiyun i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3977*4882a593Smuzhiyun i2c_w(sd, 0x35, qvga ? 0x1e : 0x9e);
3978*4882a593Smuzhiyun i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3979*4882a593Smuzhiyun i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
3980*4882a593Smuzhiyun break;
3981*4882a593Smuzhiyun case SEN_OV7620:
3982*4882a593Smuzhiyun case SEN_OV7620AE:
3983*4882a593Smuzhiyun case SEN_OV76BE:
3984*4882a593Smuzhiyun i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3985*4882a593Smuzhiyun i2c_w_mask(sd, 0x28, qvga ? 0x00 : 0x20, 0x20);
3986*4882a593Smuzhiyun i2c_w(sd, 0x24, qvga ? 0x20 : 0x3a);
3987*4882a593Smuzhiyun i2c_w(sd, 0x25, qvga ? 0x30 : 0x60);
3988*4882a593Smuzhiyun i2c_w_mask(sd, 0x2d, qvga ? 0x40 : 0x00, 0x40);
3989*4882a593Smuzhiyun i2c_w_mask(sd, 0x67, qvga ? 0xb0 : 0x90, 0xf0);
3990*4882a593Smuzhiyun i2c_w_mask(sd, 0x74, qvga ? 0x20 : 0x00, 0x20);
3991*4882a593Smuzhiyun i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3992*4882a593Smuzhiyun i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
3993*4882a593Smuzhiyun if (sd->sensor == SEN_OV76BE)
3994*4882a593Smuzhiyun i2c_w(sd, 0x35, qvga ? 0x1e : 0x9e);
3995*4882a593Smuzhiyun break;
3996*4882a593Smuzhiyun case SEN_OV7640:
3997*4882a593Smuzhiyun case SEN_OV7648:
3998*4882a593Smuzhiyun i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3999*4882a593Smuzhiyun i2c_w_mask(sd, 0x28, qvga ? 0x00 : 0x20, 0x20);
4000*4882a593Smuzhiyun /* Setting this undocumented bit in qvga mode removes a very
4001*4882a593Smuzhiyun annoying vertical shaking of the image */
4002*4882a593Smuzhiyun i2c_w_mask(sd, 0x2d, qvga ? 0x40 : 0x00, 0x40);
4003*4882a593Smuzhiyun /* Unknown */
4004*4882a593Smuzhiyun i2c_w_mask(sd, 0x67, qvga ? 0xf0 : 0x90, 0xf0);
4005*4882a593Smuzhiyun /* Allow higher automatic gain (to allow higher framerates) */
4006*4882a593Smuzhiyun i2c_w_mask(sd, 0x74, qvga ? 0x20 : 0x00, 0x20);
4007*4882a593Smuzhiyun i2c_w_mask(sd, 0x12, 0x04, 0x04); /* AWB: 1 */
4008*4882a593Smuzhiyun break;
4009*4882a593Smuzhiyun case SEN_OV7670:
4010*4882a593Smuzhiyun /* set COM7_FMT_VGA or COM7_FMT_QVGA
4011*4882a593Smuzhiyun * do we need to set anything else?
4012*4882a593Smuzhiyun * HSTART etc are set in set_ov_sensor_window itself */
4013*4882a593Smuzhiyun i2c_w_mask(sd, OV7670_R12_COM7,
4014*4882a593Smuzhiyun qvga ? OV7670_COM7_FMT_QVGA : OV7670_COM7_FMT_VGA,
4015*4882a593Smuzhiyun OV7670_COM7_FMT_MASK);
4016*4882a593Smuzhiyun i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
4017*4882a593Smuzhiyun i2c_w_mask(sd, OV7670_R13_COM8, OV7670_COM8_AWB,
4018*4882a593Smuzhiyun OV7670_COM8_AWB);
4019*4882a593Smuzhiyun if (qvga) { /* QVGA from ov7670.c by
4020*4882a593Smuzhiyun * Jonathan Corbet */
4021*4882a593Smuzhiyun xstart = 164;
4022*4882a593Smuzhiyun xend = 28;
4023*4882a593Smuzhiyun ystart = 14;
4024*4882a593Smuzhiyun yend = 494;
4025*4882a593Smuzhiyun } else { /* VGA */
4026*4882a593Smuzhiyun xstart = 158;
4027*4882a593Smuzhiyun xend = 14;
4028*4882a593Smuzhiyun ystart = 10;
4029*4882a593Smuzhiyun yend = 490;
4030*4882a593Smuzhiyun }
4031*4882a593Smuzhiyun /* OV7670 hardware window registers are split across
4032*4882a593Smuzhiyun * multiple locations */
4033*4882a593Smuzhiyun i2c_w(sd, OV7670_R17_HSTART, xstart >> 3);
4034*4882a593Smuzhiyun i2c_w(sd, OV7670_R18_HSTOP, xend >> 3);
4035*4882a593Smuzhiyun v = i2c_r(sd, OV7670_R32_HREF);
4036*4882a593Smuzhiyun v = (v & 0xc0) | ((xend & 0x7) << 3) | (xstart & 0x07);
4037*4882a593Smuzhiyun msleep(10); /* need to sleep between read and write to
4038*4882a593Smuzhiyun * same reg! */
4039*4882a593Smuzhiyun i2c_w(sd, OV7670_R32_HREF, v);
4040*4882a593Smuzhiyun
4041*4882a593Smuzhiyun i2c_w(sd, OV7670_R19_VSTART, ystart >> 2);
4042*4882a593Smuzhiyun i2c_w(sd, OV7670_R1A_VSTOP, yend >> 2);
4043*4882a593Smuzhiyun v = i2c_r(sd, OV7670_R03_VREF);
4044*4882a593Smuzhiyun v = (v & 0xc0) | ((yend & 0x3) << 2) | (ystart & 0x03);
4045*4882a593Smuzhiyun msleep(10); /* need to sleep between read and write to
4046*4882a593Smuzhiyun * same reg! */
4047*4882a593Smuzhiyun i2c_w(sd, OV7670_R03_VREF, v);
4048*4882a593Smuzhiyun break;
4049*4882a593Smuzhiyun case SEN_OV6620:
4050*4882a593Smuzhiyun i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
4051*4882a593Smuzhiyun i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
4052*4882a593Smuzhiyun i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
4053*4882a593Smuzhiyun break;
4054*4882a593Smuzhiyun case SEN_OV6630:
4055*4882a593Smuzhiyun case SEN_OV66308AF:
4056*4882a593Smuzhiyun i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
4057*4882a593Smuzhiyun i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
4058*4882a593Smuzhiyun break;
4059*4882a593Smuzhiyun case SEN_OV9600: {
4060*4882a593Smuzhiyun const struct ov_i2c_regvals *vals;
4061*4882a593Smuzhiyun static const struct ov_i2c_regvals sxga_15[] = {
4062*4882a593Smuzhiyun {0x11, 0x80}, {0x14, 0x3e}, {0x24, 0x85}, {0x25, 0x75}
4063*4882a593Smuzhiyun };
4064*4882a593Smuzhiyun static const struct ov_i2c_regvals sxga_7_5[] = {
4065*4882a593Smuzhiyun {0x11, 0x81}, {0x14, 0x3e}, {0x24, 0x85}, {0x25, 0x75}
4066*4882a593Smuzhiyun };
4067*4882a593Smuzhiyun static const struct ov_i2c_regvals vga_30[] = {
4068*4882a593Smuzhiyun {0x11, 0x81}, {0x14, 0x7e}, {0x24, 0x70}, {0x25, 0x60}
4069*4882a593Smuzhiyun };
4070*4882a593Smuzhiyun static const struct ov_i2c_regvals vga_15[] = {
4071*4882a593Smuzhiyun {0x11, 0x83}, {0x14, 0x3e}, {0x24, 0x80}, {0x25, 0x70}
4072*4882a593Smuzhiyun };
4073*4882a593Smuzhiyun
4074*4882a593Smuzhiyun /* frame rates:
4075*4882a593Smuzhiyun * 15fps / 7.5 fps for 1280x1024
4076*4882a593Smuzhiyun * 30fps / 15fps for 640x480
4077*4882a593Smuzhiyun */
4078*4882a593Smuzhiyun i2c_w_mask(sd, 0x12, qvga ? 0x40 : 0x00, 0x40);
4079*4882a593Smuzhiyun if (qvga)
4080*4882a593Smuzhiyun vals = sd->frame_rate < 30 ? vga_15 : vga_30;
4081*4882a593Smuzhiyun else
4082*4882a593Smuzhiyun vals = sd->frame_rate < 15 ? sxga_7_5 : sxga_15;
4083*4882a593Smuzhiyun write_i2c_regvals(sd, vals, ARRAY_SIZE(sxga_15));
4084*4882a593Smuzhiyun return;
4085*4882a593Smuzhiyun }
4086*4882a593Smuzhiyun default:
4087*4882a593Smuzhiyun return;
4088*4882a593Smuzhiyun }
4089*4882a593Smuzhiyun
4090*4882a593Smuzhiyun /******** Clock programming ********/
4091*4882a593Smuzhiyun i2c_w(sd, 0x11, sd->clockdiv);
4092*4882a593Smuzhiyun }
4093*4882a593Smuzhiyun
4094*4882a593Smuzhiyun /* this function works for bridge ov519 and sensors ov7660 and ov7670 only */
sethvflip(struct gspca_dev * gspca_dev,s32 hflip,s32 vflip)4095*4882a593Smuzhiyun static void sethvflip(struct gspca_dev *gspca_dev, s32 hflip, s32 vflip)
4096*4882a593Smuzhiyun {
4097*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
4098*4882a593Smuzhiyun
4099*4882a593Smuzhiyun if (sd->gspca_dev.streaming)
4100*4882a593Smuzhiyun reg_w(sd, OV519_R51_RESET1, 0x0f); /* block stream */
4101*4882a593Smuzhiyun i2c_w_mask(sd, OV7670_R1E_MVFP,
4102*4882a593Smuzhiyun OV7670_MVFP_MIRROR * hflip | OV7670_MVFP_VFLIP * vflip,
4103*4882a593Smuzhiyun OV7670_MVFP_MIRROR | OV7670_MVFP_VFLIP);
4104*4882a593Smuzhiyun if (sd->gspca_dev.streaming)
4105*4882a593Smuzhiyun reg_w(sd, OV519_R51_RESET1, 0x00); /* restart stream */
4106*4882a593Smuzhiyun }
4107*4882a593Smuzhiyun
set_ov_sensor_window(struct sd * sd)4108*4882a593Smuzhiyun static void set_ov_sensor_window(struct sd *sd)
4109*4882a593Smuzhiyun {
4110*4882a593Smuzhiyun struct gspca_dev *gspca_dev;
4111*4882a593Smuzhiyun int qvga, crop;
4112*4882a593Smuzhiyun int hwsbase, hwebase, vwsbase, vwebase, hwscale, vwscale;
4113*4882a593Smuzhiyun
4114*4882a593Smuzhiyun /* mode setup is fully handled in mode_init_ov_sensor_regs for these */
4115*4882a593Smuzhiyun switch (sd->sensor) {
4116*4882a593Smuzhiyun case SEN_OV2610:
4117*4882a593Smuzhiyun case SEN_OV2610AE:
4118*4882a593Smuzhiyun case SEN_OV3610:
4119*4882a593Smuzhiyun case SEN_OV7670:
4120*4882a593Smuzhiyun case SEN_OV9600:
4121*4882a593Smuzhiyun mode_init_ov_sensor_regs(sd);
4122*4882a593Smuzhiyun return;
4123*4882a593Smuzhiyun case SEN_OV7660:
4124*4882a593Smuzhiyun ov519_set_mode(sd);
4125*4882a593Smuzhiyun ov519_set_fr(sd);
4126*4882a593Smuzhiyun return;
4127*4882a593Smuzhiyun }
4128*4882a593Smuzhiyun
4129*4882a593Smuzhiyun gspca_dev = &sd->gspca_dev;
4130*4882a593Smuzhiyun qvga = gspca_dev->cam.cam_mode[gspca_dev->curr_mode].priv & 1;
4131*4882a593Smuzhiyun crop = gspca_dev->cam.cam_mode[gspca_dev->curr_mode].priv & 2;
4132*4882a593Smuzhiyun
4133*4882a593Smuzhiyun /* The different sensor ICs handle setting up of window differently.
4134*4882a593Smuzhiyun * IF YOU SET IT WRONG, YOU WILL GET ALL ZERO ISOC DATA FROM OV51x!! */
4135*4882a593Smuzhiyun switch (sd->sensor) {
4136*4882a593Smuzhiyun case SEN_OV8610:
4137*4882a593Smuzhiyun hwsbase = 0x1e;
4138*4882a593Smuzhiyun hwebase = 0x1e;
4139*4882a593Smuzhiyun vwsbase = 0x02;
4140*4882a593Smuzhiyun vwebase = 0x02;
4141*4882a593Smuzhiyun break;
4142*4882a593Smuzhiyun case SEN_OV7610:
4143*4882a593Smuzhiyun case SEN_OV76BE:
4144*4882a593Smuzhiyun hwsbase = 0x38;
4145*4882a593Smuzhiyun hwebase = 0x3a;
4146*4882a593Smuzhiyun vwsbase = vwebase = 0x05;
4147*4882a593Smuzhiyun break;
4148*4882a593Smuzhiyun case SEN_OV6620:
4149*4882a593Smuzhiyun case SEN_OV6630:
4150*4882a593Smuzhiyun case SEN_OV66308AF:
4151*4882a593Smuzhiyun hwsbase = 0x38;
4152*4882a593Smuzhiyun hwebase = 0x3a;
4153*4882a593Smuzhiyun vwsbase = 0x05;
4154*4882a593Smuzhiyun vwebase = 0x06;
4155*4882a593Smuzhiyun if (sd->sensor == SEN_OV66308AF && qvga)
4156*4882a593Smuzhiyun /* HDG: this fixes U and V getting swapped */
4157*4882a593Smuzhiyun hwsbase++;
4158*4882a593Smuzhiyun if (crop) {
4159*4882a593Smuzhiyun hwsbase += 8;
4160*4882a593Smuzhiyun hwebase += 8;
4161*4882a593Smuzhiyun vwsbase += 11;
4162*4882a593Smuzhiyun vwebase += 11;
4163*4882a593Smuzhiyun }
4164*4882a593Smuzhiyun break;
4165*4882a593Smuzhiyun case SEN_OV7620:
4166*4882a593Smuzhiyun case SEN_OV7620AE:
4167*4882a593Smuzhiyun hwsbase = 0x2f; /* From 7620.SET (spec is wrong) */
4168*4882a593Smuzhiyun hwebase = 0x2f;
4169*4882a593Smuzhiyun vwsbase = vwebase = 0x05;
4170*4882a593Smuzhiyun break;
4171*4882a593Smuzhiyun case SEN_OV7640:
4172*4882a593Smuzhiyun case SEN_OV7648:
4173*4882a593Smuzhiyun hwsbase = 0x1a;
4174*4882a593Smuzhiyun hwebase = 0x1a;
4175*4882a593Smuzhiyun vwsbase = vwebase = 0x03;
4176*4882a593Smuzhiyun break;
4177*4882a593Smuzhiyun default:
4178*4882a593Smuzhiyun return;
4179*4882a593Smuzhiyun }
4180*4882a593Smuzhiyun
4181*4882a593Smuzhiyun switch (sd->sensor) {
4182*4882a593Smuzhiyun case SEN_OV6620:
4183*4882a593Smuzhiyun case SEN_OV6630:
4184*4882a593Smuzhiyun case SEN_OV66308AF:
4185*4882a593Smuzhiyun if (qvga) { /* QCIF */
4186*4882a593Smuzhiyun hwscale = 0;
4187*4882a593Smuzhiyun vwscale = 0;
4188*4882a593Smuzhiyun } else { /* CIF */
4189*4882a593Smuzhiyun hwscale = 1;
4190*4882a593Smuzhiyun vwscale = 1; /* The datasheet says 0;
4191*4882a593Smuzhiyun * it's wrong */
4192*4882a593Smuzhiyun }
4193*4882a593Smuzhiyun break;
4194*4882a593Smuzhiyun case SEN_OV8610:
4195*4882a593Smuzhiyun if (qvga) { /* QSVGA */
4196*4882a593Smuzhiyun hwscale = 1;
4197*4882a593Smuzhiyun vwscale = 1;
4198*4882a593Smuzhiyun } else { /* SVGA */
4199*4882a593Smuzhiyun hwscale = 2;
4200*4882a593Smuzhiyun vwscale = 2;
4201*4882a593Smuzhiyun }
4202*4882a593Smuzhiyun break;
4203*4882a593Smuzhiyun default: /* SEN_OV7xx0 */
4204*4882a593Smuzhiyun if (qvga) { /* QVGA */
4205*4882a593Smuzhiyun hwscale = 1;
4206*4882a593Smuzhiyun vwscale = 0;
4207*4882a593Smuzhiyun } else { /* VGA */
4208*4882a593Smuzhiyun hwscale = 2;
4209*4882a593Smuzhiyun vwscale = 1;
4210*4882a593Smuzhiyun }
4211*4882a593Smuzhiyun }
4212*4882a593Smuzhiyun
4213*4882a593Smuzhiyun mode_init_ov_sensor_regs(sd);
4214*4882a593Smuzhiyun
4215*4882a593Smuzhiyun i2c_w(sd, 0x17, hwsbase);
4216*4882a593Smuzhiyun i2c_w(sd, 0x18, hwebase + (sd->sensor_width >> hwscale));
4217*4882a593Smuzhiyun i2c_w(sd, 0x19, vwsbase);
4218*4882a593Smuzhiyun i2c_w(sd, 0x1a, vwebase + (sd->sensor_height >> vwscale));
4219*4882a593Smuzhiyun }
4220*4882a593Smuzhiyun
4221*4882a593Smuzhiyun /* -- start the camera -- */
sd_start(struct gspca_dev * gspca_dev)4222*4882a593Smuzhiyun static int sd_start(struct gspca_dev *gspca_dev)
4223*4882a593Smuzhiyun {
4224*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
4225*4882a593Smuzhiyun
4226*4882a593Smuzhiyun /* Default for most bridges, allow bridge_mode_init_regs to override */
4227*4882a593Smuzhiyun sd->sensor_width = sd->gspca_dev.pixfmt.width;
4228*4882a593Smuzhiyun sd->sensor_height = sd->gspca_dev.pixfmt.height;
4229*4882a593Smuzhiyun
4230*4882a593Smuzhiyun switch (sd->bridge) {
4231*4882a593Smuzhiyun case BRIDGE_OV511:
4232*4882a593Smuzhiyun case BRIDGE_OV511PLUS:
4233*4882a593Smuzhiyun ov511_mode_init_regs(sd);
4234*4882a593Smuzhiyun break;
4235*4882a593Smuzhiyun case BRIDGE_OV518:
4236*4882a593Smuzhiyun case BRIDGE_OV518PLUS:
4237*4882a593Smuzhiyun ov518_mode_init_regs(sd);
4238*4882a593Smuzhiyun break;
4239*4882a593Smuzhiyun case BRIDGE_OV519:
4240*4882a593Smuzhiyun ov519_mode_init_regs(sd);
4241*4882a593Smuzhiyun break;
4242*4882a593Smuzhiyun /* case BRIDGE_OVFX2: nothing to do */
4243*4882a593Smuzhiyun case BRIDGE_W9968CF:
4244*4882a593Smuzhiyun w9968cf_mode_init_regs(sd);
4245*4882a593Smuzhiyun break;
4246*4882a593Smuzhiyun }
4247*4882a593Smuzhiyun
4248*4882a593Smuzhiyun set_ov_sensor_window(sd);
4249*4882a593Smuzhiyun
4250*4882a593Smuzhiyun /* Force clear snapshot state in case the snapshot button was
4251*4882a593Smuzhiyun pressed while we weren't streaming */
4252*4882a593Smuzhiyun sd->snapshot_needs_reset = 1;
4253*4882a593Smuzhiyun sd_reset_snapshot(gspca_dev);
4254*4882a593Smuzhiyun
4255*4882a593Smuzhiyun sd->first_frame = 3;
4256*4882a593Smuzhiyun
4257*4882a593Smuzhiyun ov51x_restart(sd);
4258*4882a593Smuzhiyun ov51x_led_control(sd, 1);
4259*4882a593Smuzhiyun return gspca_dev->usb_err;
4260*4882a593Smuzhiyun }
4261*4882a593Smuzhiyun
sd_stopN(struct gspca_dev * gspca_dev)4262*4882a593Smuzhiyun static void sd_stopN(struct gspca_dev *gspca_dev)
4263*4882a593Smuzhiyun {
4264*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
4265*4882a593Smuzhiyun
4266*4882a593Smuzhiyun ov51x_stop(sd);
4267*4882a593Smuzhiyun ov51x_led_control(sd, 0);
4268*4882a593Smuzhiyun }
4269*4882a593Smuzhiyun
sd_stop0(struct gspca_dev * gspca_dev)4270*4882a593Smuzhiyun static void sd_stop0(struct gspca_dev *gspca_dev)
4271*4882a593Smuzhiyun {
4272*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
4273*4882a593Smuzhiyun
4274*4882a593Smuzhiyun if (!sd->gspca_dev.present)
4275*4882a593Smuzhiyun return;
4276*4882a593Smuzhiyun if (sd->bridge == BRIDGE_W9968CF)
4277*4882a593Smuzhiyun w9968cf_stop0(sd);
4278*4882a593Smuzhiyun
4279*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_INPUT)
4280*4882a593Smuzhiyun /* If the last button state is pressed, release it now! */
4281*4882a593Smuzhiyun if (sd->snapshot_pressed) {
4282*4882a593Smuzhiyun input_report_key(gspca_dev->input_dev, KEY_CAMERA, 0);
4283*4882a593Smuzhiyun input_sync(gspca_dev->input_dev);
4284*4882a593Smuzhiyun sd->snapshot_pressed = 0;
4285*4882a593Smuzhiyun }
4286*4882a593Smuzhiyun #endif
4287*4882a593Smuzhiyun if (sd->bridge == BRIDGE_OV519)
4288*4882a593Smuzhiyun reg_w(sd, OV519_R57_SNAPSHOT, 0x23);
4289*4882a593Smuzhiyun }
4290*4882a593Smuzhiyun
ov51x_handle_button(struct gspca_dev * gspca_dev,u8 state)4291*4882a593Smuzhiyun static void ov51x_handle_button(struct gspca_dev *gspca_dev, u8 state)
4292*4882a593Smuzhiyun {
4293*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
4294*4882a593Smuzhiyun
4295*4882a593Smuzhiyun if (sd->snapshot_pressed != state) {
4296*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_INPUT)
4297*4882a593Smuzhiyun input_report_key(gspca_dev->input_dev, KEY_CAMERA, state);
4298*4882a593Smuzhiyun input_sync(gspca_dev->input_dev);
4299*4882a593Smuzhiyun #endif
4300*4882a593Smuzhiyun if (state)
4301*4882a593Smuzhiyun sd->snapshot_needs_reset = 1;
4302*4882a593Smuzhiyun
4303*4882a593Smuzhiyun sd->snapshot_pressed = state;
4304*4882a593Smuzhiyun } else {
4305*4882a593Smuzhiyun /* On the ov511 / ov519 we need to reset the button state
4306*4882a593Smuzhiyun multiple times, as resetting does not work as long as the
4307*4882a593Smuzhiyun button stays pressed */
4308*4882a593Smuzhiyun switch (sd->bridge) {
4309*4882a593Smuzhiyun case BRIDGE_OV511:
4310*4882a593Smuzhiyun case BRIDGE_OV511PLUS:
4311*4882a593Smuzhiyun case BRIDGE_OV519:
4312*4882a593Smuzhiyun if (state)
4313*4882a593Smuzhiyun sd->snapshot_needs_reset = 1;
4314*4882a593Smuzhiyun break;
4315*4882a593Smuzhiyun }
4316*4882a593Smuzhiyun }
4317*4882a593Smuzhiyun }
4318*4882a593Smuzhiyun
ov511_pkt_scan(struct gspca_dev * gspca_dev,u8 * in,int len)4319*4882a593Smuzhiyun static void ov511_pkt_scan(struct gspca_dev *gspca_dev,
4320*4882a593Smuzhiyun u8 *in, /* isoc packet */
4321*4882a593Smuzhiyun int len) /* iso packet length */
4322*4882a593Smuzhiyun {
4323*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
4324*4882a593Smuzhiyun
4325*4882a593Smuzhiyun /* SOF/EOF packets have 1st to 8th bytes zeroed and the 9th
4326*4882a593Smuzhiyun * byte non-zero. The EOF packet has image width/height in the
4327*4882a593Smuzhiyun * 10th and 11th bytes. The 9th byte is given as follows:
4328*4882a593Smuzhiyun *
4329*4882a593Smuzhiyun * bit 7: EOF
4330*4882a593Smuzhiyun * 6: compression enabled
4331*4882a593Smuzhiyun * 5: 422/420/400 modes
4332*4882a593Smuzhiyun * 4: 422/420/400 modes
4333*4882a593Smuzhiyun * 3: 1
4334*4882a593Smuzhiyun * 2: snapshot button on
4335*4882a593Smuzhiyun * 1: snapshot frame
4336*4882a593Smuzhiyun * 0: even/odd field
4337*4882a593Smuzhiyun */
4338*4882a593Smuzhiyun if (!(in[0] | in[1] | in[2] | in[3] | in[4] | in[5] | in[6] | in[7]) &&
4339*4882a593Smuzhiyun (in[8] & 0x08)) {
4340*4882a593Smuzhiyun ov51x_handle_button(gspca_dev, (in[8] >> 2) & 1);
4341*4882a593Smuzhiyun if (in[8] & 0x80) {
4342*4882a593Smuzhiyun /* Frame end */
4343*4882a593Smuzhiyun if ((in[9] + 1) * 8 != gspca_dev->pixfmt.width ||
4344*4882a593Smuzhiyun (in[10] + 1) * 8 != gspca_dev->pixfmt.height) {
4345*4882a593Smuzhiyun gspca_err(gspca_dev, "Invalid frame size, got: %dx%d, requested: %dx%d\n",
4346*4882a593Smuzhiyun (in[9] + 1) * 8, (in[10] + 1) * 8,
4347*4882a593Smuzhiyun gspca_dev->pixfmt.width,
4348*4882a593Smuzhiyun gspca_dev->pixfmt.height);
4349*4882a593Smuzhiyun gspca_dev->last_packet_type = DISCARD_PACKET;
4350*4882a593Smuzhiyun return;
4351*4882a593Smuzhiyun }
4352*4882a593Smuzhiyun /* Add 11 byte footer to frame, might be useful */
4353*4882a593Smuzhiyun gspca_frame_add(gspca_dev, LAST_PACKET, in, 11);
4354*4882a593Smuzhiyun return;
4355*4882a593Smuzhiyun } else {
4356*4882a593Smuzhiyun /* Frame start */
4357*4882a593Smuzhiyun gspca_frame_add(gspca_dev, FIRST_PACKET, in, 0);
4358*4882a593Smuzhiyun sd->packet_nr = 0;
4359*4882a593Smuzhiyun }
4360*4882a593Smuzhiyun }
4361*4882a593Smuzhiyun
4362*4882a593Smuzhiyun /* Ignore the packet number */
4363*4882a593Smuzhiyun len--;
4364*4882a593Smuzhiyun
4365*4882a593Smuzhiyun /* intermediate packet */
4366*4882a593Smuzhiyun gspca_frame_add(gspca_dev, INTER_PACKET, in, len);
4367*4882a593Smuzhiyun }
4368*4882a593Smuzhiyun
ov518_pkt_scan(struct gspca_dev * gspca_dev,u8 * data,int len)4369*4882a593Smuzhiyun static void ov518_pkt_scan(struct gspca_dev *gspca_dev,
4370*4882a593Smuzhiyun u8 *data, /* isoc packet */
4371*4882a593Smuzhiyun int len) /* iso packet length */
4372*4882a593Smuzhiyun {
4373*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
4374*4882a593Smuzhiyun
4375*4882a593Smuzhiyun /* A false positive here is likely, until OVT gives me
4376*4882a593Smuzhiyun * the definitive SOF/EOF format */
4377*4882a593Smuzhiyun if ((!(data[0] | data[1] | data[2] | data[3] | data[5])) && data[6]) {
4378*4882a593Smuzhiyun ov51x_handle_button(gspca_dev, (data[6] >> 1) & 1);
4379*4882a593Smuzhiyun gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0);
4380*4882a593Smuzhiyun gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0);
4381*4882a593Smuzhiyun sd->packet_nr = 0;
4382*4882a593Smuzhiyun }
4383*4882a593Smuzhiyun
4384*4882a593Smuzhiyun if (gspca_dev->last_packet_type == DISCARD_PACKET)
4385*4882a593Smuzhiyun return;
4386*4882a593Smuzhiyun
4387*4882a593Smuzhiyun /* Does this device use packet numbers ? */
4388*4882a593Smuzhiyun if (len & 7) {
4389*4882a593Smuzhiyun len--;
4390*4882a593Smuzhiyun if (sd->packet_nr == data[len])
4391*4882a593Smuzhiyun sd->packet_nr++;
4392*4882a593Smuzhiyun /* The last few packets of the frame (which are all 0's
4393*4882a593Smuzhiyun except that they may contain part of the footer), are
4394*4882a593Smuzhiyun numbered 0 */
4395*4882a593Smuzhiyun else if (sd->packet_nr == 0 || data[len]) {
4396*4882a593Smuzhiyun gspca_err(gspca_dev, "Invalid packet nr: %d (expect: %d)\n",
4397*4882a593Smuzhiyun (int)data[len], (int)sd->packet_nr);
4398*4882a593Smuzhiyun gspca_dev->last_packet_type = DISCARD_PACKET;
4399*4882a593Smuzhiyun return;
4400*4882a593Smuzhiyun }
4401*4882a593Smuzhiyun }
4402*4882a593Smuzhiyun
4403*4882a593Smuzhiyun /* intermediate packet */
4404*4882a593Smuzhiyun gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
4405*4882a593Smuzhiyun }
4406*4882a593Smuzhiyun
ov519_pkt_scan(struct gspca_dev * gspca_dev,u8 * data,int len)4407*4882a593Smuzhiyun static void ov519_pkt_scan(struct gspca_dev *gspca_dev,
4408*4882a593Smuzhiyun u8 *data, /* isoc packet */
4409*4882a593Smuzhiyun int len) /* iso packet length */
4410*4882a593Smuzhiyun {
4411*4882a593Smuzhiyun /* Header of ov519 is 16 bytes:
4412*4882a593Smuzhiyun * Byte Value Description
4413*4882a593Smuzhiyun * 0 0xff magic
4414*4882a593Smuzhiyun * 1 0xff magic
4415*4882a593Smuzhiyun * 2 0xff magic
4416*4882a593Smuzhiyun * 3 0xXX 0x50 = SOF, 0x51 = EOF
4417*4882a593Smuzhiyun * 9 0xXX 0x01 initial frame without data,
4418*4882a593Smuzhiyun * 0x00 standard frame with image
4419*4882a593Smuzhiyun * 14 Lo in EOF: length of image data / 8
4420*4882a593Smuzhiyun * 15 Hi
4421*4882a593Smuzhiyun */
4422*4882a593Smuzhiyun
4423*4882a593Smuzhiyun if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff) {
4424*4882a593Smuzhiyun switch (data[3]) {
4425*4882a593Smuzhiyun case 0x50: /* start of frame */
4426*4882a593Smuzhiyun /* Don't check the button state here, as the state
4427*4882a593Smuzhiyun usually (always ?) changes at EOF and checking it
4428*4882a593Smuzhiyun here leads to unnecessary snapshot state resets. */
4429*4882a593Smuzhiyun #define HDRSZ 16
4430*4882a593Smuzhiyun data += HDRSZ;
4431*4882a593Smuzhiyun len -= HDRSZ;
4432*4882a593Smuzhiyun #undef HDRSZ
4433*4882a593Smuzhiyun if (data[0] == 0xff || data[1] == 0xd8)
4434*4882a593Smuzhiyun gspca_frame_add(gspca_dev, FIRST_PACKET,
4435*4882a593Smuzhiyun data, len);
4436*4882a593Smuzhiyun else
4437*4882a593Smuzhiyun gspca_dev->last_packet_type = DISCARD_PACKET;
4438*4882a593Smuzhiyun return;
4439*4882a593Smuzhiyun case 0x51: /* end of frame */
4440*4882a593Smuzhiyun ov51x_handle_button(gspca_dev, data[11] & 1);
4441*4882a593Smuzhiyun if (data[9] != 0)
4442*4882a593Smuzhiyun gspca_dev->last_packet_type = DISCARD_PACKET;
4443*4882a593Smuzhiyun gspca_frame_add(gspca_dev, LAST_PACKET,
4444*4882a593Smuzhiyun NULL, 0);
4445*4882a593Smuzhiyun return;
4446*4882a593Smuzhiyun }
4447*4882a593Smuzhiyun }
4448*4882a593Smuzhiyun
4449*4882a593Smuzhiyun /* intermediate packet */
4450*4882a593Smuzhiyun gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
4451*4882a593Smuzhiyun }
4452*4882a593Smuzhiyun
ovfx2_pkt_scan(struct gspca_dev * gspca_dev,u8 * data,int len)4453*4882a593Smuzhiyun static void ovfx2_pkt_scan(struct gspca_dev *gspca_dev,
4454*4882a593Smuzhiyun u8 *data, /* isoc packet */
4455*4882a593Smuzhiyun int len) /* iso packet length */
4456*4882a593Smuzhiyun {
4457*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
4458*4882a593Smuzhiyun
4459*4882a593Smuzhiyun gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
4460*4882a593Smuzhiyun
4461*4882a593Smuzhiyun /* A short read signals EOF */
4462*4882a593Smuzhiyun if (len < gspca_dev->cam.bulk_size) {
4463*4882a593Smuzhiyun /* If the frame is short, and it is one of the first ones
4464*4882a593Smuzhiyun the sensor and bridge are still syncing, so drop it. */
4465*4882a593Smuzhiyun if (sd->first_frame) {
4466*4882a593Smuzhiyun sd->first_frame--;
4467*4882a593Smuzhiyun if (gspca_dev->image_len <
4468*4882a593Smuzhiyun sd->gspca_dev.pixfmt.width *
4469*4882a593Smuzhiyun sd->gspca_dev.pixfmt.height)
4470*4882a593Smuzhiyun gspca_dev->last_packet_type = DISCARD_PACKET;
4471*4882a593Smuzhiyun }
4472*4882a593Smuzhiyun gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0);
4473*4882a593Smuzhiyun gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0);
4474*4882a593Smuzhiyun }
4475*4882a593Smuzhiyun }
4476*4882a593Smuzhiyun
sd_pkt_scan(struct gspca_dev * gspca_dev,u8 * data,int len)4477*4882a593Smuzhiyun static void sd_pkt_scan(struct gspca_dev *gspca_dev,
4478*4882a593Smuzhiyun u8 *data, /* isoc packet */
4479*4882a593Smuzhiyun int len) /* iso packet length */
4480*4882a593Smuzhiyun {
4481*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
4482*4882a593Smuzhiyun
4483*4882a593Smuzhiyun switch (sd->bridge) {
4484*4882a593Smuzhiyun case BRIDGE_OV511:
4485*4882a593Smuzhiyun case BRIDGE_OV511PLUS:
4486*4882a593Smuzhiyun ov511_pkt_scan(gspca_dev, data, len);
4487*4882a593Smuzhiyun break;
4488*4882a593Smuzhiyun case BRIDGE_OV518:
4489*4882a593Smuzhiyun case BRIDGE_OV518PLUS:
4490*4882a593Smuzhiyun ov518_pkt_scan(gspca_dev, data, len);
4491*4882a593Smuzhiyun break;
4492*4882a593Smuzhiyun case BRIDGE_OV519:
4493*4882a593Smuzhiyun ov519_pkt_scan(gspca_dev, data, len);
4494*4882a593Smuzhiyun break;
4495*4882a593Smuzhiyun case BRIDGE_OVFX2:
4496*4882a593Smuzhiyun ovfx2_pkt_scan(gspca_dev, data, len);
4497*4882a593Smuzhiyun break;
4498*4882a593Smuzhiyun case BRIDGE_W9968CF:
4499*4882a593Smuzhiyun w9968cf_pkt_scan(gspca_dev, data, len);
4500*4882a593Smuzhiyun break;
4501*4882a593Smuzhiyun }
4502*4882a593Smuzhiyun }
4503*4882a593Smuzhiyun
4504*4882a593Smuzhiyun /* -- management routines -- */
4505*4882a593Smuzhiyun
setbrightness(struct gspca_dev * gspca_dev,s32 val)4506*4882a593Smuzhiyun static void setbrightness(struct gspca_dev *gspca_dev, s32 val)
4507*4882a593Smuzhiyun {
4508*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
4509*4882a593Smuzhiyun static const struct ov_i2c_regvals brit_7660[][7] = {
4510*4882a593Smuzhiyun {{0x0f, 0x6a}, {0x24, 0x40}, {0x25, 0x2b}, {0x26, 0x90},
4511*4882a593Smuzhiyun {0x27, 0xe0}, {0x28, 0xe0}, {0x2c, 0xe0}},
4512*4882a593Smuzhiyun {{0x0f, 0x6a}, {0x24, 0x50}, {0x25, 0x40}, {0x26, 0xa1},
4513*4882a593Smuzhiyun {0x27, 0xc0}, {0x28, 0xc0}, {0x2c, 0xc0}},
4514*4882a593Smuzhiyun {{0x0f, 0x6a}, {0x24, 0x68}, {0x25, 0x58}, {0x26, 0xc2},
4515*4882a593Smuzhiyun {0x27, 0xa0}, {0x28, 0xa0}, {0x2c, 0xa0}},
4516*4882a593Smuzhiyun {{0x0f, 0x6a}, {0x24, 0x70}, {0x25, 0x68}, {0x26, 0xd3},
4517*4882a593Smuzhiyun {0x27, 0x80}, {0x28, 0x80}, {0x2c, 0x80}},
4518*4882a593Smuzhiyun {{0x0f, 0x6a}, {0x24, 0x80}, {0x25, 0x70}, {0x26, 0xd3},
4519*4882a593Smuzhiyun {0x27, 0x20}, {0x28, 0x20}, {0x2c, 0x20}},
4520*4882a593Smuzhiyun {{0x0f, 0x6a}, {0x24, 0x88}, {0x25, 0x78}, {0x26, 0xd3},
4521*4882a593Smuzhiyun {0x27, 0x40}, {0x28, 0x40}, {0x2c, 0x40}},
4522*4882a593Smuzhiyun {{0x0f, 0x6a}, {0x24, 0x90}, {0x25, 0x80}, {0x26, 0xd4},
4523*4882a593Smuzhiyun {0x27, 0x60}, {0x28, 0x60}, {0x2c, 0x60}}
4524*4882a593Smuzhiyun };
4525*4882a593Smuzhiyun
4526*4882a593Smuzhiyun switch (sd->sensor) {
4527*4882a593Smuzhiyun case SEN_OV8610:
4528*4882a593Smuzhiyun case SEN_OV7610:
4529*4882a593Smuzhiyun case SEN_OV76BE:
4530*4882a593Smuzhiyun case SEN_OV6620:
4531*4882a593Smuzhiyun case SEN_OV6630:
4532*4882a593Smuzhiyun case SEN_OV66308AF:
4533*4882a593Smuzhiyun case SEN_OV7640:
4534*4882a593Smuzhiyun case SEN_OV7648:
4535*4882a593Smuzhiyun i2c_w(sd, OV7610_REG_BRT, val);
4536*4882a593Smuzhiyun break;
4537*4882a593Smuzhiyun case SEN_OV7620:
4538*4882a593Smuzhiyun case SEN_OV7620AE:
4539*4882a593Smuzhiyun i2c_w(sd, OV7610_REG_BRT, val);
4540*4882a593Smuzhiyun break;
4541*4882a593Smuzhiyun case SEN_OV7660:
4542*4882a593Smuzhiyun write_i2c_regvals(sd, brit_7660[val],
4543*4882a593Smuzhiyun ARRAY_SIZE(brit_7660[0]));
4544*4882a593Smuzhiyun break;
4545*4882a593Smuzhiyun case SEN_OV7670:
4546*4882a593Smuzhiyun /*win trace
4547*4882a593Smuzhiyun * i2c_w_mask(sd, OV7670_R13_COM8, 0, OV7670_COM8_AEC); */
4548*4882a593Smuzhiyun i2c_w(sd, OV7670_R55_BRIGHT, ov7670_abs_to_sm(val));
4549*4882a593Smuzhiyun break;
4550*4882a593Smuzhiyun }
4551*4882a593Smuzhiyun }
4552*4882a593Smuzhiyun
setcontrast(struct gspca_dev * gspca_dev,s32 val)4553*4882a593Smuzhiyun static void setcontrast(struct gspca_dev *gspca_dev, s32 val)
4554*4882a593Smuzhiyun {
4555*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
4556*4882a593Smuzhiyun static const struct ov_i2c_regvals contrast_7660[][31] = {
4557*4882a593Smuzhiyun {{0x6c, 0xf0}, {0x6d, 0xf0}, {0x6e, 0xf8}, {0x6f, 0xa0},
4558*4882a593Smuzhiyun {0x70, 0x58}, {0x71, 0x38}, {0x72, 0x30}, {0x73, 0x30},
4559*4882a593Smuzhiyun {0x74, 0x28}, {0x75, 0x28}, {0x76, 0x24}, {0x77, 0x24},
4560*4882a593Smuzhiyun {0x78, 0x22}, {0x79, 0x28}, {0x7a, 0x2a}, {0x7b, 0x34},
4561*4882a593Smuzhiyun {0x7c, 0x0f}, {0x7d, 0x1e}, {0x7e, 0x3d}, {0x7f, 0x65},
4562*4882a593Smuzhiyun {0x80, 0x70}, {0x81, 0x77}, {0x82, 0x7d}, {0x83, 0x83},
4563*4882a593Smuzhiyun {0x84, 0x88}, {0x85, 0x8d}, {0x86, 0x96}, {0x87, 0x9f},
4564*4882a593Smuzhiyun {0x88, 0xb0}, {0x89, 0xc4}, {0x8a, 0xd9}},
4565*4882a593Smuzhiyun {{0x6c, 0xf0}, {0x6d, 0xf0}, {0x6e, 0xf8}, {0x6f, 0x94},
4566*4882a593Smuzhiyun {0x70, 0x58}, {0x71, 0x40}, {0x72, 0x30}, {0x73, 0x30},
4567*4882a593Smuzhiyun {0x74, 0x30}, {0x75, 0x30}, {0x76, 0x2c}, {0x77, 0x24},
4568*4882a593Smuzhiyun {0x78, 0x22}, {0x79, 0x28}, {0x7a, 0x2a}, {0x7b, 0x31},
4569*4882a593Smuzhiyun {0x7c, 0x0f}, {0x7d, 0x1e}, {0x7e, 0x3d}, {0x7f, 0x62},
4570*4882a593Smuzhiyun {0x80, 0x6d}, {0x81, 0x75}, {0x82, 0x7b}, {0x83, 0x81},
4571*4882a593Smuzhiyun {0x84, 0x87}, {0x85, 0x8d}, {0x86, 0x98}, {0x87, 0xa1},
4572*4882a593Smuzhiyun {0x88, 0xb2}, {0x89, 0xc6}, {0x8a, 0xdb}},
4573*4882a593Smuzhiyun {{0x6c, 0xf0}, {0x6d, 0xf0}, {0x6e, 0xf0}, {0x6f, 0x84},
4574*4882a593Smuzhiyun {0x70, 0x58}, {0x71, 0x48}, {0x72, 0x40}, {0x73, 0x40},
4575*4882a593Smuzhiyun {0x74, 0x28}, {0x75, 0x28}, {0x76, 0x28}, {0x77, 0x24},
4576*4882a593Smuzhiyun {0x78, 0x26}, {0x79, 0x28}, {0x7a, 0x28}, {0x7b, 0x34},
4577*4882a593Smuzhiyun {0x7c, 0x0f}, {0x7d, 0x1e}, {0x7e, 0x3c}, {0x7f, 0x5d},
4578*4882a593Smuzhiyun {0x80, 0x68}, {0x81, 0x71}, {0x82, 0x79}, {0x83, 0x81},
4579*4882a593Smuzhiyun {0x84, 0x86}, {0x85, 0x8b}, {0x86, 0x95}, {0x87, 0x9e},
4580*4882a593Smuzhiyun {0x88, 0xb1}, {0x89, 0xc5}, {0x8a, 0xd9}},
4581*4882a593Smuzhiyun {{0x6c, 0xf0}, {0x6d, 0xf0}, {0x6e, 0xf0}, {0x6f, 0x70},
4582*4882a593Smuzhiyun {0x70, 0x58}, {0x71, 0x58}, {0x72, 0x48}, {0x73, 0x48},
4583*4882a593Smuzhiyun {0x74, 0x38}, {0x75, 0x40}, {0x76, 0x34}, {0x77, 0x34},
4584*4882a593Smuzhiyun {0x78, 0x2e}, {0x79, 0x28}, {0x7a, 0x24}, {0x7b, 0x22},
4585*4882a593Smuzhiyun {0x7c, 0x0f}, {0x7d, 0x1e}, {0x7e, 0x3c}, {0x7f, 0x58},
4586*4882a593Smuzhiyun {0x80, 0x63}, {0x81, 0x6e}, {0x82, 0x77}, {0x83, 0x80},
4587*4882a593Smuzhiyun {0x84, 0x87}, {0x85, 0x8f}, {0x86, 0x9c}, {0x87, 0xa9},
4588*4882a593Smuzhiyun {0x88, 0xc0}, {0x89, 0xd4}, {0x8a, 0xe6}},
4589*4882a593Smuzhiyun {{0x6c, 0xa0}, {0x6d, 0xf0}, {0x6e, 0x90}, {0x6f, 0x80},
4590*4882a593Smuzhiyun {0x70, 0x70}, {0x71, 0x80}, {0x72, 0x60}, {0x73, 0x60},
4591*4882a593Smuzhiyun {0x74, 0x58}, {0x75, 0x60}, {0x76, 0x4c}, {0x77, 0x38},
4592*4882a593Smuzhiyun {0x78, 0x38}, {0x79, 0x2a}, {0x7a, 0x20}, {0x7b, 0x0e},
4593*4882a593Smuzhiyun {0x7c, 0x0a}, {0x7d, 0x14}, {0x7e, 0x26}, {0x7f, 0x46},
4594*4882a593Smuzhiyun {0x80, 0x54}, {0x81, 0x64}, {0x82, 0x70}, {0x83, 0x7c},
4595*4882a593Smuzhiyun {0x84, 0x87}, {0x85, 0x93}, {0x86, 0xa6}, {0x87, 0xb4},
4596*4882a593Smuzhiyun {0x88, 0xd0}, {0x89, 0xe5}, {0x8a, 0xf5}},
4597*4882a593Smuzhiyun {{0x6c, 0x60}, {0x6d, 0x80}, {0x6e, 0x60}, {0x6f, 0x80},
4598*4882a593Smuzhiyun {0x70, 0x80}, {0x71, 0x80}, {0x72, 0x88}, {0x73, 0x30},
4599*4882a593Smuzhiyun {0x74, 0x70}, {0x75, 0x68}, {0x76, 0x64}, {0x77, 0x50},
4600*4882a593Smuzhiyun {0x78, 0x3c}, {0x79, 0x22}, {0x7a, 0x10}, {0x7b, 0x08},
4601*4882a593Smuzhiyun {0x7c, 0x06}, {0x7d, 0x0e}, {0x7e, 0x1a}, {0x7f, 0x3a},
4602*4882a593Smuzhiyun {0x80, 0x4a}, {0x81, 0x5a}, {0x82, 0x6b}, {0x83, 0x7b},
4603*4882a593Smuzhiyun {0x84, 0x89}, {0x85, 0x96}, {0x86, 0xaf}, {0x87, 0xc3},
4604*4882a593Smuzhiyun {0x88, 0xe1}, {0x89, 0xf2}, {0x8a, 0xfa}},
4605*4882a593Smuzhiyun {{0x6c, 0x20}, {0x6d, 0x40}, {0x6e, 0x20}, {0x6f, 0x60},
4606*4882a593Smuzhiyun {0x70, 0x88}, {0x71, 0xc8}, {0x72, 0xc0}, {0x73, 0xb8},
4607*4882a593Smuzhiyun {0x74, 0xa8}, {0x75, 0xb8}, {0x76, 0x80}, {0x77, 0x5c},
4608*4882a593Smuzhiyun {0x78, 0x26}, {0x79, 0x10}, {0x7a, 0x08}, {0x7b, 0x04},
4609*4882a593Smuzhiyun {0x7c, 0x02}, {0x7d, 0x06}, {0x7e, 0x0a}, {0x7f, 0x22},
4610*4882a593Smuzhiyun {0x80, 0x33}, {0x81, 0x4c}, {0x82, 0x64}, {0x83, 0x7b},
4611*4882a593Smuzhiyun {0x84, 0x90}, {0x85, 0xa7}, {0x86, 0xc7}, {0x87, 0xde},
4612*4882a593Smuzhiyun {0x88, 0xf1}, {0x89, 0xf9}, {0x8a, 0xfd}},
4613*4882a593Smuzhiyun };
4614*4882a593Smuzhiyun
4615*4882a593Smuzhiyun switch (sd->sensor) {
4616*4882a593Smuzhiyun case SEN_OV7610:
4617*4882a593Smuzhiyun case SEN_OV6620:
4618*4882a593Smuzhiyun i2c_w(sd, OV7610_REG_CNT, val);
4619*4882a593Smuzhiyun break;
4620*4882a593Smuzhiyun case SEN_OV6630:
4621*4882a593Smuzhiyun case SEN_OV66308AF:
4622*4882a593Smuzhiyun i2c_w_mask(sd, OV7610_REG_CNT, val >> 4, 0x0f);
4623*4882a593Smuzhiyun break;
4624*4882a593Smuzhiyun case SEN_OV8610: {
4625*4882a593Smuzhiyun static const u8 ctab[] = {
4626*4882a593Smuzhiyun 0x03, 0x09, 0x0b, 0x0f, 0x53, 0x6f, 0x35, 0x7f
4627*4882a593Smuzhiyun };
4628*4882a593Smuzhiyun
4629*4882a593Smuzhiyun /* Use Y gamma control instead. Bit 0 enables it. */
4630*4882a593Smuzhiyun i2c_w(sd, 0x64, ctab[val >> 5]);
4631*4882a593Smuzhiyun break;
4632*4882a593Smuzhiyun }
4633*4882a593Smuzhiyun case SEN_OV7620:
4634*4882a593Smuzhiyun case SEN_OV7620AE: {
4635*4882a593Smuzhiyun static const u8 ctab[] = {
4636*4882a593Smuzhiyun 0x01, 0x05, 0x09, 0x11, 0x15, 0x35, 0x37, 0x57,
4637*4882a593Smuzhiyun 0x5b, 0xa5, 0xa7, 0xc7, 0xc9, 0xcf, 0xef, 0xff
4638*4882a593Smuzhiyun };
4639*4882a593Smuzhiyun
4640*4882a593Smuzhiyun /* Use Y gamma control instead. Bit 0 enables it. */
4641*4882a593Smuzhiyun i2c_w(sd, 0x64, ctab[val >> 4]);
4642*4882a593Smuzhiyun break;
4643*4882a593Smuzhiyun }
4644*4882a593Smuzhiyun case SEN_OV7660:
4645*4882a593Smuzhiyun write_i2c_regvals(sd, contrast_7660[val],
4646*4882a593Smuzhiyun ARRAY_SIZE(contrast_7660[0]));
4647*4882a593Smuzhiyun break;
4648*4882a593Smuzhiyun case SEN_OV7670:
4649*4882a593Smuzhiyun /* check that this isn't just the same as ov7610 */
4650*4882a593Smuzhiyun i2c_w(sd, OV7670_R56_CONTRAS, val >> 1);
4651*4882a593Smuzhiyun break;
4652*4882a593Smuzhiyun }
4653*4882a593Smuzhiyun }
4654*4882a593Smuzhiyun
setexposure(struct gspca_dev * gspca_dev,s32 val)4655*4882a593Smuzhiyun static void setexposure(struct gspca_dev *gspca_dev, s32 val)
4656*4882a593Smuzhiyun {
4657*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
4658*4882a593Smuzhiyun
4659*4882a593Smuzhiyun i2c_w(sd, 0x10, val);
4660*4882a593Smuzhiyun }
4661*4882a593Smuzhiyun
setcolors(struct gspca_dev * gspca_dev,s32 val)4662*4882a593Smuzhiyun static void setcolors(struct gspca_dev *gspca_dev, s32 val)
4663*4882a593Smuzhiyun {
4664*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
4665*4882a593Smuzhiyun static const struct ov_i2c_regvals colors_7660[][6] = {
4666*4882a593Smuzhiyun {{0x4f, 0x28}, {0x50, 0x2a}, {0x51, 0x02}, {0x52, 0x0a},
4667*4882a593Smuzhiyun {0x53, 0x19}, {0x54, 0x23}},
4668*4882a593Smuzhiyun {{0x4f, 0x47}, {0x50, 0x4a}, {0x51, 0x03}, {0x52, 0x11},
4669*4882a593Smuzhiyun {0x53, 0x2c}, {0x54, 0x3e}},
4670*4882a593Smuzhiyun {{0x4f, 0x66}, {0x50, 0x6b}, {0x51, 0x05}, {0x52, 0x19},
4671*4882a593Smuzhiyun {0x53, 0x40}, {0x54, 0x59}},
4672*4882a593Smuzhiyun {{0x4f, 0x84}, {0x50, 0x8b}, {0x51, 0x06}, {0x52, 0x20},
4673*4882a593Smuzhiyun {0x53, 0x53}, {0x54, 0x73}},
4674*4882a593Smuzhiyun {{0x4f, 0xa3}, {0x50, 0xab}, {0x51, 0x08}, {0x52, 0x28},
4675*4882a593Smuzhiyun {0x53, 0x66}, {0x54, 0x8e}},
4676*4882a593Smuzhiyun };
4677*4882a593Smuzhiyun
4678*4882a593Smuzhiyun switch (sd->sensor) {
4679*4882a593Smuzhiyun case SEN_OV8610:
4680*4882a593Smuzhiyun case SEN_OV7610:
4681*4882a593Smuzhiyun case SEN_OV76BE:
4682*4882a593Smuzhiyun case SEN_OV6620:
4683*4882a593Smuzhiyun case SEN_OV6630:
4684*4882a593Smuzhiyun case SEN_OV66308AF:
4685*4882a593Smuzhiyun i2c_w(sd, OV7610_REG_SAT, val);
4686*4882a593Smuzhiyun break;
4687*4882a593Smuzhiyun case SEN_OV7620:
4688*4882a593Smuzhiyun case SEN_OV7620AE:
4689*4882a593Smuzhiyun /* Use UV gamma control instead. Bits 0 & 7 are reserved. */
4690*4882a593Smuzhiyun /* rc = ov_i2c_write(sd->dev, 0x62, (val >> 9) & 0x7e);
4691*4882a593Smuzhiyun if (rc < 0)
4692*4882a593Smuzhiyun goto out; */
4693*4882a593Smuzhiyun i2c_w(sd, OV7610_REG_SAT, val);
4694*4882a593Smuzhiyun break;
4695*4882a593Smuzhiyun case SEN_OV7640:
4696*4882a593Smuzhiyun case SEN_OV7648:
4697*4882a593Smuzhiyun i2c_w(sd, OV7610_REG_SAT, val & 0xf0);
4698*4882a593Smuzhiyun break;
4699*4882a593Smuzhiyun case SEN_OV7660:
4700*4882a593Smuzhiyun write_i2c_regvals(sd, colors_7660[val],
4701*4882a593Smuzhiyun ARRAY_SIZE(colors_7660[0]));
4702*4882a593Smuzhiyun break;
4703*4882a593Smuzhiyun case SEN_OV7670:
4704*4882a593Smuzhiyun /* supported later once I work out how to do it
4705*4882a593Smuzhiyun * transparently fail now! */
4706*4882a593Smuzhiyun /* set REG_COM13 values for UV sat auto mode */
4707*4882a593Smuzhiyun break;
4708*4882a593Smuzhiyun }
4709*4882a593Smuzhiyun }
4710*4882a593Smuzhiyun
setautobright(struct gspca_dev * gspca_dev,s32 val)4711*4882a593Smuzhiyun static void setautobright(struct gspca_dev *gspca_dev, s32 val)
4712*4882a593Smuzhiyun {
4713*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
4714*4882a593Smuzhiyun
4715*4882a593Smuzhiyun i2c_w_mask(sd, 0x2d, val ? 0x10 : 0x00, 0x10);
4716*4882a593Smuzhiyun }
4717*4882a593Smuzhiyun
setfreq_i(struct sd * sd,s32 val)4718*4882a593Smuzhiyun static void setfreq_i(struct sd *sd, s32 val)
4719*4882a593Smuzhiyun {
4720*4882a593Smuzhiyun if (sd->sensor == SEN_OV7660
4721*4882a593Smuzhiyun || sd->sensor == SEN_OV7670) {
4722*4882a593Smuzhiyun switch (val) {
4723*4882a593Smuzhiyun case 0: /* Banding filter disabled */
4724*4882a593Smuzhiyun i2c_w_mask(sd, OV7670_R13_COM8, 0, OV7670_COM8_BFILT);
4725*4882a593Smuzhiyun break;
4726*4882a593Smuzhiyun case 1: /* 50 hz */
4727*4882a593Smuzhiyun i2c_w_mask(sd, OV7670_R13_COM8, OV7670_COM8_BFILT,
4728*4882a593Smuzhiyun OV7670_COM8_BFILT);
4729*4882a593Smuzhiyun i2c_w_mask(sd, OV7670_R3B_COM11, 0x08, 0x18);
4730*4882a593Smuzhiyun break;
4731*4882a593Smuzhiyun case 2: /* 60 hz */
4732*4882a593Smuzhiyun i2c_w_mask(sd, OV7670_R13_COM8, OV7670_COM8_BFILT,
4733*4882a593Smuzhiyun OV7670_COM8_BFILT);
4734*4882a593Smuzhiyun i2c_w_mask(sd, OV7670_R3B_COM11, 0x00, 0x18);
4735*4882a593Smuzhiyun break;
4736*4882a593Smuzhiyun case 3: /* Auto hz - ov7670 only */
4737*4882a593Smuzhiyun i2c_w_mask(sd, OV7670_R13_COM8, OV7670_COM8_BFILT,
4738*4882a593Smuzhiyun OV7670_COM8_BFILT);
4739*4882a593Smuzhiyun i2c_w_mask(sd, OV7670_R3B_COM11, OV7670_COM11_HZAUTO,
4740*4882a593Smuzhiyun 0x18);
4741*4882a593Smuzhiyun break;
4742*4882a593Smuzhiyun }
4743*4882a593Smuzhiyun } else {
4744*4882a593Smuzhiyun switch (val) {
4745*4882a593Smuzhiyun case 0: /* Banding filter disabled */
4746*4882a593Smuzhiyun i2c_w_mask(sd, 0x2d, 0x00, 0x04);
4747*4882a593Smuzhiyun i2c_w_mask(sd, 0x2a, 0x00, 0x80);
4748*4882a593Smuzhiyun break;
4749*4882a593Smuzhiyun case 1: /* 50 hz (filter on and framerate adj) */
4750*4882a593Smuzhiyun i2c_w_mask(sd, 0x2d, 0x04, 0x04);
4751*4882a593Smuzhiyun i2c_w_mask(sd, 0x2a, 0x80, 0x80);
4752*4882a593Smuzhiyun /* 20 fps -> 16.667 fps */
4753*4882a593Smuzhiyun if (sd->sensor == SEN_OV6620 ||
4754*4882a593Smuzhiyun sd->sensor == SEN_OV6630 ||
4755*4882a593Smuzhiyun sd->sensor == SEN_OV66308AF)
4756*4882a593Smuzhiyun i2c_w(sd, 0x2b, 0x5e);
4757*4882a593Smuzhiyun else
4758*4882a593Smuzhiyun i2c_w(sd, 0x2b, 0xac);
4759*4882a593Smuzhiyun break;
4760*4882a593Smuzhiyun case 2: /* 60 hz (filter on, ...) */
4761*4882a593Smuzhiyun i2c_w_mask(sd, 0x2d, 0x04, 0x04);
4762*4882a593Smuzhiyun if (sd->sensor == SEN_OV6620 ||
4763*4882a593Smuzhiyun sd->sensor == SEN_OV6630 ||
4764*4882a593Smuzhiyun sd->sensor == SEN_OV66308AF) {
4765*4882a593Smuzhiyun /* 20 fps -> 15 fps */
4766*4882a593Smuzhiyun i2c_w_mask(sd, 0x2a, 0x80, 0x80);
4767*4882a593Smuzhiyun i2c_w(sd, 0x2b, 0xa8);
4768*4882a593Smuzhiyun } else {
4769*4882a593Smuzhiyun /* no framerate adj. */
4770*4882a593Smuzhiyun i2c_w_mask(sd, 0x2a, 0x00, 0x80);
4771*4882a593Smuzhiyun }
4772*4882a593Smuzhiyun break;
4773*4882a593Smuzhiyun }
4774*4882a593Smuzhiyun }
4775*4882a593Smuzhiyun }
4776*4882a593Smuzhiyun
setfreq(struct gspca_dev * gspca_dev,s32 val)4777*4882a593Smuzhiyun static void setfreq(struct gspca_dev *gspca_dev, s32 val)
4778*4882a593Smuzhiyun {
4779*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
4780*4882a593Smuzhiyun
4781*4882a593Smuzhiyun setfreq_i(sd, val);
4782*4882a593Smuzhiyun
4783*4882a593Smuzhiyun /* Ugly but necessary */
4784*4882a593Smuzhiyun if (sd->bridge == BRIDGE_W9968CF)
4785*4882a593Smuzhiyun w9968cf_set_crop_window(sd);
4786*4882a593Smuzhiyun }
4787*4882a593Smuzhiyun
sd_get_jcomp(struct gspca_dev * gspca_dev,struct v4l2_jpegcompression * jcomp)4788*4882a593Smuzhiyun static int sd_get_jcomp(struct gspca_dev *gspca_dev,
4789*4882a593Smuzhiyun struct v4l2_jpegcompression *jcomp)
4790*4882a593Smuzhiyun {
4791*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
4792*4882a593Smuzhiyun
4793*4882a593Smuzhiyun if (sd->bridge != BRIDGE_W9968CF)
4794*4882a593Smuzhiyun return -ENOTTY;
4795*4882a593Smuzhiyun
4796*4882a593Smuzhiyun memset(jcomp, 0, sizeof *jcomp);
4797*4882a593Smuzhiyun jcomp->quality = v4l2_ctrl_g_ctrl(sd->jpegqual);
4798*4882a593Smuzhiyun jcomp->jpeg_markers = V4L2_JPEG_MARKER_DHT | V4L2_JPEG_MARKER_DQT |
4799*4882a593Smuzhiyun V4L2_JPEG_MARKER_DRI;
4800*4882a593Smuzhiyun return 0;
4801*4882a593Smuzhiyun }
4802*4882a593Smuzhiyun
sd_set_jcomp(struct gspca_dev * gspca_dev,const struct v4l2_jpegcompression * jcomp)4803*4882a593Smuzhiyun static int sd_set_jcomp(struct gspca_dev *gspca_dev,
4804*4882a593Smuzhiyun const struct v4l2_jpegcompression *jcomp)
4805*4882a593Smuzhiyun {
4806*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
4807*4882a593Smuzhiyun
4808*4882a593Smuzhiyun if (sd->bridge != BRIDGE_W9968CF)
4809*4882a593Smuzhiyun return -ENOTTY;
4810*4882a593Smuzhiyun
4811*4882a593Smuzhiyun v4l2_ctrl_s_ctrl(sd->jpegqual, jcomp->quality);
4812*4882a593Smuzhiyun return 0;
4813*4882a593Smuzhiyun }
4814*4882a593Smuzhiyun
sd_g_volatile_ctrl(struct v4l2_ctrl * ctrl)4815*4882a593Smuzhiyun static int sd_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
4816*4882a593Smuzhiyun {
4817*4882a593Smuzhiyun struct gspca_dev *gspca_dev =
4818*4882a593Smuzhiyun container_of(ctrl->handler, struct gspca_dev, ctrl_handler);
4819*4882a593Smuzhiyun struct sd *sd = (struct sd *)gspca_dev;
4820*4882a593Smuzhiyun
4821*4882a593Smuzhiyun gspca_dev->usb_err = 0;
4822*4882a593Smuzhiyun
4823*4882a593Smuzhiyun switch (ctrl->id) {
4824*4882a593Smuzhiyun case V4L2_CID_AUTOGAIN:
4825*4882a593Smuzhiyun gspca_dev->exposure->val = i2c_r(sd, 0x10);
4826*4882a593Smuzhiyun break;
4827*4882a593Smuzhiyun }
4828*4882a593Smuzhiyun return 0;
4829*4882a593Smuzhiyun }
4830*4882a593Smuzhiyun
sd_s_ctrl(struct v4l2_ctrl * ctrl)4831*4882a593Smuzhiyun static int sd_s_ctrl(struct v4l2_ctrl *ctrl)
4832*4882a593Smuzhiyun {
4833*4882a593Smuzhiyun struct gspca_dev *gspca_dev =
4834*4882a593Smuzhiyun container_of(ctrl->handler, struct gspca_dev, ctrl_handler);
4835*4882a593Smuzhiyun struct sd *sd = (struct sd *)gspca_dev;
4836*4882a593Smuzhiyun
4837*4882a593Smuzhiyun gspca_dev->usb_err = 0;
4838*4882a593Smuzhiyun
4839*4882a593Smuzhiyun if (!gspca_dev->streaming)
4840*4882a593Smuzhiyun return 0;
4841*4882a593Smuzhiyun
4842*4882a593Smuzhiyun switch (ctrl->id) {
4843*4882a593Smuzhiyun case V4L2_CID_BRIGHTNESS:
4844*4882a593Smuzhiyun setbrightness(gspca_dev, ctrl->val);
4845*4882a593Smuzhiyun break;
4846*4882a593Smuzhiyun case V4L2_CID_CONTRAST:
4847*4882a593Smuzhiyun setcontrast(gspca_dev, ctrl->val);
4848*4882a593Smuzhiyun break;
4849*4882a593Smuzhiyun case V4L2_CID_POWER_LINE_FREQUENCY:
4850*4882a593Smuzhiyun setfreq(gspca_dev, ctrl->val);
4851*4882a593Smuzhiyun break;
4852*4882a593Smuzhiyun case V4L2_CID_AUTOBRIGHTNESS:
4853*4882a593Smuzhiyun if (ctrl->is_new)
4854*4882a593Smuzhiyun setautobright(gspca_dev, ctrl->val);
4855*4882a593Smuzhiyun if (!ctrl->val && sd->brightness->is_new)
4856*4882a593Smuzhiyun setbrightness(gspca_dev, sd->brightness->val);
4857*4882a593Smuzhiyun break;
4858*4882a593Smuzhiyun case V4L2_CID_SATURATION:
4859*4882a593Smuzhiyun setcolors(gspca_dev, ctrl->val);
4860*4882a593Smuzhiyun break;
4861*4882a593Smuzhiyun case V4L2_CID_HFLIP:
4862*4882a593Smuzhiyun sethvflip(gspca_dev, ctrl->val, sd->vflip->val);
4863*4882a593Smuzhiyun break;
4864*4882a593Smuzhiyun case V4L2_CID_AUTOGAIN:
4865*4882a593Smuzhiyun if (ctrl->is_new)
4866*4882a593Smuzhiyun setautogain(gspca_dev, ctrl->val);
4867*4882a593Smuzhiyun if (!ctrl->val && gspca_dev->exposure->is_new)
4868*4882a593Smuzhiyun setexposure(gspca_dev, gspca_dev->exposure->val);
4869*4882a593Smuzhiyun break;
4870*4882a593Smuzhiyun case V4L2_CID_JPEG_COMPRESSION_QUALITY:
4871*4882a593Smuzhiyun return -EBUSY; /* Should never happen, as we grab the ctrl */
4872*4882a593Smuzhiyun }
4873*4882a593Smuzhiyun return gspca_dev->usb_err;
4874*4882a593Smuzhiyun }
4875*4882a593Smuzhiyun
4876*4882a593Smuzhiyun static const struct v4l2_ctrl_ops sd_ctrl_ops = {
4877*4882a593Smuzhiyun .g_volatile_ctrl = sd_g_volatile_ctrl,
4878*4882a593Smuzhiyun .s_ctrl = sd_s_ctrl,
4879*4882a593Smuzhiyun };
4880*4882a593Smuzhiyun
sd_init_controls(struct gspca_dev * gspca_dev)4881*4882a593Smuzhiyun static int sd_init_controls(struct gspca_dev *gspca_dev)
4882*4882a593Smuzhiyun {
4883*4882a593Smuzhiyun struct sd *sd = (struct sd *)gspca_dev;
4884*4882a593Smuzhiyun struct v4l2_ctrl_handler *hdl = &gspca_dev->ctrl_handler;
4885*4882a593Smuzhiyun
4886*4882a593Smuzhiyun gspca_dev->vdev.ctrl_handler = hdl;
4887*4882a593Smuzhiyun v4l2_ctrl_handler_init(hdl, 10);
4888*4882a593Smuzhiyun if (valid_controls[sd->sensor].has_brightness)
4889*4882a593Smuzhiyun sd->brightness = v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
4890*4882a593Smuzhiyun V4L2_CID_BRIGHTNESS, 0,
4891*4882a593Smuzhiyun sd->sensor == SEN_OV7660 ? 6 : 255, 1,
4892*4882a593Smuzhiyun sd->sensor == SEN_OV7660 ? 3 : 127);
4893*4882a593Smuzhiyun if (valid_controls[sd->sensor].has_contrast) {
4894*4882a593Smuzhiyun if (sd->sensor == SEN_OV7660)
4895*4882a593Smuzhiyun v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
4896*4882a593Smuzhiyun V4L2_CID_CONTRAST, 0, 6, 1, 3);
4897*4882a593Smuzhiyun else
4898*4882a593Smuzhiyun v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
4899*4882a593Smuzhiyun V4L2_CID_CONTRAST, 0, 255, 1,
4900*4882a593Smuzhiyun (sd->sensor == SEN_OV6630 ||
4901*4882a593Smuzhiyun sd->sensor == SEN_OV66308AF) ? 200 : 127);
4902*4882a593Smuzhiyun }
4903*4882a593Smuzhiyun if (valid_controls[sd->sensor].has_sat)
4904*4882a593Smuzhiyun v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
4905*4882a593Smuzhiyun V4L2_CID_SATURATION, 0,
4906*4882a593Smuzhiyun sd->sensor == SEN_OV7660 ? 4 : 255, 1,
4907*4882a593Smuzhiyun sd->sensor == SEN_OV7660 ? 2 : 127);
4908*4882a593Smuzhiyun if (valid_controls[sd->sensor].has_exposure)
4909*4882a593Smuzhiyun gspca_dev->exposure = v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
4910*4882a593Smuzhiyun V4L2_CID_EXPOSURE, 0, 255, 1, 127);
4911*4882a593Smuzhiyun if (valid_controls[sd->sensor].has_hvflip) {
4912*4882a593Smuzhiyun sd->hflip = v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
4913*4882a593Smuzhiyun V4L2_CID_HFLIP, 0, 1, 1, 0);
4914*4882a593Smuzhiyun sd->vflip = v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
4915*4882a593Smuzhiyun V4L2_CID_VFLIP, 0, 1, 1, 0);
4916*4882a593Smuzhiyun }
4917*4882a593Smuzhiyun if (valid_controls[sd->sensor].has_autobright)
4918*4882a593Smuzhiyun sd->autobright = v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
4919*4882a593Smuzhiyun V4L2_CID_AUTOBRIGHTNESS, 0, 1, 1, 1);
4920*4882a593Smuzhiyun if (valid_controls[sd->sensor].has_autogain)
4921*4882a593Smuzhiyun gspca_dev->autogain = v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
4922*4882a593Smuzhiyun V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
4923*4882a593Smuzhiyun if (valid_controls[sd->sensor].has_freq) {
4924*4882a593Smuzhiyun if (sd->sensor == SEN_OV7670)
4925*4882a593Smuzhiyun sd->freq = v4l2_ctrl_new_std_menu(hdl, &sd_ctrl_ops,
4926*4882a593Smuzhiyun V4L2_CID_POWER_LINE_FREQUENCY,
4927*4882a593Smuzhiyun V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
4928*4882a593Smuzhiyun V4L2_CID_POWER_LINE_FREQUENCY_AUTO);
4929*4882a593Smuzhiyun else
4930*4882a593Smuzhiyun sd->freq = v4l2_ctrl_new_std_menu(hdl, &sd_ctrl_ops,
4931*4882a593Smuzhiyun V4L2_CID_POWER_LINE_FREQUENCY,
4932*4882a593Smuzhiyun V4L2_CID_POWER_LINE_FREQUENCY_60HZ, 0, 0);
4933*4882a593Smuzhiyun }
4934*4882a593Smuzhiyun if (sd->bridge == BRIDGE_W9968CF)
4935*4882a593Smuzhiyun sd->jpegqual = v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
4936*4882a593Smuzhiyun V4L2_CID_JPEG_COMPRESSION_QUALITY,
4937*4882a593Smuzhiyun QUALITY_MIN, QUALITY_MAX, 1, QUALITY_DEF);
4938*4882a593Smuzhiyun
4939*4882a593Smuzhiyun if (hdl->error) {
4940*4882a593Smuzhiyun gspca_err(gspca_dev, "Could not initialize controls\n");
4941*4882a593Smuzhiyun return hdl->error;
4942*4882a593Smuzhiyun }
4943*4882a593Smuzhiyun if (gspca_dev->autogain)
4944*4882a593Smuzhiyun v4l2_ctrl_auto_cluster(3, &gspca_dev->autogain, 0, true);
4945*4882a593Smuzhiyun if (sd->autobright)
4946*4882a593Smuzhiyun v4l2_ctrl_auto_cluster(2, &sd->autobright, 0, false);
4947*4882a593Smuzhiyun if (sd->hflip)
4948*4882a593Smuzhiyun v4l2_ctrl_cluster(2, &sd->hflip);
4949*4882a593Smuzhiyun return 0;
4950*4882a593Smuzhiyun }
4951*4882a593Smuzhiyun
4952*4882a593Smuzhiyun /* sub-driver description */
4953*4882a593Smuzhiyun static const struct sd_desc sd_desc = {
4954*4882a593Smuzhiyun .name = MODULE_NAME,
4955*4882a593Smuzhiyun .config = sd_config,
4956*4882a593Smuzhiyun .init = sd_init,
4957*4882a593Smuzhiyun .init_controls = sd_init_controls,
4958*4882a593Smuzhiyun .isoc_init = sd_isoc_init,
4959*4882a593Smuzhiyun .start = sd_start,
4960*4882a593Smuzhiyun .stopN = sd_stopN,
4961*4882a593Smuzhiyun .stop0 = sd_stop0,
4962*4882a593Smuzhiyun .pkt_scan = sd_pkt_scan,
4963*4882a593Smuzhiyun .dq_callback = sd_reset_snapshot,
4964*4882a593Smuzhiyun .get_jcomp = sd_get_jcomp,
4965*4882a593Smuzhiyun .set_jcomp = sd_set_jcomp,
4966*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_INPUT)
4967*4882a593Smuzhiyun .other_input = 1,
4968*4882a593Smuzhiyun #endif
4969*4882a593Smuzhiyun };
4970*4882a593Smuzhiyun
4971*4882a593Smuzhiyun /* -- module initialisation -- */
4972*4882a593Smuzhiyun static const struct usb_device_id device_table[] = {
4973*4882a593Smuzhiyun {USB_DEVICE(0x041e, 0x4003), .driver_info = BRIDGE_W9968CF },
4974*4882a593Smuzhiyun {USB_DEVICE(0x041e, 0x4052),
4975*4882a593Smuzhiyun .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
4976*4882a593Smuzhiyun {USB_DEVICE(0x041e, 0x405f), .driver_info = BRIDGE_OV519 },
4977*4882a593Smuzhiyun {USB_DEVICE(0x041e, 0x4060), .driver_info = BRIDGE_OV519 },
4978*4882a593Smuzhiyun {USB_DEVICE(0x041e, 0x4061), .driver_info = BRIDGE_OV519 },
4979*4882a593Smuzhiyun {USB_DEVICE(0x041e, 0x4064), .driver_info = BRIDGE_OV519 },
4980*4882a593Smuzhiyun {USB_DEVICE(0x041e, 0x4067), .driver_info = BRIDGE_OV519 },
4981*4882a593Smuzhiyun {USB_DEVICE(0x041e, 0x4068), .driver_info = BRIDGE_OV519 },
4982*4882a593Smuzhiyun {USB_DEVICE(0x045e, 0x028c),
4983*4882a593Smuzhiyun .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
4984*4882a593Smuzhiyun {USB_DEVICE(0x054c, 0x0154), .driver_info = BRIDGE_OV519 },
4985*4882a593Smuzhiyun {USB_DEVICE(0x054c, 0x0155), .driver_info = BRIDGE_OV519 },
4986*4882a593Smuzhiyun {USB_DEVICE(0x05a9, 0x0511), .driver_info = BRIDGE_OV511 },
4987*4882a593Smuzhiyun {USB_DEVICE(0x05a9, 0x0518), .driver_info = BRIDGE_OV518 },
4988*4882a593Smuzhiyun {USB_DEVICE(0x05a9, 0x0519),
4989*4882a593Smuzhiyun .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
4990*4882a593Smuzhiyun {USB_DEVICE(0x05a9, 0x0530),
4991*4882a593Smuzhiyun .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
4992*4882a593Smuzhiyun {USB_DEVICE(0x05a9, 0x2800), .driver_info = BRIDGE_OVFX2 },
4993*4882a593Smuzhiyun {USB_DEVICE(0x05a9, 0x4519), .driver_info = BRIDGE_OV519 },
4994*4882a593Smuzhiyun {USB_DEVICE(0x05a9, 0x8519), .driver_info = BRIDGE_OV519 },
4995*4882a593Smuzhiyun {USB_DEVICE(0x05a9, 0xa511), .driver_info = BRIDGE_OV511PLUS },
4996*4882a593Smuzhiyun {USB_DEVICE(0x05a9, 0xa518), .driver_info = BRIDGE_OV518PLUS },
4997*4882a593Smuzhiyun {USB_DEVICE(0x0813, 0x0002), .driver_info = BRIDGE_OV511PLUS },
4998*4882a593Smuzhiyun {USB_DEVICE(0x0b62, 0x0059), .driver_info = BRIDGE_OVFX2 },
4999*4882a593Smuzhiyun {USB_DEVICE(0x0e96, 0xc001), .driver_info = BRIDGE_OVFX2 },
5000*4882a593Smuzhiyun {USB_DEVICE(0x1046, 0x9967), .driver_info = BRIDGE_W9968CF },
5001*4882a593Smuzhiyun {USB_DEVICE(0x8020, 0xef04), .driver_info = BRIDGE_OVFX2 },
5002*4882a593Smuzhiyun {}
5003*4882a593Smuzhiyun };
5004*4882a593Smuzhiyun
5005*4882a593Smuzhiyun MODULE_DEVICE_TABLE(usb, device_table);
5006*4882a593Smuzhiyun
5007*4882a593Smuzhiyun /* -- device connect -- */
sd_probe(struct usb_interface * intf,const struct usb_device_id * id)5008*4882a593Smuzhiyun static int sd_probe(struct usb_interface *intf,
5009*4882a593Smuzhiyun const struct usb_device_id *id)
5010*4882a593Smuzhiyun {
5011*4882a593Smuzhiyun return gspca_dev_probe(intf, id, &sd_desc, sizeof(struct sd),
5012*4882a593Smuzhiyun THIS_MODULE);
5013*4882a593Smuzhiyun }
5014*4882a593Smuzhiyun
5015*4882a593Smuzhiyun static struct usb_driver sd_driver = {
5016*4882a593Smuzhiyun .name = MODULE_NAME,
5017*4882a593Smuzhiyun .id_table = device_table,
5018*4882a593Smuzhiyun .probe = sd_probe,
5019*4882a593Smuzhiyun .disconnect = gspca_disconnect,
5020*4882a593Smuzhiyun #ifdef CONFIG_PM
5021*4882a593Smuzhiyun .suspend = gspca_suspend,
5022*4882a593Smuzhiyun .resume = gspca_resume,
5023*4882a593Smuzhiyun .reset_resume = gspca_resume,
5024*4882a593Smuzhiyun #endif
5025*4882a593Smuzhiyun };
5026*4882a593Smuzhiyun
5027*4882a593Smuzhiyun module_usb_driver(sd_driver);
5028*4882a593Smuzhiyun
5029*4882a593Smuzhiyun module_param(frame_rate, int, 0644);
5030*4882a593Smuzhiyun MODULE_PARM_DESC(frame_rate, "Frame rate (5, 10, 15, 20 or 30 fps)");
5031