1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun /*
4*4882a593Smuzhiyun * Driver for the ov9650 sensor
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2008 Erik Andrén
7*4882a593Smuzhiyun * Copyright (C) 2007 Ilyes Gouta. Based on the m5603x Linux Driver Project.
8*4882a593Smuzhiyun * Copyright (C) 2005 m5603x Linux Driver Project <m5602@x3ng.com.br>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Portions of code to USB interface and ALi driver software,
11*4882a593Smuzhiyun * Copyright (c) 2006 Willem Duinker
12*4882a593Smuzhiyun * v4l2 interface modeled after the V4L2 driver
13*4882a593Smuzhiyun * for SN9C10x PC Camera Controllers
14*4882a593Smuzhiyun */
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "m5602_ov9650.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun static int ov9650_s_ctrl(struct v4l2_ctrl *ctrl);
21*4882a593Smuzhiyun static void ov9650_dump_registers(struct sd *sd);
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun static const unsigned char preinit_ov9650[][3] = {
24*4882a593Smuzhiyun /* [INITCAM] */
25*4882a593Smuzhiyun {BRIDGE, M5602_XB_MCU_CLK_DIV, 0x02},
26*4882a593Smuzhiyun {BRIDGE, M5602_XB_MCU_CLK_CTRL, 0xb0},
27*4882a593Smuzhiyun {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00},
28*4882a593Smuzhiyun {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
29*4882a593Smuzhiyun {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
30*4882a593Smuzhiyun {BRIDGE, M5602_XB_SENSOR_CTRL, 0x00},
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun {BRIDGE, M5602_XB_SENSOR_TYPE, 0x08},
33*4882a593Smuzhiyun {BRIDGE, M5602_XB_GPIO_DIR, 0x05},
34*4882a593Smuzhiyun {BRIDGE, M5602_XB_GPIO_DAT, 0x04},
35*4882a593Smuzhiyun {BRIDGE, M5602_XB_GPIO_EN_H, 0x06},
36*4882a593Smuzhiyun {BRIDGE, M5602_XB_GPIO_DIR_H, 0x06},
37*4882a593Smuzhiyun {BRIDGE, M5602_XB_GPIO_DAT_H, 0x00},
38*4882a593Smuzhiyun {BRIDGE, M5602_XB_GPIO_DAT, 0x00},
39*4882a593Smuzhiyun {BRIDGE, M5602_XB_I2C_CLK_DIV, 0x0a},
40*4882a593Smuzhiyun /* Reset chip */
41*4882a593Smuzhiyun {SENSOR, OV9650_COM7, OV9650_REGISTER_RESET},
42*4882a593Smuzhiyun /* Enable double clock */
43*4882a593Smuzhiyun {SENSOR, OV9650_CLKRC, 0x80},
44*4882a593Smuzhiyun /* Do something out of spec with the power */
45*4882a593Smuzhiyun {SENSOR, OV9650_OFON, 0x40}
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun static const unsigned char init_ov9650[][3] = {
49*4882a593Smuzhiyun /* [INITCAM] */
50*4882a593Smuzhiyun {BRIDGE, M5602_XB_MCU_CLK_DIV, 0x02},
51*4882a593Smuzhiyun {BRIDGE, M5602_XB_MCU_CLK_CTRL, 0xb0},
52*4882a593Smuzhiyun {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00},
53*4882a593Smuzhiyun {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
54*4882a593Smuzhiyun {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
55*4882a593Smuzhiyun {BRIDGE, M5602_XB_SENSOR_CTRL, 0x00},
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun {BRIDGE, M5602_XB_SENSOR_TYPE, 0x08},
58*4882a593Smuzhiyun {BRIDGE, M5602_XB_GPIO_DIR, 0x05},
59*4882a593Smuzhiyun {BRIDGE, M5602_XB_GPIO_DAT, 0x04},
60*4882a593Smuzhiyun {BRIDGE, M5602_XB_GPIO_EN_H, 0x06},
61*4882a593Smuzhiyun {BRIDGE, M5602_XB_GPIO_DIR_H, 0x06},
62*4882a593Smuzhiyun {BRIDGE, M5602_XB_GPIO_DAT_H, 0x00},
63*4882a593Smuzhiyun {BRIDGE, M5602_XB_GPIO_DAT, 0x00},
64*4882a593Smuzhiyun {BRIDGE, M5602_XB_I2C_CLK_DIV, 0x0a},
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Reset chip */
67*4882a593Smuzhiyun {SENSOR, OV9650_COM7, OV9650_REGISTER_RESET},
68*4882a593Smuzhiyun /* One extra reset is needed in order to make the sensor behave
69*4882a593Smuzhiyun properly when resuming from ram, could be a timing issue */
70*4882a593Smuzhiyun {SENSOR, OV9650_COM7, OV9650_REGISTER_RESET},
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Enable double clock */
73*4882a593Smuzhiyun {SENSOR, OV9650_CLKRC, 0x80},
74*4882a593Smuzhiyun /* Do something out of spec with the power */
75*4882a593Smuzhiyun {SENSOR, OV9650_OFON, 0x40},
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* Set fast AGC/AEC algorithm with unlimited step size */
78*4882a593Smuzhiyun {SENSOR, OV9650_COM8, OV9650_FAST_AGC_AEC |
79*4882a593Smuzhiyun OV9650_AEC_UNLIM_STEP_SIZE},
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun {SENSOR, OV9650_CHLF, 0x10},
82*4882a593Smuzhiyun {SENSOR, OV9650_ARBLM, 0xbf},
83*4882a593Smuzhiyun {SENSOR, OV9650_ACOM38, 0x81},
84*4882a593Smuzhiyun /* Turn off color matrix coefficient double option */
85*4882a593Smuzhiyun {SENSOR, OV9650_COM16, 0x00},
86*4882a593Smuzhiyun /* Enable color matrix for RGB/YUV, Delay Y channel,
87*4882a593Smuzhiyun set output Y/UV delay to 1 */
88*4882a593Smuzhiyun {SENSOR, OV9650_COM13, 0x19},
89*4882a593Smuzhiyun /* Enable digital BLC, Set output mode to U Y V Y */
90*4882a593Smuzhiyun {SENSOR, OV9650_TSLB, 0x0c},
91*4882a593Smuzhiyun /* Limit the AGC/AEC stable upper region */
92*4882a593Smuzhiyun {SENSOR, OV9650_COM24, 0x00},
93*4882a593Smuzhiyun /* Enable HREF and some out of spec things */
94*4882a593Smuzhiyun {SENSOR, OV9650_COM12, 0x73},
95*4882a593Smuzhiyun /* Set all DBLC offset signs to positive and
96*4882a593Smuzhiyun do some out of spec stuff */
97*4882a593Smuzhiyun {SENSOR, OV9650_DBLC1, 0xdf},
98*4882a593Smuzhiyun {SENSOR, OV9650_COM21, 0x06},
99*4882a593Smuzhiyun {SENSOR, OV9650_RSVD35, 0x91},
100*4882a593Smuzhiyun /* Necessary, no camera stream without it */
101*4882a593Smuzhiyun {SENSOR, OV9650_RSVD16, 0x06},
102*4882a593Smuzhiyun {SENSOR, OV9650_RSVD94, 0x99},
103*4882a593Smuzhiyun {SENSOR, OV9650_RSVD95, 0x99},
104*4882a593Smuzhiyun {SENSOR, OV9650_RSVD96, 0x04},
105*4882a593Smuzhiyun /* Enable full range output */
106*4882a593Smuzhiyun {SENSOR, OV9650_COM15, 0x0},
107*4882a593Smuzhiyun /* Enable HREF at optical black, enable ADBLC bias,
108*4882a593Smuzhiyun enable ADBLC, reset timings at format change */
109*4882a593Smuzhiyun {SENSOR, OV9650_COM6, 0x4b},
110*4882a593Smuzhiyun /* Subtract 32 from the B channel bias */
111*4882a593Smuzhiyun {SENSOR, OV9650_BBIAS, 0xa0},
112*4882a593Smuzhiyun /* Subtract 32 from the Gb channel bias */
113*4882a593Smuzhiyun {SENSOR, OV9650_GbBIAS, 0xa0},
114*4882a593Smuzhiyun /* Do not bypass the analog BLC and to some out of spec stuff */
115*4882a593Smuzhiyun {SENSOR, OV9650_Gr_COM, 0x00},
116*4882a593Smuzhiyun /* Subtract 32 from the R channel bias */
117*4882a593Smuzhiyun {SENSOR, OV9650_RBIAS, 0xa0},
118*4882a593Smuzhiyun /* Subtract 32 from the R channel bias */
119*4882a593Smuzhiyun {SENSOR, OV9650_RBIAS, 0x0},
120*4882a593Smuzhiyun {SENSOR, OV9650_COM26, 0x80},
121*4882a593Smuzhiyun {SENSOR, OV9650_ACOMA9, 0x98},
122*4882a593Smuzhiyun /* Set the AGC/AEC stable region upper limit */
123*4882a593Smuzhiyun {SENSOR, OV9650_AEW, 0x68},
124*4882a593Smuzhiyun /* Set the AGC/AEC stable region lower limit */
125*4882a593Smuzhiyun {SENSOR, OV9650_AEB, 0x5c},
126*4882a593Smuzhiyun /* Set the high and low limit nibbles to 3 */
127*4882a593Smuzhiyun {SENSOR, OV9650_VPT, 0xc3},
128*4882a593Smuzhiyun /* Set the Automatic Gain Ceiling (AGC) to 128x,
129*4882a593Smuzhiyun drop VSYNC at frame drop,
130*4882a593Smuzhiyun limit exposure timing,
131*4882a593Smuzhiyun drop frame when the AEC step is larger than the exposure gap */
132*4882a593Smuzhiyun {SENSOR, OV9650_COM9, 0x6e},
133*4882a593Smuzhiyun /* Set VSYNC negative, Set RESET to SLHS (slave mode horizontal sync)
134*4882a593Smuzhiyun and set PWDN to SLVS (slave mode vertical sync) */
135*4882a593Smuzhiyun {SENSOR, OV9650_COM10, 0x42},
136*4882a593Smuzhiyun /* Set horizontal column start high to default value */
137*4882a593Smuzhiyun {SENSOR, OV9650_HSTART, 0x1a}, /* 210 */
138*4882a593Smuzhiyun /* Set horizontal column end */
139*4882a593Smuzhiyun {SENSOR, OV9650_HSTOP, 0xbf}, /* 1534 */
140*4882a593Smuzhiyun /* Complementing register to the two writes above */
141*4882a593Smuzhiyun {SENSOR, OV9650_HREF, 0xb2},
142*4882a593Smuzhiyun /* Set vertical row start high bits */
143*4882a593Smuzhiyun {SENSOR, OV9650_VSTRT, 0x02},
144*4882a593Smuzhiyun /* Set vertical row end low bits */
145*4882a593Smuzhiyun {SENSOR, OV9650_VSTOP, 0x7e},
146*4882a593Smuzhiyun /* Set complementing vertical frame control */
147*4882a593Smuzhiyun {SENSOR, OV9650_VREF, 0x10},
148*4882a593Smuzhiyun {SENSOR, OV9650_ADC, 0x04},
149*4882a593Smuzhiyun {SENSOR, OV9650_HV, 0x40},
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun /* Enable denoise, and white-pixel erase */
152*4882a593Smuzhiyun {SENSOR, OV9650_COM22, OV9650_DENOISE_ENABLE |
153*4882a593Smuzhiyun OV9650_WHITE_PIXEL_ENABLE |
154*4882a593Smuzhiyun OV9650_WHITE_PIXEL_OPTION},
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun /* Enable VARIOPIXEL */
157*4882a593Smuzhiyun {SENSOR, OV9650_COM3, OV9650_VARIOPIXEL},
158*4882a593Smuzhiyun {SENSOR, OV9650_COM4, OV9650_QVGA_VARIOPIXEL},
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun /* Put the sensor in soft sleep mode */
161*4882a593Smuzhiyun {SENSOR, OV9650_COM2, OV9650_SOFT_SLEEP | OV9650_OUTPUT_DRIVE_2X},
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun static const unsigned char res_init_ov9650[][3] = {
165*4882a593Smuzhiyun {SENSOR, OV9650_COM2, OV9650_OUTPUT_DRIVE_2X},
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun {BRIDGE, M5602_XB_LINE_OF_FRAME_H, 0x82},
168*4882a593Smuzhiyun {BRIDGE, M5602_XB_LINE_OF_FRAME_L, 0x00},
169*4882a593Smuzhiyun {BRIDGE, M5602_XB_PIX_OF_LINE_H, 0x82},
170*4882a593Smuzhiyun {BRIDGE, M5602_XB_PIX_OF_LINE_L, 0x00},
171*4882a593Smuzhiyun {BRIDGE, M5602_XB_SIG_INI, 0x01}
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun /* Vertically and horizontally flips the image if matched, needed for machines
175*4882a593Smuzhiyun where the sensor is mounted upside down */
176*4882a593Smuzhiyun static
177*4882a593Smuzhiyun const
178*4882a593Smuzhiyun struct dmi_system_id ov9650_flip_dmi_table[] = {
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun .ident = "ASUS A6Ja",
181*4882a593Smuzhiyun .matches = {
182*4882a593Smuzhiyun DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
183*4882a593Smuzhiyun DMI_MATCH(DMI_PRODUCT_NAME, "A6J")
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun },
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun .ident = "ASUS A6JC",
188*4882a593Smuzhiyun .matches = {
189*4882a593Smuzhiyun DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
190*4882a593Smuzhiyun DMI_MATCH(DMI_PRODUCT_NAME, "A6JC")
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun },
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun .ident = "ASUS A6K",
195*4882a593Smuzhiyun .matches = {
196*4882a593Smuzhiyun DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
197*4882a593Smuzhiyun DMI_MATCH(DMI_PRODUCT_NAME, "A6K")
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun },
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun .ident = "ASUS A6Kt",
202*4882a593Smuzhiyun .matches = {
203*4882a593Smuzhiyun DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
204*4882a593Smuzhiyun DMI_MATCH(DMI_PRODUCT_NAME, "A6Kt")
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun },
207*4882a593Smuzhiyun {
208*4882a593Smuzhiyun .ident = "ASUS A6VA",
209*4882a593Smuzhiyun .matches = {
210*4882a593Smuzhiyun DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
211*4882a593Smuzhiyun DMI_MATCH(DMI_PRODUCT_NAME, "A6VA")
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun },
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun .ident = "ASUS A6VC",
217*4882a593Smuzhiyun .matches = {
218*4882a593Smuzhiyun DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
219*4882a593Smuzhiyun DMI_MATCH(DMI_PRODUCT_NAME, "A6VC")
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun },
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun .ident = "ASUS A6VM",
224*4882a593Smuzhiyun .matches = {
225*4882a593Smuzhiyun DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
226*4882a593Smuzhiyun DMI_MATCH(DMI_PRODUCT_NAME, "A6VM")
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun },
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun .ident = "ASUS A7V",
231*4882a593Smuzhiyun .matches = {
232*4882a593Smuzhiyun DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
233*4882a593Smuzhiyun DMI_MATCH(DMI_PRODUCT_NAME, "A7V")
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun },
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun .ident = "Alienware Aurora m9700",
238*4882a593Smuzhiyun .matches = {
239*4882a593Smuzhiyun DMI_MATCH(DMI_SYS_VENDOR, "alienware"),
240*4882a593Smuzhiyun DMI_MATCH(DMI_PRODUCT_NAME, "Aurora m9700")
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun },
243*4882a593Smuzhiyun {}
244*4882a593Smuzhiyun };
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun static struct v4l2_pix_format ov9650_modes[] = {
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun 176,
249*4882a593Smuzhiyun 144,
250*4882a593Smuzhiyun V4L2_PIX_FMT_SBGGR8,
251*4882a593Smuzhiyun V4L2_FIELD_NONE,
252*4882a593Smuzhiyun .sizeimage =
253*4882a593Smuzhiyun 176 * 144,
254*4882a593Smuzhiyun .bytesperline = 176,
255*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_SRGB,
256*4882a593Smuzhiyun .priv = 9
257*4882a593Smuzhiyun }, {
258*4882a593Smuzhiyun 320,
259*4882a593Smuzhiyun 240,
260*4882a593Smuzhiyun V4L2_PIX_FMT_SBGGR8,
261*4882a593Smuzhiyun V4L2_FIELD_NONE,
262*4882a593Smuzhiyun .sizeimage =
263*4882a593Smuzhiyun 320 * 240,
264*4882a593Smuzhiyun .bytesperline = 320,
265*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_SRGB,
266*4882a593Smuzhiyun .priv = 8
267*4882a593Smuzhiyun }, {
268*4882a593Smuzhiyun 352,
269*4882a593Smuzhiyun 288,
270*4882a593Smuzhiyun V4L2_PIX_FMT_SBGGR8,
271*4882a593Smuzhiyun V4L2_FIELD_NONE,
272*4882a593Smuzhiyun .sizeimage =
273*4882a593Smuzhiyun 352 * 288,
274*4882a593Smuzhiyun .bytesperline = 352,
275*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_SRGB,
276*4882a593Smuzhiyun .priv = 9
277*4882a593Smuzhiyun }, {
278*4882a593Smuzhiyun 640,
279*4882a593Smuzhiyun 480,
280*4882a593Smuzhiyun V4L2_PIX_FMT_SBGGR8,
281*4882a593Smuzhiyun V4L2_FIELD_NONE,
282*4882a593Smuzhiyun .sizeimage =
283*4882a593Smuzhiyun 640 * 480,
284*4882a593Smuzhiyun .bytesperline = 640,
285*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_SRGB,
286*4882a593Smuzhiyun .priv = 9
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun };
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun static const struct v4l2_ctrl_ops ov9650_ctrl_ops = {
291*4882a593Smuzhiyun .s_ctrl = ov9650_s_ctrl,
292*4882a593Smuzhiyun };
293*4882a593Smuzhiyun
ov9650_probe(struct sd * sd)294*4882a593Smuzhiyun int ov9650_probe(struct sd *sd)
295*4882a593Smuzhiyun {
296*4882a593Smuzhiyun int err = 0;
297*4882a593Smuzhiyun u8 prod_id = 0, ver_id = 0, i;
298*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun if (force_sensor) {
301*4882a593Smuzhiyun if (force_sensor == OV9650_SENSOR) {
302*4882a593Smuzhiyun pr_info("Forcing an %s sensor\n", ov9650.name);
303*4882a593Smuzhiyun goto sensor_found;
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun /* If we want to force another sensor,
306*4882a593Smuzhiyun don't try to probe this one */
307*4882a593Smuzhiyun return -ENODEV;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_PROBE, "Probing for an ov9650 sensor\n");
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun /* Run the pre-init before probing the sensor */
313*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(preinit_ov9650) && !err; i++) {
314*4882a593Smuzhiyun u8 data = preinit_ov9650[i][2];
315*4882a593Smuzhiyun if (preinit_ov9650[i][0] == SENSOR)
316*4882a593Smuzhiyun err = m5602_write_sensor(sd,
317*4882a593Smuzhiyun preinit_ov9650[i][1], &data, 1);
318*4882a593Smuzhiyun else
319*4882a593Smuzhiyun err = m5602_write_bridge(sd,
320*4882a593Smuzhiyun preinit_ov9650[i][1], data);
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun if (err < 0)
324*4882a593Smuzhiyun return err;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun if (m5602_read_sensor(sd, OV9650_PID, &prod_id, 1))
327*4882a593Smuzhiyun return -ENODEV;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun if (m5602_read_sensor(sd, OV9650_VER, &ver_id, 1))
330*4882a593Smuzhiyun return -ENODEV;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun if ((prod_id == 0x96) && (ver_id == 0x52)) {
333*4882a593Smuzhiyun pr_info("Detected an ov9650 sensor\n");
334*4882a593Smuzhiyun goto sensor_found;
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun return -ENODEV;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun sensor_found:
339*4882a593Smuzhiyun sd->gspca_dev.cam.cam_mode = ov9650_modes;
340*4882a593Smuzhiyun sd->gspca_dev.cam.nmodes = ARRAY_SIZE(ov9650_modes);
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun return 0;
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
ov9650_init(struct sd * sd)345*4882a593Smuzhiyun int ov9650_init(struct sd *sd)
346*4882a593Smuzhiyun {
347*4882a593Smuzhiyun int i, err = 0;
348*4882a593Smuzhiyun u8 data;
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun if (dump_sensor)
351*4882a593Smuzhiyun ov9650_dump_registers(sd);
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(init_ov9650) && !err; i++) {
354*4882a593Smuzhiyun data = init_ov9650[i][2];
355*4882a593Smuzhiyun if (init_ov9650[i][0] == SENSOR)
356*4882a593Smuzhiyun err = m5602_write_sensor(sd, init_ov9650[i][1],
357*4882a593Smuzhiyun &data, 1);
358*4882a593Smuzhiyun else
359*4882a593Smuzhiyun err = m5602_write_bridge(sd, init_ov9650[i][1], data);
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun return 0;
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun
ov9650_init_controls(struct sd * sd)365*4882a593Smuzhiyun int ov9650_init_controls(struct sd *sd)
366*4882a593Smuzhiyun {
367*4882a593Smuzhiyun struct v4l2_ctrl_handler *hdl = &sd->gspca_dev.ctrl_handler;
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun sd->gspca_dev.vdev.ctrl_handler = hdl;
370*4882a593Smuzhiyun v4l2_ctrl_handler_init(hdl, 9);
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun sd->auto_white_bal = v4l2_ctrl_new_std(hdl, &ov9650_ctrl_ops,
373*4882a593Smuzhiyun V4L2_CID_AUTO_WHITE_BALANCE,
374*4882a593Smuzhiyun 0, 1, 1, 1);
375*4882a593Smuzhiyun sd->red_bal = v4l2_ctrl_new_std(hdl, &ov9650_ctrl_ops,
376*4882a593Smuzhiyun V4L2_CID_RED_BALANCE, 0, 255, 1,
377*4882a593Smuzhiyun RED_GAIN_DEFAULT);
378*4882a593Smuzhiyun sd->blue_bal = v4l2_ctrl_new_std(hdl, &ov9650_ctrl_ops,
379*4882a593Smuzhiyun V4L2_CID_BLUE_BALANCE, 0, 255, 1,
380*4882a593Smuzhiyun BLUE_GAIN_DEFAULT);
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun sd->autoexpo = v4l2_ctrl_new_std_menu(hdl, &ov9650_ctrl_ops,
383*4882a593Smuzhiyun V4L2_CID_EXPOSURE_AUTO, 1, 0, V4L2_EXPOSURE_AUTO);
384*4882a593Smuzhiyun sd->expo = v4l2_ctrl_new_std(hdl, &ov9650_ctrl_ops, V4L2_CID_EXPOSURE,
385*4882a593Smuzhiyun 0, 0x1ff, 4, EXPOSURE_DEFAULT);
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun sd->autogain = v4l2_ctrl_new_std(hdl, &ov9650_ctrl_ops,
388*4882a593Smuzhiyun V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
389*4882a593Smuzhiyun sd->gain = v4l2_ctrl_new_std(hdl, &ov9650_ctrl_ops, V4L2_CID_GAIN, 0,
390*4882a593Smuzhiyun 0x3ff, 1, GAIN_DEFAULT);
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun sd->hflip = v4l2_ctrl_new_std(hdl, &ov9650_ctrl_ops, V4L2_CID_HFLIP,
393*4882a593Smuzhiyun 0, 1, 1, 0);
394*4882a593Smuzhiyun sd->vflip = v4l2_ctrl_new_std(hdl, &ov9650_ctrl_ops, V4L2_CID_VFLIP,
395*4882a593Smuzhiyun 0, 1, 1, 0);
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun if (hdl->error) {
398*4882a593Smuzhiyun pr_err("Could not initialize controls\n");
399*4882a593Smuzhiyun return hdl->error;
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun v4l2_ctrl_auto_cluster(3, &sd->auto_white_bal, 0, false);
403*4882a593Smuzhiyun v4l2_ctrl_auto_cluster(2, &sd->autoexpo, 0, false);
404*4882a593Smuzhiyun v4l2_ctrl_auto_cluster(2, &sd->autogain, 0, false);
405*4882a593Smuzhiyun v4l2_ctrl_cluster(2, &sd->hflip);
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun return 0;
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun
ov9650_start(struct sd * sd)410*4882a593Smuzhiyun int ov9650_start(struct sd *sd)
411*4882a593Smuzhiyun {
412*4882a593Smuzhiyun u8 data;
413*4882a593Smuzhiyun int i, err = 0;
414*4882a593Smuzhiyun struct cam *cam = &sd->gspca_dev.cam;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun int width = cam->cam_mode[sd->gspca_dev.curr_mode].width;
417*4882a593Smuzhiyun int height = cam->cam_mode[sd->gspca_dev.curr_mode].height;
418*4882a593Smuzhiyun int ver_offs = cam->cam_mode[sd->gspca_dev.curr_mode].priv;
419*4882a593Smuzhiyun int hor_offs = OV9650_LEFT_OFFSET;
420*4882a593Smuzhiyun struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun if ((!dmi_check_system(ov9650_flip_dmi_table) &&
423*4882a593Smuzhiyun sd->vflip->val) ||
424*4882a593Smuzhiyun (dmi_check_system(ov9650_flip_dmi_table) &&
425*4882a593Smuzhiyun !sd->vflip->val))
426*4882a593Smuzhiyun ver_offs--;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun if (width <= 320)
429*4882a593Smuzhiyun hor_offs /= 2;
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun /* Synthesize the vsync/hsync setup */
432*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(res_init_ov9650) && !err; i++) {
433*4882a593Smuzhiyun if (res_init_ov9650[i][0] == BRIDGE)
434*4882a593Smuzhiyun err = m5602_write_bridge(sd, res_init_ov9650[i][1],
435*4882a593Smuzhiyun res_init_ov9650[i][2]);
436*4882a593Smuzhiyun else if (res_init_ov9650[i][0] == SENSOR) {
437*4882a593Smuzhiyun data = res_init_ov9650[i][2];
438*4882a593Smuzhiyun err = m5602_write_sensor(sd,
439*4882a593Smuzhiyun res_init_ov9650[i][1], &data, 1);
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun if (err < 0)
443*4882a593Smuzhiyun return err;
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA,
446*4882a593Smuzhiyun ((ver_offs >> 8) & 0xff));
447*4882a593Smuzhiyun if (err < 0)
448*4882a593Smuzhiyun return err;
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA, (ver_offs & 0xff));
451*4882a593Smuzhiyun if (err < 0)
452*4882a593Smuzhiyun return err;
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA, 0);
455*4882a593Smuzhiyun if (err < 0)
456*4882a593Smuzhiyun return err;
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA, (height >> 8) & 0xff);
459*4882a593Smuzhiyun if (err < 0)
460*4882a593Smuzhiyun return err;
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA, (height & 0xff));
463*4882a593Smuzhiyun if (err < 0)
464*4882a593Smuzhiyun return err;
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun for (i = 0; i < 2 && !err; i++)
467*4882a593Smuzhiyun err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA, 0);
468*4882a593Smuzhiyun if (err < 0)
469*4882a593Smuzhiyun return err;
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun err = m5602_write_bridge(sd, M5602_XB_SIG_INI, 0);
472*4882a593Smuzhiyun if (err < 0)
473*4882a593Smuzhiyun return err;
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun err = m5602_write_bridge(sd, M5602_XB_SIG_INI, 2);
476*4882a593Smuzhiyun if (err < 0)
477*4882a593Smuzhiyun return err;
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun err = m5602_write_bridge(sd, M5602_XB_HSYNC_PARA,
480*4882a593Smuzhiyun (hor_offs >> 8) & 0xff);
481*4882a593Smuzhiyun if (err < 0)
482*4882a593Smuzhiyun return err;
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun err = m5602_write_bridge(sd, M5602_XB_HSYNC_PARA, hor_offs & 0xff);
485*4882a593Smuzhiyun if (err < 0)
486*4882a593Smuzhiyun return err;
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun err = m5602_write_bridge(sd, M5602_XB_HSYNC_PARA,
489*4882a593Smuzhiyun ((width + hor_offs) >> 8) & 0xff);
490*4882a593Smuzhiyun if (err < 0)
491*4882a593Smuzhiyun return err;
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun err = m5602_write_bridge(sd, M5602_XB_HSYNC_PARA,
494*4882a593Smuzhiyun ((width + hor_offs) & 0xff));
495*4882a593Smuzhiyun if (err < 0)
496*4882a593Smuzhiyun return err;
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun err = m5602_write_bridge(sd, M5602_XB_SIG_INI, 0);
499*4882a593Smuzhiyun if (err < 0)
500*4882a593Smuzhiyun return err;
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun switch (width) {
503*4882a593Smuzhiyun case 640:
504*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_CONF, "Configuring camera for VGA mode\n");
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun data = OV9650_VGA_SELECT | OV9650_RGB_SELECT |
507*4882a593Smuzhiyun OV9650_RAW_RGB_SELECT;
508*4882a593Smuzhiyun err = m5602_write_sensor(sd, OV9650_COM7, &data, 1);
509*4882a593Smuzhiyun break;
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun case 352:
512*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_CONF, "Configuring camera for CIF mode\n");
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun data = OV9650_CIF_SELECT | OV9650_RGB_SELECT |
515*4882a593Smuzhiyun OV9650_RAW_RGB_SELECT;
516*4882a593Smuzhiyun err = m5602_write_sensor(sd, OV9650_COM7, &data, 1);
517*4882a593Smuzhiyun break;
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun case 320:
520*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_CONF, "Configuring camera for QVGA mode\n");
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun data = OV9650_QVGA_SELECT | OV9650_RGB_SELECT |
523*4882a593Smuzhiyun OV9650_RAW_RGB_SELECT;
524*4882a593Smuzhiyun err = m5602_write_sensor(sd, OV9650_COM7, &data, 1);
525*4882a593Smuzhiyun break;
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun case 176:
528*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_CONF, "Configuring camera for QCIF mode\n");
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun data = OV9650_QCIF_SELECT | OV9650_RGB_SELECT |
531*4882a593Smuzhiyun OV9650_RAW_RGB_SELECT;
532*4882a593Smuzhiyun err = m5602_write_sensor(sd, OV9650_COM7, &data, 1);
533*4882a593Smuzhiyun break;
534*4882a593Smuzhiyun }
535*4882a593Smuzhiyun return err;
536*4882a593Smuzhiyun }
537*4882a593Smuzhiyun
ov9650_stop(struct sd * sd)538*4882a593Smuzhiyun int ov9650_stop(struct sd *sd)
539*4882a593Smuzhiyun {
540*4882a593Smuzhiyun u8 data = OV9650_SOFT_SLEEP | OV9650_OUTPUT_DRIVE_2X;
541*4882a593Smuzhiyun return m5602_write_sensor(sd, OV9650_COM2, &data, 1);
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun
ov9650_disconnect(struct sd * sd)544*4882a593Smuzhiyun void ov9650_disconnect(struct sd *sd)
545*4882a593Smuzhiyun {
546*4882a593Smuzhiyun ov9650_stop(sd);
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun sd->sensor = NULL;
549*4882a593Smuzhiyun }
550*4882a593Smuzhiyun
ov9650_set_exposure(struct gspca_dev * gspca_dev,__s32 val)551*4882a593Smuzhiyun static int ov9650_set_exposure(struct gspca_dev *gspca_dev, __s32 val)
552*4882a593Smuzhiyun {
553*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
554*4882a593Smuzhiyun u8 i2c_data;
555*4882a593Smuzhiyun int err;
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_CONF, "Set exposure to %d\n", val);
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun /* The 6 MSBs */
560*4882a593Smuzhiyun i2c_data = (val >> 10) & 0x3f;
561*4882a593Smuzhiyun err = m5602_write_sensor(sd, OV9650_AECHM,
562*4882a593Smuzhiyun &i2c_data, 1);
563*4882a593Smuzhiyun if (err < 0)
564*4882a593Smuzhiyun return err;
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun /* The 8 middle bits */
567*4882a593Smuzhiyun i2c_data = (val >> 2) & 0xff;
568*4882a593Smuzhiyun err = m5602_write_sensor(sd, OV9650_AECH,
569*4882a593Smuzhiyun &i2c_data, 1);
570*4882a593Smuzhiyun if (err < 0)
571*4882a593Smuzhiyun return err;
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun /* The 2 LSBs */
574*4882a593Smuzhiyun i2c_data = val & 0x03;
575*4882a593Smuzhiyun err = m5602_write_sensor(sd, OV9650_COM1, &i2c_data, 1);
576*4882a593Smuzhiyun return err;
577*4882a593Smuzhiyun }
578*4882a593Smuzhiyun
ov9650_set_gain(struct gspca_dev * gspca_dev,__s32 val)579*4882a593Smuzhiyun static int ov9650_set_gain(struct gspca_dev *gspca_dev, __s32 val)
580*4882a593Smuzhiyun {
581*4882a593Smuzhiyun int err;
582*4882a593Smuzhiyun u8 i2c_data;
583*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_CONF, "Setting gain to %d\n", val);
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun /* The 2 MSB */
588*4882a593Smuzhiyun /* Read the OV9650_VREF register first to avoid
589*4882a593Smuzhiyun corrupting the VREF high and low bits */
590*4882a593Smuzhiyun err = m5602_read_sensor(sd, OV9650_VREF, &i2c_data, 1);
591*4882a593Smuzhiyun if (err < 0)
592*4882a593Smuzhiyun return err;
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun /* Mask away all uninteresting bits */
595*4882a593Smuzhiyun i2c_data = ((val & 0x0300) >> 2) |
596*4882a593Smuzhiyun (i2c_data & 0x3f);
597*4882a593Smuzhiyun err = m5602_write_sensor(sd, OV9650_VREF, &i2c_data, 1);
598*4882a593Smuzhiyun if (err < 0)
599*4882a593Smuzhiyun return err;
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun /* The 8 LSBs */
602*4882a593Smuzhiyun i2c_data = val & 0xff;
603*4882a593Smuzhiyun err = m5602_write_sensor(sd, OV9650_GAIN, &i2c_data, 1);
604*4882a593Smuzhiyun return err;
605*4882a593Smuzhiyun }
606*4882a593Smuzhiyun
ov9650_set_red_balance(struct gspca_dev * gspca_dev,__s32 val)607*4882a593Smuzhiyun static int ov9650_set_red_balance(struct gspca_dev *gspca_dev, __s32 val)
608*4882a593Smuzhiyun {
609*4882a593Smuzhiyun int err;
610*4882a593Smuzhiyun u8 i2c_data;
611*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_CONF, "Set red gain to %d\n", val);
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun i2c_data = val & 0xff;
616*4882a593Smuzhiyun err = m5602_write_sensor(sd, OV9650_RED, &i2c_data, 1);
617*4882a593Smuzhiyun return err;
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun
ov9650_set_blue_balance(struct gspca_dev * gspca_dev,__s32 val)620*4882a593Smuzhiyun static int ov9650_set_blue_balance(struct gspca_dev *gspca_dev, __s32 val)
621*4882a593Smuzhiyun {
622*4882a593Smuzhiyun int err;
623*4882a593Smuzhiyun u8 i2c_data;
624*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_CONF, "Set blue gain to %d\n", val);
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun i2c_data = val & 0xff;
629*4882a593Smuzhiyun err = m5602_write_sensor(sd, OV9650_BLUE, &i2c_data, 1);
630*4882a593Smuzhiyun return err;
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun
ov9650_set_hvflip(struct gspca_dev * gspca_dev)633*4882a593Smuzhiyun static int ov9650_set_hvflip(struct gspca_dev *gspca_dev)
634*4882a593Smuzhiyun {
635*4882a593Smuzhiyun int err;
636*4882a593Smuzhiyun u8 i2c_data;
637*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
638*4882a593Smuzhiyun int hflip = sd->hflip->val;
639*4882a593Smuzhiyun int vflip = sd->vflip->val;
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_CONF, "Set hvflip to %d %d\n", hflip, vflip);
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun if (dmi_check_system(ov9650_flip_dmi_table))
644*4882a593Smuzhiyun vflip = !vflip;
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun i2c_data = (hflip << 5) | (vflip << 4);
647*4882a593Smuzhiyun err = m5602_write_sensor(sd, OV9650_MVFP, &i2c_data, 1);
648*4882a593Smuzhiyun if (err < 0)
649*4882a593Smuzhiyun return err;
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun /* When vflip is toggled we need to readjust the bridge hsync/vsync */
652*4882a593Smuzhiyun if (gspca_dev->streaming)
653*4882a593Smuzhiyun err = ov9650_start(sd);
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun return err;
656*4882a593Smuzhiyun }
657*4882a593Smuzhiyun
ov9650_set_auto_exposure(struct gspca_dev * gspca_dev,__s32 val)658*4882a593Smuzhiyun static int ov9650_set_auto_exposure(struct gspca_dev *gspca_dev,
659*4882a593Smuzhiyun __s32 val)
660*4882a593Smuzhiyun {
661*4882a593Smuzhiyun int err;
662*4882a593Smuzhiyun u8 i2c_data;
663*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_CONF, "Set auto exposure control to %d\n", val);
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun err = m5602_read_sensor(sd, OV9650_COM8, &i2c_data, 1);
668*4882a593Smuzhiyun if (err < 0)
669*4882a593Smuzhiyun return err;
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun val = (val == V4L2_EXPOSURE_AUTO);
672*4882a593Smuzhiyun i2c_data = ((i2c_data & 0xfe) | ((val & 0x01) << 0));
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun return m5602_write_sensor(sd, OV9650_COM8, &i2c_data, 1);
675*4882a593Smuzhiyun }
676*4882a593Smuzhiyun
ov9650_set_auto_white_balance(struct gspca_dev * gspca_dev,__s32 val)677*4882a593Smuzhiyun static int ov9650_set_auto_white_balance(struct gspca_dev *gspca_dev,
678*4882a593Smuzhiyun __s32 val)
679*4882a593Smuzhiyun {
680*4882a593Smuzhiyun int err;
681*4882a593Smuzhiyun u8 i2c_data;
682*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_CONF, "Set auto white balance to %d\n", val);
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun err = m5602_read_sensor(sd, OV9650_COM8, &i2c_data, 1);
687*4882a593Smuzhiyun if (err < 0)
688*4882a593Smuzhiyun return err;
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun i2c_data = ((i2c_data & 0xfd) | ((val & 0x01) << 1));
691*4882a593Smuzhiyun err = m5602_write_sensor(sd, OV9650_COM8, &i2c_data, 1);
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun return err;
694*4882a593Smuzhiyun }
695*4882a593Smuzhiyun
ov9650_set_auto_gain(struct gspca_dev * gspca_dev,__s32 val)696*4882a593Smuzhiyun static int ov9650_set_auto_gain(struct gspca_dev *gspca_dev, __s32 val)
697*4882a593Smuzhiyun {
698*4882a593Smuzhiyun int err;
699*4882a593Smuzhiyun u8 i2c_data;
700*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun gspca_dbg(gspca_dev, D_CONF, "Set auto gain control to %d\n", val);
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun err = m5602_read_sensor(sd, OV9650_COM8, &i2c_data, 1);
705*4882a593Smuzhiyun if (err < 0)
706*4882a593Smuzhiyun return err;
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun i2c_data = ((i2c_data & 0xfb) | ((val & 0x01) << 2));
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun return m5602_write_sensor(sd, OV9650_COM8, &i2c_data, 1);
711*4882a593Smuzhiyun }
712*4882a593Smuzhiyun
ov9650_s_ctrl(struct v4l2_ctrl * ctrl)713*4882a593Smuzhiyun static int ov9650_s_ctrl(struct v4l2_ctrl *ctrl)
714*4882a593Smuzhiyun {
715*4882a593Smuzhiyun struct gspca_dev *gspca_dev =
716*4882a593Smuzhiyun container_of(ctrl->handler, struct gspca_dev, ctrl_handler);
717*4882a593Smuzhiyun struct sd *sd = (struct sd *) gspca_dev;
718*4882a593Smuzhiyun int err;
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun if (!gspca_dev->streaming)
721*4882a593Smuzhiyun return 0;
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun switch (ctrl->id) {
724*4882a593Smuzhiyun case V4L2_CID_AUTO_WHITE_BALANCE:
725*4882a593Smuzhiyun err = ov9650_set_auto_white_balance(gspca_dev, ctrl->val);
726*4882a593Smuzhiyun if (err || ctrl->val)
727*4882a593Smuzhiyun return err;
728*4882a593Smuzhiyun err = ov9650_set_red_balance(gspca_dev, sd->red_bal->val);
729*4882a593Smuzhiyun if (err)
730*4882a593Smuzhiyun return err;
731*4882a593Smuzhiyun err = ov9650_set_blue_balance(gspca_dev, sd->blue_bal->val);
732*4882a593Smuzhiyun break;
733*4882a593Smuzhiyun case V4L2_CID_EXPOSURE_AUTO:
734*4882a593Smuzhiyun err = ov9650_set_auto_exposure(gspca_dev, ctrl->val);
735*4882a593Smuzhiyun if (err || ctrl->val == V4L2_EXPOSURE_AUTO)
736*4882a593Smuzhiyun return err;
737*4882a593Smuzhiyun err = ov9650_set_exposure(gspca_dev, sd->expo->val);
738*4882a593Smuzhiyun break;
739*4882a593Smuzhiyun case V4L2_CID_AUTOGAIN:
740*4882a593Smuzhiyun err = ov9650_set_auto_gain(gspca_dev, ctrl->val);
741*4882a593Smuzhiyun if (err || ctrl->val)
742*4882a593Smuzhiyun return err;
743*4882a593Smuzhiyun err = ov9650_set_gain(gspca_dev, sd->gain->val);
744*4882a593Smuzhiyun break;
745*4882a593Smuzhiyun case V4L2_CID_HFLIP:
746*4882a593Smuzhiyun err = ov9650_set_hvflip(gspca_dev);
747*4882a593Smuzhiyun break;
748*4882a593Smuzhiyun default:
749*4882a593Smuzhiyun return -EINVAL;
750*4882a593Smuzhiyun }
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun return err;
753*4882a593Smuzhiyun }
754*4882a593Smuzhiyun
ov9650_dump_registers(struct sd * sd)755*4882a593Smuzhiyun static void ov9650_dump_registers(struct sd *sd)
756*4882a593Smuzhiyun {
757*4882a593Smuzhiyun int address;
758*4882a593Smuzhiyun pr_info("Dumping the ov9650 register state\n");
759*4882a593Smuzhiyun for (address = 0; address < 0xa9; address++) {
760*4882a593Smuzhiyun u8 value;
761*4882a593Smuzhiyun m5602_read_sensor(sd, address, &value, 1);
762*4882a593Smuzhiyun pr_info("register 0x%x contains 0x%x\n", address, value);
763*4882a593Smuzhiyun }
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun pr_info("ov9650 register state dump complete\n");
766*4882a593Smuzhiyun
767*4882a593Smuzhiyun pr_info("Probing for which registers that are read/write\n");
768*4882a593Smuzhiyun for (address = 0; address < 0xff; address++) {
769*4882a593Smuzhiyun u8 old_value, ctrl_value;
770*4882a593Smuzhiyun u8 test_value[2] = {0xff, 0xff};
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun m5602_read_sensor(sd, address, &old_value, 1);
773*4882a593Smuzhiyun m5602_write_sensor(sd, address, test_value, 1);
774*4882a593Smuzhiyun m5602_read_sensor(sd, address, &ctrl_value, 1);
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun if (ctrl_value == test_value[0])
777*4882a593Smuzhiyun pr_info("register 0x%x is writeable\n", address);
778*4882a593Smuzhiyun else
779*4882a593Smuzhiyun pr_info("register 0x%x is read only\n", address);
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun /* Restore original value */
782*4882a593Smuzhiyun m5602_write_sensor(sd, address, &old_value, 1);
783*4882a593Smuzhiyun }
784*4882a593Smuzhiyun }
785