xref: /OK3568_Linux_fs/kernel/drivers/media/usb/dvb-usb/dib0700_devices.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /* Linux driver for devices based on the DiBcom DiB0700 USB bridge
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  *  Copyright (C) 2005-9 DiBcom, SA et al
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun #include "dib0700.h"
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include "dib3000mc.h"
9*4882a593Smuzhiyun #include "dib7000m.h"
10*4882a593Smuzhiyun #include "dib7000p.h"
11*4882a593Smuzhiyun #include "dib8000.h"
12*4882a593Smuzhiyun #include "dib9000.h"
13*4882a593Smuzhiyun #include "mt2060.h"
14*4882a593Smuzhiyun #include "mt2266.h"
15*4882a593Smuzhiyun #include "tuner-xc2028.h"
16*4882a593Smuzhiyun #include "xc5000.h"
17*4882a593Smuzhiyun #include "xc4000.h"
18*4882a593Smuzhiyun #include "s5h1411.h"
19*4882a593Smuzhiyun #include "dib0070.h"
20*4882a593Smuzhiyun #include "dib0090.h"
21*4882a593Smuzhiyun #include "lgdt3305.h"
22*4882a593Smuzhiyun #include "mxl5007t.h"
23*4882a593Smuzhiyun #include "mn88472.h"
24*4882a593Smuzhiyun #include "tda18250.h"
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun static int force_lna_activation;
28*4882a593Smuzhiyun module_param(force_lna_activation, int, 0644);
29*4882a593Smuzhiyun MODULE_PARM_DESC(force_lna_activation, "force the activation of Low-Noise-Amplifier(s) (LNA), if applicable for the device (default: 0=automatic/off).");
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun struct dib0700_adapter_state {
32*4882a593Smuzhiyun 	int (*set_param_save) (struct dvb_frontend *);
33*4882a593Smuzhiyun 	const struct firmware *frontend_firmware;
34*4882a593Smuzhiyun 	struct dib7000p_ops dib7000p_ops;
35*4882a593Smuzhiyun 	struct dib8000_ops dib8000_ops;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun /* Hauppauge Nova-T 500 (aka Bristol)
39*4882a593Smuzhiyun  *  has a LNA on GPIO0 which is enabled by setting 1 */
40*4882a593Smuzhiyun static struct mt2060_config bristol_mt2060_config[2] = {
41*4882a593Smuzhiyun 	{
42*4882a593Smuzhiyun 		.i2c_address = 0x60,
43*4882a593Smuzhiyun 		.clock_out   = 3,
44*4882a593Smuzhiyun 	}, {
45*4882a593Smuzhiyun 		.i2c_address = 0x61,
46*4882a593Smuzhiyun 	}
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun static struct dibx000_agc_config bristol_dib3000p_mt2060_agc_config = {
51*4882a593Smuzhiyun 	.band_caps = BAND_VHF | BAND_UHF,
52*4882a593Smuzhiyun 	.setup     = (1 << 8) | (5 << 5) | (0 << 4) | (0 << 3) | (0 << 2) | (2 << 0),
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	.agc1_max = 42598,
55*4882a593Smuzhiyun 	.agc1_min = 17694,
56*4882a593Smuzhiyun 	.agc2_max = 45875,
57*4882a593Smuzhiyun 	.agc2_min = 0,
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	.agc1_pt1 = 0,
60*4882a593Smuzhiyun 	.agc1_pt2 = 59,
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	.agc1_slope1 = 0,
63*4882a593Smuzhiyun 	.agc1_slope2 = 69,
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	.agc2_pt1 = 0,
66*4882a593Smuzhiyun 	.agc2_pt2 = 59,
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	.agc2_slope1 = 111,
69*4882a593Smuzhiyun 	.agc2_slope2 = 28,
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun static struct dib3000mc_config bristol_dib3000mc_config[2] = {
73*4882a593Smuzhiyun 	{	.agc          = &bristol_dib3000p_mt2060_agc_config,
74*4882a593Smuzhiyun 		.max_time     = 0x196,
75*4882a593Smuzhiyun 		.ln_adc_level = 0x1cc7,
76*4882a593Smuzhiyun 		.output_mpeg2_in_188_bytes = 1,
77*4882a593Smuzhiyun 	},
78*4882a593Smuzhiyun 	{	.agc          = &bristol_dib3000p_mt2060_agc_config,
79*4882a593Smuzhiyun 		.max_time     = 0x196,
80*4882a593Smuzhiyun 		.ln_adc_level = 0x1cc7,
81*4882a593Smuzhiyun 		.output_mpeg2_in_188_bytes = 1,
82*4882a593Smuzhiyun 	}
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun 
bristol_frontend_attach(struct dvb_usb_adapter * adap)85*4882a593Smuzhiyun static int bristol_frontend_attach(struct dvb_usb_adapter *adap)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun 	struct dib0700_state *st = adap->dev->priv;
88*4882a593Smuzhiyun 	if (adap->id == 0) {
89*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO6,  GPIO_OUT, 0); msleep(10);
90*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO6,  GPIO_OUT, 1); msleep(10);
91*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0); msleep(10);
92*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1); msleep(10);
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 		if (force_lna_activation)
95*4882a593Smuzhiyun 			dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
96*4882a593Smuzhiyun 		else
97*4882a593Smuzhiyun 			dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 0);
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 		if (dib3000mc_i2c_enumeration(&adap->dev->i2c_adap, 2, DEFAULT_DIB3000P_I2C_ADDRESS, bristol_dib3000mc_config) != 0) {
100*4882a593Smuzhiyun 			dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 0); msleep(10);
101*4882a593Smuzhiyun 			return -ENODEV;
102*4882a593Smuzhiyun 		}
103*4882a593Smuzhiyun 	}
104*4882a593Smuzhiyun 	st->mt2060_if1[adap->id] = 1220;
105*4882a593Smuzhiyun 	return (adap->fe_adap[0].fe = dvb_attach(dib3000mc_attach, &adap->dev->i2c_adap,
106*4882a593Smuzhiyun 		(10 + adap->id) << 1, &bristol_dib3000mc_config[adap->id])) == NULL ? -ENODEV : 0;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun 
eeprom_read(struct i2c_adapter * adap,u8 adrs,u8 * pval)109*4882a593Smuzhiyun static int eeprom_read(struct i2c_adapter *adap,u8 adrs,u8 *pval)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun 	struct i2c_msg msg[2] = {
112*4882a593Smuzhiyun 		{ .addr = 0x50, .flags = 0,        .buf = &adrs, .len = 1 },
113*4882a593Smuzhiyun 		{ .addr = 0x50, .flags = I2C_M_RD, .buf = pval,  .len = 1 },
114*4882a593Smuzhiyun 	};
115*4882a593Smuzhiyun 	if (i2c_transfer(adap, msg, 2) != 2) return -EREMOTEIO;
116*4882a593Smuzhiyun 	return 0;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun 
bristol_tuner_attach(struct dvb_usb_adapter * adap)119*4882a593Smuzhiyun static int bristol_tuner_attach(struct dvb_usb_adapter *adap)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun 	struct i2c_adapter *prim_i2c = &adap->dev->i2c_adap;
122*4882a593Smuzhiyun 	struct i2c_adapter *tun_i2c = dib3000mc_get_tuner_i2c_master(adap->fe_adap[0].fe, 1);
123*4882a593Smuzhiyun 	s8 a;
124*4882a593Smuzhiyun 	int if1=1220;
125*4882a593Smuzhiyun 	if (adap->dev->udev->descriptor.idVendor  == cpu_to_le16(USB_VID_HAUPPAUGE) &&
126*4882a593Smuzhiyun 		adap->dev->udev->descriptor.idProduct == cpu_to_le16(USB_PID_HAUPPAUGE_NOVA_T_500_2)) {
127*4882a593Smuzhiyun 		if (!eeprom_read(prim_i2c,0x59 + adap->id,&a)) if1=1220+a;
128*4882a593Smuzhiyun 	}
129*4882a593Smuzhiyun 	return dvb_attach(mt2060_attach, adap->fe_adap[0].fe, tun_i2c,
130*4882a593Smuzhiyun 			  &bristol_mt2060_config[adap->id], if1) == NULL ?
131*4882a593Smuzhiyun 			  -ENODEV : 0;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun /* STK7700D: Pinnacle/Terratec/Hauppauge Dual DVB-T Diversity */
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun /* MT226x */
137*4882a593Smuzhiyun static struct dibx000_agc_config stk7700d_7000p_mt2266_agc_config[2] = {
138*4882a593Smuzhiyun 	{
139*4882a593Smuzhiyun 		BAND_UHF,
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 		/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=1, P_agc_inv_pwm2=1,
142*4882a593Smuzhiyun 		* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
143*4882a593Smuzhiyun 		(0 << 15) | (0 << 14) | (1 << 11) | (1 << 10) | (1 << 9) | (0 << 8)
144*4882a593Smuzhiyun 	    | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 		1130,
147*4882a593Smuzhiyun 		21,
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 		0,
150*4882a593Smuzhiyun 		118,
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 		0,
153*4882a593Smuzhiyun 		3530,
154*4882a593Smuzhiyun 		1,
155*4882a593Smuzhiyun 		0,
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 		65535,
158*4882a593Smuzhiyun 		33770,
159*4882a593Smuzhiyun 		65535,
160*4882a593Smuzhiyun 		23592,
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 		0,
163*4882a593Smuzhiyun 		62,
164*4882a593Smuzhiyun 		255,
165*4882a593Smuzhiyun 		64,
166*4882a593Smuzhiyun 		64,
167*4882a593Smuzhiyun 		132,
168*4882a593Smuzhiyun 		192,
169*4882a593Smuzhiyun 		80,
170*4882a593Smuzhiyun 		80,
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 		17,
173*4882a593Smuzhiyun 		27,
174*4882a593Smuzhiyun 		23,
175*4882a593Smuzhiyun 		51,
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 		1,
178*4882a593Smuzhiyun 	}, {
179*4882a593Smuzhiyun 		BAND_VHF | BAND_LBAND,
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 		/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=1, P_agc_inv_pwm2=1,
182*4882a593Smuzhiyun 		* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
183*4882a593Smuzhiyun 		(0 << 15) | (0 << 14) | (1 << 11) | (1 << 10) | (1 << 9) | (0 << 8)
184*4882a593Smuzhiyun 	    | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0),
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 		2372,
187*4882a593Smuzhiyun 		21,
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 		0,
190*4882a593Smuzhiyun 		118,
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 		0,
193*4882a593Smuzhiyun 		3530,
194*4882a593Smuzhiyun 		1,
195*4882a593Smuzhiyun 		0,
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 		65535,
198*4882a593Smuzhiyun 		0,
199*4882a593Smuzhiyun 		65535,
200*4882a593Smuzhiyun 		23592,
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 		0,
203*4882a593Smuzhiyun 		128,
204*4882a593Smuzhiyun 		128,
205*4882a593Smuzhiyun 		128,
206*4882a593Smuzhiyun 		0,
207*4882a593Smuzhiyun 		128,
208*4882a593Smuzhiyun 		253,
209*4882a593Smuzhiyun 		81,
210*4882a593Smuzhiyun 		0,
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 		17,
213*4882a593Smuzhiyun 		27,
214*4882a593Smuzhiyun 		23,
215*4882a593Smuzhiyun 		51,
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 		1,
218*4882a593Smuzhiyun 	}
219*4882a593Smuzhiyun };
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun static struct dibx000_bandwidth_config stk7700d_mt2266_pll_config = {
222*4882a593Smuzhiyun 	.internal = 60000,
223*4882a593Smuzhiyun 	.sampling = 30000,
224*4882a593Smuzhiyun 	.pll_prediv = 1,
225*4882a593Smuzhiyun 	.pll_ratio = 8,
226*4882a593Smuzhiyun 	.pll_range = 3,
227*4882a593Smuzhiyun 	.pll_reset = 1,
228*4882a593Smuzhiyun 	.pll_bypass = 0,
229*4882a593Smuzhiyun 	.enable_refdiv = 0,
230*4882a593Smuzhiyun 	.bypclk_div = 0,
231*4882a593Smuzhiyun 	.IO_CLK_en_core = 1,
232*4882a593Smuzhiyun 	.ADClkSrc = 1,
233*4882a593Smuzhiyun 	.modulo = 2,
234*4882a593Smuzhiyun 	.sad_cfg = (3 << 14) | (1 << 12) | (524 << 0),
235*4882a593Smuzhiyun 	.ifreq = 0,
236*4882a593Smuzhiyun 	.timf = 20452225,
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun static struct dib7000p_config stk7700d_dib7000p_mt2266_config[] = {
240*4882a593Smuzhiyun 	{	.output_mpeg2_in_188_bytes = 1,
241*4882a593Smuzhiyun 		.hostbus_diversity = 1,
242*4882a593Smuzhiyun 		.tuner_is_baseband = 1,
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 		.agc_config_count = 2,
245*4882a593Smuzhiyun 		.agc = stk7700d_7000p_mt2266_agc_config,
246*4882a593Smuzhiyun 		.bw  = &stk7700d_mt2266_pll_config,
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 		.gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
249*4882a593Smuzhiyun 		.gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
250*4882a593Smuzhiyun 		.gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
251*4882a593Smuzhiyun 	},
252*4882a593Smuzhiyun 	{	.output_mpeg2_in_188_bytes = 1,
253*4882a593Smuzhiyun 		.hostbus_diversity = 1,
254*4882a593Smuzhiyun 		.tuner_is_baseband = 1,
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 		.agc_config_count = 2,
257*4882a593Smuzhiyun 		.agc = stk7700d_7000p_mt2266_agc_config,
258*4882a593Smuzhiyun 		.bw  = &stk7700d_mt2266_pll_config,
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun 		.gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
261*4882a593Smuzhiyun 		.gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
262*4882a593Smuzhiyun 		.gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
263*4882a593Smuzhiyun 	}
264*4882a593Smuzhiyun };
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun static struct mt2266_config stk7700d_mt2266_config[2] = {
267*4882a593Smuzhiyun 	{	.i2c_address = 0x60
268*4882a593Smuzhiyun 	},
269*4882a593Smuzhiyun 	{	.i2c_address = 0x60
270*4882a593Smuzhiyun 	}
271*4882a593Smuzhiyun };
272*4882a593Smuzhiyun 
stk7700P2_frontend_attach(struct dvb_usb_adapter * adap)273*4882a593Smuzhiyun static int stk7700P2_frontend_attach(struct dvb_usb_adapter *adap)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	if (!dvb_attach(dib7000p_attach, &state->dib7000p_ops))
278*4882a593Smuzhiyun 		return -ENODEV;
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	if (adap->id == 0) {
281*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
282*4882a593Smuzhiyun 		msleep(10);
283*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
284*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
285*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
286*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
287*4882a593Smuzhiyun 		msleep(10);
288*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
289*4882a593Smuzhiyun 		msleep(10);
290*4882a593Smuzhiyun 		if (state->dib7000p_ops.i2c_enumeration(&adap->dev->i2c_adap, 1, 18,
291*4882a593Smuzhiyun 					     stk7700d_dib7000p_mt2266_config)
292*4882a593Smuzhiyun 		    != 0) {
293*4882a593Smuzhiyun 			err("%s: state->dib7000p_ops.i2c_enumeration failed.  Cannot continue\n", __func__);
294*4882a593Smuzhiyun 			dvb_detach(state->dib7000p_ops.set_wbd_ref);
295*4882a593Smuzhiyun 			return -ENODEV;
296*4882a593Smuzhiyun 		}
297*4882a593Smuzhiyun 	}
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib7000p_ops.init(&adap->dev->i2c_adap,
300*4882a593Smuzhiyun 			   0x80 + (adap->id << 1),
301*4882a593Smuzhiyun 			   &stk7700d_dib7000p_mt2266_config[adap->id]);
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ? -ENODEV : 0;
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun 
stk7700d_frontend_attach(struct dvb_usb_adapter * adap)306*4882a593Smuzhiyun static int stk7700d_frontend_attach(struct dvb_usb_adapter *adap)
307*4882a593Smuzhiyun {
308*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	if (!dvb_attach(dib7000p_attach, &state->dib7000p_ops))
311*4882a593Smuzhiyun 		return -ENODEV;
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	if (adap->id == 0) {
314*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
315*4882a593Smuzhiyun 		msleep(10);
316*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
317*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
318*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
319*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
320*4882a593Smuzhiyun 		msleep(10);
321*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
322*4882a593Smuzhiyun 		msleep(10);
323*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
324*4882a593Smuzhiyun 		if (state->dib7000p_ops.i2c_enumeration(&adap->dev->i2c_adap, 2, 18,
325*4882a593Smuzhiyun 					     stk7700d_dib7000p_mt2266_config)
326*4882a593Smuzhiyun 		    != 0) {
327*4882a593Smuzhiyun 			err("%s: state->dib7000p_ops.i2c_enumeration failed.  Cannot continue\n", __func__);
328*4882a593Smuzhiyun 			dvb_detach(state->dib7000p_ops.set_wbd_ref);
329*4882a593Smuzhiyun 			return -ENODEV;
330*4882a593Smuzhiyun 		}
331*4882a593Smuzhiyun 	}
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib7000p_ops.init(&adap->dev->i2c_adap,
334*4882a593Smuzhiyun 			   0x80 + (adap->id << 1),
335*4882a593Smuzhiyun 			   &stk7700d_dib7000p_mt2266_config[adap->id]);
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ? -ENODEV : 0;
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun 
stk7700d_tuner_attach(struct dvb_usb_adapter * adap)340*4882a593Smuzhiyun static int stk7700d_tuner_attach(struct dvb_usb_adapter *adap)
341*4882a593Smuzhiyun {
342*4882a593Smuzhiyun 	struct i2c_adapter *tun_i2c;
343*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	tun_i2c = state->dib7000p_ops.get_i2c_master(adap->fe_adap[0].fe,
346*4882a593Smuzhiyun 					    DIBX000_I2C_INTERFACE_TUNER, 1);
347*4882a593Smuzhiyun 	return dvb_attach(mt2266_attach, adap->fe_adap[0].fe, tun_i2c,
348*4882a593Smuzhiyun 		&stk7700d_mt2266_config[adap->id]) == NULL ? -ENODEV : 0;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun /* STK7700-PH: Digital/Analog Hybrid Tuner, e.h. Cinergy HT USB HE */
352*4882a593Smuzhiyun static struct dibx000_agc_config xc3028_agc_config = {
353*4882a593Smuzhiyun 	.band_caps = BAND_VHF | BAND_UHF,
354*4882a593Smuzhiyun 	/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
355*4882a593Smuzhiyun 	 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
356*4882a593Smuzhiyun 	 * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
357*4882a593Smuzhiyun 	.setup = (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0),
358*4882a593Smuzhiyun 	.inv_gain = 712,
359*4882a593Smuzhiyun 	.time_stabiliz = 21,
360*4882a593Smuzhiyun 	.alpha_level = 0,
361*4882a593Smuzhiyun 	.thlock = 118,
362*4882a593Smuzhiyun 	.wbd_inv = 0,
363*4882a593Smuzhiyun 	.wbd_ref = 2867,
364*4882a593Smuzhiyun 	.wbd_sel = 0,
365*4882a593Smuzhiyun 	.wbd_alpha = 2,
366*4882a593Smuzhiyun 	.agc1_max = 0,
367*4882a593Smuzhiyun 	.agc1_min = 0,
368*4882a593Smuzhiyun 	.agc2_max = 39718,
369*4882a593Smuzhiyun 	.agc2_min = 9930,
370*4882a593Smuzhiyun 	.agc1_pt1 = 0,
371*4882a593Smuzhiyun 	.agc1_pt2 = 0,
372*4882a593Smuzhiyun 	.agc1_pt3 = 0,
373*4882a593Smuzhiyun 	.agc1_slope1 = 0,
374*4882a593Smuzhiyun 	.agc1_slope2 = 0,
375*4882a593Smuzhiyun 	.agc2_pt1 = 0,
376*4882a593Smuzhiyun 	.agc2_pt2 = 128,
377*4882a593Smuzhiyun 	.agc2_slope1 = 29,
378*4882a593Smuzhiyun 	.agc2_slope2 = 29,
379*4882a593Smuzhiyun 	.alpha_mant = 17,
380*4882a593Smuzhiyun 	.alpha_exp = 27,
381*4882a593Smuzhiyun 	.beta_mant = 23,
382*4882a593Smuzhiyun 	.beta_exp = 51,
383*4882a593Smuzhiyun 	.perform_agc_softsplit = 1,
384*4882a593Smuzhiyun };
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun /* PLL Configuration for COFDM BW_MHz = 8.00 with external clock = 30.00 */
387*4882a593Smuzhiyun static struct dibx000_bandwidth_config xc3028_bw_config = {
388*4882a593Smuzhiyun 	.internal = 60000,
389*4882a593Smuzhiyun 	.sampling = 30000,
390*4882a593Smuzhiyun 	.pll_prediv = 1,
391*4882a593Smuzhiyun 	.pll_ratio = 8,
392*4882a593Smuzhiyun 	.pll_range = 3,
393*4882a593Smuzhiyun 	.pll_reset = 1,
394*4882a593Smuzhiyun 	.pll_bypass = 0,
395*4882a593Smuzhiyun 	.enable_refdiv = 0,
396*4882a593Smuzhiyun 	.bypclk_div = 0,
397*4882a593Smuzhiyun 	.IO_CLK_en_core = 1,
398*4882a593Smuzhiyun 	.ADClkSrc = 1,
399*4882a593Smuzhiyun 	.modulo = 0,
400*4882a593Smuzhiyun 	.sad_cfg = (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
401*4882a593Smuzhiyun 	.ifreq = (1 << 25) | 5816102,  /* ifreq = 5.200000 MHz */
402*4882a593Smuzhiyun 	.timf = 20452225,
403*4882a593Smuzhiyun 	.xtal_hz = 30000000,
404*4882a593Smuzhiyun };
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun static struct dib7000p_config stk7700ph_dib7700_xc3028_config = {
407*4882a593Smuzhiyun 	.output_mpeg2_in_188_bytes = 1,
408*4882a593Smuzhiyun 	.tuner_is_baseband = 1,
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	.agc_config_count = 1,
411*4882a593Smuzhiyun 	.agc = &xc3028_agc_config,
412*4882a593Smuzhiyun 	.bw  = &xc3028_bw_config,
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	.gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
415*4882a593Smuzhiyun 	.gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
416*4882a593Smuzhiyun 	.gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
417*4882a593Smuzhiyun };
418*4882a593Smuzhiyun 
stk7700ph_xc3028_callback(void * ptr,int component,int command,int arg)419*4882a593Smuzhiyun static int stk7700ph_xc3028_callback(void *ptr, int component,
420*4882a593Smuzhiyun 				     int command, int arg)
421*4882a593Smuzhiyun {
422*4882a593Smuzhiyun 	struct dvb_usb_adapter *adap = ptr;
423*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun 	switch (command) {
426*4882a593Smuzhiyun 	case XC2028_TUNER_RESET:
427*4882a593Smuzhiyun 		/* Send the tuner in then out of reset */
428*4882a593Smuzhiyun 		state->dib7000p_ops.set_gpio(adap->fe_adap[0].fe, 8, 0, 0);
429*4882a593Smuzhiyun 		msleep(10);
430*4882a593Smuzhiyun 		state->dib7000p_ops.set_gpio(adap->fe_adap[0].fe, 8, 0, 1);
431*4882a593Smuzhiyun 		break;
432*4882a593Smuzhiyun 	case XC2028_RESET_CLK:
433*4882a593Smuzhiyun 	case XC2028_I2C_FLUSH:
434*4882a593Smuzhiyun 		break;
435*4882a593Smuzhiyun 	default:
436*4882a593Smuzhiyun 		err("%s: unknown command %d, arg %d\n", __func__,
437*4882a593Smuzhiyun 			command, arg);
438*4882a593Smuzhiyun 		return -EINVAL;
439*4882a593Smuzhiyun 	}
440*4882a593Smuzhiyun 	return 0;
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun static struct xc2028_ctrl stk7700ph_xc3028_ctrl = {
444*4882a593Smuzhiyun 	.fname = XC2028_DEFAULT_FIRMWARE,
445*4882a593Smuzhiyun 	.max_len = 64,
446*4882a593Smuzhiyun 	.demod = XC3028_FE_DIBCOM52,
447*4882a593Smuzhiyun };
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun static struct xc2028_config stk7700ph_xc3028_config = {
450*4882a593Smuzhiyun 	.i2c_addr = 0x61,
451*4882a593Smuzhiyun 	.ctrl = &stk7700ph_xc3028_ctrl,
452*4882a593Smuzhiyun };
453*4882a593Smuzhiyun 
stk7700ph_frontend_attach(struct dvb_usb_adapter * adap)454*4882a593Smuzhiyun static int stk7700ph_frontend_attach(struct dvb_usb_adapter *adap)
455*4882a593Smuzhiyun {
456*4882a593Smuzhiyun 	struct usb_device_descriptor *desc = &adap->dev->udev->descriptor;
457*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun 	if (!dvb_attach(dib7000p_attach, &state->dib7000p_ops))
460*4882a593Smuzhiyun 		return -ENODEV;
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 	if (desc->idVendor  == cpu_to_le16(USB_VID_PINNACLE) &&
463*4882a593Smuzhiyun 	    desc->idProduct == cpu_to_le16(USB_PID_PINNACLE_EXPRESSCARD_320CX))
464*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 0);
465*4882a593Smuzhiyun 	else
466*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
467*4882a593Smuzhiyun 	msleep(20);
468*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
469*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
470*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
471*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
472*4882a593Smuzhiyun 	msleep(10);
473*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
474*4882a593Smuzhiyun 	msleep(20);
475*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
476*4882a593Smuzhiyun 	msleep(10);
477*4882a593Smuzhiyun 
478*4882a593Smuzhiyun 	if (state->dib7000p_ops.i2c_enumeration(&adap->dev->i2c_adap, 1, 18,
479*4882a593Smuzhiyun 				     &stk7700ph_dib7700_xc3028_config) != 0) {
480*4882a593Smuzhiyun 		err("%s: state->dib7000p_ops.i2c_enumeration failed.  Cannot continue\n",
481*4882a593Smuzhiyun 		    __func__);
482*4882a593Smuzhiyun 		dvb_detach(state->dib7000p_ops.set_wbd_ref);
483*4882a593Smuzhiyun 		return -ENODEV;
484*4882a593Smuzhiyun 	}
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib7000p_ops.init(&adap->dev->i2c_adap, 0x80,
487*4882a593Smuzhiyun 		&stk7700ph_dib7700_xc3028_config);
488*4882a593Smuzhiyun 
489*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ? -ENODEV : 0;
490*4882a593Smuzhiyun }
491*4882a593Smuzhiyun 
stk7700ph_tuner_attach(struct dvb_usb_adapter * adap)492*4882a593Smuzhiyun static int stk7700ph_tuner_attach(struct dvb_usb_adapter *adap)
493*4882a593Smuzhiyun {
494*4882a593Smuzhiyun 	struct i2c_adapter *tun_i2c;
495*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun 	tun_i2c = state->dib7000p_ops.get_i2c_master(adap->fe_adap[0].fe,
498*4882a593Smuzhiyun 		DIBX000_I2C_INTERFACE_TUNER, 1);
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun 	stk7700ph_xc3028_config.i2c_adap = tun_i2c;
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun 	/* FIXME: generalize & move to common area */
503*4882a593Smuzhiyun 	adap->fe_adap[0].fe->callback = stk7700ph_xc3028_callback;
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun 	return dvb_attach(xc2028_attach, adap->fe_adap[0].fe, &stk7700ph_xc3028_config)
506*4882a593Smuzhiyun 		== NULL ? -ENODEV : 0;
507*4882a593Smuzhiyun }
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun #define DEFAULT_RC_INTERVAL 50
510*4882a593Smuzhiyun 
511*4882a593Smuzhiyun /*
512*4882a593Smuzhiyun  * This function is used only when firmware is < 1.20 version. Newer
513*4882a593Smuzhiyun  * firmwares use bulk mode, with functions implemented at dib0700_core,
514*4882a593Smuzhiyun  * at dib0700_rc_urb_completion()
515*4882a593Smuzhiyun  */
dib0700_rc_query_old_firmware(struct dvb_usb_device * d)516*4882a593Smuzhiyun static int dib0700_rc_query_old_firmware(struct dvb_usb_device *d)
517*4882a593Smuzhiyun {
518*4882a593Smuzhiyun 	enum rc_proto protocol;
519*4882a593Smuzhiyun 	u32 scancode;
520*4882a593Smuzhiyun 	u8 toggle;
521*4882a593Smuzhiyun 	int i;
522*4882a593Smuzhiyun 	struct dib0700_state *st = d->priv;
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	if (st->fw_version >= 0x10200) {
525*4882a593Smuzhiyun 		/* For 1.20 firmware , We need to keep the RC polling
526*4882a593Smuzhiyun 		   callback so we can reuse the input device setup in
527*4882a593Smuzhiyun 		   dvb-usb-remote.c.  However, the actual work is being done
528*4882a593Smuzhiyun 		   in the bulk URB completion handler. */
529*4882a593Smuzhiyun 		return 0;
530*4882a593Smuzhiyun 	}
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun 	st->buf[0] = REQUEST_POLL_RC;
533*4882a593Smuzhiyun 	st->buf[1] = 0;
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 	i = dib0700_ctrl_rd(d, st->buf, 2, st->buf, 4);
536*4882a593Smuzhiyun 	if (i <= 0) {
537*4882a593Smuzhiyun 		err("RC Query Failed");
538*4882a593Smuzhiyun 		return -EIO;
539*4882a593Smuzhiyun 	}
540*4882a593Smuzhiyun 
541*4882a593Smuzhiyun 	/* losing half of KEY_0 events from Philipps rc5 remotes.. */
542*4882a593Smuzhiyun 	if (st->buf[0] == 0 && st->buf[1] == 0
543*4882a593Smuzhiyun 	    && st->buf[2] == 0 && st->buf[3] == 0)
544*4882a593Smuzhiyun 		return 0;
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 	/* info("%d: %2X %2X %2X %2X",dvb_usb_dib0700_ir_proto,(int)st->buf[3 - 2],(int)st->buf[3 - 3],(int)st->buf[3 - 1],(int)st->buf[3]);  */
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun 	dib0700_rc_setup(d, NULL); /* reset ir sensor data to prevent false events */
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun 	switch (d->props.rc.core.protocol) {
551*4882a593Smuzhiyun 	case RC_PROTO_BIT_NEC:
552*4882a593Smuzhiyun 		/* NEC protocol sends repeat code as 0 0 0 FF */
553*4882a593Smuzhiyun 		if ((st->buf[3 - 2] == 0x00) && (st->buf[3 - 3] == 0x00) &&
554*4882a593Smuzhiyun 		    (st->buf[3] == 0xff)) {
555*4882a593Smuzhiyun 			rc_repeat(d->rc_dev);
556*4882a593Smuzhiyun 			return 0;
557*4882a593Smuzhiyun 		}
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun 		protocol = RC_PROTO_NEC;
560*4882a593Smuzhiyun 		scancode = RC_SCANCODE_NEC(st->buf[3 - 2], st->buf[3 - 3]);
561*4882a593Smuzhiyun 		toggle = 0;
562*4882a593Smuzhiyun 		break;
563*4882a593Smuzhiyun 
564*4882a593Smuzhiyun 	default:
565*4882a593Smuzhiyun 		/* RC-5 protocol changes toggle bit on new keypress */
566*4882a593Smuzhiyun 		protocol = RC_PROTO_RC5;
567*4882a593Smuzhiyun 		scancode = RC_SCANCODE_RC5(st->buf[3 - 2], st->buf[3 - 3]);
568*4882a593Smuzhiyun 		toggle = st->buf[3 - 1];
569*4882a593Smuzhiyun 		break;
570*4882a593Smuzhiyun 	}
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun 	rc_keydown(d->rc_dev, protocol, scancode, toggle);
573*4882a593Smuzhiyun 	return 0;
574*4882a593Smuzhiyun }
575*4882a593Smuzhiyun 
576*4882a593Smuzhiyun /* STK7700P: Hauppauge Nova-T Stick, AVerMedia Volar */
577*4882a593Smuzhiyun static struct dibx000_agc_config stk7700p_7000m_mt2060_agc_config = {
578*4882a593Smuzhiyun 	BAND_UHF | BAND_VHF,
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun 	/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
581*4882a593Smuzhiyun 	 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
582*4882a593Smuzhiyun 	(0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
583*4882a593Smuzhiyun 	| (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0),
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	712,
586*4882a593Smuzhiyun 	41,
587*4882a593Smuzhiyun 
588*4882a593Smuzhiyun 	0,
589*4882a593Smuzhiyun 	118,
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun 	0,
592*4882a593Smuzhiyun 	4095,
593*4882a593Smuzhiyun 	0,
594*4882a593Smuzhiyun 	0,
595*4882a593Smuzhiyun 
596*4882a593Smuzhiyun 	42598,
597*4882a593Smuzhiyun 	17694,
598*4882a593Smuzhiyun 	45875,
599*4882a593Smuzhiyun 	2621,
600*4882a593Smuzhiyun 	0,
601*4882a593Smuzhiyun 	76,
602*4882a593Smuzhiyun 	139,
603*4882a593Smuzhiyun 	52,
604*4882a593Smuzhiyun 	59,
605*4882a593Smuzhiyun 	107,
606*4882a593Smuzhiyun 	172,
607*4882a593Smuzhiyun 	57,
608*4882a593Smuzhiyun 	70,
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun 	21,
611*4882a593Smuzhiyun 	25,
612*4882a593Smuzhiyun 	28,
613*4882a593Smuzhiyun 	48,
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun 	1,
616*4882a593Smuzhiyun 	{  0,
617*4882a593Smuzhiyun 	   107,
618*4882a593Smuzhiyun 	   51800,
619*4882a593Smuzhiyun 	   24700
620*4882a593Smuzhiyun 	},
621*4882a593Smuzhiyun };
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun static struct dibx000_agc_config stk7700p_7000p_mt2060_agc_config = {
624*4882a593Smuzhiyun 	.band_caps = BAND_UHF | BAND_VHF,
625*4882a593Smuzhiyun 	/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
626*4882a593Smuzhiyun 	 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */
627*4882a593Smuzhiyun 	.setup = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0),
628*4882a593Smuzhiyun 	.inv_gain = 712,
629*4882a593Smuzhiyun 	.time_stabiliz = 41,
630*4882a593Smuzhiyun 	.alpha_level = 0,
631*4882a593Smuzhiyun 	.thlock = 118,
632*4882a593Smuzhiyun 	.wbd_inv = 0,
633*4882a593Smuzhiyun 	.wbd_ref = 4095,
634*4882a593Smuzhiyun 	.wbd_sel = 0,
635*4882a593Smuzhiyun 	.wbd_alpha = 0,
636*4882a593Smuzhiyun 	.agc1_max = 42598,
637*4882a593Smuzhiyun 	.agc1_min = 16384,
638*4882a593Smuzhiyun 	.agc2_max = 42598,
639*4882a593Smuzhiyun 	.agc2_min = 0,
640*4882a593Smuzhiyun 	.agc1_pt1 = 0,
641*4882a593Smuzhiyun 	.agc1_pt2 = 137,
642*4882a593Smuzhiyun 	.agc1_pt3 = 255,
643*4882a593Smuzhiyun 	.agc1_slope1 = 0,
644*4882a593Smuzhiyun 	.agc1_slope2 = 255,
645*4882a593Smuzhiyun 	.agc2_pt1 = 0,
646*4882a593Smuzhiyun 	.agc2_pt2 = 0,
647*4882a593Smuzhiyun 	.agc2_slope1 = 0,
648*4882a593Smuzhiyun 	.agc2_slope2 = 41,
649*4882a593Smuzhiyun 	.alpha_mant = 15,
650*4882a593Smuzhiyun 	.alpha_exp = 25,
651*4882a593Smuzhiyun 	.beta_mant = 28,
652*4882a593Smuzhiyun 	.beta_exp = 48,
653*4882a593Smuzhiyun 	.perform_agc_softsplit = 0,
654*4882a593Smuzhiyun };
655*4882a593Smuzhiyun 
656*4882a593Smuzhiyun static struct dibx000_bandwidth_config stk7700p_pll_config = {
657*4882a593Smuzhiyun 	.internal = 60000,
658*4882a593Smuzhiyun 	.sampling = 30000,
659*4882a593Smuzhiyun 	.pll_prediv = 1,
660*4882a593Smuzhiyun 	.pll_ratio = 8,
661*4882a593Smuzhiyun 	.pll_range = 3,
662*4882a593Smuzhiyun 	.pll_reset = 1,
663*4882a593Smuzhiyun 	.pll_bypass = 0,
664*4882a593Smuzhiyun 	.enable_refdiv = 0,
665*4882a593Smuzhiyun 	.bypclk_div = 0,
666*4882a593Smuzhiyun 	.IO_CLK_en_core = 1,
667*4882a593Smuzhiyun 	.ADClkSrc = 1,
668*4882a593Smuzhiyun 	.modulo = 0,
669*4882a593Smuzhiyun 	.sad_cfg = (3 << 14) | (1 << 12) | (524 << 0),
670*4882a593Smuzhiyun 	.ifreq = 60258167,
671*4882a593Smuzhiyun 	.timf = 20452225,
672*4882a593Smuzhiyun 	.xtal_hz = 30000000,
673*4882a593Smuzhiyun };
674*4882a593Smuzhiyun 
675*4882a593Smuzhiyun static struct dib7000m_config stk7700p_dib7000m_config = {
676*4882a593Smuzhiyun 	.dvbt_mode = 1,
677*4882a593Smuzhiyun 	.output_mpeg2_in_188_bytes = 1,
678*4882a593Smuzhiyun 	.quartz_direct = 1,
679*4882a593Smuzhiyun 
680*4882a593Smuzhiyun 	.agc_config_count = 1,
681*4882a593Smuzhiyun 	.agc = &stk7700p_7000m_mt2060_agc_config,
682*4882a593Smuzhiyun 	.bw  = &stk7700p_pll_config,
683*4882a593Smuzhiyun 
684*4882a593Smuzhiyun 	.gpio_dir = DIB7000M_GPIO_DEFAULT_DIRECTIONS,
685*4882a593Smuzhiyun 	.gpio_val = DIB7000M_GPIO_DEFAULT_VALUES,
686*4882a593Smuzhiyun 	.gpio_pwm_pos = DIB7000M_GPIO_DEFAULT_PWM_POS,
687*4882a593Smuzhiyun };
688*4882a593Smuzhiyun 
689*4882a593Smuzhiyun static struct dib7000p_config stk7700p_dib7000p_config = {
690*4882a593Smuzhiyun 	.output_mpeg2_in_188_bytes = 1,
691*4882a593Smuzhiyun 
692*4882a593Smuzhiyun 	.agc_config_count = 1,
693*4882a593Smuzhiyun 	.agc = &stk7700p_7000p_mt2060_agc_config,
694*4882a593Smuzhiyun 	.bw  = &stk7700p_pll_config,
695*4882a593Smuzhiyun 
696*4882a593Smuzhiyun 	.gpio_dir = DIB7000M_GPIO_DEFAULT_DIRECTIONS,
697*4882a593Smuzhiyun 	.gpio_val = DIB7000M_GPIO_DEFAULT_VALUES,
698*4882a593Smuzhiyun 	.gpio_pwm_pos = DIB7000M_GPIO_DEFAULT_PWM_POS,
699*4882a593Smuzhiyun };
700*4882a593Smuzhiyun 
stk7700p_frontend_attach(struct dvb_usb_adapter * adap)701*4882a593Smuzhiyun static int stk7700p_frontend_attach(struct dvb_usb_adapter *adap)
702*4882a593Smuzhiyun {
703*4882a593Smuzhiyun 	struct dib0700_state *st = adap->dev->priv;
704*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
705*4882a593Smuzhiyun 
706*4882a593Smuzhiyun 	if (!dvb_attach(dib7000p_attach, &state->dib7000p_ops))
707*4882a593Smuzhiyun 		return -ENODEV;
708*4882a593Smuzhiyun 
709*4882a593Smuzhiyun 	/* unless there is no real power management in DVB - we leave the device on GPIO6 */
710*4882a593Smuzhiyun 
711*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
712*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6,  GPIO_OUT, 0); msleep(50);
713*4882a593Smuzhiyun 
714*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6,  GPIO_OUT, 1); msleep(10);
715*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO9,  GPIO_OUT, 1);
716*4882a593Smuzhiyun 
717*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0); msleep(10);
718*4882a593Smuzhiyun 	dib0700_ctrl_clock(adap->dev, 72, 1);
719*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1); msleep(100);
720*4882a593Smuzhiyun 
721*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev,  GPIO0, GPIO_OUT, 1);
722*4882a593Smuzhiyun 
723*4882a593Smuzhiyun 	st->mt2060_if1[0] = 1220;
724*4882a593Smuzhiyun 
725*4882a593Smuzhiyun 	if (state->dib7000p_ops.dib7000pc_detection(&adap->dev->i2c_adap)) {
726*4882a593Smuzhiyun 		adap->fe_adap[0].fe = state->dib7000p_ops.init(&adap->dev->i2c_adap, 18, &stk7700p_dib7000p_config);
727*4882a593Smuzhiyun 		st->is_dib7000pc = 1;
728*4882a593Smuzhiyun 	} else {
729*4882a593Smuzhiyun 		memset(&state->dib7000p_ops, 0, sizeof(state->dib7000p_ops));
730*4882a593Smuzhiyun 		adap->fe_adap[0].fe = dvb_attach(dib7000m_attach, &adap->dev->i2c_adap, 18, &stk7700p_dib7000m_config);
731*4882a593Smuzhiyun 	}
732*4882a593Smuzhiyun 
733*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ? -ENODEV : 0;
734*4882a593Smuzhiyun }
735*4882a593Smuzhiyun 
736*4882a593Smuzhiyun static struct mt2060_config stk7700p_mt2060_config = {
737*4882a593Smuzhiyun 	0x60
738*4882a593Smuzhiyun };
739*4882a593Smuzhiyun 
stk7700p_tuner_attach(struct dvb_usb_adapter * adap)740*4882a593Smuzhiyun static int stk7700p_tuner_attach(struct dvb_usb_adapter *adap)
741*4882a593Smuzhiyun {
742*4882a593Smuzhiyun 	struct i2c_adapter *prim_i2c = &adap->dev->i2c_adap;
743*4882a593Smuzhiyun 	struct dib0700_state *st = adap->dev->priv;
744*4882a593Smuzhiyun 	struct i2c_adapter *tun_i2c;
745*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
746*4882a593Smuzhiyun 	s8 a;
747*4882a593Smuzhiyun 	int if1=1220;
748*4882a593Smuzhiyun 
749*4882a593Smuzhiyun 	if (adap->dev->udev->descriptor.idVendor  == cpu_to_le16(USB_VID_HAUPPAUGE) &&
750*4882a593Smuzhiyun 		adap->dev->udev->descriptor.idProduct == cpu_to_le16(USB_PID_HAUPPAUGE_NOVA_T_STICK)) {
751*4882a593Smuzhiyun 		if (!eeprom_read(prim_i2c,0x58,&a)) if1=1220+a;
752*4882a593Smuzhiyun 	}
753*4882a593Smuzhiyun 	if (st->is_dib7000pc)
754*4882a593Smuzhiyun 		tun_i2c = state->dib7000p_ops.get_i2c_master(adap->fe_adap[0].fe, DIBX000_I2C_INTERFACE_TUNER, 1);
755*4882a593Smuzhiyun 	else
756*4882a593Smuzhiyun 		tun_i2c = dib7000m_get_i2c_master(adap->fe_adap[0].fe, DIBX000_I2C_INTERFACE_TUNER, 1);
757*4882a593Smuzhiyun 
758*4882a593Smuzhiyun 	return dvb_attach(mt2060_attach, adap->fe_adap[0].fe, tun_i2c, &stk7700p_mt2060_config,
759*4882a593Smuzhiyun 		if1) == NULL ? -ENODEV : 0;
760*4882a593Smuzhiyun }
761*4882a593Smuzhiyun 
762*4882a593Smuzhiyun /* DIB7070 generic */
763*4882a593Smuzhiyun static struct dibx000_agc_config dib7070_agc_config = {
764*4882a593Smuzhiyun 	.band_caps = BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND,
765*4882a593Smuzhiyun 	/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
766*4882a593Smuzhiyun 	 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
767*4882a593Smuzhiyun 	.setup = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
768*4882a593Smuzhiyun 	.inv_gain = 600,
769*4882a593Smuzhiyun 	.time_stabiliz = 10,
770*4882a593Smuzhiyun 	.alpha_level = 0,
771*4882a593Smuzhiyun 	.thlock = 118,
772*4882a593Smuzhiyun 	.wbd_inv = 0,
773*4882a593Smuzhiyun 	.wbd_ref = 3530,
774*4882a593Smuzhiyun 	.wbd_sel = 1,
775*4882a593Smuzhiyun 	.wbd_alpha = 5,
776*4882a593Smuzhiyun 	.agc1_max = 65535,
777*4882a593Smuzhiyun 	.agc1_min = 0,
778*4882a593Smuzhiyun 	.agc2_max = 65535,
779*4882a593Smuzhiyun 	.agc2_min = 0,
780*4882a593Smuzhiyun 	.agc1_pt1 = 0,
781*4882a593Smuzhiyun 	.agc1_pt2 = 40,
782*4882a593Smuzhiyun 	.agc1_pt3 = 183,
783*4882a593Smuzhiyun 	.agc1_slope1 = 206,
784*4882a593Smuzhiyun 	.agc1_slope2 = 255,
785*4882a593Smuzhiyun 	.agc2_pt1 = 72,
786*4882a593Smuzhiyun 	.agc2_pt2 = 152,
787*4882a593Smuzhiyun 	.agc2_slope1 = 88,
788*4882a593Smuzhiyun 	.agc2_slope2 = 90,
789*4882a593Smuzhiyun 	.alpha_mant = 17,
790*4882a593Smuzhiyun 	.alpha_exp = 27,
791*4882a593Smuzhiyun 	.beta_mant = 23,
792*4882a593Smuzhiyun 	.beta_exp = 51,
793*4882a593Smuzhiyun 	.perform_agc_softsplit = 0,
794*4882a593Smuzhiyun };
795*4882a593Smuzhiyun 
dib7070_tuner_reset(struct dvb_frontend * fe,int onoff)796*4882a593Smuzhiyun static int dib7070_tuner_reset(struct dvb_frontend *fe, int onoff)
797*4882a593Smuzhiyun {
798*4882a593Smuzhiyun 	struct dvb_usb_adapter *adap = fe->dvb->priv;
799*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
800*4882a593Smuzhiyun 
801*4882a593Smuzhiyun 	deb_info("reset: %d", onoff);
802*4882a593Smuzhiyun 	return state->dib7000p_ops.set_gpio(fe, 8, 0, !onoff);
803*4882a593Smuzhiyun }
804*4882a593Smuzhiyun 
dib7070_tuner_sleep(struct dvb_frontend * fe,int onoff)805*4882a593Smuzhiyun static int dib7070_tuner_sleep(struct dvb_frontend *fe, int onoff)
806*4882a593Smuzhiyun {
807*4882a593Smuzhiyun 	struct dvb_usb_adapter *adap = fe->dvb->priv;
808*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
809*4882a593Smuzhiyun 
810*4882a593Smuzhiyun 	deb_info("sleep: %d", onoff);
811*4882a593Smuzhiyun 	return state->dib7000p_ops.set_gpio(fe, 9, 0, onoff);
812*4882a593Smuzhiyun }
813*4882a593Smuzhiyun 
814*4882a593Smuzhiyun static struct dib0070_config dib7070p_dib0070_config[2] = {
815*4882a593Smuzhiyun 	{
816*4882a593Smuzhiyun 		.i2c_address = DEFAULT_DIB0070_I2C_ADDRESS,
817*4882a593Smuzhiyun 		.reset = dib7070_tuner_reset,
818*4882a593Smuzhiyun 		.sleep = dib7070_tuner_sleep,
819*4882a593Smuzhiyun 		.clock_khz = 12000,
820*4882a593Smuzhiyun 		.clock_pad_drive = 4,
821*4882a593Smuzhiyun 		.charge_pump = 2,
822*4882a593Smuzhiyun 	}, {
823*4882a593Smuzhiyun 		.i2c_address = DEFAULT_DIB0070_I2C_ADDRESS,
824*4882a593Smuzhiyun 		.reset = dib7070_tuner_reset,
825*4882a593Smuzhiyun 		.sleep = dib7070_tuner_sleep,
826*4882a593Smuzhiyun 		.clock_khz = 12000,
827*4882a593Smuzhiyun 		.charge_pump = 2,
828*4882a593Smuzhiyun 	}
829*4882a593Smuzhiyun };
830*4882a593Smuzhiyun 
831*4882a593Smuzhiyun static struct dib0070_config dib7770p_dib0070_config = {
832*4882a593Smuzhiyun 	 .i2c_address = DEFAULT_DIB0070_I2C_ADDRESS,
833*4882a593Smuzhiyun 	 .reset = dib7070_tuner_reset,
834*4882a593Smuzhiyun 	 .sleep = dib7070_tuner_sleep,
835*4882a593Smuzhiyun 	 .clock_khz = 12000,
836*4882a593Smuzhiyun 	 .clock_pad_drive = 0,
837*4882a593Smuzhiyun 	 .flip_chip = 1,
838*4882a593Smuzhiyun 	 .charge_pump = 2,
839*4882a593Smuzhiyun };
840*4882a593Smuzhiyun 
dib7070_set_param_override(struct dvb_frontend * fe)841*4882a593Smuzhiyun static int dib7070_set_param_override(struct dvb_frontend *fe)
842*4882a593Smuzhiyun {
843*4882a593Smuzhiyun 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
844*4882a593Smuzhiyun 	struct dvb_usb_adapter *adap = fe->dvb->priv;
845*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
846*4882a593Smuzhiyun 
847*4882a593Smuzhiyun 	u16 offset;
848*4882a593Smuzhiyun 	u8 band = BAND_OF_FREQUENCY(p->frequency/1000);
849*4882a593Smuzhiyun 	switch (band) {
850*4882a593Smuzhiyun 		case BAND_VHF: offset = 950; break;
851*4882a593Smuzhiyun 		case BAND_UHF:
852*4882a593Smuzhiyun 		default: offset = 550; break;
853*4882a593Smuzhiyun 	}
854*4882a593Smuzhiyun 	deb_info("WBD for DiB7000P: %d\n", offset + dib0070_wbd_offset(fe));
855*4882a593Smuzhiyun 	state->dib7000p_ops.set_wbd_ref(fe, offset + dib0070_wbd_offset(fe));
856*4882a593Smuzhiyun 	return state->set_param_save(fe);
857*4882a593Smuzhiyun }
858*4882a593Smuzhiyun 
dib7770_set_param_override(struct dvb_frontend * fe)859*4882a593Smuzhiyun static int dib7770_set_param_override(struct dvb_frontend *fe)
860*4882a593Smuzhiyun {
861*4882a593Smuzhiyun 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
862*4882a593Smuzhiyun 	struct dvb_usb_adapter *adap = fe->dvb->priv;
863*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
864*4882a593Smuzhiyun 
865*4882a593Smuzhiyun 	u16 offset;
866*4882a593Smuzhiyun 	u8 band = BAND_OF_FREQUENCY(p->frequency/1000);
867*4882a593Smuzhiyun 	switch (band) {
868*4882a593Smuzhiyun 	case BAND_VHF:
869*4882a593Smuzhiyun 		state->dib7000p_ops.set_gpio(fe, 0, 0, 1);
870*4882a593Smuzhiyun 		offset = 850;
871*4882a593Smuzhiyun 		break;
872*4882a593Smuzhiyun 	case BAND_UHF:
873*4882a593Smuzhiyun 	default:
874*4882a593Smuzhiyun 		state->dib7000p_ops.set_gpio(fe, 0, 0, 0);
875*4882a593Smuzhiyun 		offset = 250;
876*4882a593Smuzhiyun 		break;
877*4882a593Smuzhiyun 	}
878*4882a593Smuzhiyun 	deb_info("WBD for DiB7000P: %d\n", offset + dib0070_wbd_offset(fe));
879*4882a593Smuzhiyun 	state->dib7000p_ops.set_wbd_ref(fe, offset + dib0070_wbd_offset(fe));
880*4882a593Smuzhiyun 	return state->set_param_save(fe);
881*4882a593Smuzhiyun }
882*4882a593Smuzhiyun 
dib7770p_tuner_attach(struct dvb_usb_adapter * adap)883*4882a593Smuzhiyun static int dib7770p_tuner_attach(struct dvb_usb_adapter *adap)
884*4882a593Smuzhiyun {
885*4882a593Smuzhiyun 	struct dib0700_adapter_state *st = adap->priv;
886*4882a593Smuzhiyun 	struct i2c_adapter *tun_i2c = st->dib7000p_ops.get_i2c_master(adap->fe_adap[0].fe,
887*4882a593Smuzhiyun 			 DIBX000_I2C_INTERFACE_TUNER, 1);
888*4882a593Smuzhiyun 
889*4882a593Smuzhiyun 	if (dvb_attach(dib0070_attach, adap->fe_adap[0].fe, tun_i2c,
890*4882a593Smuzhiyun 		       &dib7770p_dib0070_config) == NULL)
891*4882a593Smuzhiyun 		return -ENODEV;
892*4882a593Smuzhiyun 
893*4882a593Smuzhiyun 	st->set_param_save = adap->fe_adap[0].fe->ops.tuner_ops.set_params;
894*4882a593Smuzhiyun 	adap->fe_adap[0].fe->ops.tuner_ops.set_params = dib7770_set_param_override;
895*4882a593Smuzhiyun 	return 0;
896*4882a593Smuzhiyun }
897*4882a593Smuzhiyun 
dib7070p_tuner_attach(struct dvb_usb_adapter * adap)898*4882a593Smuzhiyun static int dib7070p_tuner_attach(struct dvb_usb_adapter *adap)
899*4882a593Smuzhiyun {
900*4882a593Smuzhiyun 	struct dib0700_adapter_state *st = adap->priv;
901*4882a593Smuzhiyun 	struct i2c_adapter *tun_i2c = st->dib7000p_ops.get_i2c_master(adap->fe_adap[0].fe, DIBX000_I2C_INTERFACE_TUNER, 1);
902*4882a593Smuzhiyun 
903*4882a593Smuzhiyun 	if (adap->id == 0) {
904*4882a593Smuzhiyun 		if (dvb_attach(dib0070_attach, adap->fe_adap[0].fe, tun_i2c, &dib7070p_dib0070_config[0]) == NULL)
905*4882a593Smuzhiyun 			return -ENODEV;
906*4882a593Smuzhiyun 	} else {
907*4882a593Smuzhiyun 		if (dvb_attach(dib0070_attach, adap->fe_adap[0].fe, tun_i2c, &dib7070p_dib0070_config[1]) == NULL)
908*4882a593Smuzhiyun 			return -ENODEV;
909*4882a593Smuzhiyun 	}
910*4882a593Smuzhiyun 
911*4882a593Smuzhiyun 	st->set_param_save = adap->fe_adap[0].fe->ops.tuner_ops.set_params;
912*4882a593Smuzhiyun 	adap->fe_adap[0].fe->ops.tuner_ops.set_params = dib7070_set_param_override;
913*4882a593Smuzhiyun 	return 0;
914*4882a593Smuzhiyun }
915*4882a593Smuzhiyun 
stk7700p_pid_filter(struct dvb_usb_adapter * adapter,int index,u16 pid,int onoff)916*4882a593Smuzhiyun static int stk7700p_pid_filter(struct dvb_usb_adapter *adapter, int index,
917*4882a593Smuzhiyun 		u16 pid, int onoff)
918*4882a593Smuzhiyun {
919*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adapter->priv;
920*4882a593Smuzhiyun 	struct dib0700_state *st = adapter->dev->priv;
921*4882a593Smuzhiyun 
922*4882a593Smuzhiyun 	if (st->is_dib7000pc)
923*4882a593Smuzhiyun 		return state->dib7000p_ops.pid_filter(adapter->fe_adap[0].fe, index, pid, onoff);
924*4882a593Smuzhiyun 	return dib7000m_pid_filter(adapter->fe_adap[0].fe, index, pid, onoff);
925*4882a593Smuzhiyun }
926*4882a593Smuzhiyun 
stk7700p_pid_filter_ctrl(struct dvb_usb_adapter * adapter,int onoff)927*4882a593Smuzhiyun static int stk7700p_pid_filter_ctrl(struct dvb_usb_adapter *adapter, int onoff)
928*4882a593Smuzhiyun {
929*4882a593Smuzhiyun 	struct dib0700_state *st = adapter->dev->priv;
930*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adapter->priv;
931*4882a593Smuzhiyun 	if (st->is_dib7000pc)
932*4882a593Smuzhiyun 		return state->dib7000p_ops.pid_filter_ctrl(adapter->fe_adap[0].fe, onoff);
933*4882a593Smuzhiyun 	return dib7000m_pid_filter_ctrl(adapter->fe_adap[0].fe, onoff);
934*4882a593Smuzhiyun }
935*4882a593Smuzhiyun 
stk70x0p_pid_filter(struct dvb_usb_adapter * adapter,int index,u16 pid,int onoff)936*4882a593Smuzhiyun static int stk70x0p_pid_filter(struct dvb_usb_adapter *adapter, int index, u16 pid, int onoff)
937*4882a593Smuzhiyun {
938*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adapter->priv;
939*4882a593Smuzhiyun 	return state->dib7000p_ops.pid_filter(adapter->fe_adap[0].fe, index, pid, onoff);
940*4882a593Smuzhiyun }
941*4882a593Smuzhiyun 
stk70x0p_pid_filter_ctrl(struct dvb_usb_adapter * adapter,int onoff)942*4882a593Smuzhiyun static int stk70x0p_pid_filter_ctrl(struct dvb_usb_adapter *adapter, int onoff)
943*4882a593Smuzhiyun {
944*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adapter->priv;
945*4882a593Smuzhiyun 	return state->dib7000p_ops.pid_filter_ctrl(adapter->fe_adap[0].fe, onoff);
946*4882a593Smuzhiyun }
947*4882a593Smuzhiyun 
948*4882a593Smuzhiyun static struct dibx000_bandwidth_config dib7070_bw_config_12_mhz = {
949*4882a593Smuzhiyun 	.internal = 60000,
950*4882a593Smuzhiyun 	.sampling = 15000,
951*4882a593Smuzhiyun 	.pll_prediv = 1,
952*4882a593Smuzhiyun 	.pll_ratio = 20,
953*4882a593Smuzhiyun 	.pll_range = 3,
954*4882a593Smuzhiyun 	.pll_reset = 1,
955*4882a593Smuzhiyun 	.pll_bypass = 0,
956*4882a593Smuzhiyun 	.enable_refdiv = 0,
957*4882a593Smuzhiyun 	.bypclk_div = 0,
958*4882a593Smuzhiyun 	.IO_CLK_en_core = 1,
959*4882a593Smuzhiyun 	.ADClkSrc = 1,
960*4882a593Smuzhiyun 	.modulo = 2,
961*4882a593Smuzhiyun 	.sad_cfg = (3 << 14) | (1 << 12) | (524 << 0),
962*4882a593Smuzhiyun 	.ifreq = (0 << 25) | 0,
963*4882a593Smuzhiyun 	.timf = 20452225,
964*4882a593Smuzhiyun 	.xtal_hz = 12000000,
965*4882a593Smuzhiyun };
966*4882a593Smuzhiyun 
967*4882a593Smuzhiyun static struct dib7000p_config dib7070p_dib7000p_config = {
968*4882a593Smuzhiyun 	.output_mpeg2_in_188_bytes = 1,
969*4882a593Smuzhiyun 
970*4882a593Smuzhiyun 	.agc_config_count = 1,
971*4882a593Smuzhiyun 	.agc = &dib7070_agc_config,
972*4882a593Smuzhiyun 	.bw  = &dib7070_bw_config_12_mhz,
973*4882a593Smuzhiyun 	.tuner_is_baseband = 1,
974*4882a593Smuzhiyun 	.spur_protect = 1,
975*4882a593Smuzhiyun 
976*4882a593Smuzhiyun 	.gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
977*4882a593Smuzhiyun 	.gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
978*4882a593Smuzhiyun 	.gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
979*4882a593Smuzhiyun 
980*4882a593Smuzhiyun 	.hostbus_diversity = 1,
981*4882a593Smuzhiyun };
982*4882a593Smuzhiyun 
983*4882a593Smuzhiyun /* STK7070P */
stk7070p_frontend_attach(struct dvb_usb_adapter * adap)984*4882a593Smuzhiyun static int stk7070p_frontend_attach(struct dvb_usb_adapter *adap)
985*4882a593Smuzhiyun {
986*4882a593Smuzhiyun 	struct usb_device_descriptor *p = &adap->dev->udev->descriptor;
987*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
988*4882a593Smuzhiyun 
989*4882a593Smuzhiyun 	if (!dvb_attach(dib7000p_attach, &state->dib7000p_ops))
990*4882a593Smuzhiyun 		return -ENODEV;
991*4882a593Smuzhiyun 
992*4882a593Smuzhiyun 	if (p->idVendor  == cpu_to_le16(USB_VID_PINNACLE) &&
993*4882a593Smuzhiyun 	    p->idProduct == cpu_to_le16(USB_PID_PINNACLE_PCTV72E))
994*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 0);
995*4882a593Smuzhiyun 	else
996*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
997*4882a593Smuzhiyun 	msleep(10);
998*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
999*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
1000*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
1001*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
1002*4882a593Smuzhiyun 
1003*4882a593Smuzhiyun 	dib0700_ctrl_clock(adap->dev, 72, 1);
1004*4882a593Smuzhiyun 
1005*4882a593Smuzhiyun 	msleep(10);
1006*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
1007*4882a593Smuzhiyun 	msleep(10);
1008*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
1009*4882a593Smuzhiyun 
1010*4882a593Smuzhiyun 	if (state->dib7000p_ops.i2c_enumeration(&adap->dev->i2c_adap, 1, 18,
1011*4882a593Smuzhiyun 				     &dib7070p_dib7000p_config) != 0) {
1012*4882a593Smuzhiyun 		err("%s: state->dib7000p_ops.i2c_enumeration failed.  Cannot continue\n",
1013*4882a593Smuzhiyun 		    __func__);
1014*4882a593Smuzhiyun 		dvb_detach(state->dib7000p_ops.set_wbd_ref);
1015*4882a593Smuzhiyun 		return -ENODEV;
1016*4882a593Smuzhiyun 	}
1017*4882a593Smuzhiyun 
1018*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib7000p_ops.init(&adap->dev->i2c_adap, 0x80,
1019*4882a593Smuzhiyun 		&dib7070p_dib7000p_config);
1020*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ? -ENODEV : 0;
1021*4882a593Smuzhiyun }
1022*4882a593Smuzhiyun 
1023*4882a593Smuzhiyun /* STK7770P */
1024*4882a593Smuzhiyun static struct dib7000p_config dib7770p_dib7000p_config = {
1025*4882a593Smuzhiyun 	.output_mpeg2_in_188_bytes = 1,
1026*4882a593Smuzhiyun 
1027*4882a593Smuzhiyun 	.agc_config_count = 1,
1028*4882a593Smuzhiyun 	.agc = &dib7070_agc_config,
1029*4882a593Smuzhiyun 	.bw  = &dib7070_bw_config_12_mhz,
1030*4882a593Smuzhiyun 	.tuner_is_baseband = 1,
1031*4882a593Smuzhiyun 	.spur_protect = 1,
1032*4882a593Smuzhiyun 
1033*4882a593Smuzhiyun 	.gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
1034*4882a593Smuzhiyun 	.gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
1035*4882a593Smuzhiyun 	.gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
1036*4882a593Smuzhiyun 
1037*4882a593Smuzhiyun 	.hostbus_diversity = 1,
1038*4882a593Smuzhiyun 	.enable_current_mirror = 1,
1039*4882a593Smuzhiyun 	.disable_sample_and_hold = 0,
1040*4882a593Smuzhiyun };
1041*4882a593Smuzhiyun 
stk7770p_frontend_attach(struct dvb_usb_adapter * adap)1042*4882a593Smuzhiyun static int stk7770p_frontend_attach(struct dvb_usb_adapter *adap)
1043*4882a593Smuzhiyun {
1044*4882a593Smuzhiyun 	struct usb_device_descriptor *p = &adap->dev->udev->descriptor;
1045*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
1046*4882a593Smuzhiyun 
1047*4882a593Smuzhiyun 	if (!dvb_attach(dib7000p_attach, &state->dib7000p_ops))
1048*4882a593Smuzhiyun 		return -ENODEV;
1049*4882a593Smuzhiyun 
1050*4882a593Smuzhiyun 	if (p->idVendor  == cpu_to_le16(USB_VID_PINNACLE) &&
1051*4882a593Smuzhiyun 	    p->idProduct == cpu_to_le16(USB_PID_PINNACLE_PCTV72E))
1052*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 0);
1053*4882a593Smuzhiyun 	else
1054*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
1055*4882a593Smuzhiyun 	msleep(10);
1056*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
1057*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
1058*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
1059*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
1060*4882a593Smuzhiyun 
1061*4882a593Smuzhiyun 	dib0700_ctrl_clock(adap->dev, 72, 1);
1062*4882a593Smuzhiyun 
1063*4882a593Smuzhiyun 	msleep(10);
1064*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
1065*4882a593Smuzhiyun 	msleep(10);
1066*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
1067*4882a593Smuzhiyun 
1068*4882a593Smuzhiyun 	if (state->dib7000p_ops.i2c_enumeration(&adap->dev->i2c_adap, 1, 18,
1069*4882a593Smuzhiyun 				     &dib7770p_dib7000p_config) != 0) {
1070*4882a593Smuzhiyun 		err("%s: state->dib7000p_ops.i2c_enumeration failed.  Cannot continue\n",
1071*4882a593Smuzhiyun 		    __func__);
1072*4882a593Smuzhiyun 		dvb_detach(state->dib7000p_ops.set_wbd_ref);
1073*4882a593Smuzhiyun 		return -ENODEV;
1074*4882a593Smuzhiyun 	}
1075*4882a593Smuzhiyun 
1076*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib7000p_ops.init(&adap->dev->i2c_adap, 0x80,
1077*4882a593Smuzhiyun 		&dib7770p_dib7000p_config);
1078*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ? -ENODEV : 0;
1079*4882a593Smuzhiyun }
1080*4882a593Smuzhiyun 
1081*4882a593Smuzhiyun /* DIB807x generic */
1082*4882a593Smuzhiyun static struct dibx000_agc_config dib807x_agc_config[2] = {
1083*4882a593Smuzhiyun 	{
1084*4882a593Smuzhiyun 		BAND_VHF,
1085*4882a593Smuzhiyun 		/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0,
1086*4882a593Smuzhiyun 		 * P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0,
1087*4882a593Smuzhiyun 		 * P_agc_inv_pwm2=0,P_agc_inh_dc_rv_est=0,
1088*4882a593Smuzhiyun 		 * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5,
1089*4882a593Smuzhiyun 		 * P_agc_write=0 */
1090*4882a593Smuzhiyun 		(0 << 15) | (0 << 14) | (7 << 11) | (0 << 10) | (0 << 9) |
1091*4882a593Smuzhiyun 			(0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) |
1092*4882a593Smuzhiyun 			(0 << 0), /* setup*/
1093*4882a593Smuzhiyun 
1094*4882a593Smuzhiyun 		600, /* inv_gain*/
1095*4882a593Smuzhiyun 		10,  /* time_stabiliz*/
1096*4882a593Smuzhiyun 
1097*4882a593Smuzhiyun 		0,  /* alpha_level*/
1098*4882a593Smuzhiyun 		118,  /* thlock*/
1099*4882a593Smuzhiyun 
1100*4882a593Smuzhiyun 		0,     /* wbd_inv*/
1101*4882a593Smuzhiyun 		3530,  /* wbd_ref*/
1102*4882a593Smuzhiyun 		1,     /* wbd_sel*/
1103*4882a593Smuzhiyun 		5,     /* wbd_alpha*/
1104*4882a593Smuzhiyun 
1105*4882a593Smuzhiyun 		65535,  /* agc1_max*/
1106*4882a593Smuzhiyun 		0,  /* agc1_min*/
1107*4882a593Smuzhiyun 
1108*4882a593Smuzhiyun 		65535,  /* agc2_max*/
1109*4882a593Smuzhiyun 		0,      /* agc2_min*/
1110*4882a593Smuzhiyun 
1111*4882a593Smuzhiyun 		0,      /* agc1_pt1*/
1112*4882a593Smuzhiyun 		40,     /* agc1_pt2*/
1113*4882a593Smuzhiyun 		183,    /* agc1_pt3*/
1114*4882a593Smuzhiyun 		206,    /* agc1_slope1*/
1115*4882a593Smuzhiyun 		255,    /* agc1_slope2*/
1116*4882a593Smuzhiyun 		72,     /* agc2_pt1*/
1117*4882a593Smuzhiyun 		152,    /* agc2_pt2*/
1118*4882a593Smuzhiyun 		88,     /* agc2_slope1*/
1119*4882a593Smuzhiyun 		90,     /* agc2_slope2*/
1120*4882a593Smuzhiyun 
1121*4882a593Smuzhiyun 		17,  /* alpha_mant*/
1122*4882a593Smuzhiyun 		27,  /* alpha_exp*/
1123*4882a593Smuzhiyun 		23,  /* beta_mant*/
1124*4882a593Smuzhiyun 		51,  /* beta_exp*/
1125*4882a593Smuzhiyun 
1126*4882a593Smuzhiyun 		0,  /* perform_agc_softsplit*/
1127*4882a593Smuzhiyun 	}, {
1128*4882a593Smuzhiyun 		BAND_UHF,
1129*4882a593Smuzhiyun 		/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0,
1130*4882a593Smuzhiyun 		 * P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0,
1131*4882a593Smuzhiyun 		 * P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
1132*4882a593Smuzhiyun 		 * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5,
1133*4882a593Smuzhiyun 		 * P_agc_write=0 */
1134*4882a593Smuzhiyun 		(0 << 15) | (0 << 14) | (1 << 11) | (0 << 10) | (0 << 9) |
1135*4882a593Smuzhiyun 			(0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) |
1136*4882a593Smuzhiyun 			(0 << 0), /* setup */
1137*4882a593Smuzhiyun 
1138*4882a593Smuzhiyun 		600, /* inv_gain*/
1139*4882a593Smuzhiyun 		10,  /* time_stabiliz*/
1140*4882a593Smuzhiyun 
1141*4882a593Smuzhiyun 		0,  /* alpha_level*/
1142*4882a593Smuzhiyun 		118,  /* thlock*/
1143*4882a593Smuzhiyun 
1144*4882a593Smuzhiyun 		0,     /* wbd_inv*/
1145*4882a593Smuzhiyun 		3530,  /* wbd_ref*/
1146*4882a593Smuzhiyun 		1,     /* wbd_sel*/
1147*4882a593Smuzhiyun 		5,     /* wbd_alpha*/
1148*4882a593Smuzhiyun 
1149*4882a593Smuzhiyun 		65535,  /* agc1_max*/
1150*4882a593Smuzhiyun 		0,  /* agc1_min*/
1151*4882a593Smuzhiyun 
1152*4882a593Smuzhiyun 		65535,  /* agc2_max*/
1153*4882a593Smuzhiyun 		0,      /* agc2_min*/
1154*4882a593Smuzhiyun 
1155*4882a593Smuzhiyun 		0,      /* agc1_pt1*/
1156*4882a593Smuzhiyun 		40,     /* agc1_pt2*/
1157*4882a593Smuzhiyun 		183,    /* agc1_pt3*/
1158*4882a593Smuzhiyun 		206,    /* agc1_slope1*/
1159*4882a593Smuzhiyun 		255,    /* agc1_slope2*/
1160*4882a593Smuzhiyun 		72,     /* agc2_pt1*/
1161*4882a593Smuzhiyun 		152,    /* agc2_pt2*/
1162*4882a593Smuzhiyun 		88,     /* agc2_slope1*/
1163*4882a593Smuzhiyun 		90,     /* agc2_slope2*/
1164*4882a593Smuzhiyun 
1165*4882a593Smuzhiyun 		17,  /* alpha_mant*/
1166*4882a593Smuzhiyun 		27,  /* alpha_exp*/
1167*4882a593Smuzhiyun 		23,  /* beta_mant*/
1168*4882a593Smuzhiyun 		51,  /* beta_exp*/
1169*4882a593Smuzhiyun 
1170*4882a593Smuzhiyun 		0,  /* perform_agc_softsplit*/
1171*4882a593Smuzhiyun 	}
1172*4882a593Smuzhiyun };
1173*4882a593Smuzhiyun 
1174*4882a593Smuzhiyun static struct dibx000_bandwidth_config dib807x_bw_config_12_mhz = {
1175*4882a593Smuzhiyun 	.internal = 60000,
1176*4882a593Smuzhiyun 	.sampling = 15000,
1177*4882a593Smuzhiyun 	.pll_prediv = 1,
1178*4882a593Smuzhiyun 	.pll_ratio = 20,
1179*4882a593Smuzhiyun 	.pll_range = 3,
1180*4882a593Smuzhiyun 	.pll_reset = 1,
1181*4882a593Smuzhiyun 	.pll_bypass = 0,
1182*4882a593Smuzhiyun 	.enable_refdiv = 0,
1183*4882a593Smuzhiyun 	.bypclk_div = 0,
1184*4882a593Smuzhiyun 	.IO_CLK_en_core = 1,
1185*4882a593Smuzhiyun 	.ADClkSrc = 1,
1186*4882a593Smuzhiyun 	.modulo = 2,
1187*4882a593Smuzhiyun 	.sad_cfg = (3 << 14) | (1 << 12) | (599 << 0),	/* sad_cfg: refsel, sel, freq_15k*/
1188*4882a593Smuzhiyun 	.ifreq = (0 << 25) | 0,				/* ifreq = 0.000000 MHz*/
1189*4882a593Smuzhiyun 	.timf = 18179755,
1190*4882a593Smuzhiyun 	.xtal_hz = 12000000,
1191*4882a593Smuzhiyun };
1192*4882a593Smuzhiyun 
1193*4882a593Smuzhiyun static struct dib8000_config dib807x_dib8000_config[2] = {
1194*4882a593Smuzhiyun 	{
1195*4882a593Smuzhiyun 		.output_mpeg2_in_188_bytes = 1,
1196*4882a593Smuzhiyun 
1197*4882a593Smuzhiyun 		.agc_config_count = 2,
1198*4882a593Smuzhiyun 		.agc = dib807x_agc_config,
1199*4882a593Smuzhiyun 		.pll = &dib807x_bw_config_12_mhz,
1200*4882a593Smuzhiyun 		.tuner_is_baseband = 1,
1201*4882a593Smuzhiyun 
1202*4882a593Smuzhiyun 		.gpio_dir = DIB8000_GPIO_DEFAULT_DIRECTIONS,
1203*4882a593Smuzhiyun 		.gpio_val = DIB8000_GPIO_DEFAULT_VALUES,
1204*4882a593Smuzhiyun 		.gpio_pwm_pos = DIB8000_GPIO_DEFAULT_PWM_POS,
1205*4882a593Smuzhiyun 
1206*4882a593Smuzhiyun 		.hostbus_diversity = 1,
1207*4882a593Smuzhiyun 		.div_cfg = 1,
1208*4882a593Smuzhiyun 		.agc_control = &dib0070_ctrl_agc_filter,
1209*4882a593Smuzhiyun 		.output_mode = OUTMODE_MPEG2_FIFO,
1210*4882a593Smuzhiyun 		.drives = 0x2d98,
1211*4882a593Smuzhiyun 	}, {
1212*4882a593Smuzhiyun 		.output_mpeg2_in_188_bytes = 1,
1213*4882a593Smuzhiyun 
1214*4882a593Smuzhiyun 		.agc_config_count = 2,
1215*4882a593Smuzhiyun 		.agc = dib807x_agc_config,
1216*4882a593Smuzhiyun 		.pll = &dib807x_bw_config_12_mhz,
1217*4882a593Smuzhiyun 		.tuner_is_baseband = 1,
1218*4882a593Smuzhiyun 
1219*4882a593Smuzhiyun 		.gpio_dir = DIB8000_GPIO_DEFAULT_DIRECTIONS,
1220*4882a593Smuzhiyun 		.gpio_val = DIB8000_GPIO_DEFAULT_VALUES,
1221*4882a593Smuzhiyun 		.gpio_pwm_pos = DIB8000_GPIO_DEFAULT_PWM_POS,
1222*4882a593Smuzhiyun 
1223*4882a593Smuzhiyun 		.hostbus_diversity = 1,
1224*4882a593Smuzhiyun 		.agc_control = &dib0070_ctrl_agc_filter,
1225*4882a593Smuzhiyun 		.output_mode = OUTMODE_MPEG2_FIFO,
1226*4882a593Smuzhiyun 		.drives = 0x2d98,
1227*4882a593Smuzhiyun 	}
1228*4882a593Smuzhiyun };
1229*4882a593Smuzhiyun 
dib80xx_tuner_reset(struct dvb_frontend * fe,int onoff)1230*4882a593Smuzhiyun static int dib80xx_tuner_reset(struct dvb_frontend *fe, int onoff)
1231*4882a593Smuzhiyun {
1232*4882a593Smuzhiyun 	struct dvb_usb_adapter *adap = fe->dvb->priv;
1233*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
1234*4882a593Smuzhiyun 
1235*4882a593Smuzhiyun 	return state->dib8000_ops.set_gpio(fe, 5, 0, !onoff);
1236*4882a593Smuzhiyun }
1237*4882a593Smuzhiyun 
dib80xx_tuner_sleep(struct dvb_frontend * fe,int onoff)1238*4882a593Smuzhiyun static int dib80xx_tuner_sleep(struct dvb_frontend *fe, int onoff)
1239*4882a593Smuzhiyun {
1240*4882a593Smuzhiyun 	struct dvb_usb_adapter *adap = fe->dvb->priv;
1241*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
1242*4882a593Smuzhiyun 
1243*4882a593Smuzhiyun 	return state->dib8000_ops.set_gpio(fe, 0, 0, onoff);
1244*4882a593Smuzhiyun }
1245*4882a593Smuzhiyun 
1246*4882a593Smuzhiyun static const struct dib0070_wbd_gain_cfg dib8070_wbd_gain_cfg[] = {
1247*4882a593Smuzhiyun     { 240,      7},
1248*4882a593Smuzhiyun     { 0xffff,   6},
1249*4882a593Smuzhiyun };
1250*4882a593Smuzhiyun 
1251*4882a593Smuzhiyun static struct dib0070_config dib807x_dib0070_config[2] = {
1252*4882a593Smuzhiyun 	{
1253*4882a593Smuzhiyun 		.i2c_address = DEFAULT_DIB0070_I2C_ADDRESS,
1254*4882a593Smuzhiyun 		.reset = dib80xx_tuner_reset,
1255*4882a593Smuzhiyun 		.sleep = dib80xx_tuner_sleep,
1256*4882a593Smuzhiyun 		.clock_khz = 12000,
1257*4882a593Smuzhiyun 		.clock_pad_drive = 4,
1258*4882a593Smuzhiyun 		.vga_filter = 1,
1259*4882a593Smuzhiyun 		.force_crystal_mode = 1,
1260*4882a593Smuzhiyun 		.enable_third_order_filter = 1,
1261*4882a593Smuzhiyun 		.charge_pump = 0,
1262*4882a593Smuzhiyun 		.wbd_gain = dib8070_wbd_gain_cfg,
1263*4882a593Smuzhiyun 		.osc_buffer_state = 0,
1264*4882a593Smuzhiyun 		.freq_offset_khz_uhf = -100,
1265*4882a593Smuzhiyun 		.freq_offset_khz_vhf = -100,
1266*4882a593Smuzhiyun 	}, {
1267*4882a593Smuzhiyun 		.i2c_address = DEFAULT_DIB0070_I2C_ADDRESS,
1268*4882a593Smuzhiyun 		.reset = dib80xx_tuner_reset,
1269*4882a593Smuzhiyun 		.sleep = dib80xx_tuner_sleep,
1270*4882a593Smuzhiyun 		.clock_khz = 12000,
1271*4882a593Smuzhiyun 		.clock_pad_drive = 2,
1272*4882a593Smuzhiyun 		.vga_filter = 1,
1273*4882a593Smuzhiyun 		.force_crystal_mode = 1,
1274*4882a593Smuzhiyun 		.enable_third_order_filter = 1,
1275*4882a593Smuzhiyun 		.charge_pump = 0,
1276*4882a593Smuzhiyun 		.wbd_gain = dib8070_wbd_gain_cfg,
1277*4882a593Smuzhiyun 		.osc_buffer_state = 0,
1278*4882a593Smuzhiyun 		.freq_offset_khz_uhf = -25,
1279*4882a593Smuzhiyun 		.freq_offset_khz_vhf = -25,
1280*4882a593Smuzhiyun 	}
1281*4882a593Smuzhiyun };
1282*4882a593Smuzhiyun 
dib807x_set_param_override(struct dvb_frontend * fe)1283*4882a593Smuzhiyun static int dib807x_set_param_override(struct dvb_frontend *fe)
1284*4882a593Smuzhiyun {
1285*4882a593Smuzhiyun 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1286*4882a593Smuzhiyun 	struct dvb_usb_adapter *adap = fe->dvb->priv;
1287*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
1288*4882a593Smuzhiyun 
1289*4882a593Smuzhiyun 	u16 offset = dib0070_wbd_offset(fe);
1290*4882a593Smuzhiyun 	u8 band = BAND_OF_FREQUENCY(p->frequency/1000);
1291*4882a593Smuzhiyun 	switch (band) {
1292*4882a593Smuzhiyun 	case BAND_VHF:
1293*4882a593Smuzhiyun 		offset += 750;
1294*4882a593Smuzhiyun 		break;
1295*4882a593Smuzhiyun 	case BAND_UHF:  /* fall-thru wanted */
1296*4882a593Smuzhiyun 	default:
1297*4882a593Smuzhiyun 		offset += 250; break;
1298*4882a593Smuzhiyun 	}
1299*4882a593Smuzhiyun 	deb_info("WBD for DiB8000: %d\n", offset);
1300*4882a593Smuzhiyun 	state->dib8000_ops.set_wbd_ref(fe, offset);
1301*4882a593Smuzhiyun 
1302*4882a593Smuzhiyun 	return state->set_param_save(fe);
1303*4882a593Smuzhiyun }
1304*4882a593Smuzhiyun 
dib807x_tuner_attach(struct dvb_usb_adapter * adap)1305*4882a593Smuzhiyun static int dib807x_tuner_attach(struct dvb_usb_adapter *adap)
1306*4882a593Smuzhiyun {
1307*4882a593Smuzhiyun 	struct dib0700_adapter_state *st = adap->priv;
1308*4882a593Smuzhiyun 	struct i2c_adapter *tun_i2c = st->dib8000_ops.get_i2c_master(adap->fe_adap[0].fe,
1309*4882a593Smuzhiyun 			DIBX000_I2C_INTERFACE_TUNER, 1);
1310*4882a593Smuzhiyun 
1311*4882a593Smuzhiyun 	if (adap->id == 0) {
1312*4882a593Smuzhiyun 		if (dvb_attach(dib0070_attach, adap->fe_adap[0].fe, tun_i2c,
1313*4882a593Smuzhiyun 				&dib807x_dib0070_config[0]) == NULL)
1314*4882a593Smuzhiyun 			return -ENODEV;
1315*4882a593Smuzhiyun 	} else {
1316*4882a593Smuzhiyun 		if (dvb_attach(dib0070_attach, adap->fe_adap[0].fe, tun_i2c,
1317*4882a593Smuzhiyun 				&dib807x_dib0070_config[1]) == NULL)
1318*4882a593Smuzhiyun 			return -ENODEV;
1319*4882a593Smuzhiyun 	}
1320*4882a593Smuzhiyun 
1321*4882a593Smuzhiyun 	st->set_param_save = adap->fe_adap[0].fe->ops.tuner_ops.set_params;
1322*4882a593Smuzhiyun 	adap->fe_adap[0].fe->ops.tuner_ops.set_params = dib807x_set_param_override;
1323*4882a593Smuzhiyun 	return 0;
1324*4882a593Smuzhiyun }
1325*4882a593Smuzhiyun 
stk80xx_pid_filter(struct dvb_usb_adapter * adapter,int index,u16 pid,int onoff)1326*4882a593Smuzhiyun static int stk80xx_pid_filter(struct dvb_usb_adapter *adapter, int index,
1327*4882a593Smuzhiyun 	u16 pid, int onoff)
1328*4882a593Smuzhiyun {
1329*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adapter->priv;
1330*4882a593Smuzhiyun 
1331*4882a593Smuzhiyun 	return state->dib8000_ops.pid_filter(adapter->fe_adap[0].fe, index, pid, onoff);
1332*4882a593Smuzhiyun }
1333*4882a593Smuzhiyun 
stk80xx_pid_filter_ctrl(struct dvb_usb_adapter * adapter,int onoff)1334*4882a593Smuzhiyun static int stk80xx_pid_filter_ctrl(struct dvb_usb_adapter *adapter,
1335*4882a593Smuzhiyun 		int onoff)
1336*4882a593Smuzhiyun {
1337*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adapter->priv;
1338*4882a593Smuzhiyun 
1339*4882a593Smuzhiyun 	return state->dib8000_ops.pid_filter_ctrl(adapter->fe_adap[0].fe, onoff);
1340*4882a593Smuzhiyun }
1341*4882a593Smuzhiyun 
1342*4882a593Smuzhiyun /* STK807x */
stk807x_frontend_attach(struct dvb_usb_adapter * adap)1343*4882a593Smuzhiyun static int stk807x_frontend_attach(struct dvb_usb_adapter *adap)
1344*4882a593Smuzhiyun {
1345*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
1346*4882a593Smuzhiyun 
1347*4882a593Smuzhiyun 	if (!dvb_attach(dib8000_attach, &state->dib8000_ops))
1348*4882a593Smuzhiyun 		return -ENODEV;
1349*4882a593Smuzhiyun 
1350*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
1351*4882a593Smuzhiyun 	msleep(10);
1352*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
1353*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
1354*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
1355*4882a593Smuzhiyun 
1356*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
1357*4882a593Smuzhiyun 
1358*4882a593Smuzhiyun 	dib0700_ctrl_clock(adap->dev, 72, 1);
1359*4882a593Smuzhiyun 
1360*4882a593Smuzhiyun 	msleep(10);
1361*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
1362*4882a593Smuzhiyun 	msleep(10);
1363*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
1364*4882a593Smuzhiyun 
1365*4882a593Smuzhiyun 	state->dib8000_ops.i2c_enumeration(&adap->dev->i2c_adap, 1, 18,
1366*4882a593Smuzhiyun 				0x80, 0);
1367*4882a593Smuzhiyun 
1368*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib8000_ops.init(&adap->dev->i2c_adap, 0x80,
1369*4882a593Smuzhiyun 			      &dib807x_dib8000_config[0]);
1370*4882a593Smuzhiyun 
1371*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ?  -ENODEV : 0;
1372*4882a593Smuzhiyun }
1373*4882a593Smuzhiyun 
1374*4882a593Smuzhiyun /* STK807xPVR */
stk807xpvr_frontend_attach0(struct dvb_usb_adapter * adap)1375*4882a593Smuzhiyun static int stk807xpvr_frontend_attach0(struct dvb_usb_adapter *adap)
1376*4882a593Smuzhiyun {
1377*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
1378*4882a593Smuzhiyun 
1379*4882a593Smuzhiyun 	if (!dvb_attach(dib8000_attach, &state->dib8000_ops))
1380*4882a593Smuzhiyun 		return -ENODEV;
1381*4882a593Smuzhiyun 
1382*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 0);
1383*4882a593Smuzhiyun 	msleep(30);
1384*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
1385*4882a593Smuzhiyun 	msleep(500);
1386*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
1387*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
1388*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
1389*4882a593Smuzhiyun 
1390*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
1391*4882a593Smuzhiyun 
1392*4882a593Smuzhiyun 	dib0700_ctrl_clock(adap->dev, 72, 1);
1393*4882a593Smuzhiyun 
1394*4882a593Smuzhiyun 	msleep(10);
1395*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
1396*4882a593Smuzhiyun 	msleep(10);
1397*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
1398*4882a593Smuzhiyun 
1399*4882a593Smuzhiyun 	/* initialize IC 0 */
1400*4882a593Smuzhiyun 	state->dib8000_ops.i2c_enumeration(&adap->dev->i2c_adap, 1, 0x22, 0x80, 0);
1401*4882a593Smuzhiyun 
1402*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib8000_ops.init(&adap->dev->i2c_adap, 0x80,
1403*4882a593Smuzhiyun 			      &dib807x_dib8000_config[0]);
1404*4882a593Smuzhiyun 
1405*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ? -ENODEV : 0;
1406*4882a593Smuzhiyun }
1407*4882a593Smuzhiyun 
stk807xpvr_frontend_attach1(struct dvb_usb_adapter * adap)1408*4882a593Smuzhiyun static int stk807xpvr_frontend_attach1(struct dvb_usb_adapter *adap)
1409*4882a593Smuzhiyun {
1410*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
1411*4882a593Smuzhiyun 
1412*4882a593Smuzhiyun 	if (!dvb_attach(dib8000_attach, &state->dib8000_ops))
1413*4882a593Smuzhiyun 		return -ENODEV;
1414*4882a593Smuzhiyun 
1415*4882a593Smuzhiyun 	/* initialize IC 1 */
1416*4882a593Smuzhiyun 	state->dib8000_ops.i2c_enumeration(&adap->dev->i2c_adap, 1, 0x12, 0x82, 0);
1417*4882a593Smuzhiyun 
1418*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib8000_ops.init(&adap->dev->i2c_adap, 0x82,
1419*4882a593Smuzhiyun 			      &dib807x_dib8000_config[1]);
1420*4882a593Smuzhiyun 
1421*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ? -ENODEV : 0;
1422*4882a593Smuzhiyun }
1423*4882a593Smuzhiyun 
1424*4882a593Smuzhiyun /* STK8096GP */
1425*4882a593Smuzhiyun static struct dibx000_agc_config dib8090_agc_config[2] = {
1426*4882a593Smuzhiyun 	{
1427*4882a593Smuzhiyun 	.band_caps = BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND,
1428*4882a593Smuzhiyun 	/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1,
1429*4882a593Smuzhiyun 	 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
1430*4882a593Smuzhiyun 	 * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
1431*4882a593Smuzhiyun 	.setup = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
1432*4882a593Smuzhiyun 	| (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
1433*4882a593Smuzhiyun 
1434*4882a593Smuzhiyun 	.inv_gain = 787,
1435*4882a593Smuzhiyun 	.time_stabiliz = 10,
1436*4882a593Smuzhiyun 
1437*4882a593Smuzhiyun 	.alpha_level = 0,
1438*4882a593Smuzhiyun 	.thlock = 118,
1439*4882a593Smuzhiyun 
1440*4882a593Smuzhiyun 	.wbd_inv = 0,
1441*4882a593Smuzhiyun 	.wbd_ref = 3530,
1442*4882a593Smuzhiyun 	.wbd_sel = 1,
1443*4882a593Smuzhiyun 	.wbd_alpha = 5,
1444*4882a593Smuzhiyun 
1445*4882a593Smuzhiyun 	.agc1_max = 65535,
1446*4882a593Smuzhiyun 	.agc1_min = 0,
1447*4882a593Smuzhiyun 
1448*4882a593Smuzhiyun 	.agc2_max = 65535,
1449*4882a593Smuzhiyun 	.agc2_min = 0,
1450*4882a593Smuzhiyun 
1451*4882a593Smuzhiyun 	.agc1_pt1 = 0,
1452*4882a593Smuzhiyun 	.agc1_pt2 = 32,
1453*4882a593Smuzhiyun 	.agc1_pt3 = 114,
1454*4882a593Smuzhiyun 	.agc1_slope1 = 143,
1455*4882a593Smuzhiyun 	.agc1_slope2 = 144,
1456*4882a593Smuzhiyun 	.agc2_pt1 = 114,
1457*4882a593Smuzhiyun 	.agc2_pt2 = 227,
1458*4882a593Smuzhiyun 	.agc2_slope1 = 116,
1459*4882a593Smuzhiyun 	.agc2_slope2 = 117,
1460*4882a593Smuzhiyun 
1461*4882a593Smuzhiyun 	.alpha_mant = 28,
1462*4882a593Smuzhiyun 	.alpha_exp = 26,
1463*4882a593Smuzhiyun 	.beta_mant = 31,
1464*4882a593Smuzhiyun 	.beta_exp = 51,
1465*4882a593Smuzhiyun 
1466*4882a593Smuzhiyun 	.perform_agc_softsplit = 0,
1467*4882a593Smuzhiyun 	},
1468*4882a593Smuzhiyun 	{
1469*4882a593Smuzhiyun 	.band_caps = BAND_CBAND,
1470*4882a593Smuzhiyun 	/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1,
1471*4882a593Smuzhiyun 	 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
1472*4882a593Smuzhiyun 	 * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
1473*4882a593Smuzhiyun 	.setup = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
1474*4882a593Smuzhiyun 	| (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
1475*4882a593Smuzhiyun 
1476*4882a593Smuzhiyun 	.inv_gain = 787,
1477*4882a593Smuzhiyun 	.time_stabiliz = 10,
1478*4882a593Smuzhiyun 
1479*4882a593Smuzhiyun 	.alpha_level = 0,
1480*4882a593Smuzhiyun 	.thlock = 118,
1481*4882a593Smuzhiyun 
1482*4882a593Smuzhiyun 	.wbd_inv = 0,
1483*4882a593Smuzhiyun 	.wbd_ref = 3530,
1484*4882a593Smuzhiyun 	.wbd_sel = 1,
1485*4882a593Smuzhiyun 	.wbd_alpha = 5,
1486*4882a593Smuzhiyun 
1487*4882a593Smuzhiyun 	.agc1_max = 0,
1488*4882a593Smuzhiyun 	.agc1_min = 0,
1489*4882a593Smuzhiyun 
1490*4882a593Smuzhiyun 	.agc2_max = 65535,
1491*4882a593Smuzhiyun 	.agc2_min = 0,
1492*4882a593Smuzhiyun 
1493*4882a593Smuzhiyun 	.agc1_pt1 = 0,
1494*4882a593Smuzhiyun 	.agc1_pt2 = 32,
1495*4882a593Smuzhiyun 	.agc1_pt3 = 114,
1496*4882a593Smuzhiyun 	.agc1_slope1 = 143,
1497*4882a593Smuzhiyun 	.agc1_slope2 = 144,
1498*4882a593Smuzhiyun 	.agc2_pt1 = 114,
1499*4882a593Smuzhiyun 	.agc2_pt2 = 227,
1500*4882a593Smuzhiyun 	.agc2_slope1 = 116,
1501*4882a593Smuzhiyun 	.agc2_slope2 = 117,
1502*4882a593Smuzhiyun 
1503*4882a593Smuzhiyun 	.alpha_mant = 28,
1504*4882a593Smuzhiyun 	.alpha_exp = 26,
1505*4882a593Smuzhiyun 	.beta_mant = 31,
1506*4882a593Smuzhiyun 	.beta_exp = 51,
1507*4882a593Smuzhiyun 
1508*4882a593Smuzhiyun 	.perform_agc_softsplit = 0,
1509*4882a593Smuzhiyun 	}
1510*4882a593Smuzhiyun };
1511*4882a593Smuzhiyun 
1512*4882a593Smuzhiyun static struct dibx000_bandwidth_config dib8090_pll_config_12mhz = {
1513*4882a593Smuzhiyun 	.internal = 54000,
1514*4882a593Smuzhiyun 	.sampling = 13500,
1515*4882a593Smuzhiyun 
1516*4882a593Smuzhiyun 	.pll_prediv = 1,
1517*4882a593Smuzhiyun 	.pll_ratio = 18,
1518*4882a593Smuzhiyun 	.pll_range = 3,
1519*4882a593Smuzhiyun 	.pll_reset = 1,
1520*4882a593Smuzhiyun 	.pll_bypass = 0,
1521*4882a593Smuzhiyun 
1522*4882a593Smuzhiyun 	.enable_refdiv = 0,
1523*4882a593Smuzhiyun 	.bypclk_div = 0,
1524*4882a593Smuzhiyun 	.IO_CLK_en_core = 1,
1525*4882a593Smuzhiyun 	.ADClkSrc = 1,
1526*4882a593Smuzhiyun 	.modulo = 2,
1527*4882a593Smuzhiyun 
1528*4882a593Smuzhiyun 	.sad_cfg = (3 << 14) | (1 << 12) | (599 << 0),
1529*4882a593Smuzhiyun 
1530*4882a593Smuzhiyun 	.ifreq = (0 << 25) | 0,
1531*4882a593Smuzhiyun 	.timf = 20199727,
1532*4882a593Smuzhiyun 
1533*4882a593Smuzhiyun 	.xtal_hz = 12000000,
1534*4882a593Smuzhiyun };
1535*4882a593Smuzhiyun 
dib8090_get_adc_power(struct dvb_frontend * fe)1536*4882a593Smuzhiyun static int dib8090_get_adc_power(struct dvb_frontend *fe)
1537*4882a593Smuzhiyun {
1538*4882a593Smuzhiyun 	struct dvb_usb_adapter *adap = fe->dvb->priv;
1539*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
1540*4882a593Smuzhiyun 
1541*4882a593Smuzhiyun 	return state->dib8000_ops.get_adc_power(fe, 1);
1542*4882a593Smuzhiyun }
1543*4882a593Smuzhiyun 
dib8090_agc_control(struct dvb_frontend * fe,u8 restart)1544*4882a593Smuzhiyun static void dib8090_agc_control(struct dvb_frontend *fe, u8 restart)
1545*4882a593Smuzhiyun {
1546*4882a593Smuzhiyun 	deb_info("AGC control callback: %i\n", restart);
1547*4882a593Smuzhiyun 	dib0090_dcc_freq(fe, restart);
1548*4882a593Smuzhiyun 
1549*4882a593Smuzhiyun 	if (restart == 0) /* before AGC startup */
1550*4882a593Smuzhiyun 		dib0090_set_dc_servo(fe, 1);
1551*4882a593Smuzhiyun }
1552*4882a593Smuzhiyun 
1553*4882a593Smuzhiyun static struct dib8000_config dib809x_dib8000_config[2] = {
1554*4882a593Smuzhiyun 	{
1555*4882a593Smuzhiyun 	.output_mpeg2_in_188_bytes = 1,
1556*4882a593Smuzhiyun 
1557*4882a593Smuzhiyun 	.agc_config_count = 2,
1558*4882a593Smuzhiyun 	.agc = dib8090_agc_config,
1559*4882a593Smuzhiyun 	.agc_control = dib8090_agc_control,
1560*4882a593Smuzhiyun 	.pll = &dib8090_pll_config_12mhz,
1561*4882a593Smuzhiyun 	.tuner_is_baseband = 1,
1562*4882a593Smuzhiyun 
1563*4882a593Smuzhiyun 	.gpio_dir = DIB8000_GPIO_DEFAULT_DIRECTIONS,
1564*4882a593Smuzhiyun 	.gpio_val = DIB8000_GPIO_DEFAULT_VALUES,
1565*4882a593Smuzhiyun 	.gpio_pwm_pos = DIB8000_GPIO_DEFAULT_PWM_POS,
1566*4882a593Smuzhiyun 
1567*4882a593Smuzhiyun 	.hostbus_diversity = 1,
1568*4882a593Smuzhiyun 	.div_cfg = 0x31,
1569*4882a593Smuzhiyun 	.output_mode = OUTMODE_MPEG2_FIFO,
1570*4882a593Smuzhiyun 	.drives = 0x2d98,
1571*4882a593Smuzhiyun 	.diversity_delay = 48,
1572*4882a593Smuzhiyun 	.refclksel = 3,
1573*4882a593Smuzhiyun 	}, {
1574*4882a593Smuzhiyun 	.output_mpeg2_in_188_bytes = 1,
1575*4882a593Smuzhiyun 
1576*4882a593Smuzhiyun 	.agc_config_count = 2,
1577*4882a593Smuzhiyun 	.agc = dib8090_agc_config,
1578*4882a593Smuzhiyun 	.agc_control = dib8090_agc_control,
1579*4882a593Smuzhiyun 	.pll = &dib8090_pll_config_12mhz,
1580*4882a593Smuzhiyun 	.tuner_is_baseband = 1,
1581*4882a593Smuzhiyun 
1582*4882a593Smuzhiyun 	.gpio_dir = DIB8000_GPIO_DEFAULT_DIRECTIONS,
1583*4882a593Smuzhiyun 	.gpio_val = DIB8000_GPIO_DEFAULT_VALUES,
1584*4882a593Smuzhiyun 	.gpio_pwm_pos = DIB8000_GPIO_DEFAULT_PWM_POS,
1585*4882a593Smuzhiyun 
1586*4882a593Smuzhiyun 	.hostbus_diversity = 1,
1587*4882a593Smuzhiyun 	.div_cfg = 0x31,
1588*4882a593Smuzhiyun 	.output_mode = OUTMODE_DIVERSITY,
1589*4882a593Smuzhiyun 	.drives = 0x2d08,
1590*4882a593Smuzhiyun 	.diversity_delay = 1,
1591*4882a593Smuzhiyun 	.refclksel = 3,
1592*4882a593Smuzhiyun 	}
1593*4882a593Smuzhiyun };
1594*4882a593Smuzhiyun 
1595*4882a593Smuzhiyun static struct dib0090_wbd_slope dib8090_wbd_table[] = {
1596*4882a593Smuzhiyun 	/* max freq ; cold slope ; cold offset ; warm slope ; warm offset ; wbd gain */
1597*4882a593Smuzhiyun 	{ 120,     0, 500,  0,   500, 4 }, /* CBAND */
1598*4882a593Smuzhiyun 	{ 170,     0, 450,  0,   450, 4 }, /* CBAND */
1599*4882a593Smuzhiyun 	{ 380,    48, 373, 28,   259, 6 }, /* VHF */
1600*4882a593Smuzhiyun 	{ 860,    34, 700, 36,   616, 6 }, /* high UHF */
1601*4882a593Smuzhiyun 	{ 0xFFFF, 34, 700, 36,   616, 6 }, /* default */
1602*4882a593Smuzhiyun };
1603*4882a593Smuzhiyun 
1604*4882a593Smuzhiyun static struct dib0090_config dib809x_dib0090_config = {
1605*4882a593Smuzhiyun 	.io.pll_bypass = 1,
1606*4882a593Smuzhiyun 	.io.pll_range = 1,
1607*4882a593Smuzhiyun 	.io.pll_prediv = 1,
1608*4882a593Smuzhiyun 	.io.pll_loopdiv = 20,
1609*4882a593Smuzhiyun 	.io.adc_clock_ratio = 8,
1610*4882a593Smuzhiyun 	.io.pll_int_loop_filt = 0,
1611*4882a593Smuzhiyun 	.io.clock_khz = 12000,
1612*4882a593Smuzhiyun 	.reset = dib80xx_tuner_reset,
1613*4882a593Smuzhiyun 	.sleep = dib80xx_tuner_sleep,
1614*4882a593Smuzhiyun 	.clkouttobamse = 1,
1615*4882a593Smuzhiyun 	.analog_output = 1,
1616*4882a593Smuzhiyun 	.i2c_address = DEFAULT_DIB0090_I2C_ADDRESS,
1617*4882a593Smuzhiyun 	.use_pwm_agc = 1,
1618*4882a593Smuzhiyun 	.clkoutdrive = 1,
1619*4882a593Smuzhiyun 	.get_adc_power = dib8090_get_adc_power,
1620*4882a593Smuzhiyun 	.freq_offset_khz_uhf = -63,
1621*4882a593Smuzhiyun 	.freq_offset_khz_vhf = -143,
1622*4882a593Smuzhiyun 	.wbd = dib8090_wbd_table,
1623*4882a593Smuzhiyun 	.fref_clock_ratio = 6,
1624*4882a593Smuzhiyun };
1625*4882a593Smuzhiyun 
dib8090_compute_pll_parameters(struct dvb_frontend * fe)1626*4882a593Smuzhiyun static u8 dib8090_compute_pll_parameters(struct dvb_frontend *fe)
1627*4882a593Smuzhiyun {
1628*4882a593Smuzhiyun 	u8 optimal_pll_ratio = 20;
1629*4882a593Smuzhiyun 	u32 freq_adc, ratio, rest, max = 0;
1630*4882a593Smuzhiyun 	u8 pll_ratio;
1631*4882a593Smuzhiyun 
1632*4882a593Smuzhiyun 	for (pll_ratio = 17; pll_ratio <= 20; pll_ratio++) {
1633*4882a593Smuzhiyun 		freq_adc = 12 * pll_ratio * (1 << 8) / 16;
1634*4882a593Smuzhiyun 		ratio = ((fe->dtv_property_cache.frequency / 1000) * (1 << 8) / 1000) / freq_adc;
1635*4882a593Smuzhiyun 		rest = ((fe->dtv_property_cache.frequency / 1000) * (1 << 8) / 1000) - ratio * freq_adc;
1636*4882a593Smuzhiyun 
1637*4882a593Smuzhiyun 		if (rest > freq_adc / 2)
1638*4882a593Smuzhiyun 			rest = freq_adc - rest;
1639*4882a593Smuzhiyun 		deb_info("PLL ratio=%i rest=%i\n", pll_ratio, rest);
1640*4882a593Smuzhiyun 		if ((rest > max) && (rest > 717)) {
1641*4882a593Smuzhiyun 			optimal_pll_ratio = pll_ratio;
1642*4882a593Smuzhiyun 			max = rest;
1643*4882a593Smuzhiyun 		}
1644*4882a593Smuzhiyun 	}
1645*4882a593Smuzhiyun 	deb_info("optimal PLL ratio=%i\n", optimal_pll_ratio);
1646*4882a593Smuzhiyun 
1647*4882a593Smuzhiyun 	return optimal_pll_ratio;
1648*4882a593Smuzhiyun }
1649*4882a593Smuzhiyun 
dib8096_set_param_override(struct dvb_frontend * fe)1650*4882a593Smuzhiyun static int dib8096_set_param_override(struct dvb_frontend *fe)
1651*4882a593Smuzhiyun {
1652*4882a593Smuzhiyun 	struct dvb_usb_adapter *adap = fe->dvb->priv;
1653*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
1654*4882a593Smuzhiyun 	u8 pll_ratio, band = BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000);
1655*4882a593Smuzhiyun 	u16 target, ltgain, rf_gain_limit;
1656*4882a593Smuzhiyun 	u32 timf;
1657*4882a593Smuzhiyun 	int ret = 0;
1658*4882a593Smuzhiyun 	enum frontend_tune_state tune_state = CT_SHUTDOWN;
1659*4882a593Smuzhiyun 
1660*4882a593Smuzhiyun 	switch (band) {
1661*4882a593Smuzhiyun 	default:
1662*4882a593Smuzhiyun 		deb_info("Warning : Rf frequency  (%iHz) is not in the supported range, using VHF switch ", fe->dtv_property_cache.frequency);
1663*4882a593Smuzhiyun 		fallthrough;
1664*4882a593Smuzhiyun 	case BAND_VHF:
1665*4882a593Smuzhiyun 		state->dib8000_ops.set_gpio(fe, 3, 0, 1);
1666*4882a593Smuzhiyun 		break;
1667*4882a593Smuzhiyun 	case BAND_UHF:
1668*4882a593Smuzhiyun 		state->dib8000_ops.set_gpio(fe, 3, 0, 0);
1669*4882a593Smuzhiyun 		break;
1670*4882a593Smuzhiyun 	}
1671*4882a593Smuzhiyun 
1672*4882a593Smuzhiyun 	ret = state->set_param_save(fe);
1673*4882a593Smuzhiyun 	if (ret < 0)
1674*4882a593Smuzhiyun 		return ret;
1675*4882a593Smuzhiyun 
1676*4882a593Smuzhiyun 	if (fe->dtv_property_cache.bandwidth_hz != 6000000) {
1677*4882a593Smuzhiyun 		deb_info("only 6MHz bandwidth is supported\n");
1678*4882a593Smuzhiyun 		return -EINVAL;
1679*4882a593Smuzhiyun 	}
1680*4882a593Smuzhiyun 
1681*4882a593Smuzhiyun 	/* Update PLL if needed ratio */
1682*4882a593Smuzhiyun 	state->dib8000_ops.update_pll(fe, &dib8090_pll_config_12mhz, fe->dtv_property_cache.bandwidth_hz / 1000, 0);
1683*4882a593Smuzhiyun 
1684*4882a593Smuzhiyun 	/* Get optimize PLL ratio to remove spurious */
1685*4882a593Smuzhiyun 	pll_ratio = dib8090_compute_pll_parameters(fe);
1686*4882a593Smuzhiyun 	if (pll_ratio == 17)
1687*4882a593Smuzhiyun 		timf = 21387946;
1688*4882a593Smuzhiyun 	else if (pll_ratio == 18)
1689*4882a593Smuzhiyun 		timf = 20199727;
1690*4882a593Smuzhiyun 	else if (pll_ratio == 19)
1691*4882a593Smuzhiyun 		timf = 19136583;
1692*4882a593Smuzhiyun 	else
1693*4882a593Smuzhiyun 		timf = 18179756;
1694*4882a593Smuzhiyun 
1695*4882a593Smuzhiyun 	/* Update ratio */
1696*4882a593Smuzhiyun 	state->dib8000_ops.update_pll(fe, &dib8090_pll_config_12mhz, fe->dtv_property_cache.bandwidth_hz / 1000, pll_ratio);
1697*4882a593Smuzhiyun 
1698*4882a593Smuzhiyun 	state->dib8000_ops.ctrl_timf(fe, DEMOD_TIMF_SET, timf);
1699*4882a593Smuzhiyun 
1700*4882a593Smuzhiyun 	if (band != BAND_CBAND) {
1701*4882a593Smuzhiyun 		/* dib0090_get_wbd_target is returning any possible temperature compensated wbd-target */
1702*4882a593Smuzhiyun 		target = (dib0090_get_wbd_target(fe) * 8 * 18 / 33 + 1) / 2;
1703*4882a593Smuzhiyun 		state->dib8000_ops.set_wbd_ref(fe, target);
1704*4882a593Smuzhiyun 	}
1705*4882a593Smuzhiyun 
1706*4882a593Smuzhiyun 	if (band == BAND_CBAND) {
1707*4882a593Smuzhiyun 		deb_info("tuning in CBAND - soft-AGC startup\n");
1708*4882a593Smuzhiyun 		dib0090_set_tune_state(fe, CT_AGC_START);
1709*4882a593Smuzhiyun 
1710*4882a593Smuzhiyun 		do {
1711*4882a593Smuzhiyun 			ret = dib0090_gain_control(fe);
1712*4882a593Smuzhiyun 			msleep(ret);
1713*4882a593Smuzhiyun 			tune_state = dib0090_get_tune_state(fe);
1714*4882a593Smuzhiyun 			if (tune_state == CT_AGC_STEP_0)
1715*4882a593Smuzhiyun 				state->dib8000_ops.set_gpio(fe, 6, 0, 1);
1716*4882a593Smuzhiyun 			else if (tune_state == CT_AGC_STEP_1) {
1717*4882a593Smuzhiyun 				dib0090_get_current_gain(fe, NULL, NULL, &rf_gain_limit, &ltgain);
1718*4882a593Smuzhiyun 				if (rf_gain_limit < 2000) /* activate the external attenuator in case of very high input power */
1719*4882a593Smuzhiyun 					state->dib8000_ops.set_gpio(fe, 6, 0, 0);
1720*4882a593Smuzhiyun 			}
1721*4882a593Smuzhiyun 		} while (tune_state < CT_AGC_STOP);
1722*4882a593Smuzhiyun 
1723*4882a593Smuzhiyun 		deb_info("switching to PWM AGC\n");
1724*4882a593Smuzhiyun 		dib0090_pwm_gain_reset(fe);
1725*4882a593Smuzhiyun 		state->dib8000_ops.pwm_agc_reset(fe);
1726*4882a593Smuzhiyun 		state->dib8000_ops.set_tune_state(fe, CT_DEMOD_START);
1727*4882a593Smuzhiyun 	} else {
1728*4882a593Smuzhiyun 		/* for everything else than CBAND we are using standard AGC */
1729*4882a593Smuzhiyun 		deb_info("not tuning in CBAND - standard AGC startup\n");
1730*4882a593Smuzhiyun 		dib0090_pwm_gain_reset(fe);
1731*4882a593Smuzhiyun 	}
1732*4882a593Smuzhiyun 
1733*4882a593Smuzhiyun 	return 0;
1734*4882a593Smuzhiyun }
1735*4882a593Smuzhiyun 
dib809x_tuner_attach(struct dvb_usb_adapter * adap)1736*4882a593Smuzhiyun static int dib809x_tuner_attach(struct dvb_usb_adapter *adap)
1737*4882a593Smuzhiyun {
1738*4882a593Smuzhiyun 	struct dib0700_adapter_state *st = adap->priv;
1739*4882a593Smuzhiyun 	struct i2c_adapter *tun_i2c = st->dib8000_ops.get_i2c_master(adap->fe_adap[0].fe, DIBX000_I2C_INTERFACE_TUNER, 1);
1740*4882a593Smuzhiyun 
1741*4882a593Smuzhiyun 	/* FIXME: if adap->id != 0, check if it is fe_adap[1] */
1742*4882a593Smuzhiyun 	if (!dvb_attach(dib0090_register, adap->fe_adap[0].fe, tun_i2c, &dib809x_dib0090_config))
1743*4882a593Smuzhiyun 		return -ENODEV;
1744*4882a593Smuzhiyun 
1745*4882a593Smuzhiyun 	st->set_param_save = adap->fe_adap[0].fe->ops.tuner_ops.set_params;
1746*4882a593Smuzhiyun 	adap->fe_adap[0].fe->ops.tuner_ops.set_params = dib8096_set_param_override;
1747*4882a593Smuzhiyun 	return 0;
1748*4882a593Smuzhiyun }
1749*4882a593Smuzhiyun 
stk809x_frontend_attach(struct dvb_usb_adapter * adap)1750*4882a593Smuzhiyun static int stk809x_frontend_attach(struct dvb_usb_adapter *adap)
1751*4882a593Smuzhiyun {
1752*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
1753*4882a593Smuzhiyun 
1754*4882a593Smuzhiyun 	if (!dvb_attach(dib8000_attach, &state->dib8000_ops))
1755*4882a593Smuzhiyun 		return -ENODEV;
1756*4882a593Smuzhiyun 
1757*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
1758*4882a593Smuzhiyun 	msleep(10);
1759*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
1760*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
1761*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
1762*4882a593Smuzhiyun 
1763*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
1764*4882a593Smuzhiyun 
1765*4882a593Smuzhiyun 	dib0700_ctrl_clock(adap->dev, 72, 1);
1766*4882a593Smuzhiyun 
1767*4882a593Smuzhiyun 	msleep(10);
1768*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
1769*4882a593Smuzhiyun 	msleep(10);
1770*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
1771*4882a593Smuzhiyun 
1772*4882a593Smuzhiyun 	state->dib8000_ops.i2c_enumeration(&adap->dev->i2c_adap, 1, 18, 0x80, 0);
1773*4882a593Smuzhiyun 
1774*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib8000_ops.init(&adap->dev->i2c_adap, 0x80, &dib809x_dib8000_config[0]);
1775*4882a593Smuzhiyun 
1776*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ?  -ENODEV : 0;
1777*4882a593Smuzhiyun }
1778*4882a593Smuzhiyun 
stk809x_frontend1_attach(struct dvb_usb_adapter * adap)1779*4882a593Smuzhiyun static int stk809x_frontend1_attach(struct dvb_usb_adapter *adap)
1780*4882a593Smuzhiyun {
1781*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
1782*4882a593Smuzhiyun 
1783*4882a593Smuzhiyun 	if (!dvb_attach(dib8000_attach, &state->dib8000_ops))
1784*4882a593Smuzhiyun 		return -ENODEV;
1785*4882a593Smuzhiyun 
1786*4882a593Smuzhiyun 	state->dib8000_ops.i2c_enumeration(&adap->dev->i2c_adap, 1, 0x10, 0x82, 0);
1787*4882a593Smuzhiyun 
1788*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib8000_ops.init(&adap->dev->i2c_adap, 0x82, &dib809x_dib8000_config[1]);
1789*4882a593Smuzhiyun 
1790*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ?  -ENODEV : 0;
1791*4882a593Smuzhiyun }
1792*4882a593Smuzhiyun 
nim8096md_tuner_attach(struct dvb_usb_adapter * adap)1793*4882a593Smuzhiyun static int nim8096md_tuner_attach(struct dvb_usb_adapter *adap)
1794*4882a593Smuzhiyun {
1795*4882a593Smuzhiyun 	struct dib0700_adapter_state *st = adap->priv;
1796*4882a593Smuzhiyun 	struct i2c_adapter *tun_i2c;
1797*4882a593Smuzhiyun 	struct dvb_frontend *fe_slave  = st->dib8000_ops.get_slave_frontend(adap->fe_adap[0].fe, 1);
1798*4882a593Smuzhiyun 
1799*4882a593Smuzhiyun 	if (fe_slave) {
1800*4882a593Smuzhiyun 		tun_i2c = st->dib8000_ops.get_i2c_master(fe_slave, DIBX000_I2C_INTERFACE_TUNER, 1);
1801*4882a593Smuzhiyun 		if (dvb_attach(dib0090_register, fe_slave, tun_i2c, &dib809x_dib0090_config) == NULL)
1802*4882a593Smuzhiyun 			return -ENODEV;
1803*4882a593Smuzhiyun 		fe_slave->dvb = adap->fe_adap[0].fe->dvb;
1804*4882a593Smuzhiyun 		fe_slave->ops.tuner_ops.set_params = dib8096_set_param_override;
1805*4882a593Smuzhiyun 	}
1806*4882a593Smuzhiyun 	tun_i2c = st->dib8000_ops.get_i2c_master(adap->fe_adap[0].fe, DIBX000_I2C_INTERFACE_TUNER, 1);
1807*4882a593Smuzhiyun 	if (dvb_attach(dib0090_register, adap->fe_adap[0].fe, tun_i2c, &dib809x_dib0090_config) == NULL)
1808*4882a593Smuzhiyun 		return -ENODEV;
1809*4882a593Smuzhiyun 
1810*4882a593Smuzhiyun 	st->set_param_save = adap->fe_adap[0].fe->ops.tuner_ops.set_params;
1811*4882a593Smuzhiyun 	adap->fe_adap[0].fe->ops.tuner_ops.set_params = dib8096_set_param_override;
1812*4882a593Smuzhiyun 
1813*4882a593Smuzhiyun 	return 0;
1814*4882a593Smuzhiyun }
1815*4882a593Smuzhiyun 
nim8096md_frontend_attach(struct dvb_usb_adapter * adap)1816*4882a593Smuzhiyun static int nim8096md_frontend_attach(struct dvb_usb_adapter *adap)
1817*4882a593Smuzhiyun {
1818*4882a593Smuzhiyun 	struct dvb_frontend *fe_slave;
1819*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
1820*4882a593Smuzhiyun 
1821*4882a593Smuzhiyun 	if (!dvb_attach(dib8000_attach, &state->dib8000_ops))
1822*4882a593Smuzhiyun 		return -ENODEV;
1823*4882a593Smuzhiyun 
1824*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 0);
1825*4882a593Smuzhiyun 	msleep(20);
1826*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
1827*4882a593Smuzhiyun 	msleep(1000);
1828*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
1829*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
1830*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
1831*4882a593Smuzhiyun 
1832*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
1833*4882a593Smuzhiyun 
1834*4882a593Smuzhiyun 	dib0700_ctrl_clock(adap->dev, 72, 1);
1835*4882a593Smuzhiyun 
1836*4882a593Smuzhiyun 	msleep(20);
1837*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
1838*4882a593Smuzhiyun 	msleep(20);
1839*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
1840*4882a593Smuzhiyun 
1841*4882a593Smuzhiyun 	state->dib8000_ops.i2c_enumeration(&adap->dev->i2c_adap, 2, 18, 0x80, 0);
1842*4882a593Smuzhiyun 
1843*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib8000_ops.init(&adap->dev->i2c_adap, 0x80, &dib809x_dib8000_config[0]);
1844*4882a593Smuzhiyun 	if (adap->fe_adap[0].fe == NULL)
1845*4882a593Smuzhiyun 		return -ENODEV;
1846*4882a593Smuzhiyun 
1847*4882a593Smuzhiyun 	/* Needed to increment refcount */
1848*4882a593Smuzhiyun 	if (!dvb_attach(dib8000_attach, &state->dib8000_ops))
1849*4882a593Smuzhiyun 		return -ENODEV;
1850*4882a593Smuzhiyun 
1851*4882a593Smuzhiyun 	fe_slave = state->dib8000_ops.init(&adap->dev->i2c_adap, 0x82, &dib809x_dib8000_config[1]);
1852*4882a593Smuzhiyun 	state->dib8000_ops.set_slave_frontend(adap->fe_adap[0].fe, fe_slave);
1853*4882a593Smuzhiyun 
1854*4882a593Smuzhiyun 	return fe_slave == NULL ?  -ENODEV : 0;
1855*4882a593Smuzhiyun }
1856*4882a593Smuzhiyun 
1857*4882a593Smuzhiyun /* TFE8096P */
1858*4882a593Smuzhiyun static struct dibx000_agc_config dib8096p_agc_config[2] = {
1859*4882a593Smuzhiyun 	{
1860*4882a593Smuzhiyun 		.band_caps		= BAND_UHF,
1861*4882a593Smuzhiyun 		/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0,
1862*4882a593Smuzhiyun 		   P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0,
1863*4882a593Smuzhiyun 		   P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
1864*4882a593Smuzhiyun 		   P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5,
1865*4882a593Smuzhiyun 		   P_agc_write=0 */
1866*4882a593Smuzhiyun 		.setup			= (0 << 15) | (0 << 14) | (5 << 11)
1867*4882a593Smuzhiyun 			| (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5)
1868*4882a593Smuzhiyun 			| (0 << 4) | (5 << 1) | (0 << 0),
1869*4882a593Smuzhiyun 
1870*4882a593Smuzhiyun 		.inv_gain		= 684,
1871*4882a593Smuzhiyun 		.time_stabiliz	= 10,
1872*4882a593Smuzhiyun 
1873*4882a593Smuzhiyun 		.alpha_level	= 0,
1874*4882a593Smuzhiyun 		.thlock			= 118,
1875*4882a593Smuzhiyun 
1876*4882a593Smuzhiyun 		.wbd_inv		= 0,
1877*4882a593Smuzhiyun 		.wbd_ref		= 1200,
1878*4882a593Smuzhiyun 		.wbd_sel		= 3,
1879*4882a593Smuzhiyun 		.wbd_alpha		= 5,
1880*4882a593Smuzhiyun 
1881*4882a593Smuzhiyun 		.agc1_max		= 65535,
1882*4882a593Smuzhiyun 		.agc1_min		= 0,
1883*4882a593Smuzhiyun 
1884*4882a593Smuzhiyun 		.agc2_max		= 32767,
1885*4882a593Smuzhiyun 		.agc2_min		= 0,
1886*4882a593Smuzhiyun 
1887*4882a593Smuzhiyun 		.agc1_pt1		= 0,
1888*4882a593Smuzhiyun 		.agc1_pt2		= 0,
1889*4882a593Smuzhiyun 		.agc1_pt3		= 105,
1890*4882a593Smuzhiyun 		.agc1_slope1	= 0,
1891*4882a593Smuzhiyun 		.agc1_slope2	= 156,
1892*4882a593Smuzhiyun 		.agc2_pt1		= 105,
1893*4882a593Smuzhiyun 		.agc2_pt2		= 255,
1894*4882a593Smuzhiyun 		.agc2_slope1	= 54,
1895*4882a593Smuzhiyun 		.agc2_slope2	= 0,
1896*4882a593Smuzhiyun 
1897*4882a593Smuzhiyun 		.alpha_mant		= 28,
1898*4882a593Smuzhiyun 		.alpha_exp		= 26,
1899*4882a593Smuzhiyun 		.beta_mant		= 31,
1900*4882a593Smuzhiyun 		.beta_exp		= 51,
1901*4882a593Smuzhiyun 
1902*4882a593Smuzhiyun 		.perform_agc_softsplit = 0,
1903*4882a593Smuzhiyun 	} , {
1904*4882a593Smuzhiyun 		.band_caps		= BAND_FM | BAND_VHF | BAND_CBAND,
1905*4882a593Smuzhiyun 		/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0,
1906*4882a593Smuzhiyun 		   P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0,
1907*4882a593Smuzhiyun 		   P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
1908*4882a593Smuzhiyun 		   P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5,
1909*4882a593Smuzhiyun 		   P_agc_write=0 */
1910*4882a593Smuzhiyun 		.setup			= (0 << 15) | (0 << 14) | (5 << 11)
1911*4882a593Smuzhiyun 			| (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5)
1912*4882a593Smuzhiyun 			| (0 << 4) | (5 << 1) | (0 << 0),
1913*4882a593Smuzhiyun 
1914*4882a593Smuzhiyun 		.inv_gain		= 732,
1915*4882a593Smuzhiyun 		.time_stabiliz  = 10,
1916*4882a593Smuzhiyun 
1917*4882a593Smuzhiyun 		.alpha_level	= 0,
1918*4882a593Smuzhiyun 		.thlock			= 118,
1919*4882a593Smuzhiyun 
1920*4882a593Smuzhiyun 		.wbd_inv		= 0,
1921*4882a593Smuzhiyun 		.wbd_ref		= 1200,
1922*4882a593Smuzhiyun 		.wbd_sel		= 3,
1923*4882a593Smuzhiyun 		.wbd_alpha		= 5,
1924*4882a593Smuzhiyun 
1925*4882a593Smuzhiyun 		.agc1_max		= 65535,
1926*4882a593Smuzhiyun 		.agc1_min		= 0,
1927*4882a593Smuzhiyun 
1928*4882a593Smuzhiyun 		.agc2_max		= 32767,
1929*4882a593Smuzhiyun 		.agc2_min		= 0,
1930*4882a593Smuzhiyun 
1931*4882a593Smuzhiyun 		.agc1_pt1		= 0,
1932*4882a593Smuzhiyun 		.agc1_pt2		= 0,
1933*4882a593Smuzhiyun 		.agc1_pt3		= 98,
1934*4882a593Smuzhiyun 		.agc1_slope1	= 0,
1935*4882a593Smuzhiyun 		.agc1_slope2	= 167,
1936*4882a593Smuzhiyun 		.agc2_pt1		= 98,
1937*4882a593Smuzhiyun 		.agc2_pt2		= 255,
1938*4882a593Smuzhiyun 		.agc2_slope1	= 52,
1939*4882a593Smuzhiyun 		.agc2_slope2	= 0,
1940*4882a593Smuzhiyun 
1941*4882a593Smuzhiyun 		.alpha_mant		= 28,
1942*4882a593Smuzhiyun 		.alpha_exp		= 26,
1943*4882a593Smuzhiyun 		.beta_mant		= 31,
1944*4882a593Smuzhiyun 		.beta_exp		= 51,
1945*4882a593Smuzhiyun 
1946*4882a593Smuzhiyun 		.perform_agc_softsplit = 0,
1947*4882a593Smuzhiyun 	}
1948*4882a593Smuzhiyun };
1949*4882a593Smuzhiyun 
1950*4882a593Smuzhiyun static struct dibx000_bandwidth_config dib8096p_clock_config_12_mhz = {
1951*4882a593Smuzhiyun 	.internal = 108000,
1952*4882a593Smuzhiyun 	.sampling = 13500,
1953*4882a593Smuzhiyun 	.pll_prediv = 1,
1954*4882a593Smuzhiyun 	.pll_ratio = 9,
1955*4882a593Smuzhiyun 	.pll_range = 1,
1956*4882a593Smuzhiyun 	.pll_reset = 0,
1957*4882a593Smuzhiyun 	.pll_bypass = 0,
1958*4882a593Smuzhiyun 	.enable_refdiv = 0,
1959*4882a593Smuzhiyun 	.bypclk_div = 0,
1960*4882a593Smuzhiyun 	.IO_CLK_en_core = 0,
1961*4882a593Smuzhiyun 	.ADClkSrc = 0,
1962*4882a593Smuzhiyun 	.modulo = 2,
1963*4882a593Smuzhiyun 	.sad_cfg = (3 << 14) | (1 << 12) | (524 << 0),
1964*4882a593Smuzhiyun 	.ifreq = (0 << 25) | 0,
1965*4882a593Smuzhiyun 	.timf = 20199729,
1966*4882a593Smuzhiyun 	.xtal_hz = 12000000,
1967*4882a593Smuzhiyun };
1968*4882a593Smuzhiyun 
1969*4882a593Smuzhiyun static struct dib8000_config tfe8096p_dib8000_config = {
1970*4882a593Smuzhiyun 	.output_mpeg2_in_188_bytes	= 1,
1971*4882a593Smuzhiyun 	.hostbus_diversity			= 1,
1972*4882a593Smuzhiyun 	.update_lna					= NULL,
1973*4882a593Smuzhiyun 
1974*4882a593Smuzhiyun 	.agc_config_count			= 2,
1975*4882a593Smuzhiyun 	.agc						= dib8096p_agc_config,
1976*4882a593Smuzhiyun 	.pll						= &dib8096p_clock_config_12_mhz,
1977*4882a593Smuzhiyun 
1978*4882a593Smuzhiyun 	.gpio_dir					= DIB8000_GPIO_DEFAULT_DIRECTIONS,
1979*4882a593Smuzhiyun 	.gpio_val					= DIB8000_GPIO_DEFAULT_VALUES,
1980*4882a593Smuzhiyun 	.gpio_pwm_pos				= DIB8000_GPIO_DEFAULT_PWM_POS,
1981*4882a593Smuzhiyun 
1982*4882a593Smuzhiyun 	.agc_control				= NULL,
1983*4882a593Smuzhiyun 	.diversity_delay			= 48,
1984*4882a593Smuzhiyun 	.output_mode				= OUTMODE_MPEG2_FIFO,
1985*4882a593Smuzhiyun 	.enMpegOutput				= 1,
1986*4882a593Smuzhiyun };
1987*4882a593Smuzhiyun 
1988*4882a593Smuzhiyun static struct dib0090_wbd_slope dib8096p_wbd_table[] = {
1989*4882a593Smuzhiyun 	{ 380, 81, 850, 64, 540, 4},
1990*4882a593Smuzhiyun 	{ 860, 51, 866, 21, 375, 4},
1991*4882a593Smuzhiyun 	{1700, 0, 250, 0, 100, 6},
1992*4882a593Smuzhiyun 	{2600, 0, 250, 0, 100, 6},
1993*4882a593Smuzhiyun 	{ 0xFFFF, 0, 0, 0, 0, 0},
1994*4882a593Smuzhiyun };
1995*4882a593Smuzhiyun 
1996*4882a593Smuzhiyun static struct dib0090_config tfe8096p_dib0090_config = {
1997*4882a593Smuzhiyun 	.io.clock_khz			= 12000,
1998*4882a593Smuzhiyun 	.io.pll_bypass			= 0,
1999*4882a593Smuzhiyun 	.io.pll_range			= 0,
2000*4882a593Smuzhiyun 	.io.pll_prediv			= 3,
2001*4882a593Smuzhiyun 	.io.pll_loopdiv			= 6,
2002*4882a593Smuzhiyun 	.io.adc_clock_ratio		= 0,
2003*4882a593Smuzhiyun 	.io.pll_int_loop_filt	= 0,
2004*4882a593Smuzhiyun 
2005*4882a593Smuzhiyun 	.freq_offset_khz_uhf	= -143,
2006*4882a593Smuzhiyun 	.freq_offset_khz_vhf	= -143,
2007*4882a593Smuzhiyun 
2008*4882a593Smuzhiyun 	.get_adc_power			= dib8090_get_adc_power,
2009*4882a593Smuzhiyun 
2010*4882a593Smuzhiyun 	.clkouttobamse			= 1,
2011*4882a593Smuzhiyun 	.analog_output			= 0,
2012*4882a593Smuzhiyun 
2013*4882a593Smuzhiyun 	.wbd_vhf_offset			= 0,
2014*4882a593Smuzhiyun 	.wbd_cband_offset		= 0,
2015*4882a593Smuzhiyun 	.use_pwm_agc			= 1,
2016*4882a593Smuzhiyun 	.clkoutdrive			= 0,
2017*4882a593Smuzhiyun 
2018*4882a593Smuzhiyun 	.fref_clock_ratio		= 1,
2019*4882a593Smuzhiyun 
2020*4882a593Smuzhiyun 	.ls_cfg_pad_drv			= 0,
2021*4882a593Smuzhiyun 	.data_tx_drv			= 0,
2022*4882a593Smuzhiyun 	.low_if					= NULL,
2023*4882a593Smuzhiyun 	.in_soc					= 1,
2024*4882a593Smuzhiyun 	.force_cband_input		= 0,
2025*4882a593Smuzhiyun };
2026*4882a593Smuzhiyun 
2027*4882a593Smuzhiyun struct dibx090p_adc {
2028*4882a593Smuzhiyun 	u32 freq;			/* RF freq MHz */
2029*4882a593Smuzhiyun 	u32 timf;			/* New Timf */
2030*4882a593Smuzhiyun 	u32 pll_loopdiv;	/* New prediv */
2031*4882a593Smuzhiyun 	u32 pll_prediv;		/* New loopdiv */
2032*4882a593Smuzhiyun };
2033*4882a593Smuzhiyun 
2034*4882a593Smuzhiyun struct dibx090p_best_adc {
2035*4882a593Smuzhiyun 	u32 timf;
2036*4882a593Smuzhiyun 	u32 pll_loopdiv;
2037*4882a593Smuzhiyun 	u32 pll_prediv;
2038*4882a593Smuzhiyun };
2039*4882a593Smuzhiyun 
dib8096p_get_best_sampling(struct dvb_frontend * fe,struct dibx090p_best_adc * adc)2040*4882a593Smuzhiyun static int dib8096p_get_best_sampling(struct dvb_frontend *fe, struct dibx090p_best_adc *adc)
2041*4882a593Smuzhiyun {
2042*4882a593Smuzhiyun 	u8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1;
2043*4882a593Smuzhiyun 	u16 xtal = 12000;
2044*4882a593Smuzhiyun 	u16 fcp_min = 1900;  /* PLL, Minimum Frequency of phase comparator (KHz) */
2045*4882a593Smuzhiyun 	u16 fcp_max = 20000; /* PLL, Maximum Frequency of phase comparator (KHz) */
2046*4882a593Smuzhiyun 	u32 fmem_max = 140000; /* 140MHz max SDRAM freq */
2047*4882a593Smuzhiyun 	u32 fdem_min = 66000;
2048*4882a593Smuzhiyun 	u32 fcp = 0, fs = 0, fdem = 0, fmem = 0;
2049*4882a593Smuzhiyun 	u32 harmonic_id = 0;
2050*4882a593Smuzhiyun 
2051*4882a593Smuzhiyun 	adc->timf = 0;
2052*4882a593Smuzhiyun 	adc->pll_loopdiv = loopdiv;
2053*4882a593Smuzhiyun 	adc->pll_prediv = prediv;
2054*4882a593Smuzhiyun 
2055*4882a593Smuzhiyun 	deb_info("bandwidth = %d", fe->dtv_property_cache.bandwidth_hz);
2056*4882a593Smuzhiyun 
2057*4882a593Smuzhiyun 	/* Find Min and Max prediv */
2058*4882a593Smuzhiyun 	while ((xtal / max_prediv) >= fcp_min)
2059*4882a593Smuzhiyun 		max_prediv++;
2060*4882a593Smuzhiyun 
2061*4882a593Smuzhiyun 	max_prediv--;
2062*4882a593Smuzhiyun 	min_prediv = max_prediv;
2063*4882a593Smuzhiyun 	while ((xtal / min_prediv) <= fcp_max) {
2064*4882a593Smuzhiyun 		min_prediv--;
2065*4882a593Smuzhiyun 		if (min_prediv == 1)
2066*4882a593Smuzhiyun 			break;
2067*4882a593Smuzhiyun 	}
2068*4882a593Smuzhiyun 	deb_info("MIN prediv = %d : MAX prediv = %d", min_prediv, max_prediv);
2069*4882a593Smuzhiyun 
2070*4882a593Smuzhiyun 	min_prediv = 1;
2071*4882a593Smuzhiyun 
2072*4882a593Smuzhiyun 	for (prediv = min_prediv; prediv < max_prediv; prediv++) {
2073*4882a593Smuzhiyun 		fcp = xtal / prediv;
2074*4882a593Smuzhiyun 		if (fcp > fcp_min && fcp < fcp_max) {
2075*4882a593Smuzhiyun 			for (loopdiv = 1; loopdiv < 64; loopdiv++) {
2076*4882a593Smuzhiyun 				fmem = ((xtal/prediv) * loopdiv);
2077*4882a593Smuzhiyun 				fdem = fmem / 2;
2078*4882a593Smuzhiyun 				fs   = fdem / 4;
2079*4882a593Smuzhiyun 
2080*4882a593Smuzhiyun 				/* test min/max system restrictions */
2081*4882a593Smuzhiyun 				if ((fdem >= fdem_min) && (fmem <= fmem_max) && (fs >= fe->dtv_property_cache.bandwidth_hz / 1000)) {
2082*4882a593Smuzhiyun 					spur = 0;
2083*4882a593Smuzhiyun 					/* test fs harmonics positions */
2084*4882a593Smuzhiyun 					for (harmonic_id = (fe->dtv_property_cache.frequency / (1000 * fs));  harmonic_id <= ((fe->dtv_property_cache.frequency / (1000 * fs)) + 1); harmonic_id++) {
2085*4882a593Smuzhiyun 						if (((fs * harmonic_id) >= (fe->dtv_property_cache.frequency / 1000 - (fe->dtv_property_cache.bandwidth_hz / 2000))) &&  ((fs * harmonic_id) <= (fe->dtv_property_cache.frequency / 1000 + (fe->dtv_property_cache.bandwidth_hz / 2000)))) {
2086*4882a593Smuzhiyun 							spur = 1;
2087*4882a593Smuzhiyun 							break;
2088*4882a593Smuzhiyun 						}
2089*4882a593Smuzhiyun 					}
2090*4882a593Smuzhiyun 
2091*4882a593Smuzhiyun 					if (!spur) {
2092*4882a593Smuzhiyun 						adc->pll_loopdiv = loopdiv;
2093*4882a593Smuzhiyun 						adc->pll_prediv = prediv;
2094*4882a593Smuzhiyun 						adc->timf = (4260880253U / fdem) * (1 << 8);
2095*4882a593Smuzhiyun 						adc->timf += ((4260880253U % fdem) << 8) / fdem;
2096*4882a593Smuzhiyun 
2097*4882a593Smuzhiyun 						deb_info("RF %6d; BW %6d; Xtal %6d; Fmem %6d; Fdem %6d; Fs %6d; Prediv %2d; Loopdiv %2d; Timf %8d;", fe->dtv_property_cache.frequency, fe->dtv_property_cache.bandwidth_hz, xtal, fmem, fdem, fs, prediv, loopdiv, adc->timf);
2098*4882a593Smuzhiyun 						break;
2099*4882a593Smuzhiyun 					}
2100*4882a593Smuzhiyun 				}
2101*4882a593Smuzhiyun 			}
2102*4882a593Smuzhiyun 		}
2103*4882a593Smuzhiyun 		if (!spur)
2104*4882a593Smuzhiyun 			break;
2105*4882a593Smuzhiyun 	}
2106*4882a593Smuzhiyun 
2107*4882a593Smuzhiyun 	if (adc->pll_loopdiv == 0 && adc->pll_prediv == 0)
2108*4882a593Smuzhiyun 		return -EINVAL;
2109*4882a593Smuzhiyun 	return 0;
2110*4882a593Smuzhiyun }
2111*4882a593Smuzhiyun 
dib8096p_agc_startup(struct dvb_frontend * fe)2112*4882a593Smuzhiyun static int dib8096p_agc_startup(struct dvb_frontend *fe)
2113*4882a593Smuzhiyun {
2114*4882a593Smuzhiyun 	struct dvb_usb_adapter *adap = fe->dvb->priv;
2115*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
2116*4882a593Smuzhiyun 	struct dibx000_bandwidth_config pll;
2117*4882a593Smuzhiyun 	struct dibx090p_best_adc adc;
2118*4882a593Smuzhiyun 	u16 target;
2119*4882a593Smuzhiyun 	int ret;
2120*4882a593Smuzhiyun 
2121*4882a593Smuzhiyun 	ret = state->set_param_save(fe);
2122*4882a593Smuzhiyun 	if (ret < 0)
2123*4882a593Smuzhiyun 		return ret;
2124*4882a593Smuzhiyun 	memset(&pll, 0, sizeof(struct dibx000_bandwidth_config));
2125*4882a593Smuzhiyun 
2126*4882a593Smuzhiyun 	dib0090_pwm_gain_reset(fe);
2127*4882a593Smuzhiyun 	/* dib0090_get_wbd_target is returning any possible
2128*4882a593Smuzhiyun 	   temperature compensated wbd-target */
2129*4882a593Smuzhiyun 	target = (dib0090_get_wbd_target(fe) * 8  + 1) / 2;
2130*4882a593Smuzhiyun 	state->dib8000_ops.set_wbd_ref(fe, target);
2131*4882a593Smuzhiyun 
2132*4882a593Smuzhiyun 	if (dib8096p_get_best_sampling(fe, &adc) == 0) {
2133*4882a593Smuzhiyun 		pll.pll_ratio  = adc.pll_loopdiv;
2134*4882a593Smuzhiyun 		pll.pll_prediv = adc.pll_prediv;
2135*4882a593Smuzhiyun 
2136*4882a593Smuzhiyun 		dib0700_set_i2c_speed(adap->dev, 200);
2137*4882a593Smuzhiyun 		state->dib8000_ops.update_pll(fe, &pll, fe->dtv_property_cache.bandwidth_hz / 1000, 0);
2138*4882a593Smuzhiyun 		state->dib8000_ops.ctrl_timf(fe, DEMOD_TIMF_SET, adc.timf);
2139*4882a593Smuzhiyun 		dib0700_set_i2c_speed(adap->dev, 1000);
2140*4882a593Smuzhiyun 	}
2141*4882a593Smuzhiyun 	return 0;
2142*4882a593Smuzhiyun }
2143*4882a593Smuzhiyun 
tfe8096p_frontend_attach(struct dvb_usb_adapter * adap)2144*4882a593Smuzhiyun static int tfe8096p_frontend_attach(struct dvb_usb_adapter *adap)
2145*4882a593Smuzhiyun {
2146*4882a593Smuzhiyun 	struct dib0700_state *st = adap->dev->priv;
2147*4882a593Smuzhiyun 	u32 fw_version;
2148*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
2149*4882a593Smuzhiyun 
2150*4882a593Smuzhiyun 	if (!dvb_attach(dib8000_attach, &state->dib8000_ops))
2151*4882a593Smuzhiyun 		return -ENODEV;
2152*4882a593Smuzhiyun 
2153*4882a593Smuzhiyun 	dib0700_get_version(adap->dev, NULL, NULL, &fw_version, NULL);
2154*4882a593Smuzhiyun 	if (fw_version >= 0x10200)
2155*4882a593Smuzhiyun 		st->fw_use_new_i2c_api = 1;
2156*4882a593Smuzhiyun 
2157*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
2158*4882a593Smuzhiyun 	msleep(20);
2159*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
2160*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
2161*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
2162*4882a593Smuzhiyun 
2163*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
2164*4882a593Smuzhiyun 
2165*4882a593Smuzhiyun 	dib0700_ctrl_clock(adap->dev, 72, 1);
2166*4882a593Smuzhiyun 
2167*4882a593Smuzhiyun 	msleep(20);
2168*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
2169*4882a593Smuzhiyun 	msleep(20);
2170*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
2171*4882a593Smuzhiyun 
2172*4882a593Smuzhiyun 	state->dib8000_ops.i2c_enumeration(&adap->dev->i2c_adap, 1, 0x10, 0x80, 1);
2173*4882a593Smuzhiyun 
2174*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib8000_ops.init(&adap->dev->i2c_adap,
2175*4882a593Smuzhiyun 					     0x80, &tfe8096p_dib8000_config);
2176*4882a593Smuzhiyun 
2177*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ?  -ENODEV : 0;
2178*4882a593Smuzhiyun }
2179*4882a593Smuzhiyun 
tfe8096p_tuner_attach(struct dvb_usb_adapter * adap)2180*4882a593Smuzhiyun static int tfe8096p_tuner_attach(struct dvb_usb_adapter *adap)
2181*4882a593Smuzhiyun {
2182*4882a593Smuzhiyun 	struct dib0700_adapter_state *st = adap->priv;
2183*4882a593Smuzhiyun 	struct i2c_adapter *tun_i2c = st->dib8000_ops.get_i2c_tuner(adap->fe_adap[0].fe);
2184*4882a593Smuzhiyun 
2185*4882a593Smuzhiyun 	tfe8096p_dib0090_config.reset = st->dib8000_ops.tuner_sleep;
2186*4882a593Smuzhiyun 	tfe8096p_dib0090_config.sleep = st->dib8000_ops.tuner_sleep;
2187*4882a593Smuzhiyun 	tfe8096p_dib0090_config.wbd = dib8096p_wbd_table;
2188*4882a593Smuzhiyun 
2189*4882a593Smuzhiyun 	if (dvb_attach(dib0090_register, adap->fe_adap[0].fe, tun_i2c,
2190*4882a593Smuzhiyun 				&tfe8096p_dib0090_config) == NULL)
2191*4882a593Smuzhiyun 		return -ENODEV;
2192*4882a593Smuzhiyun 
2193*4882a593Smuzhiyun 	st->dib8000_ops.set_gpio(adap->fe_adap[0].fe, 8, 0, 1);
2194*4882a593Smuzhiyun 
2195*4882a593Smuzhiyun 	st->set_param_save = adap->fe_adap[0].fe->ops.tuner_ops.set_params;
2196*4882a593Smuzhiyun 	adap->fe_adap[0].fe->ops.tuner_ops.set_params = dib8096p_agc_startup;
2197*4882a593Smuzhiyun 	return 0;
2198*4882a593Smuzhiyun }
2199*4882a593Smuzhiyun 
2200*4882a593Smuzhiyun /* STK9090M */
dib90x0_pid_filter(struct dvb_usb_adapter * adapter,int index,u16 pid,int onoff)2201*4882a593Smuzhiyun static int dib90x0_pid_filter(struct dvb_usb_adapter *adapter, int index, u16 pid, int onoff)
2202*4882a593Smuzhiyun {
2203*4882a593Smuzhiyun 	return dib9000_fw_pid_filter(adapter->fe_adap[0].fe, index, pid, onoff);
2204*4882a593Smuzhiyun }
2205*4882a593Smuzhiyun 
dib90x0_pid_filter_ctrl(struct dvb_usb_adapter * adapter,int onoff)2206*4882a593Smuzhiyun static int dib90x0_pid_filter_ctrl(struct dvb_usb_adapter *adapter, int onoff)
2207*4882a593Smuzhiyun {
2208*4882a593Smuzhiyun 	return dib9000_fw_pid_filter_ctrl(adapter->fe_adap[0].fe, onoff);
2209*4882a593Smuzhiyun }
2210*4882a593Smuzhiyun 
dib90x0_tuner_reset(struct dvb_frontend * fe,int onoff)2211*4882a593Smuzhiyun static int dib90x0_tuner_reset(struct dvb_frontend *fe, int onoff)
2212*4882a593Smuzhiyun {
2213*4882a593Smuzhiyun 	return dib9000_set_gpio(fe, 5, 0, !onoff);
2214*4882a593Smuzhiyun }
2215*4882a593Smuzhiyun 
dib90x0_tuner_sleep(struct dvb_frontend * fe,int onoff)2216*4882a593Smuzhiyun static int dib90x0_tuner_sleep(struct dvb_frontend *fe, int onoff)
2217*4882a593Smuzhiyun {
2218*4882a593Smuzhiyun 	return dib9000_set_gpio(fe, 0, 0, onoff);
2219*4882a593Smuzhiyun }
2220*4882a593Smuzhiyun 
dib01x0_pmu_update(struct i2c_adapter * i2c,u16 * data,u8 len)2221*4882a593Smuzhiyun static int dib01x0_pmu_update(struct i2c_adapter *i2c, u16 *data, u8 len)
2222*4882a593Smuzhiyun {
2223*4882a593Smuzhiyun 	u8 wb[4] = { 0xc >> 8, 0xc & 0xff, 0, 0 };
2224*4882a593Smuzhiyun 	u8 rb[2];
2225*4882a593Smuzhiyun 	struct i2c_msg msg[2] = {
2226*4882a593Smuzhiyun 		{.addr = 0x1e >> 1, .flags = 0, .buf = wb, .len = 2},
2227*4882a593Smuzhiyun 		{.addr = 0x1e >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2},
2228*4882a593Smuzhiyun 	};
2229*4882a593Smuzhiyun 	u8 index_data;
2230*4882a593Smuzhiyun 
2231*4882a593Smuzhiyun 	dibx000_i2c_set_speed(i2c, 250);
2232*4882a593Smuzhiyun 
2233*4882a593Smuzhiyun 	if (i2c_transfer(i2c, msg, 2) != 2)
2234*4882a593Smuzhiyun 		return -EIO;
2235*4882a593Smuzhiyun 
2236*4882a593Smuzhiyun 	switch (rb[0] << 8 | rb[1]) {
2237*4882a593Smuzhiyun 	case 0:
2238*4882a593Smuzhiyun 			deb_info("Found DiB0170 rev1: This version of DiB0170 is not supported any longer.\n");
2239*4882a593Smuzhiyun 			return -EIO;
2240*4882a593Smuzhiyun 	case 1:
2241*4882a593Smuzhiyun 			deb_info("Found DiB0170 rev2");
2242*4882a593Smuzhiyun 			break;
2243*4882a593Smuzhiyun 	case 2:
2244*4882a593Smuzhiyun 			deb_info("Found DiB0190 rev2");
2245*4882a593Smuzhiyun 			break;
2246*4882a593Smuzhiyun 	default:
2247*4882a593Smuzhiyun 			deb_info("DiB01x0 not found");
2248*4882a593Smuzhiyun 			return -EIO;
2249*4882a593Smuzhiyun 	}
2250*4882a593Smuzhiyun 
2251*4882a593Smuzhiyun 	for (index_data = 0; index_data < len; index_data += 2) {
2252*4882a593Smuzhiyun 		wb[2] = (data[index_data + 1] >> 8) & 0xff;
2253*4882a593Smuzhiyun 		wb[3] = (data[index_data + 1]) & 0xff;
2254*4882a593Smuzhiyun 
2255*4882a593Smuzhiyun 		if (data[index_data] == 0) {
2256*4882a593Smuzhiyun 			wb[0] = (data[index_data] >> 8) & 0xff;
2257*4882a593Smuzhiyun 			wb[1] = (data[index_data]) & 0xff;
2258*4882a593Smuzhiyun 			msg[0].len = 2;
2259*4882a593Smuzhiyun 			if (i2c_transfer(i2c, msg, 2) != 2)
2260*4882a593Smuzhiyun 				return -EIO;
2261*4882a593Smuzhiyun 			wb[2] |= rb[0];
2262*4882a593Smuzhiyun 			wb[3] |= rb[1] & ~(3 << 4);
2263*4882a593Smuzhiyun 		}
2264*4882a593Smuzhiyun 
2265*4882a593Smuzhiyun 		wb[0] = (data[index_data] >> 8)&0xff;
2266*4882a593Smuzhiyun 		wb[1] = (data[index_data])&0xff;
2267*4882a593Smuzhiyun 		msg[0].len = 4;
2268*4882a593Smuzhiyun 		if (i2c_transfer(i2c, &msg[0], 1) != 1)
2269*4882a593Smuzhiyun 			return -EIO;
2270*4882a593Smuzhiyun 	}
2271*4882a593Smuzhiyun 	return 0;
2272*4882a593Smuzhiyun }
2273*4882a593Smuzhiyun 
2274*4882a593Smuzhiyun static struct dib9000_config stk9090m_config = {
2275*4882a593Smuzhiyun 	.output_mpeg2_in_188_bytes = 1,
2276*4882a593Smuzhiyun 	.output_mode = OUTMODE_MPEG2_FIFO,
2277*4882a593Smuzhiyun 	.vcxo_timer = 279620,
2278*4882a593Smuzhiyun 	.timing_frequency = 20452225,
2279*4882a593Smuzhiyun 	.demod_clock_khz = 60000,
2280*4882a593Smuzhiyun 	.xtal_clock_khz = 30000,
2281*4882a593Smuzhiyun 	.if_drives = (0 << 15) | (1 << 13) | (0 << 12) | (3 << 10) | (0 << 9) | (1 << 7) | (0 << 6) | (0 << 4) | (1 << 3) | (1 << 1) | (0),
2282*4882a593Smuzhiyun 	.subband = {
2283*4882a593Smuzhiyun 		2,
2284*4882a593Smuzhiyun 		{
2285*4882a593Smuzhiyun 			{ 240, { BOARD_GPIO_COMPONENT_DEMOD, BOARD_GPIO_FUNCTION_SUBBAND_GPIO, 0x0008, 0x0000, 0x0008 } }, /* GPIO 3 to 1 for VHF */
2286*4882a593Smuzhiyun 			{ 890, { BOARD_GPIO_COMPONENT_DEMOD, BOARD_GPIO_FUNCTION_SUBBAND_GPIO, 0x0008, 0x0000, 0x0000 } }, /* GPIO 3 to 0 for UHF */
2287*4882a593Smuzhiyun 			{ 0 },
2288*4882a593Smuzhiyun 		},
2289*4882a593Smuzhiyun 	},
2290*4882a593Smuzhiyun 	.gpio_function = {
2291*4882a593Smuzhiyun 		{ .component = BOARD_GPIO_COMPONENT_DEMOD, .function = BOARD_GPIO_FUNCTION_COMPONENT_ON, .mask = 0x10 | 0x21, .direction = 0 & ~0x21, .value = (0x10 & ~0x1) | 0x20 },
2292*4882a593Smuzhiyun 		{ .component = BOARD_GPIO_COMPONENT_DEMOD, .function = BOARD_GPIO_FUNCTION_COMPONENT_OFF, .mask = 0x10 | 0x21, .direction = 0 & ~0x21, .value = 0 | 0x21 },
2293*4882a593Smuzhiyun 	},
2294*4882a593Smuzhiyun };
2295*4882a593Smuzhiyun 
2296*4882a593Smuzhiyun static struct dib9000_config nim9090md_config[2] = {
2297*4882a593Smuzhiyun 	{
2298*4882a593Smuzhiyun 		.output_mpeg2_in_188_bytes = 1,
2299*4882a593Smuzhiyun 		.output_mode = OUTMODE_MPEG2_FIFO,
2300*4882a593Smuzhiyun 		.vcxo_timer = 279620,
2301*4882a593Smuzhiyun 		.timing_frequency = 20452225,
2302*4882a593Smuzhiyun 		.demod_clock_khz = 60000,
2303*4882a593Smuzhiyun 		.xtal_clock_khz = 30000,
2304*4882a593Smuzhiyun 		.if_drives = (0 << 15) | (1 << 13) | (0 << 12) | (3 << 10) | (0 << 9) | (1 << 7) | (0 << 6) | (0 << 4) | (1 << 3) | (1 << 1) | (0),
2305*4882a593Smuzhiyun 	}, {
2306*4882a593Smuzhiyun 		.output_mpeg2_in_188_bytes = 1,
2307*4882a593Smuzhiyun 		.output_mode = OUTMODE_DIVERSITY,
2308*4882a593Smuzhiyun 		.vcxo_timer = 279620,
2309*4882a593Smuzhiyun 		.timing_frequency = 20452225,
2310*4882a593Smuzhiyun 		.demod_clock_khz = 60000,
2311*4882a593Smuzhiyun 		.xtal_clock_khz = 30000,
2312*4882a593Smuzhiyun 		.if_drives = (0 << 15) | (1 << 13) | (0 << 12) | (3 << 10) | (0 << 9) | (1 << 7) | (0 << 6) | (0 << 4) | (1 << 3) | (1 << 1) | (0),
2313*4882a593Smuzhiyun 		.subband = {
2314*4882a593Smuzhiyun 			2,
2315*4882a593Smuzhiyun 			{
2316*4882a593Smuzhiyun 				{ 240, { BOARD_GPIO_COMPONENT_DEMOD, BOARD_GPIO_FUNCTION_SUBBAND_GPIO, 0x0006, 0x0000, 0x0006 } }, /* GPIO 1 and 2 to 1 for VHF */
2317*4882a593Smuzhiyun 				{ 890, { BOARD_GPIO_COMPONENT_DEMOD, BOARD_GPIO_FUNCTION_SUBBAND_GPIO, 0x0006, 0x0000, 0x0000 } }, /* GPIO 1 and 2 to 0 for UHF */
2318*4882a593Smuzhiyun 				{ 0 },
2319*4882a593Smuzhiyun 			},
2320*4882a593Smuzhiyun 		},
2321*4882a593Smuzhiyun 		.gpio_function = {
2322*4882a593Smuzhiyun 			{ .component = BOARD_GPIO_COMPONENT_DEMOD, .function = BOARD_GPIO_FUNCTION_COMPONENT_ON, .mask = 0x10 | 0x21, .direction = 0 & ~0x21, .value = (0x10 & ~0x1) | 0x20 },
2323*4882a593Smuzhiyun 			{ .component = BOARD_GPIO_COMPONENT_DEMOD, .function = BOARD_GPIO_FUNCTION_COMPONENT_OFF, .mask = 0x10 | 0x21, .direction = 0 & ~0x21, .value = 0 | 0x21 },
2324*4882a593Smuzhiyun 		},
2325*4882a593Smuzhiyun 	}
2326*4882a593Smuzhiyun };
2327*4882a593Smuzhiyun 
2328*4882a593Smuzhiyun static struct dib0090_config dib9090_dib0090_config = {
2329*4882a593Smuzhiyun 	.io.pll_bypass = 0,
2330*4882a593Smuzhiyun 	.io.pll_range = 1,
2331*4882a593Smuzhiyun 	.io.pll_prediv = 1,
2332*4882a593Smuzhiyun 	.io.pll_loopdiv = 8,
2333*4882a593Smuzhiyun 	.io.adc_clock_ratio = 8,
2334*4882a593Smuzhiyun 	.io.pll_int_loop_filt = 0,
2335*4882a593Smuzhiyun 	.io.clock_khz = 30000,
2336*4882a593Smuzhiyun 	.reset = dib90x0_tuner_reset,
2337*4882a593Smuzhiyun 	.sleep = dib90x0_tuner_sleep,
2338*4882a593Smuzhiyun 	.clkouttobamse = 0,
2339*4882a593Smuzhiyun 	.analog_output = 0,
2340*4882a593Smuzhiyun 	.use_pwm_agc = 0,
2341*4882a593Smuzhiyun 	.clkoutdrive = 0,
2342*4882a593Smuzhiyun 	.freq_offset_khz_uhf = 0,
2343*4882a593Smuzhiyun 	.freq_offset_khz_vhf = 0,
2344*4882a593Smuzhiyun };
2345*4882a593Smuzhiyun 
2346*4882a593Smuzhiyun static struct dib0090_config nim9090md_dib0090_config[2] = {
2347*4882a593Smuzhiyun 	{
2348*4882a593Smuzhiyun 		.io.pll_bypass = 0,
2349*4882a593Smuzhiyun 		.io.pll_range = 1,
2350*4882a593Smuzhiyun 		.io.pll_prediv = 1,
2351*4882a593Smuzhiyun 		.io.pll_loopdiv = 8,
2352*4882a593Smuzhiyun 		.io.adc_clock_ratio = 8,
2353*4882a593Smuzhiyun 		.io.pll_int_loop_filt = 0,
2354*4882a593Smuzhiyun 		.io.clock_khz = 30000,
2355*4882a593Smuzhiyun 		.reset = dib90x0_tuner_reset,
2356*4882a593Smuzhiyun 		.sleep = dib90x0_tuner_sleep,
2357*4882a593Smuzhiyun 		.clkouttobamse = 1,
2358*4882a593Smuzhiyun 		.analog_output = 0,
2359*4882a593Smuzhiyun 		.use_pwm_agc = 0,
2360*4882a593Smuzhiyun 		.clkoutdrive = 0,
2361*4882a593Smuzhiyun 		.freq_offset_khz_uhf = 0,
2362*4882a593Smuzhiyun 		.freq_offset_khz_vhf = 0,
2363*4882a593Smuzhiyun 	}, {
2364*4882a593Smuzhiyun 		.io.pll_bypass = 0,
2365*4882a593Smuzhiyun 		.io.pll_range = 1,
2366*4882a593Smuzhiyun 		.io.pll_prediv = 1,
2367*4882a593Smuzhiyun 		.io.pll_loopdiv = 8,
2368*4882a593Smuzhiyun 		.io.adc_clock_ratio = 8,
2369*4882a593Smuzhiyun 		.io.pll_int_loop_filt = 0,
2370*4882a593Smuzhiyun 		.io.clock_khz = 30000,
2371*4882a593Smuzhiyun 		.reset = dib90x0_tuner_reset,
2372*4882a593Smuzhiyun 		.sleep = dib90x0_tuner_sleep,
2373*4882a593Smuzhiyun 		.clkouttobamse = 0,
2374*4882a593Smuzhiyun 		.analog_output = 0,
2375*4882a593Smuzhiyun 		.use_pwm_agc = 0,
2376*4882a593Smuzhiyun 		.clkoutdrive = 0,
2377*4882a593Smuzhiyun 		.freq_offset_khz_uhf = 0,
2378*4882a593Smuzhiyun 		.freq_offset_khz_vhf = 0,
2379*4882a593Smuzhiyun 	}
2380*4882a593Smuzhiyun };
2381*4882a593Smuzhiyun 
2382*4882a593Smuzhiyun 
stk9090m_frontend_attach(struct dvb_usb_adapter * adap)2383*4882a593Smuzhiyun static int stk9090m_frontend_attach(struct dvb_usb_adapter *adap)
2384*4882a593Smuzhiyun {
2385*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
2386*4882a593Smuzhiyun 	struct dib0700_state *st = adap->dev->priv;
2387*4882a593Smuzhiyun 	u32 fw_version;
2388*4882a593Smuzhiyun 
2389*4882a593Smuzhiyun 	/* Make use of the new i2c functions from FW 1.20 */
2390*4882a593Smuzhiyun 	dib0700_get_version(adap->dev, NULL, NULL, &fw_version, NULL);
2391*4882a593Smuzhiyun 	if (fw_version >= 0x10200)
2392*4882a593Smuzhiyun 		st->fw_use_new_i2c_api = 1;
2393*4882a593Smuzhiyun 	dib0700_set_i2c_speed(adap->dev, 340);
2394*4882a593Smuzhiyun 
2395*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
2396*4882a593Smuzhiyun 	msleep(20);
2397*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
2398*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
2399*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
2400*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
2401*4882a593Smuzhiyun 
2402*4882a593Smuzhiyun 	dib0700_ctrl_clock(adap->dev, 72, 1);
2403*4882a593Smuzhiyun 
2404*4882a593Smuzhiyun 	msleep(20);
2405*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
2406*4882a593Smuzhiyun 	msleep(20);
2407*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
2408*4882a593Smuzhiyun 
2409*4882a593Smuzhiyun 	dib9000_i2c_enumeration(&adap->dev->i2c_adap, 1, 0x10, 0x80);
2410*4882a593Smuzhiyun 
2411*4882a593Smuzhiyun 	if (request_firmware(&state->frontend_firmware, "dib9090.fw", &adap->dev->udev->dev)) {
2412*4882a593Smuzhiyun 		deb_info("%s: Upload failed. (file not found?)\n", __func__);
2413*4882a593Smuzhiyun 		return -ENODEV;
2414*4882a593Smuzhiyun 	} else {
2415*4882a593Smuzhiyun 		deb_info("%s: firmware read %zu bytes.\n", __func__, state->frontend_firmware->size);
2416*4882a593Smuzhiyun 	}
2417*4882a593Smuzhiyun 	stk9090m_config.microcode_B_fe_size = state->frontend_firmware->size;
2418*4882a593Smuzhiyun 	stk9090m_config.microcode_B_fe_buffer = state->frontend_firmware->data;
2419*4882a593Smuzhiyun 
2420*4882a593Smuzhiyun 	adap->fe_adap[0].fe = dvb_attach(dib9000_attach, &adap->dev->i2c_adap, 0x80, &stk9090m_config);
2421*4882a593Smuzhiyun 
2422*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ?  -ENODEV : 0;
2423*4882a593Smuzhiyun }
2424*4882a593Smuzhiyun 
dib9090_tuner_attach(struct dvb_usb_adapter * adap)2425*4882a593Smuzhiyun static int dib9090_tuner_attach(struct dvb_usb_adapter *adap)
2426*4882a593Smuzhiyun {
2427*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
2428*4882a593Smuzhiyun 	struct i2c_adapter *i2c = dib9000_get_tuner_interface(adap->fe_adap[0].fe);
2429*4882a593Smuzhiyun 	u16 data_dib190[10] = {
2430*4882a593Smuzhiyun 		1, 0x1374,
2431*4882a593Smuzhiyun 		2, 0x01a2,
2432*4882a593Smuzhiyun 		7, 0x0020,
2433*4882a593Smuzhiyun 		0, 0x00ef,
2434*4882a593Smuzhiyun 		8, 0x0486,
2435*4882a593Smuzhiyun 	};
2436*4882a593Smuzhiyun 
2437*4882a593Smuzhiyun 	if (!IS_ENABLED(CONFIG_DVB_DIB9000))
2438*4882a593Smuzhiyun 		return -ENODEV;
2439*4882a593Smuzhiyun 	if (dvb_attach(dib0090_fw_register, adap->fe_adap[0].fe, i2c, &dib9090_dib0090_config) == NULL)
2440*4882a593Smuzhiyun 		return -ENODEV;
2441*4882a593Smuzhiyun 	i2c = dib9000_get_i2c_master(adap->fe_adap[0].fe, DIBX000_I2C_INTERFACE_GPIO_1_2, 0);
2442*4882a593Smuzhiyun 	if (!i2c)
2443*4882a593Smuzhiyun 		return -ENODEV;
2444*4882a593Smuzhiyun 	if (dib01x0_pmu_update(i2c, data_dib190, 10) != 0)
2445*4882a593Smuzhiyun 		return -ENODEV;
2446*4882a593Smuzhiyun 	dib0700_set_i2c_speed(adap->dev, 1500);
2447*4882a593Smuzhiyun 	if (dib9000_firmware_post_pll_init(adap->fe_adap[0].fe) < 0)
2448*4882a593Smuzhiyun 		return -ENODEV;
2449*4882a593Smuzhiyun 	release_firmware(state->frontend_firmware);
2450*4882a593Smuzhiyun 	return 0;
2451*4882a593Smuzhiyun }
2452*4882a593Smuzhiyun 
nim9090md_frontend_attach(struct dvb_usb_adapter * adap)2453*4882a593Smuzhiyun static int nim9090md_frontend_attach(struct dvb_usb_adapter *adap)
2454*4882a593Smuzhiyun {
2455*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
2456*4882a593Smuzhiyun 	struct dib0700_state *st = adap->dev->priv;
2457*4882a593Smuzhiyun 	struct i2c_adapter *i2c;
2458*4882a593Smuzhiyun 	struct dvb_frontend *fe_slave;
2459*4882a593Smuzhiyun 	u32 fw_version;
2460*4882a593Smuzhiyun 
2461*4882a593Smuzhiyun 	/* Make use of the new i2c functions from FW 1.20 */
2462*4882a593Smuzhiyun 	dib0700_get_version(adap->dev, NULL, NULL, &fw_version, NULL);
2463*4882a593Smuzhiyun 	if (fw_version >= 0x10200)
2464*4882a593Smuzhiyun 		st->fw_use_new_i2c_api = 1;
2465*4882a593Smuzhiyun 	dib0700_set_i2c_speed(adap->dev, 340);
2466*4882a593Smuzhiyun 
2467*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
2468*4882a593Smuzhiyun 	msleep(20);
2469*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
2470*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
2471*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
2472*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
2473*4882a593Smuzhiyun 
2474*4882a593Smuzhiyun 	dib0700_ctrl_clock(adap->dev, 72, 1);
2475*4882a593Smuzhiyun 
2476*4882a593Smuzhiyun 	msleep(20);
2477*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
2478*4882a593Smuzhiyun 	msleep(20);
2479*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
2480*4882a593Smuzhiyun 
2481*4882a593Smuzhiyun 	if (request_firmware(&state->frontend_firmware, "dib9090.fw", &adap->dev->udev->dev)) {
2482*4882a593Smuzhiyun 		deb_info("%s: Upload failed. (file not found?)\n", __func__);
2483*4882a593Smuzhiyun 		return -EIO;
2484*4882a593Smuzhiyun 	} else {
2485*4882a593Smuzhiyun 		deb_info("%s: firmware read %zu bytes.\n", __func__, state->frontend_firmware->size);
2486*4882a593Smuzhiyun 	}
2487*4882a593Smuzhiyun 	nim9090md_config[0].microcode_B_fe_size = state->frontend_firmware->size;
2488*4882a593Smuzhiyun 	nim9090md_config[0].microcode_B_fe_buffer = state->frontend_firmware->data;
2489*4882a593Smuzhiyun 	nim9090md_config[1].microcode_B_fe_size = state->frontend_firmware->size;
2490*4882a593Smuzhiyun 	nim9090md_config[1].microcode_B_fe_buffer = state->frontend_firmware->data;
2491*4882a593Smuzhiyun 
2492*4882a593Smuzhiyun 	dib9000_i2c_enumeration(&adap->dev->i2c_adap, 1, 0x20, 0x80);
2493*4882a593Smuzhiyun 	adap->fe_adap[0].fe = dvb_attach(dib9000_attach, &adap->dev->i2c_adap, 0x80, &nim9090md_config[0]);
2494*4882a593Smuzhiyun 
2495*4882a593Smuzhiyun 	if (adap->fe_adap[0].fe == NULL)
2496*4882a593Smuzhiyun 		return -ENODEV;
2497*4882a593Smuzhiyun 
2498*4882a593Smuzhiyun 	i2c = dib9000_get_i2c_master(adap->fe_adap[0].fe, DIBX000_I2C_INTERFACE_GPIO_3_4, 0);
2499*4882a593Smuzhiyun 	dib9000_i2c_enumeration(i2c, 1, 0x12, 0x82);
2500*4882a593Smuzhiyun 
2501*4882a593Smuzhiyun 	fe_slave = dvb_attach(dib9000_attach, i2c, 0x82, &nim9090md_config[1]);
2502*4882a593Smuzhiyun 	dib9000_set_slave_frontend(adap->fe_adap[0].fe, fe_slave);
2503*4882a593Smuzhiyun 
2504*4882a593Smuzhiyun 	return fe_slave == NULL ?  -ENODEV : 0;
2505*4882a593Smuzhiyun }
2506*4882a593Smuzhiyun 
nim9090md_tuner_attach(struct dvb_usb_adapter * adap)2507*4882a593Smuzhiyun static int nim9090md_tuner_attach(struct dvb_usb_adapter *adap)
2508*4882a593Smuzhiyun {
2509*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
2510*4882a593Smuzhiyun 	struct i2c_adapter *i2c;
2511*4882a593Smuzhiyun 	struct dvb_frontend *fe_slave;
2512*4882a593Smuzhiyun 	u16 data_dib190[10] = {
2513*4882a593Smuzhiyun 		1, 0x5374,
2514*4882a593Smuzhiyun 		2, 0x01ae,
2515*4882a593Smuzhiyun 		7, 0x0020,
2516*4882a593Smuzhiyun 		0, 0x00ef,
2517*4882a593Smuzhiyun 		8, 0x0406,
2518*4882a593Smuzhiyun 	};
2519*4882a593Smuzhiyun 	if (!IS_ENABLED(CONFIG_DVB_DIB9000))
2520*4882a593Smuzhiyun 		return -ENODEV;
2521*4882a593Smuzhiyun 	i2c = dib9000_get_tuner_interface(adap->fe_adap[0].fe);
2522*4882a593Smuzhiyun 	if (dvb_attach(dib0090_fw_register, adap->fe_adap[0].fe, i2c, &nim9090md_dib0090_config[0]) == NULL)
2523*4882a593Smuzhiyun 		return -ENODEV;
2524*4882a593Smuzhiyun 	i2c = dib9000_get_i2c_master(adap->fe_adap[0].fe, DIBX000_I2C_INTERFACE_GPIO_1_2, 0);
2525*4882a593Smuzhiyun 	if (!i2c)
2526*4882a593Smuzhiyun 		return -ENODEV;
2527*4882a593Smuzhiyun 	if (dib01x0_pmu_update(i2c, data_dib190, 10) < 0)
2528*4882a593Smuzhiyun 		return -ENODEV;
2529*4882a593Smuzhiyun 
2530*4882a593Smuzhiyun 	dib0700_set_i2c_speed(adap->dev, 1500);
2531*4882a593Smuzhiyun 	if (dib9000_firmware_post_pll_init(adap->fe_adap[0].fe) < 0)
2532*4882a593Smuzhiyun 		return -ENODEV;
2533*4882a593Smuzhiyun 
2534*4882a593Smuzhiyun 	fe_slave = dib9000_get_slave_frontend(adap->fe_adap[0].fe, 1);
2535*4882a593Smuzhiyun 	if (fe_slave != NULL) {
2536*4882a593Smuzhiyun 		i2c = dib9000_get_component_bus_interface(adap->fe_adap[0].fe);
2537*4882a593Smuzhiyun 		dib9000_set_i2c_adapter(fe_slave, i2c);
2538*4882a593Smuzhiyun 
2539*4882a593Smuzhiyun 		i2c = dib9000_get_tuner_interface(fe_slave);
2540*4882a593Smuzhiyun 		if (dvb_attach(dib0090_fw_register, fe_slave, i2c, &nim9090md_dib0090_config[1]) == NULL)
2541*4882a593Smuzhiyun 			return -ENODEV;
2542*4882a593Smuzhiyun 		fe_slave->dvb = adap->fe_adap[0].fe->dvb;
2543*4882a593Smuzhiyun 		dib9000_fw_set_component_bus_speed(adap->fe_adap[0].fe, 1500);
2544*4882a593Smuzhiyun 		if (dib9000_firmware_post_pll_init(fe_slave) < 0)
2545*4882a593Smuzhiyun 			return -ENODEV;
2546*4882a593Smuzhiyun 	}
2547*4882a593Smuzhiyun 	release_firmware(state->frontend_firmware);
2548*4882a593Smuzhiyun 
2549*4882a593Smuzhiyun 	return 0;
2550*4882a593Smuzhiyun }
2551*4882a593Smuzhiyun 
2552*4882a593Smuzhiyun /* NIM7090 */
dib7090p_get_best_sampling(struct dvb_frontend * fe,struct dibx090p_best_adc * adc)2553*4882a593Smuzhiyun static int dib7090p_get_best_sampling(struct dvb_frontend *fe , struct dibx090p_best_adc *adc)
2554*4882a593Smuzhiyun {
2555*4882a593Smuzhiyun 	u8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1;
2556*4882a593Smuzhiyun 
2557*4882a593Smuzhiyun 	u16 xtal = 12000;
2558*4882a593Smuzhiyun 	u32 fcp_min = 1900;  /* PLL Minimum Frequency comparator KHz */
2559*4882a593Smuzhiyun 	u32 fcp_max = 20000; /* PLL Maximum Frequency comparator KHz */
2560*4882a593Smuzhiyun 	u32 fdem_max = 76000;
2561*4882a593Smuzhiyun 	u32 fdem_min = 69500;
2562*4882a593Smuzhiyun 	u32 fcp = 0, fs = 0, fdem = 0;
2563*4882a593Smuzhiyun 	u32 harmonic_id = 0;
2564*4882a593Smuzhiyun 
2565*4882a593Smuzhiyun 	adc->pll_loopdiv = loopdiv;
2566*4882a593Smuzhiyun 	adc->pll_prediv = prediv;
2567*4882a593Smuzhiyun 	adc->timf = 0;
2568*4882a593Smuzhiyun 
2569*4882a593Smuzhiyun 	deb_info("bandwidth = %d fdem_min =%d", fe->dtv_property_cache.bandwidth_hz, fdem_min);
2570*4882a593Smuzhiyun 
2571*4882a593Smuzhiyun 	/* Find Min and Max prediv */
2572*4882a593Smuzhiyun 	while ((xtal/max_prediv) >= fcp_min)
2573*4882a593Smuzhiyun 		max_prediv++;
2574*4882a593Smuzhiyun 
2575*4882a593Smuzhiyun 	max_prediv--;
2576*4882a593Smuzhiyun 	min_prediv = max_prediv;
2577*4882a593Smuzhiyun 	while ((xtal/min_prediv) <= fcp_max) {
2578*4882a593Smuzhiyun 		min_prediv--;
2579*4882a593Smuzhiyun 		if (min_prediv == 1)
2580*4882a593Smuzhiyun 			break;
2581*4882a593Smuzhiyun 	}
2582*4882a593Smuzhiyun 	deb_info("MIN prediv = %d : MAX prediv = %d", min_prediv, max_prediv);
2583*4882a593Smuzhiyun 
2584*4882a593Smuzhiyun 	min_prediv = 2;
2585*4882a593Smuzhiyun 
2586*4882a593Smuzhiyun 	for (prediv = min_prediv ; prediv < max_prediv; prediv++) {
2587*4882a593Smuzhiyun 		fcp = xtal / prediv;
2588*4882a593Smuzhiyun 		if (fcp > fcp_min && fcp < fcp_max) {
2589*4882a593Smuzhiyun 			for (loopdiv = 1 ; loopdiv < 64 ; loopdiv++) {
2590*4882a593Smuzhiyun 				fdem = ((xtal/prediv) * loopdiv);
2591*4882a593Smuzhiyun 				fs   = fdem / 4;
2592*4882a593Smuzhiyun 				/* test min/max system restrictions */
2593*4882a593Smuzhiyun 
2594*4882a593Smuzhiyun 				if ((fdem >= fdem_min) && (fdem <= fdem_max) && (fs >= fe->dtv_property_cache.bandwidth_hz/1000)) {
2595*4882a593Smuzhiyun 					spur = 0;
2596*4882a593Smuzhiyun 					/* test fs harmonics positions */
2597*4882a593Smuzhiyun 					for (harmonic_id = (fe->dtv_property_cache.frequency / (1000*fs)) ;  harmonic_id <= ((fe->dtv_property_cache.frequency / (1000*fs))+1) ; harmonic_id++) {
2598*4882a593Smuzhiyun 						if (((fs*harmonic_id) >= ((fe->dtv_property_cache.frequency/1000) - (fe->dtv_property_cache.bandwidth_hz/2000))) &&  ((fs*harmonic_id) <= ((fe->dtv_property_cache.frequency/1000) + (fe->dtv_property_cache.bandwidth_hz/2000)))) {
2599*4882a593Smuzhiyun 							spur = 1;
2600*4882a593Smuzhiyun 							break;
2601*4882a593Smuzhiyun 						}
2602*4882a593Smuzhiyun 					}
2603*4882a593Smuzhiyun 
2604*4882a593Smuzhiyun 					if (!spur) {
2605*4882a593Smuzhiyun 						adc->pll_loopdiv = loopdiv;
2606*4882a593Smuzhiyun 						adc->pll_prediv = prediv;
2607*4882a593Smuzhiyun 						adc->timf = 2396745143UL/fdem*(1 << 9);
2608*4882a593Smuzhiyun 						adc->timf += ((2396745143UL%fdem) << 9)/fdem;
2609*4882a593Smuzhiyun 						deb_info("loopdiv=%i prediv=%i timf=%i", loopdiv, prediv, adc->timf);
2610*4882a593Smuzhiyun 						break;
2611*4882a593Smuzhiyun 					}
2612*4882a593Smuzhiyun 				}
2613*4882a593Smuzhiyun 			}
2614*4882a593Smuzhiyun 		}
2615*4882a593Smuzhiyun 		if (!spur)
2616*4882a593Smuzhiyun 			break;
2617*4882a593Smuzhiyun 	}
2618*4882a593Smuzhiyun 
2619*4882a593Smuzhiyun 
2620*4882a593Smuzhiyun 	if (adc->pll_loopdiv == 0 && adc->pll_prediv == 0)
2621*4882a593Smuzhiyun 		return -EINVAL;
2622*4882a593Smuzhiyun 	else
2623*4882a593Smuzhiyun 		return 0;
2624*4882a593Smuzhiyun }
2625*4882a593Smuzhiyun 
dib7090_agc_startup(struct dvb_frontend * fe)2626*4882a593Smuzhiyun static int dib7090_agc_startup(struct dvb_frontend *fe)
2627*4882a593Smuzhiyun {
2628*4882a593Smuzhiyun 	struct dvb_usb_adapter *adap = fe->dvb->priv;
2629*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
2630*4882a593Smuzhiyun 	struct dibx000_bandwidth_config pll;
2631*4882a593Smuzhiyun 	u16 target;
2632*4882a593Smuzhiyun 	struct dibx090p_best_adc adc;
2633*4882a593Smuzhiyun 	int ret;
2634*4882a593Smuzhiyun 
2635*4882a593Smuzhiyun 	ret = state->set_param_save(fe);
2636*4882a593Smuzhiyun 	if (ret < 0)
2637*4882a593Smuzhiyun 		return ret;
2638*4882a593Smuzhiyun 
2639*4882a593Smuzhiyun 	memset(&pll, 0, sizeof(struct dibx000_bandwidth_config));
2640*4882a593Smuzhiyun 	dib0090_pwm_gain_reset(fe);
2641*4882a593Smuzhiyun 	target = (dib0090_get_wbd_target(fe) * 8 + 1) / 2;
2642*4882a593Smuzhiyun 	state->dib7000p_ops.set_wbd_ref(fe, target);
2643*4882a593Smuzhiyun 
2644*4882a593Smuzhiyun 	if (dib7090p_get_best_sampling(fe, &adc) == 0) {
2645*4882a593Smuzhiyun 		pll.pll_ratio  = adc.pll_loopdiv;
2646*4882a593Smuzhiyun 		pll.pll_prediv = adc.pll_prediv;
2647*4882a593Smuzhiyun 
2648*4882a593Smuzhiyun 		state->dib7000p_ops.update_pll(fe, &pll);
2649*4882a593Smuzhiyun 		state->dib7000p_ops.ctrl_timf(fe, DEMOD_TIMF_SET, adc.timf);
2650*4882a593Smuzhiyun 	}
2651*4882a593Smuzhiyun 	return 0;
2652*4882a593Smuzhiyun }
2653*4882a593Smuzhiyun 
dib7090_agc_restart(struct dvb_frontend * fe,u8 restart)2654*4882a593Smuzhiyun static int dib7090_agc_restart(struct dvb_frontend *fe, u8 restart)
2655*4882a593Smuzhiyun {
2656*4882a593Smuzhiyun 	deb_info("AGC restart callback: %d", restart);
2657*4882a593Smuzhiyun 	if (restart == 0) /* before AGC startup */
2658*4882a593Smuzhiyun 		dib0090_set_dc_servo(fe, 1);
2659*4882a593Smuzhiyun 	return 0;
2660*4882a593Smuzhiyun }
2661*4882a593Smuzhiyun 
tfe7790p_update_lna(struct dvb_frontend * fe,u16 agc_global)2662*4882a593Smuzhiyun static int tfe7790p_update_lna(struct dvb_frontend *fe, u16 agc_global)
2663*4882a593Smuzhiyun {
2664*4882a593Smuzhiyun 	struct dvb_usb_adapter *adap = fe->dvb->priv;
2665*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
2666*4882a593Smuzhiyun 
2667*4882a593Smuzhiyun 	deb_info("update LNA: agc global=%i", agc_global);
2668*4882a593Smuzhiyun 
2669*4882a593Smuzhiyun 	if (agc_global < 25000) {
2670*4882a593Smuzhiyun 		state->dib7000p_ops.set_gpio(fe, 8, 0, 0);
2671*4882a593Smuzhiyun 		state->dib7000p_ops.set_agc1_min(fe, 0);
2672*4882a593Smuzhiyun 	} else {
2673*4882a593Smuzhiyun 		state->dib7000p_ops.set_gpio(fe, 8, 0, 1);
2674*4882a593Smuzhiyun 		state->dib7000p_ops.set_agc1_min(fe, 32768);
2675*4882a593Smuzhiyun 	}
2676*4882a593Smuzhiyun 
2677*4882a593Smuzhiyun 	return 0;
2678*4882a593Smuzhiyun }
2679*4882a593Smuzhiyun 
2680*4882a593Smuzhiyun static struct dib0090_wbd_slope dib7090_wbd_table[] = {
2681*4882a593Smuzhiyun 	{ 380,   81, 850, 64, 540,  4},
2682*4882a593Smuzhiyun 	{ 860,   51, 866, 21,  375, 4},
2683*4882a593Smuzhiyun 	{1700,    0, 250, 0,   100, 6},
2684*4882a593Smuzhiyun 	{2600,    0, 250, 0,   100, 6},
2685*4882a593Smuzhiyun 	{ 0xFFFF, 0,   0, 0,   0,   0},
2686*4882a593Smuzhiyun };
2687*4882a593Smuzhiyun 
2688*4882a593Smuzhiyun static struct dibx000_agc_config dib7090_agc_config[2] = {
2689*4882a593Smuzhiyun 	{
2690*4882a593Smuzhiyun 		.band_caps      = BAND_UHF,
2691*4882a593Smuzhiyun 		/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
2692*4882a593Smuzhiyun 		* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
2693*4882a593Smuzhiyun 		.setup          = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
2694*4882a593Smuzhiyun 
2695*4882a593Smuzhiyun 		.inv_gain       = 687,
2696*4882a593Smuzhiyun 		.time_stabiliz  = 10,
2697*4882a593Smuzhiyun 
2698*4882a593Smuzhiyun 		.alpha_level    = 0,
2699*4882a593Smuzhiyun 		.thlock         = 118,
2700*4882a593Smuzhiyun 
2701*4882a593Smuzhiyun 		.wbd_inv        = 0,
2702*4882a593Smuzhiyun 		.wbd_ref        = 1200,
2703*4882a593Smuzhiyun 		.wbd_sel        = 3,
2704*4882a593Smuzhiyun 		.wbd_alpha      = 5,
2705*4882a593Smuzhiyun 
2706*4882a593Smuzhiyun 		.agc1_max       = 65535,
2707*4882a593Smuzhiyun 		.agc1_min       = 32768,
2708*4882a593Smuzhiyun 
2709*4882a593Smuzhiyun 		.agc2_max       = 65535,
2710*4882a593Smuzhiyun 		.agc2_min       = 0,
2711*4882a593Smuzhiyun 
2712*4882a593Smuzhiyun 		.agc1_pt1       = 0,
2713*4882a593Smuzhiyun 		.agc1_pt2       = 32,
2714*4882a593Smuzhiyun 		.agc1_pt3       = 114,
2715*4882a593Smuzhiyun 		.agc1_slope1    = 143,
2716*4882a593Smuzhiyun 		.agc1_slope2    = 144,
2717*4882a593Smuzhiyun 		.agc2_pt1       = 114,
2718*4882a593Smuzhiyun 		.agc2_pt2       = 227,
2719*4882a593Smuzhiyun 		.agc2_slope1    = 116,
2720*4882a593Smuzhiyun 		.agc2_slope2    = 117,
2721*4882a593Smuzhiyun 
2722*4882a593Smuzhiyun 		.alpha_mant     = 18,
2723*4882a593Smuzhiyun 		.alpha_exp      = 0,
2724*4882a593Smuzhiyun 		.beta_mant      = 20,
2725*4882a593Smuzhiyun 		.beta_exp       = 59,
2726*4882a593Smuzhiyun 
2727*4882a593Smuzhiyun 		.perform_agc_softsplit = 0,
2728*4882a593Smuzhiyun 	} , {
2729*4882a593Smuzhiyun 		.band_caps      = BAND_FM | BAND_VHF | BAND_CBAND,
2730*4882a593Smuzhiyun 		/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
2731*4882a593Smuzhiyun 		* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
2732*4882a593Smuzhiyun 		.setup          = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
2733*4882a593Smuzhiyun 
2734*4882a593Smuzhiyun 		.inv_gain       = 732,
2735*4882a593Smuzhiyun 		.time_stabiliz  = 10,
2736*4882a593Smuzhiyun 
2737*4882a593Smuzhiyun 		.alpha_level    = 0,
2738*4882a593Smuzhiyun 		.thlock         = 118,
2739*4882a593Smuzhiyun 
2740*4882a593Smuzhiyun 		.wbd_inv        = 0,
2741*4882a593Smuzhiyun 		.wbd_ref        = 1200,
2742*4882a593Smuzhiyun 		.wbd_sel        = 3,
2743*4882a593Smuzhiyun 		.wbd_alpha      = 5,
2744*4882a593Smuzhiyun 
2745*4882a593Smuzhiyun 		.agc1_max       = 65535,
2746*4882a593Smuzhiyun 		.agc1_min       = 0,
2747*4882a593Smuzhiyun 
2748*4882a593Smuzhiyun 		.agc2_max       = 65535,
2749*4882a593Smuzhiyun 		.agc2_min       = 0,
2750*4882a593Smuzhiyun 
2751*4882a593Smuzhiyun 		.agc1_pt1       = 0,
2752*4882a593Smuzhiyun 		.agc1_pt2       = 0,
2753*4882a593Smuzhiyun 		.agc1_pt3       = 98,
2754*4882a593Smuzhiyun 		.agc1_slope1    = 0,
2755*4882a593Smuzhiyun 		.agc1_slope2    = 167,
2756*4882a593Smuzhiyun 		.agc2_pt1       = 98,
2757*4882a593Smuzhiyun 		.agc2_pt2       = 255,
2758*4882a593Smuzhiyun 		.agc2_slope1    = 104,
2759*4882a593Smuzhiyun 		.agc2_slope2    = 0,
2760*4882a593Smuzhiyun 
2761*4882a593Smuzhiyun 		.alpha_mant     = 18,
2762*4882a593Smuzhiyun 		.alpha_exp      = 0,
2763*4882a593Smuzhiyun 		.beta_mant      = 20,
2764*4882a593Smuzhiyun 		.beta_exp       = 59,
2765*4882a593Smuzhiyun 
2766*4882a593Smuzhiyun 		.perform_agc_softsplit = 0,
2767*4882a593Smuzhiyun 	}
2768*4882a593Smuzhiyun };
2769*4882a593Smuzhiyun 
2770*4882a593Smuzhiyun static struct dibx000_bandwidth_config dib7090_clock_config_12_mhz = {
2771*4882a593Smuzhiyun 	.internal = 60000,
2772*4882a593Smuzhiyun 	.sampling = 15000,
2773*4882a593Smuzhiyun 	.pll_prediv = 1,
2774*4882a593Smuzhiyun 	.pll_ratio = 5,
2775*4882a593Smuzhiyun 	.pll_range = 0,
2776*4882a593Smuzhiyun 	.pll_reset = 0,
2777*4882a593Smuzhiyun 	.pll_bypass = 0,
2778*4882a593Smuzhiyun 	.enable_refdiv = 0,
2779*4882a593Smuzhiyun 	.bypclk_div = 0,
2780*4882a593Smuzhiyun 	.IO_CLK_en_core = 1,
2781*4882a593Smuzhiyun 	.ADClkSrc = 1,
2782*4882a593Smuzhiyun 	.modulo = 2,
2783*4882a593Smuzhiyun 	.sad_cfg = (3 << 14) | (1 << 12) | (524 << 0),
2784*4882a593Smuzhiyun 	.ifreq = (0 << 25) | 0,
2785*4882a593Smuzhiyun 	.timf = 20452225,
2786*4882a593Smuzhiyun 	.xtal_hz = 15000000,
2787*4882a593Smuzhiyun };
2788*4882a593Smuzhiyun 
2789*4882a593Smuzhiyun static struct dib7000p_config nim7090_dib7000p_config = {
2790*4882a593Smuzhiyun 	.output_mpeg2_in_188_bytes  = 1,
2791*4882a593Smuzhiyun 	.hostbus_diversity			= 1,
2792*4882a593Smuzhiyun 	.tuner_is_baseband			= 1,
2793*4882a593Smuzhiyun 	.update_lna					= tfe7790p_update_lna, /* GPIO used is the same as TFE7790 */
2794*4882a593Smuzhiyun 
2795*4882a593Smuzhiyun 	.agc_config_count			= 2,
2796*4882a593Smuzhiyun 	.agc						= dib7090_agc_config,
2797*4882a593Smuzhiyun 
2798*4882a593Smuzhiyun 	.bw							= &dib7090_clock_config_12_mhz,
2799*4882a593Smuzhiyun 
2800*4882a593Smuzhiyun 	.gpio_dir					= DIB7000P_GPIO_DEFAULT_DIRECTIONS,
2801*4882a593Smuzhiyun 	.gpio_val					= DIB7000P_GPIO_DEFAULT_VALUES,
2802*4882a593Smuzhiyun 	.gpio_pwm_pos				= DIB7000P_GPIO_DEFAULT_PWM_POS,
2803*4882a593Smuzhiyun 
2804*4882a593Smuzhiyun 	.pwm_freq_div				= 0,
2805*4882a593Smuzhiyun 
2806*4882a593Smuzhiyun 	.agc_control				= dib7090_agc_restart,
2807*4882a593Smuzhiyun 
2808*4882a593Smuzhiyun 	.spur_protect				= 0,
2809*4882a593Smuzhiyun 	.disable_sample_and_hold	= 0,
2810*4882a593Smuzhiyun 	.enable_current_mirror		= 0,
2811*4882a593Smuzhiyun 	.diversity_delay			= 0,
2812*4882a593Smuzhiyun 
2813*4882a593Smuzhiyun 	.output_mode				= OUTMODE_MPEG2_FIFO,
2814*4882a593Smuzhiyun 	.enMpegOutput				= 1,
2815*4882a593Smuzhiyun };
2816*4882a593Smuzhiyun 
tfe7090p_pvr_update_lna(struct dvb_frontend * fe,u16 agc_global)2817*4882a593Smuzhiyun static int tfe7090p_pvr_update_lna(struct dvb_frontend *fe, u16 agc_global)
2818*4882a593Smuzhiyun {
2819*4882a593Smuzhiyun 	struct dvb_usb_adapter *adap = fe->dvb->priv;
2820*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
2821*4882a593Smuzhiyun 
2822*4882a593Smuzhiyun 	deb_info("TFE7090P-PVR update LNA: agc global=%i", agc_global);
2823*4882a593Smuzhiyun 	if (agc_global < 25000) {
2824*4882a593Smuzhiyun 		state->dib7000p_ops.set_gpio(fe, 5, 0, 0);
2825*4882a593Smuzhiyun 		state->dib7000p_ops.set_agc1_min(fe, 0);
2826*4882a593Smuzhiyun 	} else {
2827*4882a593Smuzhiyun 		state->dib7000p_ops.set_gpio(fe, 5, 0, 1);
2828*4882a593Smuzhiyun 		state->dib7000p_ops.set_agc1_min(fe, 32768);
2829*4882a593Smuzhiyun 	}
2830*4882a593Smuzhiyun 
2831*4882a593Smuzhiyun 	return 0;
2832*4882a593Smuzhiyun }
2833*4882a593Smuzhiyun 
2834*4882a593Smuzhiyun static struct dib7000p_config tfe7090pvr_dib7000p_config[2] = {
2835*4882a593Smuzhiyun 	{
2836*4882a593Smuzhiyun 		.output_mpeg2_in_188_bytes  = 1,
2837*4882a593Smuzhiyun 		.hostbus_diversity			= 1,
2838*4882a593Smuzhiyun 		.tuner_is_baseband			= 1,
2839*4882a593Smuzhiyun 		.update_lna					= tfe7090p_pvr_update_lna,
2840*4882a593Smuzhiyun 
2841*4882a593Smuzhiyun 		.agc_config_count			= 2,
2842*4882a593Smuzhiyun 		.agc						= dib7090_agc_config,
2843*4882a593Smuzhiyun 
2844*4882a593Smuzhiyun 		.bw							= &dib7090_clock_config_12_mhz,
2845*4882a593Smuzhiyun 
2846*4882a593Smuzhiyun 		.gpio_dir					= DIB7000P_GPIO_DEFAULT_DIRECTIONS,
2847*4882a593Smuzhiyun 		.gpio_val					= DIB7000P_GPIO_DEFAULT_VALUES,
2848*4882a593Smuzhiyun 		.gpio_pwm_pos				= DIB7000P_GPIO_DEFAULT_PWM_POS,
2849*4882a593Smuzhiyun 
2850*4882a593Smuzhiyun 		.pwm_freq_div				= 0,
2851*4882a593Smuzhiyun 
2852*4882a593Smuzhiyun 		.agc_control				= dib7090_agc_restart,
2853*4882a593Smuzhiyun 
2854*4882a593Smuzhiyun 		.spur_protect				= 0,
2855*4882a593Smuzhiyun 		.disable_sample_and_hold	= 0,
2856*4882a593Smuzhiyun 		.enable_current_mirror		= 0,
2857*4882a593Smuzhiyun 		.diversity_delay			= 0,
2858*4882a593Smuzhiyun 
2859*4882a593Smuzhiyun 		.output_mode				= OUTMODE_MPEG2_PAR_GATED_CLK,
2860*4882a593Smuzhiyun 		.default_i2c_addr			= 0x90,
2861*4882a593Smuzhiyun 		.enMpegOutput				= 1,
2862*4882a593Smuzhiyun 	}, {
2863*4882a593Smuzhiyun 		.output_mpeg2_in_188_bytes  = 1,
2864*4882a593Smuzhiyun 		.hostbus_diversity			= 1,
2865*4882a593Smuzhiyun 		.tuner_is_baseband			= 1,
2866*4882a593Smuzhiyun 		.update_lna					= tfe7090p_pvr_update_lna,
2867*4882a593Smuzhiyun 
2868*4882a593Smuzhiyun 		.agc_config_count			= 2,
2869*4882a593Smuzhiyun 		.agc						= dib7090_agc_config,
2870*4882a593Smuzhiyun 
2871*4882a593Smuzhiyun 		.bw							= &dib7090_clock_config_12_mhz,
2872*4882a593Smuzhiyun 
2873*4882a593Smuzhiyun 		.gpio_dir					= DIB7000P_GPIO_DEFAULT_DIRECTIONS,
2874*4882a593Smuzhiyun 		.gpio_val					= DIB7000P_GPIO_DEFAULT_VALUES,
2875*4882a593Smuzhiyun 		.gpio_pwm_pos				= DIB7000P_GPIO_DEFAULT_PWM_POS,
2876*4882a593Smuzhiyun 
2877*4882a593Smuzhiyun 		.pwm_freq_div				= 0,
2878*4882a593Smuzhiyun 
2879*4882a593Smuzhiyun 		.agc_control				= dib7090_agc_restart,
2880*4882a593Smuzhiyun 
2881*4882a593Smuzhiyun 		.spur_protect				= 0,
2882*4882a593Smuzhiyun 		.disable_sample_and_hold	= 0,
2883*4882a593Smuzhiyun 		.enable_current_mirror		= 0,
2884*4882a593Smuzhiyun 		.diversity_delay			= 0,
2885*4882a593Smuzhiyun 
2886*4882a593Smuzhiyun 		.output_mode				= OUTMODE_MPEG2_PAR_GATED_CLK,
2887*4882a593Smuzhiyun 		.default_i2c_addr			= 0x92,
2888*4882a593Smuzhiyun 		.enMpegOutput				= 0,
2889*4882a593Smuzhiyun 	}
2890*4882a593Smuzhiyun };
2891*4882a593Smuzhiyun 
2892*4882a593Smuzhiyun static struct dib0090_config nim7090_dib0090_config = {
2893*4882a593Smuzhiyun 	.io.clock_khz = 12000,
2894*4882a593Smuzhiyun 	.io.pll_bypass = 0,
2895*4882a593Smuzhiyun 	.io.pll_range = 0,
2896*4882a593Smuzhiyun 	.io.pll_prediv = 3,
2897*4882a593Smuzhiyun 	.io.pll_loopdiv = 6,
2898*4882a593Smuzhiyun 	.io.adc_clock_ratio = 0,
2899*4882a593Smuzhiyun 	.io.pll_int_loop_filt = 0,
2900*4882a593Smuzhiyun 
2901*4882a593Smuzhiyun 	.freq_offset_khz_uhf = 0,
2902*4882a593Smuzhiyun 	.freq_offset_khz_vhf = 0,
2903*4882a593Smuzhiyun 
2904*4882a593Smuzhiyun 	.clkouttobamse = 1,
2905*4882a593Smuzhiyun 	.analog_output = 0,
2906*4882a593Smuzhiyun 
2907*4882a593Smuzhiyun 	.wbd_vhf_offset = 0,
2908*4882a593Smuzhiyun 	.wbd_cband_offset = 0,
2909*4882a593Smuzhiyun 	.use_pwm_agc = 1,
2910*4882a593Smuzhiyun 	.clkoutdrive = 0,
2911*4882a593Smuzhiyun 
2912*4882a593Smuzhiyun 	.fref_clock_ratio = 0,
2913*4882a593Smuzhiyun 
2914*4882a593Smuzhiyun 	.wbd = dib7090_wbd_table,
2915*4882a593Smuzhiyun 
2916*4882a593Smuzhiyun 	.ls_cfg_pad_drv = 0,
2917*4882a593Smuzhiyun 	.data_tx_drv = 0,
2918*4882a593Smuzhiyun 	.low_if = NULL,
2919*4882a593Smuzhiyun 	.in_soc = 1,
2920*4882a593Smuzhiyun };
2921*4882a593Smuzhiyun 
2922*4882a593Smuzhiyun static struct dib7000p_config tfe7790p_dib7000p_config = {
2923*4882a593Smuzhiyun 	.output_mpeg2_in_188_bytes  = 1,
2924*4882a593Smuzhiyun 	.hostbus_diversity			= 1,
2925*4882a593Smuzhiyun 	.tuner_is_baseband			= 1,
2926*4882a593Smuzhiyun 	.update_lna					= tfe7790p_update_lna,
2927*4882a593Smuzhiyun 
2928*4882a593Smuzhiyun 	.agc_config_count			= 2,
2929*4882a593Smuzhiyun 	.agc						= dib7090_agc_config,
2930*4882a593Smuzhiyun 
2931*4882a593Smuzhiyun 	.bw							= &dib7090_clock_config_12_mhz,
2932*4882a593Smuzhiyun 
2933*4882a593Smuzhiyun 	.gpio_dir					= DIB7000P_GPIO_DEFAULT_DIRECTIONS,
2934*4882a593Smuzhiyun 	.gpio_val					= DIB7000P_GPIO_DEFAULT_VALUES,
2935*4882a593Smuzhiyun 	.gpio_pwm_pos				= DIB7000P_GPIO_DEFAULT_PWM_POS,
2936*4882a593Smuzhiyun 
2937*4882a593Smuzhiyun 	.pwm_freq_div				= 0,
2938*4882a593Smuzhiyun 
2939*4882a593Smuzhiyun 	.agc_control				= dib7090_agc_restart,
2940*4882a593Smuzhiyun 
2941*4882a593Smuzhiyun 	.spur_protect				= 0,
2942*4882a593Smuzhiyun 	.disable_sample_and_hold	= 0,
2943*4882a593Smuzhiyun 	.enable_current_mirror		= 0,
2944*4882a593Smuzhiyun 	.diversity_delay			= 0,
2945*4882a593Smuzhiyun 
2946*4882a593Smuzhiyun 	.output_mode				= OUTMODE_MPEG2_PAR_GATED_CLK,
2947*4882a593Smuzhiyun 	.enMpegOutput				= 1,
2948*4882a593Smuzhiyun };
2949*4882a593Smuzhiyun 
2950*4882a593Smuzhiyun static struct dib0090_config tfe7790p_dib0090_config = {
2951*4882a593Smuzhiyun 	.io.clock_khz = 12000,
2952*4882a593Smuzhiyun 	.io.pll_bypass = 0,
2953*4882a593Smuzhiyun 	.io.pll_range = 0,
2954*4882a593Smuzhiyun 	.io.pll_prediv = 3,
2955*4882a593Smuzhiyun 	.io.pll_loopdiv = 6,
2956*4882a593Smuzhiyun 	.io.adc_clock_ratio = 0,
2957*4882a593Smuzhiyun 	.io.pll_int_loop_filt = 0,
2958*4882a593Smuzhiyun 
2959*4882a593Smuzhiyun 	.freq_offset_khz_uhf = 0,
2960*4882a593Smuzhiyun 	.freq_offset_khz_vhf = 0,
2961*4882a593Smuzhiyun 
2962*4882a593Smuzhiyun 	.clkouttobamse = 1,
2963*4882a593Smuzhiyun 	.analog_output = 0,
2964*4882a593Smuzhiyun 
2965*4882a593Smuzhiyun 	.wbd_vhf_offset = 0,
2966*4882a593Smuzhiyun 	.wbd_cband_offset = 0,
2967*4882a593Smuzhiyun 	.use_pwm_agc = 1,
2968*4882a593Smuzhiyun 	.clkoutdrive = 0,
2969*4882a593Smuzhiyun 
2970*4882a593Smuzhiyun 	.fref_clock_ratio = 0,
2971*4882a593Smuzhiyun 
2972*4882a593Smuzhiyun 	.wbd = dib7090_wbd_table,
2973*4882a593Smuzhiyun 
2974*4882a593Smuzhiyun 	.ls_cfg_pad_drv = 0,
2975*4882a593Smuzhiyun 	.data_tx_drv = 0,
2976*4882a593Smuzhiyun 	.low_if = NULL,
2977*4882a593Smuzhiyun 	.in_soc = 1,
2978*4882a593Smuzhiyun 	.force_cband_input = 0,
2979*4882a593Smuzhiyun 	.is_dib7090e = 0,
2980*4882a593Smuzhiyun 	.force_crystal_mode = 1,
2981*4882a593Smuzhiyun };
2982*4882a593Smuzhiyun 
2983*4882a593Smuzhiyun static struct dib0090_config tfe7090pvr_dib0090_config[2] = {
2984*4882a593Smuzhiyun 	{
2985*4882a593Smuzhiyun 		.io.clock_khz = 12000,
2986*4882a593Smuzhiyun 		.io.pll_bypass = 0,
2987*4882a593Smuzhiyun 		.io.pll_range = 0,
2988*4882a593Smuzhiyun 		.io.pll_prediv = 3,
2989*4882a593Smuzhiyun 		.io.pll_loopdiv = 6,
2990*4882a593Smuzhiyun 		.io.adc_clock_ratio = 0,
2991*4882a593Smuzhiyun 		.io.pll_int_loop_filt = 0,
2992*4882a593Smuzhiyun 
2993*4882a593Smuzhiyun 		.freq_offset_khz_uhf = 50,
2994*4882a593Smuzhiyun 		.freq_offset_khz_vhf = 70,
2995*4882a593Smuzhiyun 
2996*4882a593Smuzhiyun 		.clkouttobamse = 1,
2997*4882a593Smuzhiyun 		.analog_output = 0,
2998*4882a593Smuzhiyun 
2999*4882a593Smuzhiyun 		.wbd_vhf_offset = 0,
3000*4882a593Smuzhiyun 		.wbd_cband_offset = 0,
3001*4882a593Smuzhiyun 		.use_pwm_agc = 1,
3002*4882a593Smuzhiyun 		.clkoutdrive = 0,
3003*4882a593Smuzhiyun 
3004*4882a593Smuzhiyun 		.fref_clock_ratio = 0,
3005*4882a593Smuzhiyun 
3006*4882a593Smuzhiyun 		.wbd = dib7090_wbd_table,
3007*4882a593Smuzhiyun 
3008*4882a593Smuzhiyun 		.ls_cfg_pad_drv = 0,
3009*4882a593Smuzhiyun 		.data_tx_drv = 0,
3010*4882a593Smuzhiyun 		.low_if = NULL,
3011*4882a593Smuzhiyun 		.in_soc = 1,
3012*4882a593Smuzhiyun 	}, {
3013*4882a593Smuzhiyun 		.io.clock_khz = 12000,
3014*4882a593Smuzhiyun 		.io.pll_bypass = 0,
3015*4882a593Smuzhiyun 		.io.pll_range = 0,
3016*4882a593Smuzhiyun 		.io.pll_prediv = 3,
3017*4882a593Smuzhiyun 		.io.pll_loopdiv = 6,
3018*4882a593Smuzhiyun 		.io.adc_clock_ratio = 0,
3019*4882a593Smuzhiyun 		.io.pll_int_loop_filt = 0,
3020*4882a593Smuzhiyun 
3021*4882a593Smuzhiyun 		.freq_offset_khz_uhf = -50,
3022*4882a593Smuzhiyun 		.freq_offset_khz_vhf = -70,
3023*4882a593Smuzhiyun 
3024*4882a593Smuzhiyun 		.clkouttobamse = 1,
3025*4882a593Smuzhiyun 		.analog_output = 0,
3026*4882a593Smuzhiyun 
3027*4882a593Smuzhiyun 		.wbd_vhf_offset = 0,
3028*4882a593Smuzhiyun 		.wbd_cband_offset = 0,
3029*4882a593Smuzhiyun 		.use_pwm_agc = 1,
3030*4882a593Smuzhiyun 		.clkoutdrive = 0,
3031*4882a593Smuzhiyun 
3032*4882a593Smuzhiyun 		.fref_clock_ratio = 0,
3033*4882a593Smuzhiyun 
3034*4882a593Smuzhiyun 		.wbd = dib7090_wbd_table,
3035*4882a593Smuzhiyun 
3036*4882a593Smuzhiyun 		.ls_cfg_pad_drv = 0,
3037*4882a593Smuzhiyun 		.data_tx_drv = 0,
3038*4882a593Smuzhiyun 		.low_if = NULL,
3039*4882a593Smuzhiyun 		.in_soc = 1,
3040*4882a593Smuzhiyun 	}
3041*4882a593Smuzhiyun };
3042*4882a593Smuzhiyun 
nim7090_frontend_attach(struct dvb_usb_adapter * adap)3043*4882a593Smuzhiyun static int nim7090_frontend_attach(struct dvb_usb_adapter *adap)
3044*4882a593Smuzhiyun {
3045*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
3046*4882a593Smuzhiyun 
3047*4882a593Smuzhiyun 	if (!dvb_attach(dib7000p_attach, &state->dib7000p_ops))
3048*4882a593Smuzhiyun 		return -ENODEV;
3049*4882a593Smuzhiyun 
3050*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
3051*4882a593Smuzhiyun 	msleep(20);
3052*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
3053*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
3054*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
3055*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
3056*4882a593Smuzhiyun 
3057*4882a593Smuzhiyun 	msleep(20);
3058*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
3059*4882a593Smuzhiyun 	msleep(20);
3060*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
3061*4882a593Smuzhiyun 
3062*4882a593Smuzhiyun 	if (state->dib7000p_ops.i2c_enumeration(&adap->dev->i2c_adap, 1, 0x10, &nim7090_dib7000p_config) != 0) {
3063*4882a593Smuzhiyun 		err("%s: state->dib7000p_ops.i2c_enumeration failed.  Cannot continue\n", __func__);
3064*4882a593Smuzhiyun 		dvb_detach(state->dib7000p_ops.set_wbd_ref);
3065*4882a593Smuzhiyun 		return -ENODEV;
3066*4882a593Smuzhiyun 	}
3067*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib7000p_ops.init(&adap->dev->i2c_adap, 0x80, &nim7090_dib7000p_config);
3068*4882a593Smuzhiyun 
3069*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ?  -ENODEV : 0;
3070*4882a593Smuzhiyun }
3071*4882a593Smuzhiyun 
nim7090_tuner_attach(struct dvb_usb_adapter * adap)3072*4882a593Smuzhiyun static int nim7090_tuner_attach(struct dvb_usb_adapter *adap)
3073*4882a593Smuzhiyun {
3074*4882a593Smuzhiyun 	struct dib0700_adapter_state *st = adap->priv;
3075*4882a593Smuzhiyun 	struct i2c_adapter *tun_i2c = st->dib7000p_ops.get_i2c_tuner(adap->fe_adap[0].fe);
3076*4882a593Smuzhiyun 
3077*4882a593Smuzhiyun 	nim7090_dib0090_config.reset = st->dib7000p_ops.tuner_sleep,
3078*4882a593Smuzhiyun 	nim7090_dib0090_config.sleep = st->dib7000p_ops.tuner_sleep,
3079*4882a593Smuzhiyun 	nim7090_dib0090_config.get_adc_power = st->dib7000p_ops.get_adc_power;
3080*4882a593Smuzhiyun 
3081*4882a593Smuzhiyun 	if (dvb_attach(dib0090_register, adap->fe_adap[0].fe, tun_i2c, &nim7090_dib0090_config) == NULL)
3082*4882a593Smuzhiyun 		return -ENODEV;
3083*4882a593Smuzhiyun 
3084*4882a593Smuzhiyun 	st->dib7000p_ops.set_gpio(adap->fe_adap[0].fe, 8, 0, 1);
3085*4882a593Smuzhiyun 
3086*4882a593Smuzhiyun 	st->set_param_save = adap->fe_adap[0].fe->ops.tuner_ops.set_params;
3087*4882a593Smuzhiyun 	adap->fe_adap[0].fe->ops.tuner_ops.set_params = dib7090_agc_startup;
3088*4882a593Smuzhiyun 	return 0;
3089*4882a593Smuzhiyun }
3090*4882a593Smuzhiyun 
tfe7090pvr_frontend0_attach(struct dvb_usb_adapter * adap)3091*4882a593Smuzhiyun static int tfe7090pvr_frontend0_attach(struct dvb_usb_adapter *adap)
3092*4882a593Smuzhiyun {
3093*4882a593Smuzhiyun 	struct dib0700_state *st = adap->dev->priv;
3094*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
3095*4882a593Smuzhiyun 
3096*4882a593Smuzhiyun 	if (!dvb_attach(dib7000p_attach, &state->dib7000p_ops))
3097*4882a593Smuzhiyun 		return -ENODEV;
3098*4882a593Smuzhiyun 
3099*4882a593Smuzhiyun 	/* The TFE7090 requires the dib0700 to not be in master mode */
3100*4882a593Smuzhiyun 	st->disable_streaming_master_mode = 1;
3101*4882a593Smuzhiyun 
3102*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
3103*4882a593Smuzhiyun 	msleep(20);
3104*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
3105*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
3106*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
3107*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
3108*4882a593Smuzhiyun 
3109*4882a593Smuzhiyun 	msleep(20);
3110*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
3111*4882a593Smuzhiyun 	msleep(20);
3112*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
3113*4882a593Smuzhiyun 
3114*4882a593Smuzhiyun 	/* initialize IC 0 */
3115*4882a593Smuzhiyun 	if (state->dib7000p_ops.i2c_enumeration(&adap->dev->i2c_adap, 1, 0x20, &tfe7090pvr_dib7000p_config[0]) != 0) {
3116*4882a593Smuzhiyun 		err("%s: state->dib7000p_ops.i2c_enumeration failed.  Cannot continue\n", __func__);
3117*4882a593Smuzhiyun 		dvb_detach(state->dib7000p_ops.set_wbd_ref);
3118*4882a593Smuzhiyun 		return -ENODEV;
3119*4882a593Smuzhiyun 	}
3120*4882a593Smuzhiyun 
3121*4882a593Smuzhiyun 	dib0700_set_i2c_speed(adap->dev, 340);
3122*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib7000p_ops.init(&adap->dev->i2c_adap, 0x90, &tfe7090pvr_dib7000p_config[0]);
3123*4882a593Smuzhiyun 	if (adap->fe_adap[0].fe == NULL)
3124*4882a593Smuzhiyun 		return -ENODEV;
3125*4882a593Smuzhiyun 
3126*4882a593Smuzhiyun 	state->dib7000p_ops.slave_reset(adap->fe_adap[0].fe);
3127*4882a593Smuzhiyun 
3128*4882a593Smuzhiyun 	return 0;
3129*4882a593Smuzhiyun }
3130*4882a593Smuzhiyun 
tfe7090pvr_frontend1_attach(struct dvb_usb_adapter * adap)3131*4882a593Smuzhiyun static int tfe7090pvr_frontend1_attach(struct dvb_usb_adapter *adap)
3132*4882a593Smuzhiyun {
3133*4882a593Smuzhiyun 	struct i2c_adapter *i2c;
3134*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
3135*4882a593Smuzhiyun 
3136*4882a593Smuzhiyun 	if (adap->dev->adapter[0].fe_adap[0].fe == NULL) {
3137*4882a593Smuzhiyun 		err("the master dib7090 has to be initialized first");
3138*4882a593Smuzhiyun 		return -ENODEV; /* the master device has not been initialized */
3139*4882a593Smuzhiyun 	}
3140*4882a593Smuzhiyun 
3141*4882a593Smuzhiyun 	if (!dvb_attach(dib7000p_attach, &state->dib7000p_ops))
3142*4882a593Smuzhiyun 		return -ENODEV;
3143*4882a593Smuzhiyun 
3144*4882a593Smuzhiyun 	i2c = state->dib7000p_ops.get_i2c_master(adap->dev->adapter[0].fe_adap[0].fe, DIBX000_I2C_INTERFACE_GPIO_6_7, 1);
3145*4882a593Smuzhiyun 	if (state->dib7000p_ops.i2c_enumeration(i2c, 1, 0x10, &tfe7090pvr_dib7000p_config[1]) != 0) {
3146*4882a593Smuzhiyun 		err("%s: state->dib7000p_ops.i2c_enumeration failed.  Cannot continue\n", __func__);
3147*4882a593Smuzhiyun 		dvb_detach(state->dib7000p_ops.set_wbd_ref);
3148*4882a593Smuzhiyun 		return -ENODEV;
3149*4882a593Smuzhiyun 	}
3150*4882a593Smuzhiyun 
3151*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib7000p_ops.init(i2c, 0x92, &tfe7090pvr_dib7000p_config[1]);
3152*4882a593Smuzhiyun 	dib0700_set_i2c_speed(adap->dev, 200);
3153*4882a593Smuzhiyun 
3154*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ? -ENODEV : 0;
3155*4882a593Smuzhiyun }
3156*4882a593Smuzhiyun 
tfe7090pvr_tuner0_attach(struct dvb_usb_adapter * adap)3157*4882a593Smuzhiyun static int tfe7090pvr_tuner0_attach(struct dvb_usb_adapter *adap)
3158*4882a593Smuzhiyun {
3159*4882a593Smuzhiyun 	struct dib0700_adapter_state *st = adap->priv;
3160*4882a593Smuzhiyun 	struct i2c_adapter *tun_i2c = st->dib7000p_ops.get_i2c_tuner(adap->fe_adap[0].fe);
3161*4882a593Smuzhiyun 
3162*4882a593Smuzhiyun 	tfe7090pvr_dib0090_config[0].reset = st->dib7000p_ops.tuner_sleep;
3163*4882a593Smuzhiyun 	tfe7090pvr_dib0090_config[0].sleep = st->dib7000p_ops.tuner_sleep;
3164*4882a593Smuzhiyun 	tfe7090pvr_dib0090_config[0].get_adc_power = st->dib7000p_ops.get_adc_power;
3165*4882a593Smuzhiyun 
3166*4882a593Smuzhiyun 	if (dvb_attach(dib0090_register, adap->fe_adap[0].fe, tun_i2c, &tfe7090pvr_dib0090_config[0]) == NULL)
3167*4882a593Smuzhiyun 		return -ENODEV;
3168*4882a593Smuzhiyun 
3169*4882a593Smuzhiyun 	st->dib7000p_ops.set_gpio(adap->fe_adap[0].fe, 8, 0, 1);
3170*4882a593Smuzhiyun 
3171*4882a593Smuzhiyun 	st->set_param_save = adap->fe_adap[0].fe->ops.tuner_ops.set_params;
3172*4882a593Smuzhiyun 	adap->fe_adap[0].fe->ops.tuner_ops.set_params = dib7090_agc_startup;
3173*4882a593Smuzhiyun 	return 0;
3174*4882a593Smuzhiyun }
3175*4882a593Smuzhiyun 
tfe7090pvr_tuner1_attach(struct dvb_usb_adapter * adap)3176*4882a593Smuzhiyun static int tfe7090pvr_tuner1_attach(struct dvb_usb_adapter *adap)
3177*4882a593Smuzhiyun {
3178*4882a593Smuzhiyun 	struct dib0700_adapter_state *st = adap->priv;
3179*4882a593Smuzhiyun 	struct i2c_adapter *tun_i2c = st->dib7000p_ops.get_i2c_tuner(adap->fe_adap[0].fe);
3180*4882a593Smuzhiyun 
3181*4882a593Smuzhiyun 	tfe7090pvr_dib0090_config[1].reset = st->dib7000p_ops.tuner_sleep;
3182*4882a593Smuzhiyun 	tfe7090pvr_dib0090_config[1].sleep = st->dib7000p_ops.tuner_sleep;
3183*4882a593Smuzhiyun 	tfe7090pvr_dib0090_config[1].get_adc_power = st->dib7000p_ops.get_adc_power;
3184*4882a593Smuzhiyun 
3185*4882a593Smuzhiyun 	if (dvb_attach(dib0090_register, adap->fe_adap[0].fe, tun_i2c, &tfe7090pvr_dib0090_config[1]) == NULL)
3186*4882a593Smuzhiyun 		return -ENODEV;
3187*4882a593Smuzhiyun 
3188*4882a593Smuzhiyun 	st->dib7000p_ops.set_gpio(adap->fe_adap[0].fe, 8, 0, 1);
3189*4882a593Smuzhiyun 
3190*4882a593Smuzhiyun 	st->set_param_save = adap->fe_adap[0].fe->ops.tuner_ops.set_params;
3191*4882a593Smuzhiyun 	adap->fe_adap[0].fe->ops.tuner_ops.set_params = dib7090_agc_startup;
3192*4882a593Smuzhiyun 	return 0;
3193*4882a593Smuzhiyun }
3194*4882a593Smuzhiyun 
tfe7790p_frontend_attach(struct dvb_usb_adapter * adap)3195*4882a593Smuzhiyun static int tfe7790p_frontend_attach(struct dvb_usb_adapter *adap)
3196*4882a593Smuzhiyun {
3197*4882a593Smuzhiyun 	struct dib0700_state *st = adap->dev->priv;
3198*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
3199*4882a593Smuzhiyun 
3200*4882a593Smuzhiyun 	if (!dvb_attach(dib7000p_attach, &state->dib7000p_ops))
3201*4882a593Smuzhiyun 		return -ENODEV;
3202*4882a593Smuzhiyun 
3203*4882a593Smuzhiyun 	/* The TFE7790P requires the dib0700 to not be in master mode */
3204*4882a593Smuzhiyun 	st->disable_streaming_master_mode = 1;
3205*4882a593Smuzhiyun 
3206*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
3207*4882a593Smuzhiyun 	msleep(20);
3208*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
3209*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
3210*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
3211*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
3212*4882a593Smuzhiyun 	msleep(20);
3213*4882a593Smuzhiyun 	dib0700_ctrl_clock(adap->dev, 72, 1);
3214*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
3215*4882a593Smuzhiyun 	msleep(20);
3216*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
3217*4882a593Smuzhiyun 
3218*4882a593Smuzhiyun 	if (state->dib7000p_ops.i2c_enumeration(&adap->dev->i2c_adap,
3219*4882a593Smuzhiyun 				1, 0x10, &tfe7790p_dib7000p_config) != 0) {
3220*4882a593Smuzhiyun 		err("%s: state->dib7000p_ops.i2c_enumeration failed.  Cannot continue\n",
3221*4882a593Smuzhiyun 				__func__);
3222*4882a593Smuzhiyun 		dvb_detach(state->dib7000p_ops.set_wbd_ref);
3223*4882a593Smuzhiyun 		return -ENODEV;
3224*4882a593Smuzhiyun 	}
3225*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib7000p_ops.init(&adap->dev->i2c_adap,
3226*4882a593Smuzhiyun 			0x80, &tfe7790p_dib7000p_config);
3227*4882a593Smuzhiyun 
3228*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ?  -ENODEV : 0;
3229*4882a593Smuzhiyun }
3230*4882a593Smuzhiyun 
tfe7790p_tuner_attach(struct dvb_usb_adapter * adap)3231*4882a593Smuzhiyun static int tfe7790p_tuner_attach(struct dvb_usb_adapter *adap)
3232*4882a593Smuzhiyun {
3233*4882a593Smuzhiyun 	struct dib0700_adapter_state *st = adap->priv;
3234*4882a593Smuzhiyun 	struct i2c_adapter *tun_i2c =
3235*4882a593Smuzhiyun 		st->dib7000p_ops.get_i2c_tuner(adap->fe_adap[0].fe);
3236*4882a593Smuzhiyun 
3237*4882a593Smuzhiyun 
3238*4882a593Smuzhiyun 	tfe7790p_dib0090_config.reset = st->dib7000p_ops.tuner_sleep;
3239*4882a593Smuzhiyun 	tfe7790p_dib0090_config.sleep = st->dib7000p_ops.tuner_sleep;
3240*4882a593Smuzhiyun 	tfe7790p_dib0090_config.get_adc_power = st->dib7000p_ops.get_adc_power;
3241*4882a593Smuzhiyun 
3242*4882a593Smuzhiyun 	if (dvb_attach(dib0090_register, adap->fe_adap[0].fe, tun_i2c,
3243*4882a593Smuzhiyun 				&tfe7790p_dib0090_config) == NULL)
3244*4882a593Smuzhiyun 		return -ENODEV;
3245*4882a593Smuzhiyun 
3246*4882a593Smuzhiyun 	st->dib7000p_ops.set_gpio(adap->fe_adap[0].fe, 8, 0, 1);
3247*4882a593Smuzhiyun 
3248*4882a593Smuzhiyun 	st->set_param_save = adap->fe_adap[0].fe->ops.tuner_ops.set_params;
3249*4882a593Smuzhiyun 	adap->fe_adap[0].fe->ops.tuner_ops.set_params = dib7090_agc_startup;
3250*4882a593Smuzhiyun 	return 0;
3251*4882a593Smuzhiyun }
3252*4882a593Smuzhiyun 
3253*4882a593Smuzhiyun /* STK7070PD */
3254*4882a593Smuzhiyun static struct dib7000p_config stk7070pd_dib7000p_config[2] = {
3255*4882a593Smuzhiyun 	{
3256*4882a593Smuzhiyun 		.output_mpeg2_in_188_bytes = 1,
3257*4882a593Smuzhiyun 
3258*4882a593Smuzhiyun 		.agc_config_count = 1,
3259*4882a593Smuzhiyun 		.agc = &dib7070_agc_config,
3260*4882a593Smuzhiyun 		.bw  = &dib7070_bw_config_12_mhz,
3261*4882a593Smuzhiyun 		.tuner_is_baseband = 1,
3262*4882a593Smuzhiyun 		.spur_protect = 1,
3263*4882a593Smuzhiyun 
3264*4882a593Smuzhiyun 		.gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
3265*4882a593Smuzhiyun 		.gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
3266*4882a593Smuzhiyun 		.gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
3267*4882a593Smuzhiyun 
3268*4882a593Smuzhiyun 		.hostbus_diversity = 1,
3269*4882a593Smuzhiyun 	}, {
3270*4882a593Smuzhiyun 		.output_mpeg2_in_188_bytes = 1,
3271*4882a593Smuzhiyun 
3272*4882a593Smuzhiyun 		.agc_config_count = 1,
3273*4882a593Smuzhiyun 		.agc = &dib7070_agc_config,
3274*4882a593Smuzhiyun 		.bw  = &dib7070_bw_config_12_mhz,
3275*4882a593Smuzhiyun 		.tuner_is_baseband = 1,
3276*4882a593Smuzhiyun 		.spur_protect = 1,
3277*4882a593Smuzhiyun 
3278*4882a593Smuzhiyun 		.gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
3279*4882a593Smuzhiyun 		.gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
3280*4882a593Smuzhiyun 		.gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
3281*4882a593Smuzhiyun 
3282*4882a593Smuzhiyun 		.hostbus_diversity = 1,
3283*4882a593Smuzhiyun 	}
3284*4882a593Smuzhiyun };
3285*4882a593Smuzhiyun 
stk7070pd_init(struct dvb_usb_device * dev)3286*4882a593Smuzhiyun static void stk7070pd_init(struct dvb_usb_device *dev)
3287*4882a593Smuzhiyun {
3288*4882a593Smuzhiyun 	dib0700_set_gpio(dev, GPIO6, GPIO_OUT, 1);
3289*4882a593Smuzhiyun 	msleep(10);
3290*4882a593Smuzhiyun 	dib0700_set_gpio(dev, GPIO9, GPIO_OUT, 1);
3291*4882a593Smuzhiyun 	dib0700_set_gpio(dev, GPIO4, GPIO_OUT, 1);
3292*4882a593Smuzhiyun 	dib0700_set_gpio(dev, GPIO7, GPIO_OUT, 1);
3293*4882a593Smuzhiyun 	dib0700_set_gpio(dev, GPIO10, GPIO_OUT, 0);
3294*4882a593Smuzhiyun 
3295*4882a593Smuzhiyun 	dib0700_ctrl_clock(dev, 72, 1);
3296*4882a593Smuzhiyun 
3297*4882a593Smuzhiyun 	msleep(10);
3298*4882a593Smuzhiyun 	dib0700_set_gpio(dev, GPIO10, GPIO_OUT, 1);
3299*4882a593Smuzhiyun }
3300*4882a593Smuzhiyun 
stk7070pd_frontend_attach0(struct dvb_usb_adapter * adap)3301*4882a593Smuzhiyun static int stk7070pd_frontend_attach0(struct dvb_usb_adapter *adap)
3302*4882a593Smuzhiyun {
3303*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
3304*4882a593Smuzhiyun 
3305*4882a593Smuzhiyun 	if (!dvb_attach(dib7000p_attach, &state->dib7000p_ops))
3306*4882a593Smuzhiyun 		return -ENODEV;
3307*4882a593Smuzhiyun 
3308*4882a593Smuzhiyun 	stk7070pd_init(adap->dev);
3309*4882a593Smuzhiyun 
3310*4882a593Smuzhiyun 	msleep(10);
3311*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
3312*4882a593Smuzhiyun 
3313*4882a593Smuzhiyun 	if (state->dib7000p_ops.i2c_enumeration(&adap->dev->i2c_adap, 2, 18,
3314*4882a593Smuzhiyun 				     stk7070pd_dib7000p_config) != 0) {
3315*4882a593Smuzhiyun 		err("%s: state->dib7000p_ops.i2c_enumeration failed.  Cannot continue\n",
3316*4882a593Smuzhiyun 		    __func__);
3317*4882a593Smuzhiyun 		dvb_detach(state->dib7000p_ops.set_wbd_ref);
3318*4882a593Smuzhiyun 		return -ENODEV;
3319*4882a593Smuzhiyun 	}
3320*4882a593Smuzhiyun 
3321*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib7000p_ops.init(&adap->dev->i2c_adap, 0x80, &stk7070pd_dib7000p_config[0]);
3322*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ? -ENODEV : 0;
3323*4882a593Smuzhiyun }
3324*4882a593Smuzhiyun 
stk7070pd_frontend_attach1(struct dvb_usb_adapter * adap)3325*4882a593Smuzhiyun static int stk7070pd_frontend_attach1(struct dvb_usb_adapter *adap)
3326*4882a593Smuzhiyun {
3327*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
3328*4882a593Smuzhiyun 
3329*4882a593Smuzhiyun 	if (!dvb_attach(dib7000p_attach, &state->dib7000p_ops))
3330*4882a593Smuzhiyun 		return -ENODEV;
3331*4882a593Smuzhiyun 
3332*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib7000p_ops.init(&adap->dev->i2c_adap, 0x82, &stk7070pd_dib7000p_config[1]);
3333*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ? -ENODEV : 0;
3334*4882a593Smuzhiyun }
3335*4882a593Smuzhiyun 
novatd_read_status_override(struct dvb_frontend * fe,enum fe_status * stat)3336*4882a593Smuzhiyun static int novatd_read_status_override(struct dvb_frontend *fe,
3337*4882a593Smuzhiyun 				       enum fe_status *stat)
3338*4882a593Smuzhiyun {
3339*4882a593Smuzhiyun 	struct dvb_usb_adapter *adap = fe->dvb->priv;
3340*4882a593Smuzhiyun 	struct dvb_usb_device *dev = adap->dev;
3341*4882a593Smuzhiyun 	struct dib0700_state *state = dev->priv;
3342*4882a593Smuzhiyun 	int ret;
3343*4882a593Smuzhiyun 
3344*4882a593Smuzhiyun 	ret = state->read_status(fe, stat);
3345*4882a593Smuzhiyun 
3346*4882a593Smuzhiyun 	if (!ret)
3347*4882a593Smuzhiyun 		dib0700_set_gpio(dev, adap->id == 0 ? GPIO1 : GPIO0, GPIO_OUT,
3348*4882a593Smuzhiyun 				!!(*stat & FE_HAS_LOCK));
3349*4882a593Smuzhiyun 
3350*4882a593Smuzhiyun 	return ret;
3351*4882a593Smuzhiyun }
3352*4882a593Smuzhiyun 
novatd_sleep_override(struct dvb_frontend * fe)3353*4882a593Smuzhiyun static int novatd_sleep_override(struct dvb_frontend* fe)
3354*4882a593Smuzhiyun {
3355*4882a593Smuzhiyun 	struct dvb_usb_adapter *adap = fe->dvb->priv;
3356*4882a593Smuzhiyun 	struct dvb_usb_device *dev = adap->dev;
3357*4882a593Smuzhiyun 	struct dib0700_state *state = dev->priv;
3358*4882a593Smuzhiyun 
3359*4882a593Smuzhiyun 	/* turn off LED */
3360*4882a593Smuzhiyun 	dib0700_set_gpio(dev, adap->id == 0 ? GPIO1 : GPIO0, GPIO_OUT, 0);
3361*4882a593Smuzhiyun 
3362*4882a593Smuzhiyun 	return state->sleep(fe);
3363*4882a593Smuzhiyun }
3364*4882a593Smuzhiyun 
3365*4882a593Smuzhiyun /*
3366*4882a593Smuzhiyun  * novatd_frontend_attach - Nova-TD specific attach
3367*4882a593Smuzhiyun  *
3368*4882a593Smuzhiyun  * Nova-TD has GPIO0, 1 and 2 for LEDs. So do not fiddle with them except for
3369*4882a593Smuzhiyun  * information purposes.
3370*4882a593Smuzhiyun  */
novatd_frontend_attach(struct dvb_usb_adapter * adap)3371*4882a593Smuzhiyun static int novatd_frontend_attach(struct dvb_usb_adapter *adap)
3372*4882a593Smuzhiyun {
3373*4882a593Smuzhiyun 	struct dvb_usb_device *dev = adap->dev;
3374*4882a593Smuzhiyun 	struct dib0700_state *st = dev->priv;
3375*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
3376*4882a593Smuzhiyun 
3377*4882a593Smuzhiyun 	if (!dvb_attach(dib7000p_attach, &state->dib7000p_ops))
3378*4882a593Smuzhiyun 		return -ENODEV;
3379*4882a593Smuzhiyun 
3380*4882a593Smuzhiyun 	if (adap->id == 0) {
3381*4882a593Smuzhiyun 		stk7070pd_init(dev);
3382*4882a593Smuzhiyun 
3383*4882a593Smuzhiyun 		/* turn the power LED on, the other two off (just in case) */
3384*4882a593Smuzhiyun 		dib0700_set_gpio(dev, GPIO0, GPIO_OUT, 0);
3385*4882a593Smuzhiyun 		dib0700_set_gpio(dev, GPIO1, GPIO_OUT, 0);
3386*4882a593Smuzhiyun 		dib0700_set_gpio(dev, GPIO2, GPIO_OUT, 1);
3387*4882a593Smuzhiyun 
3388*4882a593Smuzhiyun 		if (state->dib7000p_ops.i2c_enumeration(&dev->i2c_adap, 2, 18,
3389*4882a593Smuzhiyun 					     stk7070pd_dib7000p_config) != 0) {
3390*4882a593Smuzhiyun 			err("%s: state->dib7000p_ops.i2c_enumeration failed.  Cannot continue\n",
3391*4882a593Smuzhiyun 			    __func__);
3392*4882a593Smuzhiyun 			dvb_detach(state->dib7000p_ops.set_wbd_ref);
3393*4882a593Smuzhiyun 			return -ENODEV;
3394*4882a593Smuzhiyun 		}
3395*4882a593Smuzhiyun 	}
3396*4882a593Smuzhiyun 
3397*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib7000p_ops.init(&dev->i2c_adap,
3398*4882a593Smuzhiyun 			adap->id == 0 ? 0x80 : 0x82,
3399*4882a593Smuzhiyun 			&stk7070pd_dib7000p_config[adap->id]);
3400*4882a593Smuzhiyun 
3401*4882a593Smuzhiyun 	if (adap->fe_adap[0].fe == NULL)
3402*4882a593Smuzhiyun 		return -ENODEV;
3403*4882a593Smuzhiyun 
3404*4882a593Smuzhiyun 	st->read_status = adap->fe_adap[0].fe->ops.read_status;
3405*4882a593Smuzhiyun 	adap->fe_adap[0].fe->ops.read_status = novatd_read_status_override;
3406*4882a593Smuzhiyun 	st->sleep = adap->fe_adap[0].fe->ops.sleep;
3407*4882a593Smuzhiyun 	adap->fe_adap[0].fe->ops.sleep = novatd_sleep_override;
3408*4882a593Smuzhiyun 
3409*4882a593Smuzhiyun 	return 0;
3410*4882a593Smuzhiyun }
3411*4882a593Smuzhiyun 
3412*4882a593Smuzhiyun /* S5H1411 */
3413*4882a593Smuzhiyun static struct s5h1411_config pinnacle_801e_config = {
3414*4882a593Smuzhiyun 	.output_mode   = S5H1411_PARALLEL_OUTPUT,
3415*4882a593Smuzhiyun 	.gpio          = S5H1411_GPIO_OFF,
3416*4882a593Smuzhiyun 	.mpeg_timing   = S5H1411_MPEGTIMING_NONCONTINUOUS_NONINVERTING_CLOCK,
3417*4882a593Smuzhiyun 	.qam_if        = S5H1411_IF_44000,
3418*4882a593Smuzhiyun 	.vsb_if        = S5H1411_IF_44000,
3419*4882a593Smuzhiyun 	.inversion     = S5H1411_INVERSION_OFF,
3420*4882a593Smuzhiyun 	.status_mode   = S5H1411_DEMODLOCKING
3421*4882a593Smuzhiyun };
3422*4882a593Smuzhiyun 
3423*4882a593Smuzhiyun /* Pinnacle PCTV HD Pro 801e GPIOs map:
3424*4882a593Smuzhiyun    GPIO0  - currently unknown
3425*4882a593Smuzhiyun    GPIO1  - xc5000 tuner reset
3426*4882a593Smuzhiyun    GPIO2  - CX25843 sleep
3427*4882a593Smuzhiyun    GPIO3  - currently unknown
3428*4882a593Smuzhiyun    GPIO4  - currently unknown
3429*4882a593Smuzhiyun    GPIO6  - currently unknown
3430*4882a593Smuzhiyun    GPIO7  - currently unknown
3431*4882a593Smuzhiyun    GPIO9  - currently unknown
3432*4882a593Smuzhiyun    GPIO10 - CX25843 reset
3433*4882a593Smuzhiyun  */
s5h1411_frontend_attach(struct dvb_usb_adapter * adap)3434*4882a593Smuzhiyun static int s5h1411_frontend_attach(struct dvb_usb_adapter *adap)
3435*4882a593Smuzhiyun {
3436*4882a593Smuzhiyun 	struct dib0700_state *st = adap->dev->priv;
3437*4882a593Smuzhiyun 
3438*4882a593Smuzhiyun 	/* Make use of the new i2c functions from FW 1.20 */
3439*4882a593Smuzhiyun 	st->fw_use_new_i2c_api = 1;
3440*4882a593Smuzhiyun 
3441*4882a593Smuzhiyun 	/* The s5h1411 requires the dib0700 to not be in master mode */
3442*4882a593Smuzhiyun 	st->disable_streaming_master_mode = 1;
3443*4882a593Smuzhiyun 
3444*4882a593Smuzhiyun 	/* All msleep values taken from Windows USB trace */
3445*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 0);
3446*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO3, GPIO_OUT, 0);
3447*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
3448*4882a593Smuzhiyun 	msleep(400);
3449*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
3450*4882a593Smuzhiyun 	msleep(60);
3451*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
3452*4882a593Smuzhiyun 	msleep(30);
3453*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
3454*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
3455*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
3456*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
3457*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO2, GPIO_OUT, 0);
3458*4882a593Smuzhiyun 	msleep(30);
3459*4882a593Smuzhiyun 
3460*4882a593Smuzhiyun 	/* Put the CX25843 to sleep for now since we're in digital mode */
3461*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO2, GPIO_OUT, 1);
3462*4882a593Smuzhiyun 
3463*4882a593Smuzhiyun 	/* GPIOs are initialized, do the attach */
3464*4882a593Smuzhiyun 	adap->fe_adap[0].fe = dvb_attach(s5h1411_attach, &pinnacle_801e_config,
3465*4882a593Smuzhiyun 			      &adap->dev->i2c_adap);
3466*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ? -ENODEV : 0;
3467*4882a593Smuzhiyun }
3468*4882a593Smuzhiyun 
dib0700_xc5000_tuner_callback(void * priv,int component,int command,int arg)3469*4882a593Smuzhiyun static int dib0700_xc5000_tuner_callback(void *priv, int component,
3470*4882a593Smuzhiyun 					 int command, int arg)
3471*4882a593Smuzhiyun {
3472*4882a593Smuzhiyun 	struct dvb_usb_adapter *adap = priv;
3473*4882a593Smuzhiyun 
3474*4882a593Smuzhiyun 	if (command == XC5000_TUNER_RESET) {
3475*4882a593Smuzhiyun 		/* Reset the tuner */
3476*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO1, GPIO_OUT, 0);
3477*4882a593Smuzhiyun 		msleep(10);
3478*4882a593Smuzhiyun 		dib0700_set_gpio(adap->dev, GPIO1, GPIO_OUT, 1);
3479*4882a593Smuzhiyun 		msleep(10);
3480*4882a593Smuzhiyun 	} else {
3481*4882a593Smuzhiyun 		err("xc5000: unknown tuner callback command: %d\n", command);
3482*4882a593Smuzhiyun 		return -EINVAL;
3483*4882a593Smuzhiyun 	}
3484*4882a593Smuzhiyun 
3485*4882a593Smuzhiyun 	return 0;
3486*4882a593Smuzhiyun }
3487*4882a593Smuzhiyun 
3488*4882a593Smuzhiyun static struct xc5000_config s5h1411_xc5000_tunerconfig = {
3489*4882a593Smuzhiyun 	.i2c_address      = 0x64,
3490*4882a593Smuzhiyun 	.if_khz           = 5380,
3491*4882a593Smuzhiyun };
3492*4882a593Smuzhiyun 
xc5000_tuner_attach(struct dvb_usb_adapter * adap)3493*4882a593Smuzhiyun static int xc5000_tuner_attach(struct dvb_usb_adapter *adap)
3494*4882a593Smuzhiyun {
3495*4882a593Smuzhiyun 	/* FIXME: generalize & move to common area */
3496*4882a593Smuzhiyun 	adap->fe_adap[0].fe->callback = dib0700_xc5000_tuner_callback;
3497*4882a593Smuzhiyun 
3498*4882a593Smuzhiyun 	return dvb_attach(xc5000_attach, adap->fe_adap[0].fe, &adap->dev->i2c_adap,
3499*4882a593Smuzhiyun 			  &s5h1411_xc5000_tunerconfig)
3500*4882a593Smuzhiyun 		== NULL ? -ENODEV : 0;
3501*4882a593Smuzhiyun }
3502*4882a593Smuzhiyun 
dib0700_xc4000_tuner_callback(void * priv,int component,int command,int arg)3503*4882a593Smuzhiyun static int dib0700_xc4000_tuner_callback(void *priv, int component,
3504*4882a593Smuzhiyun 					 int command, int arg)
3505*4882a593Smuzhiyun {
3506*4882a593Smuzhiyun 	struct dvb_usb_adapter *adap = priv;
3507*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
3508*4882a593Smuzhiyun 
3509*4882a593Smuzhiyun 	if (command == XC4000_TUNER_RESET) {
3510*4882a593Smuzhiyun 		/* Reset the tuner */
3511*4882a593Smuzhiyun 		state->dib7000p_ops.set_gpio(adap->fe_adap[0].fe, 8, 0, 0);
3512*4882a593Smuzhiyun 		msleep(10);
3513*4882a593Smuzhiyun 		state->dib7000p_ops.set_gpio(adap->fe_adap[0].fe, 8, 0, 1);
3514*4882a593Smuzhiyun 	} else {
3515*4882a593Smuzhiyun 		err("xc4000: unknown tuner callback command: %d\n", command);
3516*4882a593Smuzhiyun 		return -EINVAL;
3517*4882a593Smuzhiyun 	}
3518*4882a593Smuzhiyun 
3519*4882a593Smuzhiyun 	return 0;
3520*4882a593Smuzhiyun }
3521*4882a593Smuzhiyun 
3522*4882a593Smuzhiyun static struct dibx000_agc_config stk7700p_7000p_xc4000_agc_config = {
3523*4882a593Smuzhiyun 	.band_caps = BAND_UHF | BAND_VHF,
3524*4882a593Smuzhiyun 	.setup = 0x64,
3525*4882a593Smuzhiyun 	.inv_gain = 0x02c8,
3526*4882a593Smuzhiyun 	.time_stabiliz = 0x15,
3527*4882a593Smuzhiyun 	.alpha_level = 0x00,
3528*4882a593Smuzhiyun 	.thlock = 0x76,
3529*4882a593Smuzhiyun 	.wbd_inv = 0x01,
3530*4882a593Smuzhiyun 	.wbd_ref = 0x0b33,
3531*4882a593Smuzhiyun 	.wbd_sel = 0x00,
3532*4882a593Smuzhiyun 	.wbd_alpha = 0x02,
3533*4882a593Smuzhiyun 	.agc1_max = 0x00,
3534*4882a593Smuzhiyun 	.agc1_min = 0x00,
3535*4882a593Smuzhiyun 	.agc2_max = 0x9b26,
3536*4882a593Smuzhiyun 	.agc2_min = 0x26ca,
3537*4882a593Smuzhiyun 	.agc1_pt1 = 0x00,
3538*4882a593Smuzhiyun 	.agc1_pt2 = 0x00,
3539*4882a593Smuzhiyun 	.agc1_pt3 = 0x00,
3540*4882a593Smuzhiyun 	.agc1_slope1 = 0x00,
3541*4882a593Smuzhiyun 	.agc1_slope2 = 0x00,
3542*4882a593Smuzhiyun 	.agc2_pt1 = 0x00,
3543*4882a593Smuzhiyun 	.agc2_pt2 = 0x80,
3544*4882a593Smuzhiyun 	.agc2_slope1 = 0x1d,
3545*4882a593Smuzhiyun 	.agc2_slope2 = 0x1d,
3546*4882a593Smuzhiyun 	.alpha_mant = 0x11,
3547*4882a593Smuzhiyun 	.alpha_exp = 0x1b,
3548*4882a593Smuzhiyun 	.beta_mant = 0x17,
3549*4882a593Smuzhiyun 	.beta_exp = 0x33,
3550*4882a593Smuzhiyun 	.perform_agc_softsplit = 0x00,
3551*4882a593Smuzhiyun };
3552*4882a593Smuzhiyun 
3553*4882a593Smuzhiyun static struct dibx000_bandwidth_config stk7700p_xc4000_pll_config = {
3554*4882a593Smuzhiyun 	.internal = 60000,
3555*4882a593Smuzhiyun 	.sampling = 30000,
3556*4882a593Smuzhiyun 	.pll_prediv = 1,
3557*4882a593Smuzhiyun 	.pll_ratio = 8,
3558*4882a593Smuzhiyun 	.pll_range = 3,
3559*4882a593Smuzhiyun 	.pll_reset = 1,
3560*4882a593Smuzhiyun 	.pll_bypass = 0,
3561*4882a593Smuzhiyun 	.enable_refdiv = 0,
3562*4882a593Smuzhiyun 	.bypclk_div = 0,
3563*4882a593Smuzhiyun 	.IO_CLK_en_core = 1,
3564*4882a593Smuzhiyun 	.ADClkSrc = 1,
3565*4882a593Smuzhiyun 	.modulo = 0,
3566*4882a593Smuzhiyun 	.sad_cfg = (3 << 14) | (1 << 12) | 524, /* sad_cfg: refsel, sel, freq_15k */
3567*4882a593Smuzhiyun 	.ifreq = 39370534,
3568*4882a593Smuzhiyun 	.timf = 20452225,
3569*4882a593Smuzhiyun 	.xtal_hz = 30000000
3570*4882a593Smuzhiyun };
3571*4882a593Smuzhiyun 
3572*4882a593Smuzhiyun /* FIXME: none of these inputs are validated yet */
3573*4882a593Smuzhiyun static struct dib7000p_config pctv_340e_config = {
3574*4882a593Smuzhiyun 	.output_mpeg2_in_188_bytes = 1,
3575*4882a593Smuzhiyun 
3576*4882a593Smuzhiyun 	.agc_config_count = 1,
3577*4882a593Smuzhiyun 	.agc = &stk7700p_7000p_xc4000_agc_config,
3578*4882a593Smuzhiyun 	.bw  = &stk7700p_xc4000_pll_config,
3579*4882a593Smuzhiyun 
3580*4882a593Smuzhiyun 	.gpio_dir = DIB7000M_GPIO_DEFAULT_DIRECTIONS,
3581*4882a593Smuzhiyun 	.gpio_val = DIB7000M_GPIO_DEFAULT_VALUES,
3582*4882a593Smuzhiyun 	.gpio_pwm_pos = DIB7000M_GPIO_DEFAULT_PWM_POS,
3583*4882a593Smuzhiyun };
3584*4882a593Smuzhiyun 
3585*4882a593Smuzhiyun /* PCTV 340e GPIOs map:
3586*4882a593Smuzhiyun    dib0700:
3587*4882a593Smuzhiyun    GPIO2  - CX25843 sleep
3588*4882a593Smuzhiyun    GPIO3  - CS5340 reset
3589*4882a593Smuzhiyun    GPIO5  - IRD
3590*4882a593Smuzhiyun    GPIO6  - Power Supply
3591*4882a593Smuzhiyun    GPIO8  - LNA (1=off 0=on)
3592*4882a593Smuzhiyun    GPIO10 - CX25843 reset
3593*4882a593Smuzhiyun    dib7000:
3594*4882a593Smuzhiyun    GPIO8  - xc4000 reset
3595*4882a593Smuzhiyun  */
pctv340e_frontend_attach(struct dvb_usb_adapter * adap)3596*4882a593Smuzhiyun static int pctv340e_frontend_attach(struct dvb_usb_adapter *adap)
3597*4882a593Smuzhiyun {
3598*4882a593Smuzhiyun 	struct dib0700_state *st = adap->dev->priv;
3599*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
3600*4882a593Smuzhiyun 
3601*4882a593Smuzhiyun 	if (!dvb_attach(dib7000p_attach, &state->dib7000p_ops))
3602*4882a593Smuzhiyun 		return -ENODEV;
3603*4882a593Smuzhiyun 
3604*4882a593Smuzhiyun 	/* Power Supply on */
3605*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6,  GPIO_OUT, 0);
3606*4882a593Smuzhiyun 	msleep(50);
3607*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6,  GPIO_OUT, 1);
3608*4882a593Smuzhiyun 	msleep(100); /* Allow power supply to settle before probing */
3609*4882a593Smuzhiyun 
3610*4882a593Smuzhiyun 	/* cx25843 reset */
3611*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10,  GPIO_OUT, 0);
3612*4882a593Smuzhiyun 	msleep(1); /* cx25843 datasheet say 350us required */
3613*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10,  GPIO_OUT, 1);
3614*4882a593Smuzhiyun 
3615*4882a593Smuzhiyun 	/* LNA off for now */
3616*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO8,  GPIO_OUT, 1);
3617*4882a593Smuzhiyun 
3618*4882a593Smuzhiyun 	/* Put the CX25843 to sleep for now since we're in digital mode */
3619*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO2, GPIO_OUT, 1);
3620*4882a593Smuzhiyun 
3621*4882a593Smuzhiyun 	/* FIXME: not verified yet */
3622*4882a593Smuzhiyun 	dib0700_ctrl_clock(adap->dev, 72, 1);
3623*4882a593Smuzhiyun 
3624*4882a593Smuzhiyun 	msleep(500);
3625*4882a593Smuzhiyun 
3626*4882a593Smuzhiyun 	if (state->dib7000p_ops.dib7000pc_detection(&adap->dev->i2c_adap) == 0) {
3627*4882a593Smuzhiyun 		/* Demodulator not found for some reason? */
3628*4882a593Smuzhiyun 		dvb_detach(state->dib7000p_ops.set_wbd_ref);
3629*4882a593Smuzhiyun 		return -ENODEV;
3630*4882a593Smuzhiyun 	}
3631*4882a593Smuzhiyun 
3632*4882a593Smuzhiyun 	adap->fe_adap[0].fe = state->dib7000p_ops.init(&adap->dev->i2c_adap, 0x12,
3633*4882a593Smuzhiyun 			      &pctv_340e_config);
3634*4882a593Smuzhiyun 	st->is_dib7000pc = 1;
3635*4882a593Smuzhiyun 
3636*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ? -ENODEV : 0;
3637*4882a593Smuzhiyun }
3638*4882a593Smuzhiyun 
3639*4882a593Smuzhiyun static struct xc4000_config dib7000p_xc4000_tunerconfig = {
3640*4882a593Smuzhiyun 	.i2c_address	  = 0x61,
3641*4882a593Smuzhiyun 	.default_pm	  = 1,
3642*4882a593Smuzhiyun 	.dvb_amplitude	  = 0,
3643*4882a593Smuzhiyun 	.set_smoothedcvbs = 0,
3644*4882a593Smuzhiyun 	.if_khz		  = 5400
3645*4882a593Smuzhiyun };
3646*4882a593Smuzhiyun 
xc4000_tuner_attach(struct dvb_usb_adapter * adap)3647*4882a593Smuzhiyun static int xc4000_tuner_attach(struct dvb_usb_adapter *adap)
3648*4882a593Smuzhiyun {
3649*4882a593Smuzhiyun 	struct i2c_adapter *tun_i2c;
3650*4882a593Smuzhiyun 	struct dib0700_adapter_state *state = adap->priv;
3651*4882a593Smuzhiyun 
3652*4882a593Smuzhiyun 	/* The xc4000 is not on the main i2c bus */
3653*4882a593Smuzhiyun 	tun_i2c = state->dib7000p_ops.get_i2c_master(adap->fe_adap[0].fe,
3654*4882a593Smuzhiyun 					  DIBX000_I2C_INTERFACE_TUNER, 1);
3655*4882a593Smuzhiyun 	if (tun_i2c == NULL) {
3656*4882a593Smuzhiyun 		printk(KERN_ERR "Could not reach tuner i2c bus\n");
3657*4882a593Smuzhiyun 		return 0;
3658*4882a593Smuzhiyun 	}
3659*4882a593Smuzhiyun 
3660*4882a593Smuzhiyun 	/* Setup the reset callback */
3661*4882a593Smuzhiyun 	adap->fe_adap[0].fe->callback = dib0700_xc4000_tuner_callback;
3662*4882a593Smuzhiyun 
3663*4882a593Smuzhiyun 	return dvb_attach(xc4000_attach, adap->fe_adap[0].fe, tun_i2c,
3664*4882a593Smuzhiyun 			  &dib7000p_xc4000_tunerconfig)
3665*4882a593Smuzhiyun 		== NULL ? -ENODEV : 0;
3666*4882a593Smuzhiyun }
3667*4882a593Smuzhiyun 
3668*4882a593Smuzhiyun static struct lgdt3305_config hcw_lgdt3305_config = {
3669*4882a593Smuzhiyun 	.i2c_addr           = 0x0e,
3670*4882a593Smuzhiyun 	.mpeg_mode          = LGDT3305_MPEG_PARALLEL,
3671*4882a593Smuzhiyun 	.tpclk_edge         = LGDT3305_TPCLK_FALLING_EDGE,
3672*4882a593Smuzhiyun 	.tpvalid_polarity   = LGDT3305_TP_VALID_LOW,
3673*4882a593Smuzhiyun 	.deny_i2c_rptr      = 0,
3674*4882a593Smuzhiyun 	.spectral_inversion = 1,
3675*4882a593Smuzhiyun 	.qam_if_khz         = 6000,
3676*4882a593Smuzhiyun 	.vsb_if_khz         = 6000,
3677*4882a593Smuzhiyun 	.usref_8vsb         = 0x0500,
3678*4882a593Smuzhiyun };
3679*4882a593Smuzhiyun 
3680*4882a593Smuzhiyun static struct mxl5007t_config hcw_mxl5007t_config = {
3681*4882a593Smuzhiyun 	.xtal_freq_hz = MxL_XTAL_25_MHZ,
3682*4882a593Smuzhiyun 	.if_freq_hz = MxL_IF_6_MHZ,
3683*4882a593Smuzhiyun 	.invert_if = 1,
3684*4882a593Smuzhiyun };
3685*4882a593Smuzhiyun 
3686*4882a593Smuzhiyun /* TIGER-ATSC map:
3687*4882a593Smuzhiyun    GPIO0  - LNA_CTR  (H: LNA power enabled, L: LNA power disabled)
3688*4882a593Smuzhiyun    GPIO1  - ANT_SEL  (H: VPA, L: MCX)
3689*4882a593Smuzhiyun    GPIO4  - SCL2
3690*4882a593Smuzhiyun    GPIO6  - EN_TUNER
3691*4882a593Smuzhiyun    GPIO7  - SDA2
3692*4882a593Smuzhiyun    GPIO10 - DEM_RST
3693*4882a593Smuzhiyun 
3694*4882a593Smuzhiyun    MXL is behind LG's i2c repeater.  LG is on SCL2/SDA2 gpios on the DIB
3695*4882a593Smuzhiyun  */
lgdt3305_frontend_attach(struct dvb_usb_adapter * adap)3696*4882a593Smuzhiyun static int lgdt3305_frontend_attach(struct dvb_usb_adapter *adap)
3697*4882a593Smuzhiyun {
3698*4882a593Smuzhiyun 	struct dib0700_state *st = adap->dev->priv;
3699*4882a593Smuzhiyun 
3700*4882a593Smuzhiyun 	/* Make use of the new i2c functions from FW 1.20 */
3701*4882a593Smuzhiyun 	st->fw_use_new_i2c_api = 1;
3702*4882a593Smuzhiyun 
3703*4882a593Smuzhiyun 	st->disable_streaming_master_mode = 1;
3704*4882a593Smuzhiyun 
3705*4882a593Smuzhiyun 	/* fe power enable */
3706*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 0);
3707*4882a593Smuzhiyun 	msleep(30);
3708*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
3709*4882a593Smuzhiyun 	msleep(30);
3710*4882a593Smuzhiyun 
3711*4882a593Smuzhiyun 	/* demod reset */
3712*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
3713*4882a593Smuzhiyun 	msleep(30);
3714*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
3715*4882a593Smuzhiyun 	msleep(30);
3716*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
3717*4882a593Smuzhiyun 	msleep(30);
3718*4882a593Smuzhiyun 
3719*4882a593Smuzhiyun 	adap->fe_adap[0].fe = dvb_attach(lgdt3305_attach,
3720*4882a593Smuzhiyun 			      &hcw_lgdt3305_config,
3721*4882a593Smuzhiyun 			      &adap->dev->i2c_adap);
3722*4882a593Smuzhiyun 
3723*4882a593Smuzhiyun 	return adap->fe_adap[0].fe == NULL ? -ENODEV : 0;
3724*4882a593Smuzhiyun }
3725*4882a593Smuzhiyun 
mxl5007t_tuner_attach(struct dvb_usb_adapter * adap)3726*4882a593Smuzhiyun static int mxl5007t_tuner_attach(struct dvb_usb_adapter *adap)
3727*4882a593Smuzhiyun {
3728*4882a593Smuzhiyun 	return dvb_attach(mxl5007t_attach, adap->fe_adap[0].fe,
3729*4882a593Smuzhiyun 			  &adap->dev->i2c_adap, 0x60,
3730*4882a593Smuzhiyun 			  &hcw_mxl5007t_config) == NULL ? -ENODEV : 0;
3731*4882a593Smuzhiyun }
3732*4882a593Smuzhiyun 
xbox_one_attach(struct dvb_usb_adapter * adap)3733*4882a593Smuzhiyun static int xbox_one_attach(struct dvb_usb_adapter *adap)
3734*4882a593Smuzhiyun {
3735*4882a593Smuzhiyun 	struct dib0700_state *st = adap->dev->priv;
3736*4882a593Smuzhiyun 	struct i2c_client *client_demod, *client_tuner;
3737*4882a593Smuzhiyun 	struct dvb_usb_device *d = adap->dev;
3738*4882a593Smuzhiyun 	struct mn88472_config mn88472_config = { };
3739*4882a593Smuzhiyun 	struct tda18250_config tda18250_config;
3740*4882a593Smuzhiyun 	struct i2c_board_info info;
3741*4882a593Smuzhiyun 
3742*4882a593Smuzhiyun 	st->fw_use_new_i2c_api = 1;
3743*4882a593Smuzhiyun 	st->disable_streaming_master_mode = 1;
3744*4882a593Smuzhiyun 
3745*4882a593Smuzhiyun 	/* fe power enable */
3746*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 0);
3747*4882a593Smuzhiyun 	msleep(30);
3748*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
3749*4882a593Smuzhiyun 	msleep(30);
3750*4882a593Smuzhiyun 
3751*4882a593Smuzhiyun 	/* demod reset */
3752*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
3753*4882a593Smuzhiyun 	msleep(30);
3754*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
3755*4882a593Smuzhiyun 	msleep(30);
3756*4882a593Smuzhiyun 	dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
3757*4882a593Smuzhiyun 	msleep(30);
3758*4882a593Smuzhiyun 
3759*4882a593Smuzhiyun 	/* attach demod */
3760*4882a593Smuzhiyun 	mn88472_config.fe = &adap->fe_adap[0].fe;
3761*4882a593Smuzhiyun 	mn88472_config.i2c_wr_max = 22;
3762*4882a593Smuzhiyun 	mn88472_config.xtal = 20500000;
3763*4882a593Smuzhiyun 	mn88472_config.ts_mode = PARALLEL_TS_MODE;
3764*4882a593Smuzhiyun 	mn88472_config.ts_clock = FIXED_TS_CLOCK;
3765*4882a593Smuzhiyun 	memset(&info, 0, sizeof(struct i2c_board_info));
3766*4882a593Smuzhiyun 	strscpy(info.type, "mn88472", I2C_NAME_SIZE);
3767*4882a593Smuzhiyun 	info.addr = 0x18;
3768*4882a593Smuzhiyun 	info.platform_data = &mn88472_config;
3769*4882a593Smuzhiyun 	request_module(info.type);
3770*4882a593Smuzhiyun 	client_demod = i2c_new_client_device(&d->i2c_adap, &info);
3771*4882a593Smuzhiyun 	if (!i2c_client_has_driver(client_demod))
3772*4882a593Smuzhiyun 		goto fail_demod_device;
3773*4882a593Smuzhiyun 	if (!try_module_get(client_demod->dev.driver->owner))
3774*4882a593Smuzhiyun 		goto fail_demod_module;
3775*4882a593Smuzhiyun 
3776*4882a593Smuzhiyun 	st->i2c_client_demod = client_demod;
3777*4882a593Smuzhiyun 
3778*4882a593Smuzhiyun 	adap->fe_adap[0].fe = mn88472_config.get_dvb_frontend(client_demod);
3779*4882a593Smuzhiyun 
3780*4882a593Smuzhiyun 	/* attach tuner */
3781*4882a593Smuzhiyun 	memset(&tda18250_config, 0, sizeof(tda18250_config));
3782*4882a593Smuzhiyun 	tda18250_config.if_dvbt_6 = 3950;
3783*4882a593Smuzhiyun 	tda18250_config.if_dvbt_7 = 4450;
3784*4882a593Smuzhiyun 	tda18250_config.if_dvbt_8 = 4950;
3785*4882a593Smuzhiyun 	tda18250_config.if_dvbc_6 = 4950;
3786*4882a593Smuzhiyun 	tda18250_config.if_dvbc_8 = 4950;
3787*4882a593Smuzhiyun 	tda18250_config.if_atsc = 4079;
3788*4882a593Smuzhiyun 	tda18250_config.loopthrough = true;
3789*4882a593Smuzhiyun 	tda18250_config.xtal_freq = TDA18250_XTAL_FREQ_27MHZ;
3790*4882a593Smuzhiyun 	tda18250_config.fe = adap->fe_adap[0].fe;
3791*4882a593Smuzhiyun 
3792*4882a593Smuzhiyun 	memset(&info, 0, sizeof(struct i2c_board_info));
3793*4882a593Smuzhiyun 	strscpy(info.type, "tda18250", I2C_NAME_SIZE);
3794*4882a593Smuzhiyun 	info.addr = 0x60;
3795*4882a593Smuzhiyun 	info.platform_data = &tda18250_config;
3796*4882a593Smuzhiyun 
3797*4882a593Smuzhiyun 	request_module(info.type);
3798*4882a593Smuzhiyun 	client_tuner = i2c_new_client_device(&adap->dev->i2c_adap, &info);
3799*4882a593Smuzhiyun 	if (!i2c_client_has_driver(client_tuner))
3800*4882a593Smuzhiyun 		goto fail_tuner_device;
3801*4882a593Smuzhiyun 	if (!try_module_get(client_tuner->dev.driver->owner))
3802*4882a593Smuzhiyun 		goto fail_tuner_module;
3803*4882a593Smuzhiyun 
3804*4882a593Smuzhiyun 	st->i2c_client_tuner = client_tuner;
3805*4882a593Smuzhiyun 	return 0;
3806*4882a593Smuzhiyun 
3807*4882a593Smuzhiyun fail_tuner_module:
3808*4882a593Smuzhiyun 	i2c_unregister_device(client_tuner);
3809*4882a593Smuzhiyun fail_tuner_device:
3810*4882a593Smuzhiyun 	module_put(client_demod->dev.driver->owner);
3811*4882a593Smuzhiyun fail_demod_module:
3812*4882a593Smuzhiyun 	i2c_unregister_device(client_demod);
3813*4882a593Smuzhiyun fail_demod_device:
3814*4882a593Smuzhiyun 	return -ENODEV;
3815*4882a593Smuzhiyun }
3816*4882a593Smuzhiyun 
3817*4882a593Smuzhiyun 
3818*4882a593Smuzhiyun /* DVB-USB and USB stuff follows */
3819*4882a593Smuzhiyun struct usb_device_id dib0700_usb_id_table[] = {
3820*4882a593Smuzhiyun /* 0 */	{ USB_DEVICE(USB_VID_DIBCOM,    USB_PID_DIBCOM_STK7700P) },
3821*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_DIBCOM,    USB_PID_DIBCOM_STK7700P_PC) },
3822*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_NOVA_T_500) },
3823*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_NOVA_T_500_2) },
3824*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_NOVA_T_STICK) },
3825*4882a593Smuzhiyun /* 5 */	{ USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_VOLAR) },
3826*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_COMPRO,    USB_PID_COMPRO_VIDEOMATE_U500) },
3827*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_UNIWILL,   USB_PID_UNIWILL_STK7700P) },
3828*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_LEADTEK,   USB_PID_WINFAST_DTV_DONGLE_STK7700P) },
3829*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_NOVA_T_STICK_2) },
3830*4882a593Smuzhiyun /* 10 */{ USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_VOLAR_2) },
3831*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_PINNACLE,  USB_PID_PINNACLE_PCTV2000E) },
3832*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_TERRATEC,
3833*4882a593Smuzhiyun 			USB_PID_TERRATEC_CINERGY_DT_XS_DIVERSITY) },
3834*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_NOVA_TD_STICK) },
3835*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_DIBCOM,    USB_PID_DIBCOM_STK7700D) },
3836*4882a593Smuzhiyun /* 15 */{ USB_DEVICE(USB_VID_DIBCOM,    USB_PID_DIBCOM_STK7070P) },
3837*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_PINNACLE,  USB_PID_PINNACLE_PCTV_DVB_T_FLASH) },
3838*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_DIBCOM,    USB_PID_DIBCOM_STK7070PD) },
3839*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_PINNACLE,
3840*4882a593Smuzhiyun 			USB_PID_PINNACLE_PCTV_DUAL_DIVERSITY_DVB_T) },
3841*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_COMPRO,    USB_PID_COMPRO_VIDEOMATE_U500_PC) },
3842*4882a593Smuzhiyun /* 20 */{ USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_EXPRESS) },
3843*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_GIGABYTE,  USB_PID_GIGABYTE_U7000) },
3844*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_ULTIMA_ELECTRONIC, USB_PID_ARTEC_T14BR) },
3845*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_ASUS,      USB_PID_ASUS_U3000) },
3846*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_ASUS,      USB_PID_ASUS_U3100) },
3847*4882a593Smuzhiyun /* 25 */{ USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_NOVA_T_STICK_3) },
3848*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_MYTV_T) },
3849*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_TERRATEC,  USB_PID_TERRATEC_CINERGY_HT_USB_XE) },
3850*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_PINNACLE,	USB_PID_PINNACLE_EXPRESSCARD_320CX) },
3851*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_PINNACLE,	USB_PID_PINNACLE_PCTV72E) },
3852*4882a593Smuzhiyun /* 30 */{ USB_DEVICE(USB_VID_PINNACLE,	USB_PID_PINNACLE_PCTV73E) },
3853*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_YUAN,	USB_PID_YUAN_EC372S) },
3854*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_TERRATEC,	USB_PID_TERRATEC_CINERGY_HT_EXPRESS) },
3855*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_TERRATEC,	USB_PID_TERRATEC_CINERGY_T_XXS) },
3856*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_LEADTEK,   USB_PID_WINFAST_DTV_DONGLE_STK7700P_2) },
3857*4882a593Smuzhiyun /* 35 */{ USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_NOVA_TD_STICK_52009) },
3858*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_NOVA_T_500_3) },
3859*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_GIGABYTE,  USB_PID_GIGABYTE_U8000) },
3860*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_YUAN,      USB_PID_YUAN_STK7700PH) },
3861*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_ASUS,	USB_PID_ASUS_U3000H) },
3862*4882a593Smuzhiyun /* 40 */{ USB_DEVICE(USB_VID_PINNACLE,  USB_PID_PINNACLE_PCTV801E) },
3863*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_PINNACLE,  USB_PID_PINNACLE_PCTV801E_SE) },
3864*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_TERRATEC,	USB_PID_TERRATEC_CINERGY_T_EXPRESS) },
3865*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_TERRATEC,
3866*4882a593Smuzhiyun 			USB_PID_TERRATEC_CINERGY_DT_XS_DIVERSITY_2) },
3867*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_SONY,	USB_PID_SONY_PLAYTV) },
3868*4882a593Smuzhiyun /* 45 */{ USB_DEVICE(USB_VID_YUAN,      USB_PID_YUAN_PD378S) },
3869*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_TIGER_ATSC) },
3870*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_TIGER_ATSC_B210) },
3871*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_YUAN,	USB_PID_YUAN_MC770) },
3872*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_ELGATO,	USB_PID_ELGATO_EYETV_DTT) },
3873*4882a593Smuzhiyun /* 50 */{ USB_DEVICE(USB_VID_ELGATO,	USB_PID_ELGATO_EYETV_DTT_Dlx) },
3874*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_LEADTEK,   USB_PID_WINFAST_DTV_DONGLE_H) },
3875*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_TERRATEC,	USB_PID_TERRATEC_T3) },
3876*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_TERRATEC,	USB_PID_TERRATEC_T5) },
3877*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_YUAN,      USB_PID_YUAN_STK7700D) },
3878*4882a593Smuzhiyun /* 55 */{ USB_DEVICE(USB_VID_YUAN,	USB_PID_YUAN_STK7700D_2) },
3879*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_PINNACLE,	USB_PID_PINNACLE_PCTV73A) },
3880*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_PCTV,	USB_PID_PINNACLE_PCTV73ESE) },
3881*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_PCTV,	USB_PID_PINNACLE_PCTV282E) },
3882*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_DIBCOM,	USB_PID_DIBCOM_STK7770P) },
3883*4882a593Smuzhiyun /* 60 */{ USB_DEVICE(USB_VID_TERRATEC,	USB_PID_TERRATEC_CINERGY_T_XXS_2) },
3884*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_DIBCOM,    USB_PID_DIBCOM_STK807XPVR) },
3885*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_DIBCOM,    USB_PID_DIBCOM_STK807XP) },
3886*4882a593Smuzhiyun 	{ USB_DEVICE_VER(USB_VID_PIXELVIEW, USB_PID_PIXELVIEW_SBTVD, 0x000, 0x3f00) },
3887*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_EVOLUTEPC, USB_PID_TVWAY_PLUS) },
3888*4882a593Smuzhiyun /* 65 */{ USB_DEVICE(USB_VID_PINNACLE,	USB_PID_PINNACLE_PCTV73ESE) },
3889*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_PINNACLE,	USB_PID_PINNACLE_PCTV282E) },
3890*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_DIBCOM,    USB_PID_DIBCOM_STK8096GP) },
3891*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_ELGATO,    USB_PID_ELGATO_EYETV_DIVERSITY) },
3892*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_DIBCOM,    USB_PID_DIBCOM_NIM9090M) },
3893*4882a593Smuzhiyun /* 70 */{ USB_DEVICE(USB_VID_DIBCOM,    USB_PID_DIBCOM_NIM8096MD) },
3894*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_DIBCOM,    USB_PID_DIBCOM_NIM9090MD) },
3895*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_DIBCOM,    USB_PID_DIBCOM_NIM7090) },
3896*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_DIBCOM,    USB_PID_DIBCOM_TFE7090PVR) },
3897*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_TECHNISAT, USB_PID_TECHNISAT_AIRSTAR_TELESTICK_2) },
3898*4882a593Smuzhiyun /* 75 */{ USB_DEVICE(USB_VID_MEDION,    USB_PID_CREATIX_CTX1921) },
3899*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_PINNACLE,  USB_PID_PINNACLE_PCTV340E) },
3900*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_PINNACLE,  USB_PID_PINNACLE_PCTV340E_SE) },
3901*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_DIBCOM,    USB_PID_DIBCOM_TFE7790P) },
3902*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_DIBCOM,    USB_PID_DIBCOM_TFE8096P) },
3903*4882a593Smuzhiyun /* 80 */{ USB_DEVICE(USB_VID_ELGATO,	USB_PID_ELGATO_EYETV_DTT_2) },
3904*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_PCTV,      USB_PID_PCTV_2002E) },
3905*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_PCTV,      USB_PID_PCTV_2002E_SE) },
3906*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_PCTV,      USB_PID_DIBCOM_STK8096PVR) },
3907*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_DIBCOM,    USB_PID_DIBCOM_STK8096PVR) },
3908*4882a593Smuzhiyun /* 85 */{ USB_DEVICE(USB_VID_HAMA,	USB_PID_HAMA_DVBT_HYBRID) },
3909*4882a593Smuzhiyun 	{ USB_DEVICE(USB_VID_MICROSOFT,	USB_PID_XBOX_ONE_TUNER) },
3910*4882a593Smuzhiyun 	{ 0 }		/* Terminating entry */
3911*4882a593Smuzhiyun };
3912*4882a593Smuzhiyun MODULE_DEVICE_TABLE(usb, dib0700_usb_id_table);
3913*4882a593Smuzhiyun 
3914*4882a593Smuzhiyun #define DIB0700_DEFAULT_DEVICE_PROPERTIES \
3915*4882a593Smuzhiyun 	.caps              = DVB_USB_IS_AN_I2C_ADAPTER, \
3916*4882a593Smuzhiyun 	.usb_ctrl          = DEVICE_SPECIFIC, \
3917*4882a593Smuzhiyun 	.firmware          = "dvb-usb-dib0700-1.20.fw", \
3918*4882a593Smuzhiyun 	.download_firmware = dib0700_download_firmware, \
3919*4882a593Smuzhiyun 	.no_reconnect      = 1, \
3920*4882a593Smuzhiyun 	.size_of_priv      = sizeof(struct dib0700_state), \
3921*4882a593Smuzhiyun 	.i2c_algo          = &dib0700_i2c_algo, \
3922*4882a593Smuzhiyun 	.identify_state    = dib0700_identify_state
3923*4882a593Smuzhiyun 
3924*4882a593Smuzhiyun #define DIB0700_DEFAULT_STREAMING_CONFIG(ep) \
3925*4882a593Smuzhiyun 	.streaming_ctrl   = dib0700_streaming_ctrl, \
3926*4882a593Smuzhiyun 	.stream = { \
3927*4882a593Smuzhiyun 		.type = USB_BULK, \
3928*4882a593Smuzhiyun 		.count = 4, \
3929*4882a593Smuzhiyun 		.endpoint = ep, \
3930*4882a593Smuzhiyun 		.u = { \
3931*4882a593Smuzhiyun 			.bulk = { \
3932*4882a593Smuzhiyun 				.buffersize = 39480, \
3933*4882a593Smuzhiyun 			} \
3934*4882a593Smuzhiyun 		} \
3935*4882a593Smuzhiyun 	}
3936*4882a593Smuzhiyun 
3937*4882a593Smuzhiyun #define DIB0700_NUM_FRONTENDS(n) \
3938*4882a593Smuzhiyun 	.num_frontends = n, \
3939*4882a593Smuzhiyun 	.size_of_priv     = sizeof(struct dib0700_adapter_state)
3940*4882a593Smuzhiyun 
3941*4882a593Smuzhiyun struct dvb_usb_device_properties dib0700_devices[] = {
3942*4882a593Smuzhiyun 	{
3943*4882a593Smuzhiyun 		DIB0700_DEFAULT_DEVICE_PROPERTIES,
3944*4882a593Smuzhiyun 
3945*4882a593Smuzhiyun 		.num_adapters = 1,
3946*4882a593Smuzhiyun 		.adapter = {
3947*4882a593Smuzhiyun 			{
3948*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
3949*4882a593Smuzhiyun 			.fe = {{
3950*4882a593Smuzhiyun 				.caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
3951*4882a593Smuzhiyun 				.pid_filter_count = 32,
3952*4882a593Smuzhiyun 				.pid_filter       = stk7700p_pid_filter,
3953*4882a593Smuzhiyun 				.pid_filter_ctrl  = stk7700p_pid_filter_ctrl,
3954*4882a593Smuzhiyun 				.frontend_attach  = stk7700p_frontend_attach,
3955*4882a593Smuzhiyun 				.tuner_attach     = stk7700p_tuner_attach,
3956*4882a593Smuzhiyun 
3957*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
3958*4882a593Smuzhiyun 			}},
3959*4882a593Smuzhiyun 			},
3960*4882a593Smuzhiyun 		},
3961*4882a593Smuzhiyun 
3962*4882a593Smuzhiyun 		.num_device_descs = 8,
3963*4882a593Smuzhiyun 		.devices = {
3964*4882a593Smuzhiyun 			{   "DiBcom STK7700P reference design",
3965*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[0], &dib0700_usb_id_table[1] },
3966*4882a593Smuzhiyun 				{ NULL },
3967*4882a593Smuzhiyun 			},
3968*4882a593Smuzhiyun 			{   "Hauppauge Nova-T Stick",
3969*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[4], &dib0700_usb_id_table[9], NULL },
3970*4882a593Smuzhiyun 				{ NULL },
3971*4882a593Smuzhiyun 			},
3972*4882a593Smuzhiyun 			{   "AVerMedia AVerTV DVB-T Volar",
3973*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[5], &dib0700_usb_id_table[10] },
3974*4882a593Smuzhiyun 				{ NULL },
3975*4882a593Smuzhiyun 			},
3976*4882a593Smuzhiyun 			{   "Compro Videomate U500",
3977*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[6], &dib0700_usb_id_table[19] },
3978*4882a593Smuzhiyun 				{ NULL },
3979*4882a593Smuzhiyun 			},
3980*4882a593Smuzhiyun 			{   "Uniwill STK7700P based (Hama and others)",
3981*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[7], NULL },
3982*4882a593Smuzhiyun 				{ NULL },
3983*4882a593Smuzhiyun 			},
3984*4882a593Smuzhiyun 			{   "Leadtek Winfast DTV Dongle (STK7700P based)",
3985*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[8], &dib0700_usb_id_table[34] },
3986*4882a593Smuzhiyun 				{ NULL },
3987*4882a593Smuzhiyun 			},
3988*4882a593Smuzhiyun 			{   "AVerMedia AVerTV DVB-T Express",
3989*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[20] },
3990*4882a593Smuzhiyun 				{ NULL },
3991*4882a593Smuzhiyun 			},
3992*4882a593Smuzhiyun 			{   "Gigabyte U7000",
3993*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[21], NULL },
3994*4882a593Smuzhiyun 				{ NULL },
3995*4882a593Smuzhiyun 			}
3996*4882a593Smuzhiyun 		},
3997*4882a593Smuzhiyun 
3998*4882a593Smuzhiyun 		.rc.core = {
3999*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4000*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
4001*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4002*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4003*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4004*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4005*4882a593Smuzhiyun 			.change_protocol  = dib0700_change_protocol,
4006*4882a593Smuzhiyun 		},
4007*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4008*4882a593Smuzhiyun 
4009*4882a593Smuzhiyun 		.num_adapters = 2,
4010*4882a593Smuzhiyun 		.adapter = {
4011*4882a593Smuzhiyun 			{
4012*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4013*4882a593Smuzhiyun 			.fe = {{
4014*4882a593Smuzhiyun 				.frontend_attach  = bristol_frontend_attach,
4015*4882a593Smuzhiyun 				.tuner_attach     = bristol_tuner_attach,
4016*4882a593Smuzhiyun 
4017*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4018*4882a593Smuzhiyun 			}},
4019*4882a593Smuzhiyun 			}, {
4020*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4021*4882a593Smuzhiyun 			.fe = {{
4022*4882a593Smuzhiyun 				.frontend_attach  = bristol_frontend_attach,
4023*4882a593Smuzhiyun 				.tuner_attach     = bristol_tuner_attach,
4024*4882a593Smuzhiyun 
4025*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x03),
4026*4882a593Smuzhiyun 			}},
4027*4882a593Smuzhiyun 			}
4028*4882a593Smuzhiyun 		},
4029*4882a593Smuzhiyun 
4030*4882a593Smuzhiyun 		.num_device_descs = 1,
4031*4882a593Smuzhiyun 		.devices = {
4032*4882a593Smuzhiyun 			{   "Hauppauge Nova-T 500 Dual DVB-T",
4033*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[2], &dib0700_usb_id_table[3], NULL },
4034*4882a593Smuzhiyun 				{ NULL },
4035*4882a593Smuzhiyun 			},
4036*4882a593Smuzhiyun 		},
4037*4882a593Smuzhiyun 
4038*4882a593Smuzhiyun 		.rc.core = {
4039*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4040*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
4041*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4042*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4043*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4044*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4045*4882a593Smuzhiyun 			.change_protocol = dib0700_change_protocol,
4046*4882a593Smuzhiyun 		},
4047*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4048*4882a593Smuzhiyun 
4049*4882a593Smuzhiyun 		.num_adapters = 2,
4050*4882a593Smuzhiyun 		.adapter = {
4051*4882a593Smuzhiyun 			{
4052*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4053*4882a593Smuzhiyun 			.fe = {{
4054*4882a593Smuzhiyun 				.caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4055*4882a593Smuzhiyun 				.pid_filter_count = 32,
4056*4882a593Smuzhiyun 				.pid_filter       = stk70x0p_pid_filter,
4057*4882a593Smuzhiyun 				.pid_filter_ctrl  = stk70x0p_pid_filter_ctrl,
4058*4882a593Smuzhiyun 				.frontend_attach  = stk7700d_frontend_attach,
4059*4882a593Smuzhiyun 				.tuner_attach     = stk7700d_tuner_attach,
4060*4882a593Smuzhiyun 
4061*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4062*4882a593Smuzhiyun 			}},
4063*4882a593Smuzhiyun 			}, {
4064*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4065*4882a593Smuzhiyun 			.fe = {{
4066*4882a593Smuzhiyun 				.caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4067*4882a593Smuzhiyun 				.pid_filter_count = 32,
4068*4882a593Smuzhiyun 				.pid_filter       = stk70x0p_pid_filter,
4069*4882a593Smuzhiyun 				.pid_filter_ctrl  = stk70x0p_pid_filter_ctrl,
4070*4882a593Smuzhiyun 				.frontend_attach  = stk7700d_frontend_attach,
4071*4882a593Smuzhiyun 				.tuner_attach     = stk7700d_tuner_attach,
4072*4882a593Smuzhiyun 
4073*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x03),
4074*4882a593Smuzhiyun 			}},
4075*4882a593Smuzhiyun 			}
4076*4882a593Smuzhiyun 		},
4077*4882a593Smuzhiyun 
4078*4882a593Smuzhiyun 		.num_device_descs = 5,
4079*4882a593Smuzhiyun 		.devices = {
4080*4882a593Smuzhiyun 			{   "Pinnacle PCTV 2000e",
4081*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[11], NULL },
4082*4882a593Smuzhiyun 				{ NULL },
4083*4882a593Smuzhiyun 			},
4084*4882a593Smuzhiyun 			{   "Terratec Cinergy DT XS Diversity",
4085*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[12], NULL },
4086*4882a593Smuzhiyun 				{ NULL },
4087*4882a593Smuzhiyun 			},
4088*4882a593Smuzhiyun 			{   "Hauppauge Nova-TD Stick/Elgato Eye-TV Diversity",
4089*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[13], NULL },
4090*4882a593Smuzhiyun 				{ NULL },
4091*4882a593Smuzhiyun 			},
4092*4882a593Smuzhiyun 			{   "DiBcom STK7700D reference design",
4093*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[14], NULL },
4094*4882a593Smuzhiyun 				{ NULL },
4095*4882a593Smuzhiyun 			},
4096*4882a593Smuzhiyun 			{   "YUAN High-Tech DiBcom STK7700D",
4097*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[55], NULL },
4098*4882a593Smuzhiyun 				{ NULL },
4099*4882a593Smuzhiyun 			},
4100*4882a593Smuzhiyun 
4101*4882a593Smuzhiyun 		},
4102*4882a593Smuzhiyun 
4103*4882a593Smuzhiyun 		.rc.core = {
4104*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4105*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
4106*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4107*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4108*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4109*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4110*4882a593Smuzhiyun 			.change_protocol = dib0700_change_protocol,
4111*4882a593Smuzhiyun 		},
4112*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4113*4882a593Smuzhiyun 
4114*4882a593Smuzhiyun 		.num_adapters = 1,
4115*4882a593Smuzhiyun 		.adapter = {
4116*4882a593Smuzhiyun 			{
4117*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4118*4882a593Smuzhiyun 			.fe = {{
4119*4882a593Smuzhiyun 				.caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4120*4882a593Smuzhiyun 				.pid_filter_count = 32,
4121*4882a593Smuzhiyun 				.pid_filter       = stk70x0p_pid_filter,
4122*4882a593Smuzhiyun 				.pid_filter_ctrl  = stk70x0p_pid_filter_ctrl,
4123*4882a593Smuzhiyun 				.frontend_attach  = stk7700P2_frontend_attach,
4124*4882a593Smuzhiyun 				.tuner_attach     = stk7700d_tuner_attach,
4125*4882a593Smuzhiyun 
4126*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4127*4882a593Smuzhiyun 			}},
4128*4882a593Smuzhiyun 			},
4129*4882a593Smuzhiyun 		},
4130*4882a593Smuzhiyun 
4131*4882a593Smuzhiyun 		.num_device_descs = 3,
4132*4882a593Smuzhiyun 		.devices = {
4133*4882a593Smuzhiyun 			{   "ASUS My Cinema U3000 Mini DVBT Tuner",
4134*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[23], NULL },
4135*4882a593Smuzhiyun 				{ NULL },
4136*4882a593Smuzhiyun 			},
4137*4882a593Smuzhiyun 			{   "Yuan EC372S",
4138*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[31], NULL },
4139*4882a593Smuzhiyun 				{ NULL },
4140*4882a593Smuzhiyun 			},
4141*4882a593Smuzhiyun 			{   "Terratec Cinergy T Express",
4142*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[42], NULL },
4143*4882a593Smuzhiyun 				{ NULL },
4144*4882a593Smuzhiyun 			}
4145*4882a593Smuzhiyun 		},
4146*4882a593Smuzhiyun 
4147*4882a593Smuzhiyun 		.rc.core = {
4148*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4149*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
4150*4882a593Smuzhiyun 			.module_name	  = "dib0700",
4151*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4152*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4153*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4154*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4155*4882a593Smuzhiyun 			.change_protocol = dib0700_change_protocol,
4156*4882a593Smuzhiyun 		},
4157*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4158*4882a593Smuzhiyun 
4159*4882a593Smuzhiyun 		.num_adapters = 1,
4160*4882a593Smuzhiyun 		.adapter = {
4161*4882a593Smuzhiyun 			{
4162*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4163*4882a593Smuzhiyun 			.fe = {{
4164*4882a593Smuzhiyun 				.caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4165*4882a593Smuzhiyun 				.pid_filter_count = 32,
4166*4882a593Smuzhiyun 				.pid_filter       = stk70x0p_pid_filter,
4167*4882a593Smuzhiyun 				.pid_filter_ctrl  = stk70x0p_pid_filter_ctrl,
4168*4882a593Smuzhiyun 				.frontend_attach  = stk7070p_frontend_attach,
4169*4882a593Smuzhiyun 				.tuner_attach     = dib7070p_tuner_attach,
4170*4882a593Smuzhiyun 
4171*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4172*4882a593Smuzhiyun 			}},
4173*4882a593Smuzhiyun 			},
4174*4882a593Smuzhiyun 		},
4175*4882a593Smuzhiyun 
4176*4882a593Smuzhiyun 		.num_device_descs = 12,
4177*4882a593Smuzhiyun 		.devices = {
4178*4882a593Smuzhiyun 			{   "DiBcom STK7070P reference design",
4179*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[15], NULL },
4180*4882a593Smuzhiyun 				{ NULL },
4181*4882a593Smuzhiyun 			},
4182*4882a593Smuzhiyun 			{   "Pinnacle PCTV DVB-T Flash Stick",
4183*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[16], NULL },
4184*4882a593Smuzhiyun 				{ NULL },
4185*4882a593Smuzhiyun 			},
4186*4882a593Smuzhiyun 			{   "Artec T14BR DVB-T",
4187*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[22], NULL },
4188*4882a593Smuzhiyun 				{ NULL },
4189*4882a593Smuzhiyun 			},
4190*4882a593Smuzhiyun 			{   "ASUS My Cinema U3100 Mini DVBT Tuner",
4191*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[24], NULL },
4192*4882a593Smuzhiyun 				{ NULL },
4193*4882a593Smuzhiyun 			},
4194*4882a593Smuzhiyun 			{   "Hauppauge Nova-T Stick",
4195*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[25], NULL },
4196*4882a593Smuzhiyun 				{ NULL },
4197*4882a593Smuzhiyun 			},
4198*4882a593Smuzhiyun 			{   "Hauppauge Nova-T MyTV.t",
4199*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[26], NULL },
4200*4882a593Smuzhiyun 				{ NULL },
4201*4882a593Smuzhiyun 			},
4202*4882a593Smuzhiyun 			{   "Pinnacle PCTV 72e",
4203*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[29], NULL },
4204*4882a593Smuzhiyun 				{ NULL },
4205*4882a593Smuzhiyun 			},
4206*4882a593Smuzhiyun 			{   "Pinnacle PCTV 73e",
4207*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[30], NULL },
4208*4882a593Smuzhiyun 				{ NULL },
4209*4882a593Smuzhiyun 			},
4210*4882a593Smuzhiyun 			{   "Elgato EyeTV DTT",
4211*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[49], NULL },
4212*4882a593Smuzhiyun 				{ NULL },
4213*4882a593Smuzhiyun 			},
4214*4882a593Smuzhiyun 			{   "Yuan PD378S",
4215*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[45], NULL },
4216*4882a593Smuzhiyun 				{ NULL },
4217*4882a593Smuzhiyun 			},
4218*4882a593Smuzhiyun 			{   "Elgato EyeTV Dtt Dlx PD378S",
4219*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[50], NULL },
4220*4882a593Smuzhiyun 				{ NULL },
4221*4882a593Smuzhiyun 			},
4222*4882a593Smuzhiyun 			{   "Elgato EyeTV DTT rev. 2",
4223*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[80], NULL },
4224*4882a593Smuzhiyun 				{ NULL },
4225*4882a593Smuzhiyun 			},
4226*4882a593Smuzhiyun 		},
4227*4882a593Smuzhiyun 
4228*4882a593Smuzhiyun 		.rc.core = {
4229*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4230*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
4231*4882a593Smuzhiyun 			.module_name	  = "dib0700",
4232*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4233*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4234*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4235*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4236*4882a593Smuzhiyun 			.change_protocol  = dib0700_change_protocol,
4237*4882a593Smuzhiyun 		},
4238*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4239*4882a593Smuzhiyun 
4240*4882a593Smuzhiyun 		.num_adapters = 1,
4241*4882a593Smuzhiyun 		.adapter = {
4242*4882a593Smuzhiyun 			{
4243*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4244*4882a593Smuzhiyun 			.fe = {{
4245*4882a593Smuzhiyun 				.caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4246*4882a593Smuzhiyun 				.pid_filter_count = 32,
4247*4882a593Smuzhiyun 				.pid_filter       = stk70x0p_pid_filter,
4248*4882a593Smuzhiyun 				.pid_filter_ctrl  = stk70x0p_pid_filter_ctrl,
4249*4882a593Smuzhiyun 				.frontend_attach  = stk7070p_frontend_attach,
4250*4882a593Smuzhiyun 				.tuner_attach     = dib7070p_tuner_attach,
4251*4882a593Smuzhiyun 
4252*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4253*4882a593Smuzhiyun 			}},
4254*4882a593Smuzhiyun 			},
4255*4882a593Smuzhiyun 		},
4256*4882a593Smuzhiyun 
4257*4882a593Smuzhiyun 		.num_device_descs = 3,
4258*4882a593Smuzhiyun 		.devices = {
4259*4882a593Smuzhiyun 			{   "Pinnacle PCTV 73A",
4260*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[56], NULL },
4261*4882a593Smuzhiyun 				{ NULL },
4262*4882a593Smuzhiyun 			},
4263*4882a593Smuzhiyun 			{   "Pinnacle PCTV 73e SE",
4264*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[57], &dib0700_usb_id_table[65], NULL },
4265*4882a593Smuzhiyun 				{ NULL },
4266*4882a593Smuzhiyun 			},
4267*4882a593Smuzhiyun 			{   "Pinnacle PCTV 282e",
4268*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[58], &dib0700_usb_id_table[66], NULL },
4269*4882a593Smuzhiyun 				{ NULL },
4270*4882a593Smuzhiyun 			},
4271*4882a593Smuzhiyun 		},
4272*4882a593Smuzhiyun 
4273*4882a593Smuzhiyun 		.rc.core = {
4274*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4275*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
4276*4882a593Smuzhiyun 			.module_name	  = "dib0700",
4277*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4278*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4279*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4280*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4281*4882a593Smuzhiyun 			.change_protocol  = dib0700_change_protocol,
4282*4882a593Smuzhiyun 		},
4283*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4284*4882a593Smuzhiyun 
4285*4882a593Smuzhiyun 		.num_adapters = 2,
4286*4882a593Smuzhiyun 		.adapter = {
4287*4882a593Smuzhiyun 			{
4288*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4289*4882a593Smuzhiyun 			.fe = {{
4290*4882a593Smuzhiyun 				.caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4291*4882a593Smuzhiyun 				.pid_filter_count = 32,
4292*4882a593Smuzhiyun 				.pid_filter       = stk70x0p_pid_filter,
4293*4882a593Smuzhiyun 				.pid_filter_ctrl  = stk70x0p_pid_filter_ctrl,
4294*4882a593Smuzhiyun 				.frontend_attach  = novatd_frontend_attach,
4295*4882a593Smuzhiyun 				.tuner_attach     = dib7070p_tuner_attach,
4296*4882a593Smuzhiyun 
4297*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4298*4882a593Smuzhiyun 			}},
4299*4882a593Smuzhiyun 			}, {
4300*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4301*4882a593Smuzhiyun 			.fe = {{
4302*4882a593Smuzhiyun 				.caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4303*4882a593Smuzhiyun 				.pid_filter_count = 32,
4304*4882a593Smuzhiyun 				.pid_filter       = stk70x0p_pid_filter,
4305*4882a593Smuzhiyun 				.pid_filter_ctrl  = stk70x0p_pid_filter_ctrl,
4306*4882a593Smuzhiyun 				.frontend_attach  = novatd_frontend_attach,
4307*4882a593Smuzhiyun 				.tuner_attach     = dib7070p_tuner_attach,
4308*4882a593Smuzhiyun 
4309*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x03),
4310*4882a593Smuzhiyun 			}},
4311*4882a593Smuzhiyun 			}
4312*4882a593Smuzhiyun 		},
4313*4882a593Smuzhiyun 
4314*4882a593Smuzhiyun 		.num_device_descs = 3,
4315*4882a593Smuzhiyun 		.devices = {
4316*4882a593Smuzhiyun 			{   "Hauppauge Nova-TD Stick (52009)",
4317*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[35], NULL },
4318*4882a593Smuzhiyun 				{ NULL },
4319*4882a593Smuzhiyun 			},
4320*4882a593Smuzhiyun 			{   "PCTV 2002e",
4321*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[81], NULL },
4322*4882a593Smuzhiyun 				{ NULL },
4323*4882a593Smuzhiyun 			},
4324*4882a593Smuzhiyun 			{   "PCTV 2002e SE",
4325*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[82], NULL },
4326*4882a593Smuzhiyun 				{ NULL },
4327*4882a593Smuzhiyun 			},
4328*4882a593Smuzhiyun 		},
4329*4882a593Smuzhiyun 
4330*4882a593Smuzhiyun 		.rc.core = {
4331*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4332*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
4333*4882a593Smuzhiyun 			.module_name	  = "dib0700",
4334*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4335*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4336*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4337*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4338*4882a593Smuzhiyun 			.change_protocol = dib0700_change_protocol,
4339*4882a593Smuzhiyun 		},
4340*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4341*4882a593Smuzhiyun 
4342*4882a593Smuzhiyun 		.num_adapters = 2,
4343*4882a593Smuzhiyun 		.adapter = {
4344*4882a593Smuzhiyun 			{
4345*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4346*4882a593Smuzhiyun 			.fe = {{
4347*4882a593Smuzhiyun 				.caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4348*4882a593Smuzhiyun 				.pid_filter_count = 32,
4349*4882a593Smuzhiyun 				.pid_filter       = stk70x0p_pid_filter,
4350*4882a593Smuzhiyun 				.pid_filter_ctrl  = stk70x0p_pid_filter_ctrl,
4351*4882a593Smuzhiyun 				.frontend_attach  = stk7070pd_frontend_attach0,
4352*4882a593Smuzhiyun 				.tuner_attach     = dib7070p_tuner_attach,
4353*4882a593Smuzhiyun 
4354*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4355*4882a593Smuzhiyun 			}},
4356*4882a593Smuzhiyun 			}, {
4357*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4358*4882a593Smuzhiyun 			.fe = {{
4359*4882a593Smuzhiyun 				.caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4360*4882a593Smuzhiyun 				.pid_filter_count = 32,
4361*4882a593Smuzhiyun 				.pid_filter       = stk70x0p_pid_filter,
4362*4882a593Smuzhiyun 				.pid_filter_ctrl  = stk70x0p_pid_filter_ctrl,
4363*4882a593Smuzhiyun 				.frontend_attach  = stk7070pd_frontend_attach1,
4364*4882a593Smuzhiyun 				.tuner_attach     = dib7070p_tuner_attach,
4365*4882a593Smuzhiyun 
4366*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x03),
4367*4882a593Smuzhiyun 			}},
4368*4882a593Smuzhiyun 			}
4369*4882a593Smuzhiyun 		},
4370*4882a593Smuzhiyun 
4371*4882a593Smuzhiyun 		.num_device_descs = 5,
4372*4882a593Smuzhiyun 		.devices = {
4373*4882a593Smuzhiyun 			{   "DiBcom STK7070PD reference design",
4374*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[17], NULL },
4375*4882a593Smuzhiyun 				{ NULL },
4376*4882a593Smuzhiyun 			},
4377*4882a593Smuzhiyun 			{   "Pinnacle PCTV Dual DVB-T Diversity Stick",
4378*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[18], NULL },
4379*4882a593Smuzhiyun 				{ NULL },
4380*4882a593Smuzhiyun 			},
4381*4882a593Smuzhiyun 			{   "Hauppauge Nova-TD-500 (84xxx)",
4382*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[36], NULL },
4383*4882a593Smuzhiyun 				{ NULL },
4384*4882a593Smuzhiyun 			},
4385*4882a593Smuzhiyun 			{  "Terratec Cinergy DT USB XS Diversity/ T5",
4386*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[43],
4387*4882a593Smuzhiyun 					&dib0700_usb_id_table[53], NULL},
4388*4882a593Smuzhiyun 				{ NULL },
4389*4882a593Smuzhiyun 			},
4390*4882a593Smuzhiyun 			{  "Sony PlayTV",
4391*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[44], NULL },
4392*4882a593Smuzhiyun 				{ NULL },
4393*4882a593Smuzhiyun 			},
4394*4882a593Smuzhiyun 		},
4395*4882a593Smuzhiyun 
4396*4882a593Smuzhiyun 		.rc.core = {
4397*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4398*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
4399*4882a593Smuzhiyun 			.module_name	  = "dib0700",
4400*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4401*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4402*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4403*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4404*4882a593Smuzhiyun 			.change_protocol = dib0700_change_protocol,
4405*4882a593Smuzhiyun 		},
4406*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4407*4882a593Smuzhiyun 
4408*4882a593Smuzhiyun 		.num_adapters = 2,
4409*4882a593Smuzhiyun 		.adapter = {
4410*4882a593Smuzhiyun 			{
4411*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4412*4882a593Smuzhiyun 			.fe = {{
4413*4882a593Smuzhiyun 				.caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4414*4882a593Smuzhiyun 				.pid_filter_count = 32,
4415*4882a593Smuzhiyun 				.pid_filter       = stk70x0p_pid_filter,
4416*4882a593Smuzhiyun 				.pid_filter_ctrl  = stk70x0p_pid_filter_ctrl,
4417*4882a593Smuzhiyun 				.frontend_attach  = stk7070pd_frontend_attach0,
4418*4882a593Smuzhiyun 				.tuner_attach     = dib7070p_tuner_attach,
4419*4882a593Smuzhiyun 
4420*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4421*4882a593Smuzhiyun 			}},
4422*4882a593Smuzhiyun 			}, {
4423*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4424*4882a593Smuzhiyun 			.fe = {{
4425*4882a593Smuzhiyun 				.caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4426*4882a593Smuzhiyun 				.pid_filter_count = 32,
4427*4882a593Smuzhiyun 				.pid_filter       = stk70x0p_pid_filter,
4428*4882a593Smuzhiyun 				.pid_filter_ctrl  = stk70x0p_pid_filter_ctrl,
4429*4882a593Smuzhiyun 				.frontend_attach  = stk7070pd_frontend_attach1,
4430*4882a593Smuzhiyun 				.tuner_attach     = dib7070p_tuner_attach,
4431*4882a593Smuzhiyun 
4432*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x03),
4433*4882a593Smuzhiyun 			}},
4434*4882a593Smuzhiyun 			}
4435*4882a593Smuzhiyun 		},
4436*4882a593Smuzhiyun 
4437*4882a593Smuzhiyun 		.num_device_descs = 1,
4438*4882a593Smuzhiyun 		.devices = {
4439*4882a593Smuzhiyun 			{   "Elgato EyeTV Diversity",
4440*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[68], NULL },
4441*4882a593Smuzhiyun 				{ NULL },
4442*4882a593Smuzhiyun 			},
4443*4882a593Smuzhiyun 		},
4444*4882a593Smuzhiyun 
4445*4882a593Smuzhiyun 		.rc.core = {
4446*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4447*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_NEC_TABLE,
4448*4882a593Smuzhiyun 			.module_name	  = "dib0700",
4449*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4450*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4451*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4452*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4453*4882a593Smuzhiyun 			.change_protocol  = dib0700_change_protocol,
4454*4882a593Smuzhiyun 		},
4455*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4456*4882a593Smuzhiyun 
4457*4882a593Smuzhiyun 		.num_adapters = 1,
4458*4882a593Smuzhiyun 		.adapter = {
4459*4882a593Smuzhiyun 			{
4460*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4461*4882a593Smuzhiyun 			.fe = {{
4462*4882a593Smuzhiyun 				.caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4463*4882a593Smuzhiyun 				.pid_filter_count = 32,
4464*4882a593Smuzhiyun 				.pid_filter       = stk70x0p_pid_filter,
4465*4882a593Smuzhiyun 				.pid_filter_ctrl  = stk70x0p_pid_filter_ctrl,
4466*4882a593Smuzhiyun 				.frontend_attach  = stk7700ph_frontend_attach,
4467*4882a593Smuzhiyun 				.tuner_attach     = stk7700ph_tuner_attach,
4468*4882a593Smuzhiyun 
4469*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4470*4882a593Smuzhiyun 			}},
4471*4882a593Smuzhiyun 			},
4472*4882a593Smuzhiyun 		},
4473*4882a593Smuzhiyun 
4474*4882a593Smuzhiyun 		.num_device_descs = 10,
4475*4882a593Smuzhiyun 		.devices = {
4476*4882a593Smuzhiyun 			{   "Terratec Cinergy HT USB XE",
4477*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[27], NULL },
4478*4882a593Smuzhiyun 				{ NULL },
4479*4882a593Smuzhiyun 			},
4480*4882a593Smuzhiyun 			{   "Pinnacle Expresscard 320cx",
4481*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[28], NULL },
4482*4882a593Smuzhiyun 				{ NULL },
4483*4882a593Smuzhiyun 			},
4484*4882a593Smuzhiyun 			{   "Terratec Cinergy HT Express",
4485*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[32], NULL },
4486*4882a593Smuzhiyun 				{ NULL },
4487*4882a593Smuzhiyun 			},
4488*4882a593Smuzhiyun 			{   "Gigabyte U8000-RH",
4489*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[37], NULL },
4490*4882a593Smuzhiyun 				{ NULL },
4491*4882a593Smuzhiyun 			},
4492*4882a593Smuzhiyun 			{   "YUAN High-Tech STK7700PH",
4493*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[38], NULL },
4494*4882a593Smuzhiyun 				{ NULL },
4495*4882a593Smuzhiyun 			},
4496*4882a593Smuzhiyun 			{   "Asus My Cinema-U3000Hybrid",
4497*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[39], NULL },
4498*4882a593Smuzhiyun 				{ NULL },
4499*4882a593Smuzhiyun 			},
4500*4882a593Smuzhiyun 			{   "YUAN High-Tech MC770",
4501*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[48], NULL },
4502*4882a593Smuzhiyun 				{ NULL },
4503*4882a593Smuzhiyun 			},
4504*4882a593Smuzhiyun 			{   "Leadtek WinFast DTV Dongle H",
4505*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[51], NULL },
4506*4882a593Smuzhiyun 				{ NULL },
4507*4882a593Smuzhiyun 			},
4508*4882a593Smuzhiyun 			{   "YUAN High-Tech STK7700D",
4509*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[54], NULL },
4510*4882a593Smuzhiyun 				{ NULL },
4511*4882a593Smuzhiyun 			},
4512*4882a593Smuzhiyun 			{   "Hama DVB=T Hybrid USB Stick",
4513*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[85], NULL },
4514*4882a593Smuzhiyun 				{ NULL },
4515*4882a593Smuzhiyun 			},
4516*4882a593Smuzhiyun 		},
4517*4882a593Smuzhiyun 
4518*4882a593Smuzhiyun 		.rc.core = {
4519*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4520*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
4521*4882a593Smuzhiyun 			.module_name	  = "dib0700",
4522*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4523*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4524*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4525*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4526*4882a593Smuzhiyun 			.change_protocol  = dib0700_change_protocol,
4527*4882a593Smuzhiyun 		},
4528*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4529*4882a593Smuzhiyun 		.num_adapters = 1,
4530*4882a593Smuzhiyun 		.adapter = {
4531*4882a593Smuzhiyun 			{
4532*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4533*4882a593Smuzhiyun 			.fe = {{
4534*4882a593Smuzhiyun 				.frontend_attach  = s5h1411_frontend_attach,
4535*4882a593Smuzhiyun 				.tuner_attach     = xc5000_tuner_attach,
4536*4882a593Smuzhiyun 
4537*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4538*4882a593Smuzhiyun 			}},
4539*4882a593Smuzhiyun 			},
4540*4882a593Smuzhiyun 		},
4541*4882a593Smuzhiyun 
4542*4882a593Smuzhiyun 		.num_device_descs = 2,
4543*4882a593Smuzhiyun 		.devices = {
4544*4882a593Smuzhiyun 			{   "Pinnacle PCTV HD Pro USB Stick",
4545*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[40], NULL },
4546*4882a593Smuzhiyun 				{ NULL },
4547*4882a593Smuzhiyun 			},
4548*4882a593Smuzhiyun 			{   "Pinnacle PCTV HD USB Stick",
4549*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[41], NULL },
4550*4882a593Smuzhiyun 				{ NULL },
4551*4882a593Smuzhiyun 			},
4552*4882a593Smuzhiyun 		},
4553*4882a593Smuzhiyun 
4554*4882a593Smuzhiyun 		.rc.core = {
4555*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4556*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
4557*4882a593Smuzhiyun 			.module_name	  = "dib0700",
4558*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4559*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4560*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4561*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4562*4882a593Smuzhiyun 			.change_protocol  = dib0700_change_protocol,
4563*4882a593Smuzhiyun 		},
4564*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4565*4882a593Smuzhiyun 		.num_adapters = 1,
4566*4882a593Smuzhiyun 		.adapter = {
4567*4882a593Smuzhiyun 			{
4568*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4569*4882a593Smuzhiyun 			.fe = {{
4570*4882a593Smuzhiyun 				.frontend_attach  = lgdt3305_frontend_attach,
4571*4882a593Smuzhiyun 				.tuner_attach     = mxl5007t_tuner_attach,
4572*4882a593Smuzhiyun 
4573*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4574*4882a593Smuzhiyun 			}},
4575*4882a593Smuzhiyun 			},
4576*4882a593Smuzhiyun 		},
4577*4882a593Smuzhiyun 
4578*4882a593Smuzhiyun 		.num_device_descs = 2,
4579*4882a593Smuzhiyun 		.devices = {
4580*4882a593Smuzhiyun 			{   "Hauppauge ATSC MiniCard (B200)",
4581*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[46], NULL },
4582*4882a593Smuzhiyun 				{ NULL },
4583*4882a593Smuzhiyun 			},
4584*4882a593Smuzhiyun 			{   "Hauppauge ATSC MiniCard (B210)",
4585*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[47], NULL },
4586*4882a593Smuzhiyun 				{ NULL },
4587*4882a593Smuzhiyun 			},
4588*4882a593Smuzhiyun 		},
4589*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4590*4882a593Smuzhiyun 
4591*4882a593Smuzhiyun 		.num_adapters = 1,
4592*4882a593Smuzhiyun 		.adapter = {
4593*4882a593Smuzhiyun 			{
4594*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4595*4882a593Smuzhiyun 			.fe = {{
4596*4882a593Smuzhiyun 				.caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4597*4882a593Smuzhiyun 				.pid_filter_count = 32,
4598*4882a593Smuzhiyun 				.pid_filter       = stk70x0p_pid_filter,
4599*4882a593Smuzhiyun 				.pid_filter_ctrl  = stk70x0p_pid_filter_ctrl,
4600*4882a593Smuzhiyun 				.frontend_attach  = stk7770p_frontend_attach,
4601*4882a593Smuzhiyun 				.tuner_attach     = dib7770p_tuner_attach,
4602*4882a593Smuzhiyun 
4603*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4604*4882a593Smuzhiyun 			}},
4605*4882a593Smuzhiyun 			},
4606*4882a593Smuzhiyun 		},
4607*4882a593Smuzhiyun 
4608*4882a593Smuzhiyun 		.num_device_descs = 4,
4609*4882a593Smuzhiyun 		.devices = {
4610*4882a593Smuzhiyun 			{   "DiBcom STK7770P reference design",
4611*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[59], NULL },
4612*4882a593Smuzhiyun 				{ NULL },
4613*4882a593Smuzhiyun 			},
4614*4882a593Smuzhiyun 			{   "Terratec Cinergy T USB XXS (HD)/ T3",
4615*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[33],
4616*4882a593Smuzhiyun 					&dib0700_usb_id_table[52],
4617*4882a593Smuzhiyun 					&dib0700_usb_id_table[60], NULL},
4618*4882a593Smuzhiyun 				{ NULL },
4619*4882a593Smuzhiyun 			},
4620*4882a593Smuzhiyun 			{   "TechniSat AirStar TeleStick 2",
4621*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[74], NULL },
4622*4882a593Smuzhiyun 				{ NULL },
4623*4882a593Smuzhiyun 			},
4624*4882a593Smuzhiyun 			{   "Medion CTX1921 DVB-T USB",
4625*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[75], NULL },
4626*4882a593Smuzhiyun 				{ NULL },
4627*4882a593Smuzhiyun 			},
4628*4882a593Smuzhiyun 		},
4629*4882a593Smuzhiyun 
4630*4882a593Smuzhiyun 		.rc.core = {
4631*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4632*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
4633*4882a593Smuzhiyun 			.module_name	  = "dib0700",
4634*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4635*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4636*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4637*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4638*4882a593Smuzhiyun 			.change_protocol  = dib0700_change_protocol,
4639*4882a593Smuzhiyun 		},
4640*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4641*4882a593Smuzhiyun 		.num_adapters = 1,
4642*4882a593Smuzhiyun 		.adapter = {
4643*4882a593Smuzhiyun 			{
4644*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4645*4882a593Smuzhiyun 			.fe = {{
4646*4882a593Smuzhiyun 				.caps  = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4647*4882a593Smuzhiyun 				.pid_filter_count = 32,
4648*4882a593Smuzhiyun 				.pid_filter = stk80xx_pid_filter,
4649*4882a593Smuzhiyun 				.pid_filter_ctrl = stk80xx_pid_filter_ctrl,
4650*4882a593Smuzhiyun 				.frontend_attach  = stk807x_frontend_attach,
4651*4882a593Smuzhiyun 				.tuner_attach     = dib807x_tuner_attach,
4652*4882a593Smuzhiyun 
4653*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4654*4882a593Smuzhiyun 			}},
4655*4882a593Smuzhiyun 			},
4656*4882a593Smuzhiyun 		},
4657*4882a593Smuzhiyun 
4658*4882a593Smuzhiyun 		.num_device_descs = 3,
4659*4882a593Smuzhiyun 		.devices = {
4660*4882a593Smuzhiyun 			{   "DiBcom STK807xP reference design",
4661*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[62], NULL },
4662*4882a593Smuzhiyun 				{ NULL },
4663*4882a593Smuzhiyun 			},
4664*4882a593Smuzhiyun 			{   "Prolink Pixelview SBTVD",
4665*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[63], NULL },
4666*4882a593Smuzhiyun 				{ NULL },
4667*4882a593Smuzhiyun 			},
4668*4882a593Smuzhiyun 			{   "EvolutePC TVWay+",
4669*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[64], NULL },
4670*4882a593Smuzhiyun 				{ NULL },
4671*4882a593Smuzhiyun 			},
4672*4882a593Smuzhiyun 		},
4673*4882a593Smuzhiyun 
4674*4882a593Smuzhiyun 		.rc.core = {
4675*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4676*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_NEC_TABLE,
4677*4882a593Smuzhiyun 			.module_name	  = "dib0700",
4678*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4679*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4680*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4681*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4682*4882a593Smuzhiyun 			.change_protocol  = dib0700_change_protocol,
4683*4882a593Smuzhiyun 		},
4684*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4685*4882a593Smuzhiyun 		.num_adapters = 2,
4686*4882a593Smuzhiyun 		.adapter = {
4687*4882a593Smuzhiyun 			{
4688*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4689*4882a593Smuzhiyun 			.fe = {{
4690*4882a593Smuzhiyun 				.caps  = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4691*4882a593Smuzhiyun 				.pid_filter_count = 32,
4692*4882a593Smuzhiyun 				.pid_filter = stk80xx_pid_filter,
4693*4882a593Smuzhiyun 				.pid_filter_ctrl = stk80xx_pid_filter_ctrl,
4694*4882a593Smuzhiyun 				.frontend_attach  = stk807xpvr_frontend_attach0,
4695*4882a593Smuzhiyun 				.tuner_attach     = dib807x_tuner_attach,
4696*4882a593Smuzhiyun 
4697*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4698*4882a593Smuzhiyun 			}},
4699*4882a593Smuzhiyun 			},
4700*4882a593Smuzhiyun 			{
4701*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4702*4882a593Smuzhiyun 			.fe = {{
4703*4882a593Smuzhiyun 				.caps  = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4704*4882a593Smuzhiyun 				.pid_filter_count = 32,
4705*4882a593Smuzhiyun 				.pid_filter = stk80xx_pid_filter,
4706*4882a593Smuzhiyun 				.pid_filter_ctrl = stk80xx_pid_filter_ctrl,
4707*4882a593Smuzhiyun 				.frontend_attach  = stk807xpvr_frontend_attach1,
4708*4882a593Smuzhiyun 				.tuner_attach     = dib807x_tuner_attach,
4709*4882a593Smuzhiyun 
4710*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x03),
4711*4882a593Smuzhiyun 			}},
4712*4882a593Smuzhiyun 			},
4713*4882a593Smuzhiyun 		},
4714*4882a593Smuzhiyun 
4715*4882a593Smuzhiyun 		.num_device_descs = 1,
4716*4882a593Smuzhiyun 		.devices = {
4717*4882a593Smuzhiyun 			{   "DiBcom STK807xPVR reference design",
4718*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[61], NULL },
4719*4882a593Smuzhiyun 				{ NULL },
4720*4882a593Smuzhiyun 			},
4721*4882a593Smuzhiyun 		},
4722*4882a593Smuzhiyun 
4723*4882a593Smuzhiyun 		.rc.core = {
4724*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4725*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
4726*4882a593Smuzhiyun 			.module_name	  = "dib0700",
4727*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4728*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4729*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4730*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4731*4882a593Smuzhiyun 			.change_protocol  = dib0700_change_protocol,
4732*4882a593Smuzhiyun 		},
4733*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4734*4882a593Smuzhiyun 		.num_adapters = 1,
4735*4882a593Smuzhiyun 		.adapter = {
4736*4882a593Smuzhiyun 			{
4737*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4738*4882a593Smuzhiyun 			.fe = {{
4739*4882a593Smuzhiyun 				.caps  = DVB_USB_ADAP_HAS_PID_FILTER |
4740*4882a593Smuzhiyun 					DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4741*4882a593Smuzhiyun 				.pid_filter_count = 32,
4742*4882a593Smuzhiyun 				.pid_filter = stk80xx_pid_filter,
4743*4882a593Smuzhiyun 				.pid_filter_ctrl = stk80xx_pid_filter_ctrl,
4744*4882a593Smuzhiyun 				.frontend_attach  = stk809x_frontend_attach,
4745*4882a593Smuzhiyun 				.tuner_attach     = dib809x_tuner_attach,
4746*4882a593Smuzhiyun 
4747*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4748*4882a593Smuzhiyun 			}},
4749*4882a593Smuzhiyun 			},
4750*4882a593Smuzhiyun 		},
4751*4882a593Smuzhiyun 
4752*4882a593Smuzhiyun 		.num_device_descs = 1,
4753*4882a593Smuzhiyun 		.devices = {
4754*4882a593Smuzhiyun 			{   "DiBcom STK8096GP reference design",
4755*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[67], NULL },
4756*4882a593Smuzhiyun 				{ NULL },
4757*4882a593Smuzhiyun 			},
4758*4882a593Smuzhiyun 		},
4759*4882a593Smuzhiyun 
4760*4882a593Smuzhiyun 		.rc.core = {
4761*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4762*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
4763*4882a593Smuzhiyun 			.module_name	  = "dib0700",
4764*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4765*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4766*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4767*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4768*4882a593Smuzhiyun 			.change_protocol  = dib0700_change_protocol,
4769*4882a593Smuzhiyun 		},
4770*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4771*4882a593Smuzhiyun 		.num_adapters = 1,
4772*4882a593Smuzhiyun 		.adapter = {
4773*4882a593Smuzhiyun 			{
4774*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4775*4882a593Smuzhiyun 			.fe = {{
4776*4882a593Smuzhiyun 				.caps  = DVB_USB_ADAP_HAS_PID_FILTER |
4777*4882a593Smuzhiyun 					DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4778*4882a593Smuzhiyun 				.pid_filter_count = 32,
4779*4882a593Smuzhiyun 				.pid_filter = dib90x0_pid_filter,
4780*4882a593Smuzhiyun 				.pid_filter_ctrl = dib90x0_pid_filter_ctrl,
4781*4882a593Smuzhiyun 				.frontend_attach  = stk9090m_frontend_attach,
4782*4882a593Smuzhiyun 				.tuner_attach     = dib9090_tuner_attach,
4783*4882a593Smuzhiyun 
4784*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4785*4882a593Smuzhiyun 			}},
4786*4882a593Smuzhiyun 			},
4787*4882a593Smuzhiyun 		},
4788*4882a593Smuzhiyun 
4789*4882a593Smuzhiyun 		.num_device_descs = 1,
4790*4882a593Smuzhiyun 		.devices = {
4791*4882a593Smuzhiyun 			{   "DiBcom STK9090M reference design",
4792*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[69], NULL },
4793*4882a593Smuzhiyun 				{ NULL },
4794*4882a593Smuzhiyun 			},
4795*4882a593Smuzhiyun 		},
4796*4882a593Smuzhiyun 
4797*4882a593Smuzhiyun 		.rc.core = {
4798*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4799*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
4800*4882a593Smuzhiyun 			.module_name	  = "dib0700",
4801*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4802*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4803*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4804*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4805*4882a593Smuzhiyun 			.change_protocol  = dib0700_change_protocol,
4806*4882a593Smuzhiyun 		},
4807*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4808*4882a593Smuzhiyun 		.num_adapters = 1,
4809*4882a593Smuzhiyun 		.adapter = {
4810*4882a593Smuzhiyun 			{
4811*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4812*4882a593Smuzhiyun 			.fe = {{
4813*4882a593Smuzhiyun 				.caps  = DVB_USB_ADAP_HAS_PID_FILTER |
4814*4882a593Smuzhiyun 					DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4815*4882a593Smuzhiyun 				.pid_filter_count = 32,
4816*4882a593Smuzhiyun 				.pid_filter = stk80xx_pid_filter,
4817*4882a593Smuzhiyun 				.pid_filter_ctrl = stk80xx_pid_filter_ctrl,
4818*4882a593Smuzhiyun 				.frontend_attach  = nim8096md_frontend_attach,
4819*4882a593Smuzhiyun 				.tuner_attach     = nim8096md_tuner_attach,
4820*4882a593Smuzhiyun 
4821*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4822*4882a593Smuzhiyun 			}},
4823*4882a593Smuzhiyun 			},
4824*4882a593Smuzhiyun 		},
4825*4882a593Smuzhiyun 
4826*4882a593Smuzhiyun 		.num_device_descs = 1,
4827*4882a593Smuzhiyun 		.devices = {
4828*4882a593Smuzhiyun 			{   "DiBcom NIM8096MD reference design",
4829*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[70], NULL },
4830*4882a593Smuzhiyun 				{ NULL },
4831*4882a593Smuzhiyun 			},
4832*4882a593Smuzhiyun 		},
4833*4882a593Smuzhiyun 
4834*4882a593Smuzhiyun 		.rc.core = {
4835*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4836*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
4837*4882a593Smuzhiyun 			.module_name	  = "dib0700",
4838*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4839*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4840*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4841*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4842*4882a593Smuzhiyun 			.change_protocol  = dib0700_change_protocol,
4843*4882a593Smuzhiyun 		},
4844*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4845*4882a593Smuzhiyun 		.num_adapters = 1,
4846*4882a593Smuzhiyun 		.adapter = {
4847*4882a593Smuzhiyun 			{
4848*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4849*4882a593Smuzhiyun 			.fe = {{
4850*4882a593Smuzhiyun 				.caps  = DVB_USB_ADAP_HAS_PID_FILTER |
4851*4882a593Smuzhiyun 					DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4852*4882a593Smuzhiyun 				.pid_filter_count = 32,
4853*4882a593Smuzhiyun 				.pid_filter = dib90x0_pid_filter,
4854*4882a593Smuzhiyun 				.pid_filter_ctrl = dib90x0_pid_filter_ctrl,
4855*4882a593Smuzhiyun 				.frontend_attach  = nim9090md_frontend_attach,
4856*4882a593Smuzhiyun 				.tuner_attach     = nim9090md_tuner_attach,
4857*4882a593Smuzhiyun 
4858*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4859*4882a593Smuzhiyun 			}},
4860*4882a593Smuzhiyun 			},
4861*4882a593Smuzhiyun 		},
4862*4882a593Smuzhiyun 
4863*4882a593Smuzhiyun 		.num_device_descs = 1,
4864*4882a593Smuzhiyun 		.devices = {
4865*4882a593Smuzhiyun 			{   "DiBcom NIM9090MD reference design",
4866*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[71], NULL },
4867*4882a593Smuzhiyun 				{ NULL },
4868*4882a593Smuzhiyun 			},
4869*4882a593Smuzhiyun 		},
4870*4882a593Smuzhiyun 
4871*4882a593Smuzhiyun 		.rc.core = {
4872*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4873*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
4874*4882a593Smuzhiyun 			.module_name	  = "dib0700",
4875*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4876*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4877*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4878*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4879*4882a593Smuzhiyun 			.change_protocol  = dib0700_change_protocol,
4880*4882a593Smuzhiyun 		},
4881*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4882*4882a593Smuzhiyun 		.num_adapters = 1,
4883*4882a593Smuzhiyun 		.adapter = {
4884*4882a593Smuzhiyun 			{
4885*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4886*4882a593Smuzhiyun 			.fe = {{
4887*4882a593Smuzhiyun 				.caps  = DVB_USB_ADAP_HAS_PID_FILTER |
4888*4882a593Smuzhiyun 					DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4889*4882a593Smuzhiyun 				.pid_filter_count = 32,
4890*4882a593Smuzhiyun 				.pid_filter = stk70x0p_pid_filter,
4891*4882a593Smuzhiyun 				.pid_filter_ctrl = stk70x0p_pid_filter_ctrl,
4892*4882a593Smuzhiyun 				.frontend_attach  = nim7090_frontend_attach,
4893*4882a593Smuzhiyun 				.tuner_attach     = nim7090_tuner_attach,
4894*4882a593Smuzhiyun 
4895*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4896*4882a593Smuzhiyun 			}},
4897*4882a593Smuzhiyun 			},
4898*4882a593Smuzhiyun 		},
4899*4882a593Smuzhiyun 
4900*4882a593Smuzhiyun 		.num_device_descs = 1,
4901*4882a593Smuzhiyun 		.devices = {
4902*4882a593Smuzhiyun 			{   "DiBcom NIM7090 reference design",
4903*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[72], NULL },
4904*4882a593Smuzhiyun 				{ NULL },
4905*4882a593Smuzhiyun 			},
4906*4882a593Smuzhiyun 		},
4907*4882a593Smuzhiyun 
4908*4882a593Smuzhiyun 		.rc.core = {
4909*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4910*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
4911*4882a593Smuzhiyun 			.module_name	  = "dib0700",
4912*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4913*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4914*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4915*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4916*4882a593Smuzhiyun 			.change_protocol  = dib0700_change_protocol,
4917*4882a593Smuzhiyun 		},
4918*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4919*4882a593Smuzhiyun 		.num_adapters = 2,
4920*4882a593Smuzhiyun 		.adapter = {
4921*4882a593Smuzhiyun 			{
4922*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4923*4882a593Smuzhiyun 			.fe = {{
4924*4882a593Smuzhiyun 				.caps  = DVB_USB_ADAP_HAS_PID_FILTER |
4925*4882a593Smuzhiyun 					DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4926*4882a593Smuzhiyun 				.pid_filter_count = 32,
4927*4882a593Smuzhiyun 				.pid_filter = stk70x0p_pid_filter,
4928*4882a593Smuzhiyun 				.pid_filter_ctrl = stk70x0p_pid_filter_ctrl,
4929*4882a593Smuzhiyun 				.frontend_attach  = tfe7090pvr_frontend0_attach,
4930*4882a593Smuzhiyun 				.tuner_attach     = tfe7090pvr_tuner0_attach,
4931*4882a593Smuzhiyun 
4932*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x03),
4933*4882a593Smuzhiyun 			}},
4934*4882a593Smuzhiyun 			},
4935*4882a593Smuzhiyun 			{
4936*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4937*4882a593Smuzhiyun 			.fe = {{
4938*4882a593Smuzhiyun 				.caps  = DVB_USB_ADAP_HAS_PID_FILTER |
4939*4882a593Smuzhiyun 					DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
4940*4882a593Smuzhiyun 				.pid_filter_count = 32,
4941*4882a593Smuzhiyun 				.pid_filter = stk70x0p_pid_filter,
4942*4882a593Smuzhiyun 				.pid_filter_ctrl = stk70x0p_pid_filter_ctrl,
4943*4882a593Smuzhiyun 				.frontend_attach  = tfe7090pvr_frontend1_attach,
4944*4882a593Smuzhiyun 				.tuner_attach     = tfe7090pvr_tuner1_attach,
4945*4882a593Smuzhiyun 
4946*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4947*4882a593Smuzhiyun 			}},
4948*4882a593Smuzhiyun 			},
4949*4882a593Smuzhiyun 		},
4950*4882a593Smuzhiyun 
4951*4882a593Smuzhiyun 		.num_device_descs = 1,
4952*4882a593Smuzhiyun 		.devices = {
4953*4882a593Smuzhiyun 			{   "DiBcom TFE7090PVR reference design",
4954*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[73], NULL },
4955*4882a593Smuzhiyun 				{ NULL },
4956*4882a593Smuzhiyun 			},
4957*4882a593Smuzhiyun 		},
4958*4882a593Smuzhiyun 
4959*4882a593Smuzhiyun 		.rc.core = {
4960*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4961*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
4962*4882a593Smuzhiyun 			.module_name	  = "dib0700",
4963*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4964*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
4965*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
4966*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
4967*4882a593Smuzhiyun 			.change_protocol  = dib0700_change_protocol,
4968*4882a593Smuzhiyun 		},
4969*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
4970*4882a593Smuzhiyun 		.num_adapters = 1,
4971*4882a593Smuzhiyun 		.adapter = {
4972*4882a593Smuzhiyun 			{
4973*4882a593Smuzhiyun 			DIB0700_NUM_FRONTENDS(1),
4974*4882a593Smuzhiyun 			.fe = {{
4975*4882a593Smuzhiyun 				.frontend_attach  = pctv340e_frontend_attach,
4976*4882a593Smuzhiyun 				.tuner_attach     = xc4000_tuner_attach,
4977*4882a593Smuzhiyun 
4978*4882a593Smuzhiyun 				DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
4979*4882a593Smuzhiyun 			}},
4980*4882a593Smuzhiyun 			},
4981*4882a593Smuzhiyun 		},
4982*4882a593Smuzhiyun 
4983*4882a593Smuzhiyun 		.num_device_descs = 2,
4984*4882a593Smuzhiyun 		.devices = {
4985*4882a593Smuzhiyun 			{   "Pinnacle PCTV 340e HD Pro USB Stick",
4986*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[76], NULL },
4987*4882a593Smuzhiyun 				{ NULL },
4988*4882a593Smuzhiyun 			},
4989*4882a593Smuzhiyun 			{   "Pinnacle PCTV Hybrid Stick Solo",
4990*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[77], NULL },
4991*4882a593Smuzhiyun 				{ NULL },
4992*4882a593Smuzhiyun 			},
4993*4882a593Smuzhiyun 		},
4994*4882a593Smuzhiyun 		.rc.core = {
4995*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
4996*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
4997*4882a593Smuzhiyun 			.module_name	  = "dib0700",
4998*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
4999*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
5000*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
5001*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
5002*4882a593Smuzhiyun 			.change_protocol  = dib0700_change_protocol,
5003*4882a593Smuzhiyun 		},
5004*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
5005*4882a593Smuzhiyun 		.num_adapters = 1,
5006*4882a593Smuzhiyun 		.adapter = {
5007*4882a593Smuzhiyun 			{
5008*4882a593Smuzhiyun 				DIB0700_NUM_FRONTENDS(1),
5009*4882a593Smuzhiyun 				.fe = {{
5010*4882a593Smuzhiyun 					.caps  = DVB_USB_ADAP_HAS_PID_FILTER |
5011*4882a593Smuzhiyun 						DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
5012*4882a593Smuzhiyun 					.pid_filter_count = 32,
5013*4882a593Smuzhiyun 					.pid_filter = stk70x0p_pid_filter,
5014*4882a593Smuzhiyun 					.pid_filter_ctrl = stk70x0p_pid_filter_ctrl,
5015*4882a593Smuzhiyun 					.frontend_attach  = tfe7790p_frontend_attach,
5016*4882a593Smuzhiyun 					.tuner_attach     = tfe7790p_tuner_attach,
5017*4882a593Smuzhiyun 
5018*4882a593Smuzhiyun 					DIB0700_DEFAULT_STREAMING_CONFIG(0x03),
5019*4882a593Smuzhiyun 				} },
5020*4882a593Smuzhiyun 			},
5021*4882a593Smuzhiyun 		},
5022*4882a593Smuzhiyun 
5023*4882a593Smuzhiyun 		.num_device_descs = 1,
5024*4882a593Smuzhiyun 		.devices = {
5025*4882a593Smuzhiyun 			{   "DiBcom TFE7790P reference design",
5026*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[78], NULL },
5027*4882a593Smuzhiyun 				{ NULL },
5028*4882a593Smuzhiyun 			},
5029*4882a593Smuzhiyun 		},
5030*4882a593Smuzhiyun 
5031*4882a593Smuzhiyun 		.rc.core = {
5032*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
5033*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
5034*4882a593Smuzhiyun 			.module_name	  = "dib0700",
5035*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
5036*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
5037*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
5038*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
5039*4882a593Smuzhiyun 			.change_protocol  = dib0700_change_protocol,
5040*4882a593Smuzhiyun 		},
5041*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
5042*4882a593Smuzhiyun 		.num_adapters = 1,
5043*4882a593Smuzhiyun 		.adapter = {
5044*4882a593Smuzhiyun 			{
5045*4882a593Smuzhiyun 				DIB0700_NUM_FRONTENDS(1),
5046*4882a593Smuzhiyun 				.fe = {{
5047*4882a593Smuzhiyun 					.caps  = DVB_USB_ADAP_HAS_PID_FILTER |
5048*4882a593Smuzhiyun 						DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
5049*4882a593Smuzhiyun 					.pid_filter_count = 32,
5050*4882a593Smuzhiyun 					.pid_filter = stk80xx_pid_filter,
5051*4882a593Smuzhiyun 					.pid_filter_ctrl = stk80xx_pid_filter_ctrl,
5052*4882a593Smuzhiyun 					.frontend_attach  = tfe8096p_frontend_attach,
5053*4882a593Smuzhiyun 					.tuner_attach     = tfe8096p_tuner_attach,
5054*4882a593Smuzhiyun 
5055*4882a593Smuzhiyun 					DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
5056*4882a593Smuzhiyun 
5057*4882a593Smuzhiyun 				} },
5058*4882a593Smuzhiyun 			},
5059*4882a593Smuzhiyun 		},
5060*4882a593Smuzhiyun 
5061*4882a593Smuzhiyun 		.num_device_descs = 1,
5062*4882a593Smuzhiyun 		.devices = {
5063*4882a593Smuzhiyun 			{   "DiBcom TFE8096P reference design",
5064*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[79], NULL },
5065*4882a593Smuzhiyun 				{ NULL },
5066*4882a593Smuzhiyun 			},
5067*4882a593Smuzhiyun 		},
5068*4882a593Smuzhiyun 
5069*4882a593Smuzhiyun 		.rc.core = {
5070*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
5071*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
5072*4882a593Smuzhiyun 			.module_name	  = "dib0700",
5073*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
5074*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
5075*4882a593Smuzhiyun 					    RC_PROTO_BIT_RC6_MCE |
5076*4882a593Smuzhiyun 					    RC_PROTO_BIT_NEC,
5077*4882a593Smuzhiyun 			.change_protocol  = dib0700_change_protocol,
5078*4882a593Smuzhiyun 		},
5079*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
5080*4882a593Smuzhiyun 		.num_adapters = 2,
5081*4882a593Smuzhiyun 		.adapter = {
5082*4882a593Smuzhiyun 			{
5083*4882a593Smuzhiyun 				.num_frontends = 1,
5084*4882a593Smuzhiyun 				.fe = {{
5085*4882a593Smuzhiyun 					.caps  = DVB_USB_ADAP_HAS_PID_FILTER |
5086*4882a593Smuzhiyun 						DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
5087*4882a593Smuzhiyun 					.pid_filter_count = 32,
5088*4882a593Smuzhiyun 					.pid_filter = stk80xx_pid_filter,
5089*4882a593Smuzhiyun 					.pid_filter_ctrl = stk80xx_pid_filter_ctrl,
5090*4882a593Smuzhiyun 					.frontend_attach  = stk809x_frontend_attach,
5091*4882a593Smuzhiyun 					.tuner_attach     = dib809x_tuner_attach,
5092*4882a593Smuzhiyun 
5093*4882a593Smuzhiyun 					DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
5094*4882a593Smuzhiyun 				} },
5095*4882a593Smuzhiyun 				.size_of_priv =
5096*4882a593Smuzhiyun 					sizeof(struct dib0700_adapter_state),
5097*4882a593Smuzhiyun 			}, {
5098*4882a593Smuzhiyun 				.num_frontends = 1,
5099*4882a593Smuzhiyun 				.fe = { {
5100*4882a593Smuzhiyun 					.caps  = DVB_USB_ADAP_HAS_PID_FILTER |
5101*4882a593Smuzhiyun 						DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
5102*4882a593Smuzhiyun 					.pid_filter_count = 32,
5103*4882a593Smuzhiyun 					.pid_filter = stk80xx_pid_filter,
5104*4882a593Smuzhiyun 					.pid_filter_ctrl = stk80xx_pid_filter_ctrl,
5105*4882a593Smuzhiyun 					.frontend_attach  = stk809x_frontend1_attach,
5106*4882a593Smuzhiyun 					.tuner_attach     = dib809x_tuner_attach,
5107*4882a593Smuzhiyun 
5108*4882a593Smuzhiyun 					DIB0700_DEFAULT_STREAMING_CONFIG(0x03),
5109*4882a593Smuzhiyun 				} },
5110*4882a593Smuzhiyun 				.size_of_priv =
5111*4882a593Smuzhiyun 					sizeof(struct dib0700_adapter_state),
5112*4882a593Smuzhiyun 			},
5113*4882a593Smuzhiyun 		},
5114*4882a593Smuzhiyun 		.num_device_descs = 1,
5115*4882a593Smuzhiyun 		.devices = {
5116*4882a593Smuzhiyun 			{   "DiBcom STK8096-PVR reference design",
5117*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[83],
5118*4882a593Smuzhiyun 					&dib0700_usb_id_table[84], NULL},
5119*4882a593Smuzhiyun 				{ NULL },
5120*4882a593Smuzhiyun 			},
5121*4882a593Smuzhiyun 		},
5122*4882a593Smuzhiyun 
5123*4882a593Smuzhiyun 		.rc.core = {
5124*4882a593Smuzhiyun 			.rc_interval      = DEFAULT_RC_INTERVAL,
5125*4882a593Smuzhiyun 			.rc_codes         = RC_MAP_DIB0700_RC5_TABLE,
5126*4882a593Smuzhiyun 			.module_name  = "dib0700",
5127*4882a593Smuzhiyun 			.rc_query         = dib0700_rc_query_old_firmware,
5128*4882a593Smuzhiyun 			.allowed_protos   = RC_PROTO_BIT_RC5 |
5129*4882a593Smuzhiyun 				RC_PROTO_BIT_RC6_MCE |
5130*4882a593Smuzhiyun 				RC_PROTO_BIT_NEC,
5131*4882a593Smuzhiyun 			.change_protocol  = dib0700_change_protocol,
5132*4882a593Smuzhiyun 		},
5133*4882a593Smuzhiyun 	}, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
5134*4882a593Smuzhiyun 		.num_adapters = 1,
5135*4882a593Smuzhiyun 		.adapter = {
5136*4882a593Smuzhiyun 			{
5137*4882a593Smuzhiyun 				DIB0700_NUM_FRONTENDS(1),
5138*4882a593Smuzhiyun 				.fe = {{
5139*4882a593Smuzhiyun 					.frontend_attach = xbox_one_attach,
5140*4882a593Smuzhiyun 
5141*4882a593Smuzhiyun 					DIB0700_DEFAULT_STREAMING_CONFIG(0x82),
5142*4882a593Smuzhiyun 				} },
5143*4882a593Smuzhiyun 			},
5144*4882a593Smuzhiyun 		},
5145*4882a593Smuzhiyun 		.num_device_descs = 1,
5146*4882a593Smuzhiyun 		.devices = {
5147*4882a593Smuzhiyun 			{ "Microsoft Xbox One Digital TV Tuner",
5148*4882a593Smuzhiyun 				{ &dib0700_usb_id_table[86], NULL },
5149*4882a593Smuzhiyun 				{ NULL },
5150*4882a593Smuzhiyun 			},
5151*4882a593Smuzhiyun 		},
5152*4882a593Smuzhiyun 	},
5153*4882a593Smuzhiyun };
5154*4882a593Smuzhiyun 
5155*4882a593Smuzhiyun int dib0700_device_count = ARRAY_SIZE(dib0700_devices);
5156