1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * mxl111sf-reg.h - driver for the MaxLinear MXL111SF 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2010-2014 Michael Krufky <mkrufky@linuxtv.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _DVB_USB_MXL111SF_REG_H_ 9*4882a593Smuzhiyun #define _DVB_USB_MXL111SF_REG_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CHIP_ID_REG 0xFC 12*4882a593Smuzhiyun #define TOP_CHIP_REV_ID_REG 0xFA 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define V6_SNR_RB_LSB_REG 0x27 15*4882a593Smuzhiyun #define V6_SNR_RB_MSB_REG 0x28 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define V6_N_ACCUMULATE_REG 0x11 18*4882a593Smuzhiyun #define V6_RS_AVG_ERRORS_LSB_REG 0x2C 19*4882a593Smuzhiyun #define V6_RS_AVG_ERRORS_MSB_REG 0x2D 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define V6_IRQ_STATUS_REG 0x24 22*4882a593Smuzhiyun #define IRQ_MASK_FEC_LOCK 0x10 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define V6_SYNC_LOCK_REG 0x28 25*4882a593Smuzhiyun #define SYNC_LOCK_MASK 0x10 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define V6_RS_LOCK_DET_REG 0x28 28*4882a593Smuzhiyun #define RS_LOCK_DET_MASK 0x08 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define V6_INITACQ_NODETECT_REG 0x20 31*4882a593Smuzhiyun #define V6_FORCE_NFFT_CPSIZE_REG 0x20 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define V6_CODE_RATE_TPS_REG 0x29 34*4882a593Smuzhiyun #define V6_CODE_RATE_TPS_MASK 0x07 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define V6_CP_LOCK_DET_REG 0x28 38*4882a593Smuzhiyun #define V6_CP_LOCK_DET_MASK 0x04 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define V6_TPS_HIERACHY_REG 0x29 41*4882a593Smuzhiyun #define V6_TPS_HIERARCHY_INFO_MASK 0x40 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define V6_MODORDER_TPS_REG 0x2A 44*4882a593Smuzhiyun #define V6_PARAM_CONSTELLATION_MASK 0x30 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define V6_MODE_TPS_REG 0x2A 47*4882a593Smuzhiyun #define V6_PARAM_FFT_MODE_MASK 0x0C 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define V6_CP_TPS_REG 0x29 51*4882a593Smuzhiyun #define V6_PARAM_GI_MASK 0x30 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define V6_TPS_LOCK_REG 0x2A 54*4882a593Smuzhiyun #define V6_PARAM_TPS_LOCK_MASK 0x40 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define V6_FEC_PER_COUNT_REG 0x2E 57*4882a593Smuzhiyun #define V6_FEC_PER_SCALE_REG 0x2B 58*4882a593Smuzhiyun #define V6_FEC_PER_SCALE_MASK 0x03 59*4882a593Smuzhiyun #define V6_FEC_PER_CLR_REG 0x20 60*4882a593Smuzhiyun #define V6_FEC_PER_CLR_MASK 0x01 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define V6_PIN_MUX_MODE_REG 0x1B 63*4882a593Smuzhiyun #define V6_ENABLE_PIN_MUX 0x1E 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define V6_I2S_NUM_SAMPLES_REG 0x16 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define V6_MPEG_IN_CLK_INV_REG 0x17 68*4882a593Smuzhiyun #define V6_MPEG_IN_CTRL_REG 0x18 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define V6_INVERTED_CLK_PHASE 0x20 71*4882a593Smuzhiyun #define V6_MPEG_IN_DATA_PARALLEL 0x01 72*4882a593Smuzhiyun #define V6_MPEG_IN_DATA_SERIAL 0x02 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define V6_INVERTED_MPEG_SYNC 0x04 75*4882a593Smuzhiyun #define V6_INVERTED_MPEG_VALID 0x08 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define TSIF_INPUT_PARALLEL 0 78*4882a593Smuzhiyun #define TSIF_INPUT_SERIAL 1 79*4882a593Smuzhiyun #define TSIF_NORMAL 0 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define V6_MPEG_INOUT_BIT_ORDER_CTRL_REG 0x19 82*4882a593Smuzhiyun #define V6_MPEG_SER_MSB_FIRST 0x80 83*4882a593Smuzhiyun #define MPEG_SER_MSB_FIRST_ENABLED 0x01 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define V6_656_I2S_BUFF_STATUS_REG 0x2F 86*4882a593Smuzhiyun #define V6_656_OVERFLOW_MASK_BIT 0x08 87*4882a593Smuzhiyun #define V6_I2S_OVERFLOW_MASK_BIT 0x01 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define V6_I2S_STREAM_START_BIT_REG 0x14 90*4882a593Smuzhiyun #define V6_I2S_STREAM_END_BIT_REG 0x15 91*4882a593Smuzhiyun #define I2S_RIGHT_JUSTIFIED 0 92*4882a593Smuzhiyun #define I2S_LEFT_JUSTIFIED 1 93*4882a593Smuzhiyun #define I2S_DATA_FORMAT 2 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define V6_TUNER_LOOP_THRU_CONTROL_REG 0x09 96*4882a593Smuzhiyun #define V6_ENABLE_LOOP_THRU 0x01 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define TOTAL_NUM_IF_OUTPUT_FREQ 16 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define TUNER_NORMAL_IF_SPECTRUM 0x0 101*4882a593Smuzhiyun #define TUNER_INVERT_IF_SPECTRUM 0x10 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define V6_TUNER_IF_SEL_REG 0x06 104*4882a593Smuzhiyun #define V6_TUNER_IF_FCW_REG 0x3C 105*4882a593Smuzhiyun #define V6_TUNER_IF_FCW_BYP_REG 0x3D 106*4882a593Smuzhiyun #define V6_RF_LOCK_STATUS_REG 0x23 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define NUM_DIG_TV_CHANNEL 1000 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define V6_DIG_CLK_FREQ_SEL_REG 0x07 111*4882a593Smuzhiyun #define V6_REF_SYNTH_INT_REG 0x5C 112*4882a593Smuzhiyun #define V6_REF_SYNTH_REMAIN_REG 0x58 113*4882a593Smuzhiyun #define V6_DIG_RFREFSELECT_REG 0x32 114*4882a593Smuzhiyun #define V6_XTAL_CLK_OUT_GAIN_REG 0x31 115*4882a593Smuzhiyun #define V6_TUNER_LOOP_THRU_CTRL_REG 0x09 116*4882a593Smuzhiyun #define V6_DIG_XTAL_ENABLE_REG 0x06 117*4882a593Smuzhiyun #define V6_DIG_XTAL_BIAS_REG 0x66 118*4882a593Smuzhiyun #define V6_XTAL_CAP_REG 0x08 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define V6_GPO_CTRL_REG 0x18 121*4882a593Smuzhiyun #define MXL_GPO_0 0x00 122*4882a593Smuzhiyun #define MXL_GPO_1 0x01 123*4882a593Smuzhiyun #define V6_GPO_0_MASK 0x10 124*4882a593Smuzhiyun #define V6_GPO_1_MASK 0x20 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define V6_111SF_GPO_CTRL_REG 0x19 127*4882a593Smuzhiyun #define MXL_111SF_GPO_1 0x00 128*4882a593Smuzhiyun #define MXL_111SF_GPO_2 0x01 129*4882a593Smuzhiyun #define MXL_111SF_GPO_3 0x02 130*4882a593Smuzhiyun #define MXL_111SF_GPO_4 0x03 131*4882a593Smuzhiyun #define MXL_111SF_GPO_5 0x04 132*4882a593Smuzhiyun #define MXL_111SF_GPO_6 0x05 133*4882a593Smuzhiyun #define MXL_111SF_GPO_7 0x06 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define MXL_111SF_GPO_0_MASK 0x01 136*4882a593Smuzhiyun #define MXL_111SF_GPO_1_MASK 0x02 137*4882a593Smuzhiyun #define MXL_111SF_GPO_2_MASK 0x04 138*4882a593Smuzhiyun #define MXL_111SF_GPO_3_MASK 0x08 139*4882a593Smuzhiyun #define MXL_111SF_GPO_4_MASK 0x10 140*4882a593Smuzhiyun #define MXL_111SF_GPO_5_MASK 0x20 141*4882a593Smuzhiyun #define MXL_111SF_GPO_6_MASK 0x40 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #define V6_ATSC_CONFIG_REG 0x0A 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #define MXL_MODE_REG 0x03 146*4882a593Smuzhiyun #define START_TUNE_REG 0x1C 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #define V6_IDAC_HYSTERESIS_REG 0x0B 149*4882a593Smuzhiyun #define V6_IDAC_SETTINGS_REG 0x0C 150*4882a593Smuzhiyun #define IDAC_MANUAL_CONTROL 1 151*4882a593Smuzhiyun #define IDAC_CURRENT_SINKING_ENABLE 1 152*4882a593Smuzhiyun #define IDAC_MANUAL_CONTROL_BIT_MASK 0x80 153*4882a593Smuzhiyun #define IDAC_CURRENT_SINKING_BIT_MASK 0x40 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun #define V8_SPI_MODE_REG 0xE9 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #define V6_DIG_RF_PWR_LSB_REG 0x46 158*4882a593Smuzhiyun #define V6_DIG_RF_PWR_MSB_REG 0x47 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun #endif /* _DVB_USB_MXL111SF_REG_H_ */ 161