1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Afatech AF9035 DVB USB driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009 Antti Palosaari <crope@iki.fi> 6*4882a593Smuzhiyun * Copyright (C) 2012 Antti Palosaari <crope@iki.fi> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef AF9035_H 10*4882a593Smuzhiyun #define AF9035_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/platform_device.h> 13*4882a593Smuzhiyun #include "dvb_usb.h" 14*4882a593Smuzhiyun #include "af9033.h" 15*4882a593Smuzhiyun #include "tua9001.h" 16*4882a593Smuzhiyun #include "fc0011.h" 17*4882a593Smuzhiyun #include "fc0012.h" 18*4882a593Smuzhiyun #include "mxl5007t.h" 19*4882a593Smuzhiyun #include "tda18218.h" 20*4882a593Smuzhiyun #include "fc2580.h" 21*4882a593Smuzhiyun #include "it913x.h" 22*4882a593Smuzhiyun #include "si2168.h" 23*4882a593Smuzhiyun #include "si2157.h" 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun struct reg_val { 26*4882a593Smuzhiyun u32 reg; 27*4882a593Smuzhiyun u8 val; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun struct reg_val_mask { 31*4882a593Smuzhiyun u32 reg; 32*4882a593Smuzhiyun u8 val; 33*4882a593Smuzhiyun u8 mask; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun struct usb_req { 37*4882a593Smuzhiyun u8 cmd; 38*4882a593Smuzhiyun u8 mbox; 39*4882a593Smuzhiyun u8 wlen; 40*4882a593Smuzhiyun u8 *wbuf; 41*4882a593Smuzhiyun u8 rlen; 42*4882a593Smuzhiyun u8 *rbuf; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun struct state { 46*4882a593Smuzhiyun #define BUF_LEN 64 47*4882a593Smuzhiyun u8 buf[BUF_LEN]; 48*4882a593Smuzhiyun u8 seq; /* packet sequence number */ 49*4882a593Smuzhiyun u8 prechip_version; 50*4882a593Smuzhiyun u8 chip_version; 51*4882a593Smuzhiyun u16 chip_type; 52*4882a593Smuzhiyun u8 eeprom[256]; 53*4882a593Smuzhiyun bool no_eeprom; 54*4882a593Smuzhiyun u8 ir_mode; 55*4882a593Smuzhiyun u8 ir_type; 56*4882a593Smuzhiyun u8 dual_mode:1; 57*4882a593Smuzhiyun u8 no_read:1; 58*4882a593Smuzhiyun u8 af9033_i2c_addr[2]; 59*4882a593Smuzhiyun u8 it930x_addresses; 60*4882a593Smuzhiyun struct af9033_config af9033_config[2]; 61*4882a593Smuzhiyun struct af9033_ops ops; 62*4882a593Smuzhiyun #define AF9035_I2C_CLIENT_MAX 4 63*4882a593Smuzhiyun struct i2c_client *i2c_client[AF9035_I2C_CLIENT_MAX]; 64*4882a593Smuzhiyun struct i2c_adapter *i2c_adapter_demod; 65*4882a593Smuzhiyun struct platform_device *platform_device_tuner[2]; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun struct address_table { 69*4882a593Smuzhiyun u8 frontend_i2c_addr; 70*4882a593Smuzhiyun u8 tuner_i2c_addr; 71*4882a593Smuzhiyun u8 tuner_if_port; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun static const struct address_table it930x_addresses_table[] = { 75*4882a593Smuzhiyun { 0x67, 0x63, 1 }, 76*4882a593Smuzhiyun { 0x64, 0x60, 0 }, 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun static const u32 clock_lut_af9035[] = { 80*4882a593Smuzhiyun 20480000, /* FPGA */ 81*4882a593Smuzhiyun 16384000, /* 16.38 MHz */ 82*4882a593Smuzhiyun 20480000, /* 20.48 MHz */ 83*4882a593Smuzhiyun 36000000, /* 36.00 MHz */ 84*4882a593Smuzhiyun 30000000, /* 30.00 MHz */ 85*4882a593Smuzhiyun 26000000, /* 26.00 MHz */ 86*4882a593Smuzhiyun 28000000, /* 28.00 MHz */ 87*4882a593Smuzhiyun 32000000, /* 32.00 MHz */ 88*4882a593Smuzhiyun 34000000, /* 34.00 MHz */ 89*4882a593Smuzhiyun 24000000, /* 24.00 MHz */ 90*4882a593Smuzhiyun 22000000, /* 22.00 MHz */ 91*4882a593Smuzhiyun 12000000, /* 12.00 MHz */ 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun static const u32 clock_lut_it9135[] = { 95*4882a593Smuzhiyun 12000000, /* 12.00 MHz */ 96*4882a593Smuzhiyun 20480000, /* 20.48 MHz */ 97*4882a593Smuzhiyun 36000000, /* 36.00 MHz */ 98*4882a593Smuzhiyun 30000000, /* 30.00 MHz */ 99*4882a593Smuzhiyun 26000000, /* 26.00 MHz */ 100*4882a593Smuzhiyun 28000000, /* 28.00 MHz */ 101*4882a593Smuzhiyun 32000000, /* 32.00 MHz */ 102*4882a593Smuzhiyun 34000000, /* 34.00 MHz */ 103*4882a593Smuzhiyun 24000000, /* 24.00 MHz */ 104*4882a593Smuzhiyun 22000000, /* 22.00 MHz */ 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define AF9035_FIRMWARE_AF9035 "dvb-usb-af9035-02.fw" 108*4882a593Smuzhiyun #define AF9035_FIRMWARE_IT9135_V1 "dvb-usb-it9135-01.fw" 109*4882a593Smuzhiyun #define AF9035_FIRMWARE_IT9135_V2 "dvb-usb-it9135-02.fw" 110*4882a593Smuzhiyun #define AF9035_FIRMWARE_IT9303 "dvb-usb-it9303-01.fw" 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* 113*4882a593Smuzhiyun * eeprom is memory mapped as read only. Writing that memory mapped address 114*4882a593Smuzhiyun * will not corrupt eeprom. 115*4882a593Smuzhiyun * 116*4882a593Smuzhiyun * TS mode: 117*4882a593Smuzhiyun * 0 TS 118*4882a593Smuzhiyun * 1 DCA + PIP 119*4882a593Smuzhiyun * 3 PIP 120*4882a593Smuzhiyun * 5 DCA + PIP (AF9035 only) 121*4882a593Smuzhiyun * n DCA 122*4882a593Smuzhiyun * 123*4882a593Smuzhiyun * Values 0, 3 and 5 are seen to this day. 0 for single TS and 3/5 for dual TS. 124*4882a593Smuzhiyun */ 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define EEPROM_BASE_AF9035 0x42f5 127*4882a593Smuzhiyun #define EEPROM_BASE_IT9135 0x4994 128*4882a593Smuzhiyun #define EEPROM_SHIFT 0x10 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define EEPROM_IR_MODE 0x18 131*4882a593Smuzhiyun #define EEPROM_TS_MODE 0x31 132*4882a593Smuzhiyun #define EEPROM_2ND_DEMOD_ADDR 0x32 133*4882a593Smuzhiyun #define EEPROM_IR_TYPE 0x34 134*4882a593Smuzhiyun #define EEPROM_1_IF_L 0x38 135*4882a593Smuzhiyun #define EEPROM_1_IF_H 0x39 136*4882a593Smuzhiyun #define EEPROM_1_TUNER_ID 0x3c 137*4882a593Smuzhiyun #define EEPROM_2_IF_L 0x48 138*4882a593Smuzhiyun #define EEPROM_2_IF_H 0x49 139*4882a593Smuzhiyun #define EEPROM_2_TUNER_ID 0x4c 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* USB commands */ 142*4882a593Smuzhiyun #define CMD_MEM_RD 0x00 143*4882a593Smuzhiyun #define CMD_MEM_WR 0x01 144*4882a593Smuzhiyun #define CMD_I2C_RD 0x02 145*4882a593Smuzhiyun #define CMD_I2C_WR 0x03 146*4882a593Smuzhiyun #define CMD_IR_GET 0x18 147*4882a593Smuzhiyun #define CMD_FW_DL 0x21 148*4882a593Smuzhiyun #define CMD_FW_QUERYINFO 0x22 149*4882a593Smuzhiyun #define CMD_FW_BOOT 0x23 150*4882a593Smuzhiyun #define CMD_FW_DL_BEGIN 0x24 151*4882a593Smuzhiyun #define CMD_FW_DL_END 0x25 152*4882a593Smuzhiyun #define CMD_FW_SCATTER_WR 0x29 153*4882a593Smuzhiyun #define CMD_GENERIC_I2C_RD 0x2a 154*4882a593Smuzhiyun #define CMD_GENERIC_I2C_WR 0x2b 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #endif 157