1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun cx231xx.h - driver for Conexant Cx23100/101/102 USB video capture devices
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6*4882a593Smuzhiyun Based on em28xx driver
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #ifndef _CX231XX_H
11*4882a593Smuzhiyun #define _CX231XX_H
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/videodev2.h>
14*4882a593Smuzhiyun #include <linux/types.h>
15*4882a593Smuzhiyun #include <linux/ioctl.h>
16*4882a593Smuzhiyun #include <linux/i2c.h>
17*4882a593Smuzhiyun #include <linux/workqueue.h>
18*4882a593Smuzhiyun #include <linux/mutex.h>
19*4882a593Smuzhiyun #include <linux/usb.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <media/drv-intf/cx2341x.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <media/videobuf2-vmalloc.h>
24*4882a593Smuzhiyun #include <media/v4l2-device.h>
25*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
26*4882a593Smuzhiyun #include <media/v4l2-fh.h>
27*4882a593Smuzhiyun #include <media/rc-core.h>
28*4882a593Smuzhiyun #include <media/i2c/ir-kbd-i2c.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #include "cx231xx-reg.h"
31*4882a593Smuzhiyun #include "cx231xx-pcb-cfg.h"
32*4882a593Smuzhiyun #include "cx231xx-conf-reg.h"
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define DRIVER_NAME "cx231xx"
35*4882a593Smuzhiyun #define PWR_SLEEP_INTERVAL 10
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* I2C addresses for control block in Cx231xx */
38*4882a593Smuzhiyun #define AFE_DEVICE_ADDRESS 0x60
39*4882a593Smuzhiyun #define I2S_BLK_DEVICE_ADDRESS 0x98
40*4882a593Smuzhiyun #define VID_BLK_I2C_ADDRESS 0x88
41*4882a593Smuzhiyun #define VERVE_I2C_ADDRESS 0x40
42*4882a593Smuzhiyun #define DIF_USE_BASEBAND 0xFFFFFFFF
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* Boards supported by driver */
45*4882a593Smuzhiyun #define CX231XX_BOARD_UNKNOWN 0
46*4882a593Smuzhiyun #define CX231XX_BOARD_CNXT_CARRAERA 1
47*4882a593Smuzhiyun #define CX231XX_BOARD_CNXT_SHELBY 2
48*4882a593Smuzhiyun #define CX231XX_BOARD_CNXT_RDE_253S 3
49*4882a593Smuzhiyun #define CX231XX_BOARD_CNXT_RDU_253S 4
50*4882a593Smuzhiyun #define CX231XX_BOARD_CNXT_VIDEO_GRABBER 5
51*4882a593Smuzhiyun #define CX231XX_BOARD_CNXT_RDE_250 6
52*4882a593Smuzhiyun #define CX231XX_BOARD_CNXT_RDU_250 7
53*4882a593Smuzhiyun #define CX231XX_BOARD_HAUPPAUGE_EXETER 8
54*4882a593Smuzhiyun #define CX231XX_BOARD_HAUPPAUGE_USBLIVE2 9
55*4882a593Smuzhiyun #define CX231XX_BOARD_PV_PLAYTV_USB_HYBRID 10
56*4882a593Smuzhiyun #define CX231XX_BOARD_PV_XCAPTURE_USB 11
57*4882a593Smuzhiyun #define CX231XX_BOARD_KWORLD_UB430_USB_HYBRID 12
58*4882a593Smuzhiyun #define CX231XX_BOARD_ICONBIT_U100 13
59*4882a593Smuzhiyun #define CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL 14
60*4882a593Smuzhiyun #define CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC 15
61*4882a593Smuzhiyun #define CX231XX_BOARD_ELGATO_VIDEO_CAPTURE_V2 16
62*4882a593Smuzhiyun #define CX231XX_BOARD_OTG102 17
63*4882a593Smuzhiyun #define CX231XX_BOARD_KWORLD_UB445_USB_HYBRID 18
64*4882a593Smuzhiyun #define CX231XX_BOARD_HAUPPAUGE_930C_HD_1113xx 19
65*4882a593Smuzhiyun #define CX231XX_BOARD_HAUPPAUGE_930C_HD_1114xx 20
66*4882a593Smuzhiyun #define CX231XX_BOARD_HAUPPAUGE_955Q 21
67*4882a593Smuzhiyun #define CX231XX_BOARD_TERRATEC_GRABBY 22
68*4882a593Smuzhiyun #define CX231XX_BOARD_EVROMEDIA_FULL_HYBRID_FULLHD 23
69*4882a593Smuzhiyun #define CX231XX_BOARD_ASTROMETA_T2HYBRID 24
70*4882a593Smuzhiyun #define CX231XX_BOARD_THE_IMAGING_SOURCE_DFG_USB2_PRO 25
71*4882a593Smuzhiyun #define CX231XX_BOARD_HAUPPAUGE_935C 26
72*4882a593Smuzhiyun #define CX231XX_BOARD_HAUPPAUGE_975 27
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* Limits minimum and default number of buffers */
75*4882a593Smuzhiyun #define CX231XX_MIN_BUF 4
76*4882a593Smuzhiyun #define CX231XX_DEF_BUF 12
77*4882a593Smuzhiyun #define CX231XX_DEF_VBI_BUF 6
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun #define VBI_LINE_COUNT 17
80*4882a593Smuzhiyun #define VBI_LINE_LENGTH 1440
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /*Limits the max URB message size */
83*4882a593Smuzhiyun #define URB_MAX_CTRL_SIZE 80
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* Params for validated field */
86*4882a593Smuzhiyun #define CX231XX_BOARD_NOT_VALIDATED 1
87*4882a593Smuzhiyun #define CX231XX_BOARD_VALIDATED 0
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* maximum number of cx231xx boards */
90*4882a593Smuzhiyun #define CX231XX_MAXBOARDS 8
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /* maximum number of frames that can be queued */
93*4882a593Smuzhiyun #define CX231XX_NUM_FRAMES 5
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* number of buffers for isoc transfers */
96*4882a593Smuzhiyun #define CX231XX_NUM_BUFS 8
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun /* number of packets for each buffer
99*4882a593Smuzhiyun windows requests only 40 packets .. so we better do the same
100*4882a593Smuzhiyun this is what I found out for all alternate numbers there!
101*4882a593Smuzhiyun */
102*4882a593Smuzhiyun #define CX231XX_NUM_PACKETS 40
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* default alternate; 0 means choose the best */
105*4882a593Smuzhiyun #define CX231XX_PINOUT 0
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun #define CX231XX_INTERLACED_DEFAULT 1
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* time to wait when stopping the isoc transfer */
110*4882a593Smuzhiyun #define CX231XX_URB_TIMEOUT \
111*4882a593Smuzhiyun msecs_to_jiffies(CX231XX_NUM_BUFS * CX231XX_NUM_PACKETS)
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun #define CX231xx_NORMS (\
114*4882a593Smuzhiyun V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \
115*4882a593Smuzhiyun V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
116*4882a593Smuzhiyun V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \
117*4882a593Smuzhiyun V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK)
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun #define SLEEP_S5H1432 30
120*4882a593Smuzhiyun #define CX23417_OSC_EN 8
121*4882a593Smuzhiyun #define CX23417_RESET 9
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun struct cx23417_fmt {
124*4882a593Smuzhiyun u32 fourcc; /* v4l2 format id */
125*4882a593Smuzhiyun int depth;
126*4882a593Smuzhiyun int flags;
127*4882a593Smuzhiyun u32 cxformat;
128*4882a593Smuzhiyun };
129*4882a593Smuzhiyun enum cx231xx_mode {
130*4882a593Smuzhiyun CX231XX_SUSPEND,
131*4882a593Smuzhiyun CX231XX_ANALOG_MODE,
132*4882a593Smuzhiyun CX231XX_DIGITAL_MODE,
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun enum cx231xx_std_mode {
136*4882a593Smuzhiyun CX231XX_TV_AIR = 0,
137*4882a593Smuzhiyun CX231XX_TV_CABLE
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun enum cx231xx_stream_state {
141*4882a593Smuzhiyun STREAM_OFF,
142*4882a593Smuzhiyun STREAM_INTERRUPT,
143*4882a593Smuzhiyun STREAM_ON,
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun struct cx231xx;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun struct cx231xx_isoc_ctl {
149*4882a593Smuzhiyun /* max packet size of isoc transaction */
150*4882a593Smuzhiyun int max_pkt_size;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun /* number of allocated urbs */
153*4882a593Smuzhiyun int num_bufs;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun /* urb for isoc transfers */
156*4882a593Smuzhiyun struct urb **urb;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun /* transfer buffers for isoc transfer */
159*4882a593Smuzhiyun char **transfer_buffer;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun /* Last buffer command and region */
162*4882a593Smuzhiyun u8 cmd;
163*4882a593Smuzhiyun int pos, size, pktsize;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun /* Last field: ODD or EVEN? */
166*4882a593Smuzhiyun int field;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun /* Stores incomplete commands */
169*4882a593Smuzhiyun u32 tmp_buf;
170*4882a593Smuzhiyun int tmp_buf_len;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun /* Stores already requested buffers */
173*4882a593Smuzhiyun struct cx231xx_buffer *buf;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun /* Stores the number of received fields */
176*4882a593Smuzhiyun int nfields;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun /* isoc urb callback */
179*4882a593Smuzhiyun int (*isoc_copy) (struct cx231xx *dev, struct urb *urb);
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun struct cx231xx_bulk_ctl {
183*4882a593Smuzhiyun /* max packet size of bulk transaction */
184*4882a593Smuzhiyun int max_pkt_size;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun /* number of allocated urbs */
187*4882a593Smuzhiyun int num_bufs;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun /* urb for bulk transfers */
190*4882a593Smuzhiyun struct urb **urb;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun /* transfer buffers for bulk transfer */
193*4882a593Smuzhiyun char **transfer_buffer;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun /* Last buffer command and region */
196*4882a593Smuzhiyun u8 cmd;
197*4882a593Smuzhiyun int pos, size, pktsize;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun /* Last field: ODD or EVEN? */
200*4882a593Smuzhiyun int field;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun /* Stores incomplete commands */
203*4882a593Smuzhiyun u32 tmp_buf;
204*4882a593Smuzhiyun int tmp_buf_len;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun /* Stores already requested buffers */
207*4882a593Smuzhiyun struct cx231xx_buffer *buf;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun /* Stores the number of received fields */
210*4882a593Smuzhiyun int nfields;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun /* bulk urb callback */
213*4882a593Smuzhiyun int (*bulk_copy) (struct cx231xx *dev, struct urb *urb);
214*4882a593Smuzhiyun };
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun struct cx231xx_fmt {
217*4882a593Smuzhiyun char *name;
218*4882a593Smuzhiyun u32 fourcc; /* v4l2 format id */
219*4882a593Smuzhiyun int depth;
220*4882a593Smuzhiyun int reg;
221*4882a593Smuzhiyun };
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun /* buffer for one video frame */
224*4882a593Smuzhiyun struct cx231xx_buffer {
225*4882a593Smuzhiyun /* common v4l buffer stuff -- must be first */
226*4882a593Smuzhiyun struct vb2_v4l2_buffer vb;
227*4882a593Smuzhiyun struct list_head list;
228*4882a593Smuzhiyun struct list_head frame;
229*4882a593Smuzhiyun int top_field;
230*4882a593Smuzhiyun int receiving;
231*4882a593Smuzhiyun };
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun enum ps_package_head {
234*4882a593Smuzhiyun CX231XX_NEED_ADD_PS_PACKAGE_HEAD = 0,
235*4882a593Smuzhiyun CX231XX_NONEED_PS_PACKAGE_HEAD
236*4882a593Smuzhiyun };
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun struct cx231xx_dmaqueue {
239*4882a593Smuzhiyun struct list_head active;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun wait_queue_head_t wq;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun /* Counters to control buffer fill */
244*4882a593Smuzhiyun int pos;
245*4882a593Smuzhiyun u8 is_partial_line;
246*4882a593Smuzhiyun u8 partial_buf[8];
247*4882a593Smuzhiyun u8 last_sav;
248*4882a593Smuzhiyun int current_field;
249*4882a593Smuzhiyun u32 bytes_left_in_line;
250*4882a593Smuzhiyun u32 lines_completed;
251*4882a593Smuzhiyun u8 field1_done;
252*4882a593Smuzhiyun u32 lines_per_field;
253*4882a593Smuzhiyun u32 sequence;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun /*Mpeg2 control buffer*/
256*4882a593Smuzhiyun u8 *p_left_data;
257*4882a593Smuzhiyun u32 left_data_count;
258*4882a593Smuzhiyun u8 mpeg_buffer_done;
259*4882a593Smuzhiyun u32 mpeg_buffer_completed;
260*4882a593Smuzhiyun enum ps_package_head add_ps_package_head;
261*4882a593Smuzhiyun char ps_head[10];
262*4882a593Smuzhiyun };
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun /* inputs */
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun #define MAX_CX231XX_INPUT 4
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun enum cx231xx_itype {
269*4882a593Smuzhiyun CX231XX_VMUX_COMPOSITE1 = 1,
270*4882a593Smuzhiyun CX231XX_VMUX_SVIDEO,
271*4882a593Smuzhiyun CX231XX_VMUX_TELEVISION,
272*4882a593Smuzhiyun CX231XX_VMUX_CABLE,
273*4882a593Smuzhiyun CX231XX_RADIO,
274*4882a593Smuzhiyun CX231XX_VMUX_DVB,
275*4882a593Smuzhiyun };
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun enum cx231xx_v_input {
278*4882a593Smuzhiyun CX231XX_VIN_1_1 = 0x1,
279*4882a593Smuzhiyun CX231XX_VIN_2_1,
280*4882a593Smuzhiyun CX231XX_VIN_3_1,
281*4882a593Smuzhiyun CX231XX_VIN_4_1,
282*4882a593Smuzhiyun CX231XX_VIN_1_2 = 0x01,
283*4882a593Smuzhiyun CX231XX_VIN_2_2,
284*4882a593Smuzhiyun CX231XX_VIN_3_2,
285*4882a593Smuzhiyun CX231XX_VIN_1_3 = 0x1,
286*4882a593Smuzhiyun CX231XX_VIN_2_3,
287*4882a593Smuzhiyun CX231XX_VIN_3_3,
288*4882a593Smuzhiyun };
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun /* cx231xx has two audio inputs: tuner and line in */
291*4882a593Smuzhiyun enum cx231xx_amux {
292*4882a593Smuzhiyun /* This is the only entry for cx231xx tuner input */
293*4882a593Smuzhiyun CX231XX_AMUX_VIDEO, /* cx231xx tuner */
294*4882a593Smuzhiyun CX231XX_AMUX_LINE_IN, /* Line In */
295*4882a593Smuzhiyun };
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun struct cx231xx_reg_seq {
298*4882a593Smuzhiyun unsigned char bit;
299*4882a593Smuzhiyun unsigned char val;
300*4882a593Smuzhiyun int sleep;
301*4882a593Smuzhiyun };
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun struct cx231xx_input {
304*4882a593Smuzhiyun enum cx231xx_itype type;
305*4882a593Smuzhiyun unsigned int vmux;
306*4882a593Smuzhiyun enum cx231xx_amux amux;
307*4882a593Smuzhiyun struct cx231xx_reg_seq *gpio;
308*4882a593Smuzhiyun };
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun #define INPUT(nr) (&cx231xx_boards[dev->model].input[nr])
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun enum cx231xx_decoder {
313*4882a593Smuzhiyun CX231XX_NODECODER,
314*4882a593Smuzhiyun CX231XX_AVDECODER
315*4882a593Smuzhiyun };
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun enum CX231XX_I2C_MASTER_PORT {
318*4882a593Smuzhiyun I2C_0 = 0, /* master 0 - internal connection */
319*4882a593Smuzhiyun I2C_1 = 1, /* master 1 - used with mux */
320*4882a593Smuzhiyun I2C_2 = 2, /* master 2 */
321*4882a593Smuzhiyun I2C_1_MUX_1 = 3, /* master 1 - port 1 (I2C_DEMOD_EN = 0) */
322*4882a593Smuzhiyun I2C_1_MUX_3 = 4 /* master 1 - port 3 (I2C_DEMOD_EN = 1) */
323*4882a593Smuzhiyun };
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun struct cx231xx_board {
326*4882a593Smuzhiyun char *name;
327*4882a593Smuzhiyun int vchannels;
328*4882a593Smuzhiyun int tuner_type;
329*4882a593Smuzhiyun int tuner_addr;
330*4882a593Smuzhiyun v4l2_std_id norm; /* tv norm */
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun /* demod related */
333*4882a593Smuzhiyun int demod_addr;
334*4882a593Smuzhiyun int demod_addr2;
335*4882a593Smuzhiyun u8 demod_xfer_mode; /* 0 - Serial; 1 - parallel */
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun /* GPIO Pins */
338*4882a593Smuzhiyun struct cx231xx_reg_seq *dvb_gpio;
339*4882a593Smuzhiyun struct cx231xx_reg_seq *suspend_gpio;
340*4882a593Smuzhiyun struct cx231xx_reg_seq *tuner_gpio;
341*4882a593Smuzhiyun /* Negative means don't use it */
342*4882a593Smuzhiyun s8 tuner_sif_gpio;
343*4882a593Smuzhiyun s8 tuner_scl_gpio;
344*4882a593Smuzhiyun s8 tuner_sda_gpio;
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun /* PIN ctrl */
347*4882a593Smuzhiyun u32 ctl_pin_status_mask;
348*4882a593Smuzhiyun u8 agc_analog_digital_select_gpio;
349*4882a593Smuzhiyun u32 gpio_pin_status_mask;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun /* i2c masters */
352*4882a593Smuzhiyun u8 tuner_i2c_master;
353*4882a593Smuzhiyun u8 demod_i2c_master;
354*4882a593Smuzhiyun u8 ir_i2c_master;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun /* for devices with I2C chips for IR */
357*4882a593Smuzhiyun char *rc_map_name;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun unsigned int max_range_640_480:1;
360*4882a593Smuzhiyun unsigned int has_dvb:1;
361*4882a593Smuzhiyun unsigned int has_417:1;
362*4882a593Smuzhiyun unsigned int valid:1;
363*4882a593Smuzhiyun unsigned int no_alt_vanc:1;
364*4882a593Smuzhiyun unsigned int external_av:1;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun unsigned char xclk, i2c_speed;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun enum cx231xx_decoder decoder;
369*4882a593Smuzhiyun int output_mode;
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun struct cx231xx_input input[MAX_CX231XX_INPUT];
372*4882a593Smuzhiyun struct cx231xx_input radio;
373*4882a593Smuzhiyun struct rc_map *ir_codes;
374*4882a593Smuzhiyun };
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun /* device states */
377*4882a593Smuzhiyun enum cx231xx_dev_state {
378*4882a593Smuzhiyun DEV_INITIALIZED = 0x01,
379*4882a593Smuzhiyun DEV_DISCONNECTED = 0x02,
380*4882a593Smuzhiyun };
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun enum AFE_MODE {
383*4882a593Smuzhiyun AFE_MODE_LOW_IF,
384*4882a593Smuzhiyun AFE_MODE_BASEBAND,
385*4882a593Smuzhiyun AFE_MODE_EU_HI_IF,
386*4882a593Smuzhiyun AFE_MODE_US_HI_IF,
387*4882a593Smuzhiyun AFE_MODE_JAPAN_HI_IF
388*4882a593Smuzhiyun };
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun enum AUDIO_INPUT {
391*4882a593Smuzhiyun AUDIO_INPUT_MUTE,
392*4882a593Smuzhiyun AUDIO_INPUT_LINE,
393*4882a593Smuzhiyun AUDIO_INPUT_TUNER_TV,
394*4882a593Smuzhiyun AUDIO_INPUT_SPDIF,
395*4882a593Smuzhiyun AUDIO_INPUT_TUNER_FM
396*4882a593Smuzhiyun };
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun #define CX231XX_AUDIO_BUFS 5
399*4882a593Smuzhiyun #define CX231XX_NUM_AUDIO_PACKETS 16
400*4882a593Smuzhiyun #define CX231XX_ISO_NUM_AUDIO_PACKETS 64
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun /* cx231xx extensions */
403*4882a593Smuzhiyun #define CX231XX_AUDIO 0x10
404*4882a593Smuzhiyun #define CX231XX_DVB 0x20
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun struct cx231xx_audio {
407*4882a593Smuzhiyun char name[50];
408*4882a593Smuzhiyun char *transfer_buffer[CX231XX_AUDIO_BUFS];
409*4882a593Smuzhiyun struct urb *urb[CX231XX_AUDIO_BUFS];
410*4882a593Smuzhiyun struct usb_device *udev;
411*4882a593Smuzhiyun unsigned int capture_transfer_done;
412*4882a593Smuzhiyun struct snd_pcm_substream *capture_pcm_substream;
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun unsigned int hwptr_done_capture;
415*4882a593Smuzhiyun struct snd_card *sndcard;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun int users, shutdown;
418*4882a593Smuzhiyun /* locks */
419*4882a593Smuzhiyun spinlock_t slock;
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun int alt; /* alternate */
422*4882a593Smuzhiyun int max_pkt_size; /* max packet size of isoc transaction */
423*4882a593Smuzhiyun int num_alt; /* Number of alternative settings */
424*4882a593Smuzhiyun unsigned int *alt_max_pkt_size; /* array of wMaxPacketSize */
425*4882a593Smuzhiyun u16 end_point_addr;
426*4882a593Smuzhiyun };
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun struct cx231xx;
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun /*****************************************************************/
431*4882a593Smuzhiyun /* set/get i2c */
432*4882a593Smuzhiyun /* 00--1Mb/s, 01-400kb/s, 10--100kb/s, 11--5Mb/s */
433*4882a593Smuzhiyun #define I2C_SPEED_1M 0x0
434*4882a593Smuzhiyun #define I2C_SPEED_400K 0x1
435*4882a593Smuzhiyun #define I2C_SPEED_100K 0x2
436*4882a593Smuzhiyun #define I2C_SPEED_5M 0x3
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun /* 0-- STOP transaction */
439*4882a593Smuzhiyun #define I2C_STOP 0x0
440*4882a593Smuzhiyun /* 1-- do not transmit STOP at end of transaction */
441*4882a593Smuzhiyun #define I2C_NOSTOP 0x1
442*4882a593Smuzhiyun /* 1--allow slave to insert clock wait states */
443*4882a593Smuzhiyun #define I2C_SYNC 0x1
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun struct cx231xx_i2c {
446*4882a593Smuzhiyun struct cx231xx *dev;
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun int nr;
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun /* i2c i/o */
451*4882a593Smuzhiyun struct i2c_adapter i2c_adap;
452*4882a593Smuzhiyun int i2c_rc;
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun /* different settings for each bus */
455*4882a593Smuzhiyun u8 i2c_period;
456*4882a593Smuzhiyun u8 i2c_nostop;
457*4882a593Smuzhiyun u8 i2c_reserve;
458*4882a593Smuzhiyun };
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun struct cx231xx_i2c_xfer_data {
461*4882a593Smuzhiyun u8 dev_addr;
462*4882a593Smuzhiyun u8 direction; /* 1 - IN, 0 - OUT */
463*4882a593Smuzhiyun u8 saddr_len; /* sub address len */
464*4882a593Smuzhiyun u16 saddr_dat; /* sub addr data */
465*4882a593Smuzhiyun u8 buf_size; /* buffer size */
466*4882a593Smuzhiyun u8 *p_buffer; /* pointer to the buffer */
467*4882a593Smuzhiyun };
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun struct VENDOR_REQUEST_IN {
470*4882a593Smuzhiyun u8 bRequest;
471*4882a593Smuzhiyun u16 wValue;
472*4882a593Smuzhiyun u16 wIndex;
473*4882a593Smuzhiyun u16 wLength;
474*4882a593Smuzhiyun u8 direction;
475*4882a593Smuzhiyun u8 bData;
476*4882a593Smuzhiyun u8 *pBuff;
477*4882a593Smuzhiyun };
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun struct cx231xx_tvnorm {
480*4882a593Smuzhiyun char *name;
481*4882a593Smuzhiyun v4l2_std_id id;
482*4882a593Smuzhiyun u32 cxiformat;
483*4882a593Smuzhiyun u32 cxoformat;
484*4882a593Smuzhiyun };
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun enum TRANSFER_TYPE {
487*4882a593Smuzhiyun Raw_Video = 0,
488*4882a593Smuzhiyun Audio,
489*4882a593Smuzhiyun Vbi, /* VANC */
490*4882a593Smuzhiyun Sliced_cc, /* HANC */
491*4882a593Smuzhiyun TS1_serial_mode,
492*4882a593Smuzhiyun TS2,
493*4882a593Smuzhiyun TS1_parallel_mode
494*4882a593Smuzhiyun } ;
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun struct cx231xx_video_mode {
497*4882a593Smuzhiyun /* Isoc control struct */
498*4882a593Smuzhiyun struct cx231xx_dmaqueue vidq;
499*4882a593Smuzhiyun struct cx231xx_isoc_ctl isoc_ctl;
500*4882a593Smuzhiyun struct cx231xx_bulk_ctl bulk_ctl;
501*4882a593Smuzhiyun /* locks */
502*4882a593Smuzhiyun spinlock_t slock;
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun /* usb transfer */
505*4882a593Smuzhiyun int alt; /* alternate */
506*4882a593Smuzhiyun int max_pkt_size; /* max packet size of isoc transaction */
507*4882a593Smuzhiyun int num_alt; /* Number of alternative settings */
508*4882a593Smuzhiyun unsigned int *alt_max_pkt_size; /* array of wMaxPacketSize */
509*4882a593Smuzhiyun u16 end_point_addr;
510*4882a593Smuzhiyun };
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun struct cx231xx_tsport {
513*4882a593Smuzhiyun struct cx231xx *dev;
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun int nr;
516*4882a593Smuzhiyun int sram_chno;
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun /* dma queues */
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun u32 ts_packet_size;
521*4882a593Smuzhiyun u32 ts_packet_count;
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun int width;
524*4882a593Smuzhiyun int height;
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun /* locks */
527*4882a593Smuzhiyun spinlock_t slock;
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun /* registers */
530*4882a593Smuzhiyun u32 reg_gpcnt;
531*4882a593Smuzhiyun u32 reg_gpcnt_ctl;
532*4882a593Smuzhiyun u32 reg_dma_ctl;
533*4882a593Smuzhiyun u32 reg_lngth;
534*4882a593Smuzhiyun u32 reg_hw_sop_ctrl;
535*4882a593Smuzhiyun u32 reg_gen_ctrl;
536*4882a593Smuzhiyun u32 reg_bd_pkt_status;
537*4882a593Smuzhiyun u32 reg_sop_status;
538*4882a593Smuzhiyun u32 reg_fifo_ovfl_stat;
539*4882a593Smuzhiyun u32 reg_vld_misc;
540*4882a593Smuzhiyun u32 reg_ts_clk_en;
541*4882a593Smuzhiyun u32 reg_ts_int_msk;
542*4882a593Smuzhiyun u32 reg_ts_int_stat;
543*4882a593Smuzhiyun u32 reg_src_sel;
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun /* Default register vals */
546*4882a593Smuzhiyun int pci_irqmask;
547*4882a593Smuzhiyun u32 dma_ctl_val;
548*4882a593Smuzhiyun u32 ts_int_msk_val;
549*4882a593Smuzhiyun u32 gen_ctrl_val;
550*4882a593Smuzhiyun u32 ts_clk_en_val;
551*4882a593Smuzhiyun u32 src_sel_val;
552*4882a593Smuzhiyun u32 vld_misc_val;
553*4882a593Smuzhiyun u32 hw_sop_ctrl_val;
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun /* Allow a single tsport to have multiple frontends */
556*4882a593Smuzhiyun u32 num_frontends;
557*4882a593Smuzhiyun void *port_priv;
558*4882a593Smuzhiyun };
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun /* main device struct */
561*4882a593Smuzhiyun struct cx231xx {
562*4882a593Smuzhiyun /* generic device properties */
563*4882a593Smuzhiyun char name[30]; /* name (including minor) of the device */
564*4882a593Smuzhiyun int model; /* index in the device_data struct */
565*4882a593Smuzhiyun int devno; /* marks the number of this device */
566*4882a593Smuzhiyun struct device *dev; /* pointer to USB interface's dev */
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun struct cx231xx_board board;
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun /* For I2C IR support */
571*4882a593Smuzhiyun struct IR_i2c_init_data init_data;
572*4882a593Smuzhiyun struct i2c_client *ir_i2c_client;
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun unsigned int stream_on:1; /* Locks streams */
575*4882a593Smuzhiyun unsigned int vbi_stream_on:1; /* Locks streams for VBI */
576*4882a593Smuzhiyun unsigned int has_audio_class:1;
577*4882a593Smuzhiyun unsigned int has_alsa_audio:1;
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun unsigned int i2c_scan_running:1; /* true only during i2c_scan */
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun struct cx231xx_fmt *format;
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun struct v4l2_device v4l2_dev;
584*4882a593Smuzhiyun struct v4l2_subdev *sd_cx25840;
585*4882a593Smuzhiyun struct v4l2_subdev *sd_tuner;
586*4882a593Smuzhiyun struct v4l2_ctrl_handler ctrl_handler;
587*4882a593Smuzhiyun struct v4l2_ctrl_handler radio_ctrl_handler;
588*4882a593Smuzhiyun struct cx2341x_handler mpeg_ctrl_handler;
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun struct work_struct wq_trigger; /* Trigger to start/stop audio for alsa module */
591*4882a593Smuzhiyun atomic_t stream_started; /* stream should be running if true */
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun struct list_head devlist;
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun int tuner_type; /* type of the tuner */
596*4882a593Smuzhiyun int tuner_addr; /* tuner address */
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
599*4882a593Smuzhiyun struct cx231xx_i2c i2c_bus[3];
600*4882a593Smuzhiyun struct i2c_mux_core *muxc;
601*4882a593Smuzhiyun struct i2c_adapter *i2c_mux_adap[2];
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun unsigned int xc_fw_load_done:1;
604*4882a593Smuzhiyun unsigned int port_3_switch_enabled:1;
605*4882a593Smuzhiyun /* locks */
606*4882a593Smuzhiyun struct mutex gpio_i2c_lock;
607*4882a593Smuzhiyun struct mutex i2c_lock;
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun /* video for linux */
610*4882a593Smuzhiyun int users; /* user count for exclusive use */
611*4882a593Smuzhiyun struct video_device vdev; /* video for linux device struct */
612*4882a593Smuzhiyun v4l2_std_id norm; /* selected tv norm */
613*4882a593Smuzhiyun int ctl_freq; /* selected frequency */
614*4882a593Smuzhiyun unsigned int ctl_ainput; /* selected audio input */
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun /* frame properties */
617*4882a593Smuzhiyun int width; /* current frame width */
618*4882a593Smuzhiyun int height; /* current frame height */
619*4882a593Smuzhiyun int interlaced; /* 1=interlace fields, 0=just top fields */
620*4882a593Smuzhiyun unsigned int size;
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun struct cx231xx_audio adev;
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun /* states */
625*4882a593Smuzhiyun enum cx231xx_dev_state state;
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun struct work_struct request_module_wk;
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun /* locks */
630*4882a593Smuzhiyun struct mutex lock;
631*4882a593Smuzhiyun struct mutex ctrl_urb_lock; /* protects urb_buf */
632*4882a593Smuzhiyun struct list_head inqueue, outqueue;
633*4882a593Smuzhiyun wait_queue_head_t open, wait_frame, wait_stream;
634*4882a593Smuzhiyun struct video_device vbi_dev;
635*4882a593Smuzhiyun struct video_device radio_dev;
636*4882a593Smuzhiyun
637*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
638*4882a593Smuzhiyun struct media_device *media_dev;
639*4882a593Smuzhiyun struct media_pad video_pad, vbi_pad;
640*4882a593Smuzhiyun struct media_entity input_ent[MAX_CX231XX_INPUT];
641*4882a593Smuzhiyun struct media_pad input_pad[MAX_CX231XX_INPUT];
642*4882a593Smuzhiyun #endif
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun struct vb2_queue vidq;
645*4882a593Smuzhiyun struct vb2_queue vbiq;
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun unsigned char eedata[256];
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun struct cx231xx_video_mode video_mode;
650*4882a593Smuzhiyun struct cx231xx_video_mode vbi_mode;
651*4882a593Smuzhiyun struct cx231xx_video_mode sliced_cc_mode;
652*4882a593Smuzhiyun struct cx231xx_video_mode ts1_mode;
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun atomic_t devlist_count;
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun struct usb_device *udev; /* the usb device */
657*4882a593Smuzhiyun char urb_buf[URB_MAX_CTRL_SIZE]; /* urb control msg buffer */
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun /* helper funcs that call usb_control_msg */
660*4882a593Smuzhiyun int (*cx231xx_read_ctrl_reg) (struct cx231xx *dev, u8 req, u16 reg,
661*4882a593Smuzhiyun char *buf, int len);
662*4882a593Smuzhiyun int (*cx231xx_write_ctrl_reg) (struct cx231xx *dev, u8 req, u16 reg,
663*4882a593Smuzhiyun char *buf, int len);
664*4882a593Smuzhiyun int (*cx231xx_send_usb_command) (struct cx231xx_i2c *i2c_bus,
665*4882a593Smuzhiyun struct cx231xx_i2c_xfer_data *req_data);
666*4882a593Smuzhiyun int (*cx231xx_gpio_i2c_read) (struct cx231xx *dev, u8 dev_addr,
667*4882a593Smuzhiyun u8 *buf, u8 len);
668*4882a593Smuzhiyun int (*cx231xx_gpio_i2c_write) (struct cx231xx *dev, u8 dev_addr,
669*4882a593Smuzhiyun u8 *buf, u8 len);
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun int (*cx231xx_set_analog_freq) (struct cx231xx *dev, u32 freq);
672*4882a593Smuzhiyun int (*cx231xx_reset_analog_tuner) (struct cx231xx *dev);
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun enum cx231xx_mode mode;
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun struct cx231xx_dvb *dvb;
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun /* Cx231xx supported PCB config's */
679*4882a593Smuzhiyun struct pcb_config current_pcb_config;
680*4882a593Smuzhiyun u8 current_scenario_idx;
681*4882a593Smuzhiyun u8 interface_count;
682*4882a593Smuzhiyun u8 max_iad_interface_count;
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun /* GPIO related register direction and values */
685*4882a593Smuzhiyun u32 gpio_dir;
686*4882a593Smuzhiyun u32 gpio_val;
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun /* Power Modes */
689*4882a593Smuzhiyun int power_mode;
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun /* afe parameters */
692*4882a593Smuzhiyun enum AFE_MODE afe_mode;
693*4882a593Smuzhiyun u32 afe_ref_count;
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun /* video related parameters */
696*4882a593Smuzhiyun u32 video_input;
697*4882a593Smuzhiyun u32 active_mode;
698*4882a593Smuzhiyun u8 vbi_or_sliced_cc_mode; /* 0 - vbi ; 1 - sliced cc mode */
699*4882a593Smuzhiyun enum cx231xx_std_mode std_mode; /* 0 - Air; 1 - cable */
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun /*mode: digital=1 or analog=0*/
702*4882a593Smuzhiyun u8 mode_tv;
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun u8 USE_ISO;
705*4882a593Smuzhiyun struct cx231xx_tvnorm encodernorm;
706*4882a593Smuzhiyun struct cx231xx_tsport ts1, ts2;
707*4882a593Smuzhiyun struct vb2_queue mpegq;
708*4882a593Smuzhiyun struct video_device v4l_device;
709*4882a593Smuzhiyun atomic_t v4l_reader_count;
710*4882a593Smuzhiyun u32 freq;
711*4882a593Smuzhiyun unsigned int input;
712*4882a593Smuzhiyun u32 cx23417_mailbox;
713*4882a593Smuzhiyun u32 __iomem *lmmio;
714*4882a593Smuzhiyun u8 __iomem *bmmio;
715*4882a593Smuzhiyun };
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun extern struct list_head cx231xx_devlist;
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun #define cx25840_call(cx231xx, o, f, args...) \
720*4882a593Smuzhiyun v4l2_subdev_call(cx231xx->sd_cx25840, o, f, ##args)
721*4882a593Smuzhiyun #define tuner_call(cx231xx, o, f, args...) \
722*4882a593Smuzhiyun v4l2_subdev_call(cx231xx->sd_tuner, o, f, ##args)
723*4882a593Smuzhiyun #define call_all(dev, o, f, args...) \
724*4882a593Smuzhiyun v4l2_device_call_until_err(&dev->v4l2_dev, 0, o, f, ##args)
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun struct cx231xx_ops {
727*4882a593Smuzhiyun struct list_head next;
728*4882a593Smuzhiyun char *name;
729*4882a593Smuzhiyun int id;
730*4882a593Smuzhiyun int (*init) (struct cx231xx *);
731*4882a593Smuzhiyun int (*fini) (struct cx231xx *);
732*4882a593Smuzhiyun };
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun /* call back functions in dvb module */
735*4882a593Smuzhiyun int cx231xx_set_analog_freq(struct cx231xx *dev, u32 freq);
736*4882a593Smuzhiyun int cx231xx_reset_analog_tuner(struct cx231xx *dev);
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun /* Provided by cx231xx-i2c.c */
739*4882a593Smuzhiyun void cx231xx_do_i2c_scan(struct cx231xx *dev, int i2c_port);
740*4882a593Smuzhiyun int cx231xx_i2c_register(struct cx231xx_i2c *bus);
741*4882a593Smuzhiyun void cx231xx_i2c_unregister(struct cx231xx_i2c *bus);
742*4882a593Smuzhiyun int cx231xx_i2c_mux_create(struct cx231xx *dev);
743*4882a593Smuzhiyun int cx231xx_i2c_mux_register(struct cx231xx *dev, int mux_no);
744*4882a593Smuzhiyun void cx231xx_i2c_mux_unregister(struct cx231xx *dev);
745*4882a593Smuzhiyun struct i2c_adapter *cx231xx_get_i2c_adap(struct cx231xx *dev, int i2c_port);
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun /* Internal block control functions */
748*4882a593Smuzhiyun int cx231xx_read_i2c_master(struct cx231xx *dev, u8 dev_addr, u16 saddr,
749*4882a593Smuzhiyun u8 saddr_len, u32 *data, u8 data_len, int master);
750*4882a593Smuzhiyun int cx231xx_write_i2c_master(struct cx231xx *dev, u8 dev_addr, u16 saddr,
751*4882a593Smuzhiyun u8 saddr_len, u32 data, u8 data_len, int master);
752*4882a593Smuzhiyun int cx231xx_read_i2c_data(struct cx231xx *dev, u8 dev_addr,
753*4882a593Smuzhiyun u16 saddr, u8 saddr_len, u32 *data, u8 data_len);
754*4882a593Smuzhiyun int cx231xx_write_i2c_data(struct cx231xx *dev, u8 dev_addr,
755*4882a593Smuzhiyun u16 saddr, u8 saddr_len, u32 data, u8 data_len);
756*4882a593Smuzhiyun int cx231xx_reg_mask_write(struct cx231xx *dev, u8 dev_addr, u8 size,
757*4882a593Smuzhiyun u16 register_address, u8 bit_start, u8 bit_end,
758*4882a593Smuzhiyun u32 value);
759*4882a593Smuzhiyun int cx231xx_read_modify_write_i2c_dword(struct cx231xx *dev, u8 dev_addr,
760*4882a593Smuzhiyun u16 saddr, u32 mask, u32 value);
761*4882a593Smuzhiyun u32 cx231xx_set_field(u32 field_mask, u32 data);
762*4882a593Smuzhiyun
763*4882a593Smuzhiyun /*verve r/w*/
764*4882a593Smuzhiyun void initGPIO(struct cx231xx *dev);
765*4882a593Smuzhiyun void uninitGPIO(struct cx231xx *dev);
766*4882a593Smuzhiyun /* afe related functions */
767*4882a593Smuzhiyun int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count);
768*4882a593Smuzhiyun int cx231xx_afe_init_channels(struct cx231xx *dev);
769*4882a593Smuzhiyun int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev);
770*4882a593Smuzhiyun int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux);
771*4882a593Smuzhiyun int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode);
772*4882a593Smuzhiyun int cx231xx_afe_update_power_control(struct cx231xx *dev,
773*4882a593Smuzhiyun enum AV_MODE avmode);
774*4882a593Smuzhiyun int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input);
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun /* i2s block related functions */
777*4882a593Smuzhiyun int cx231xx_i2s_blk_initialize(struct cx231xx *dev);
778*4882a593Smuzhiyun int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
779*4882a593Smuzhiyun enum AV_MODE avmode);
780*4882a593Smuzhiyun int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input);
781*4882a593Smuzhiyun
782*4882a593Smuzhiyun /* DIF related functions */
783*4882a593Smuzhiyun int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
784*4882a593Smuzhiyun u32 function_mode, u32 standard);
785*4882a593Smuzhiyun void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
786*4882a593Smuzhiyun u8 spectral_invert, u32 mode);
787*4882a593Smuzhiyun u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd);
788*4882a593Smuzhiyun void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
789*4882a593Smuzhiyun u8 spectral_invert, u32 mode);
790*4882a593Smuzhiyun void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev);
791*4882a593Smuzhiyun void reset_s5h1432_demod(struct cx231xx *dev);
792*4882a593Smuzhiyun void cx231xx_dump_HH_reg(struct cx231xx *dev);
793*4882a593Smuzhiyun void update_HH_register_after_set_DIF(struct cx231xx *dev);
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard);
798*4882a593Smuzhiyun int cx231xx_tuner_pre_channel_change(struct cx231xx *dev);
799*4882a593Smuzhiyun int cx231xx_tuner_post_channel_change(struct cx231xx *dev);
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun /* video parser functions */
802*4882a593Smuzhiyun u8 cx231xx_find_next_SAV_EAV(u8 *p_buffer, u32 buffer_size,
803*4882a593Smuzhiyun u32 *p_bytes_used);
804*4882a593Smuzhiyun u8 cx231xx_find_boundary_SAV_EAV(u8 *p_buffer, u8 *partial_buf,
805*4882a593Smuzhiyun u32 *p_bytes_used);
806*4882a593Smuzhiyun int cx231xx_do_copy(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
807*4882a593Smuzhiyun u8 *p_buffer, u32 bytes_to_copy);
808*4882a593Smuzhiyun void cx231xx_reset_video_buffer(struct cx231xx *dev,
809*4882a593Smuzhiyun struct cx231xx_dmaqueue *dma_q);
810*4882a593Smuzhiyun u8 cx231xx_is_buffer_done(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q);
811*4882a593Smuzhiyun u32 cx231xx_copy_video_line(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
812*4882a593Smuzhiyun u8 *p_line, u32 length, int field_number);
813*4882a593Smuzhiyun u32 cx231xx_get_video_line(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
814*4882a593Smuzhiyun u8 sav_eav, u8 *p_buffer, u32 buffer_size);
815*4882a593Smuzhiyun void cx231xx_swab(u16 *from, u16 *to, u16 len);
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun /* Provided by cx231xx-core.c */
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun u32 cx231xx_request_buffers(struct cx231xx *dev, u32 count);
820*4882a593Smuzhiyun void cx231xx_queue_unusedframes(struct cx231xx *dev);
821*4882a593Smuzhiyun void cx231xx_release_buffers(struct cx231xx *dev);
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun /* read from control pipe */
824*4882a593Smuzhiyun int cx231xx_read_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg,
825*4882a593Smuzhiyun char *buf, int len);
826*4882a593Smuzhiyun
827*4882a593Smuzhiyun /* write to control pipe */
828*4882a593Smuzhiyun int cx231xx_write_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg,
829*4882a593Smuzhiyun char *buf, int len);
830*4882a593Smuzhiyun int cx231xx_mode_register(struct cx231xx *dev, u16 address, u32 mode);
831*4882a593Smuzhiyun
832*4882a593Smuzhiyun int cx231xx_send_vendor_cmd(struct cx231xx *dev,
833*4882a593Smuzhiyun struct VENDOR_REQUEST_IN *ven_req);
834*4882a593Smuzhiyun int cx231xx_send_usb_command(struct cx231xx_i2c *i2c_bus,
835*4882a593Smuzhiyun struct cx231xx_i2c_xfer_data *req_data);
836*4882a593Smuzhiyun
837*4882a593Smuzhiyun /* Gpio related functions */
838*4882a593Smuzhiyun int cx231xx_send_gpio_cmd(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val,
839*4882a593Smuzhiyun u8 len, u8 request, u8 direction);
840*4882a593Smuzhiyun int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value);
841*4882a593Smuzhiyun int cx231xx_set_gpio_direction(struct cx231xx *dev, int pin_number,
842*4882a593Smuzhiyun int pin_value);
843*4882a593Smuzhiyun
844*4882a593Smuzhiyun int cx231xx_gpio_i2c_start(struct cx231xx *dev);
845*4882a593Smuzhiyun int cx231xx_gpio_i2c_end(struct cx231xx *dev);
846*4882a593Smuzhiyun int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data);
847*4882a593Smuzhiyun int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf);
848*4882a593Smuzhiyun int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev);
849*4882a593Smuzhiyun int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev);
850*4882a593Smuzhiyun int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev);
851*4882a593Smuzhiyun
852*4882a593Smuzhiyun int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len);
853*4882a593Smuzhiyun int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len);
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun /* audio related functions */
856*4882a593Smuzhiyun int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
857*4882a593Smuzhiyun enum AUDIO_INPUT audio_input);
858*4882a593Smuzhiyun
859*4882a593Smuzhiyun int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type);
860*4882a593Smuzhiyun int cx231xx_set_video_alternate(struct cx231xx *dev);
861*4882a593Smuzhiyun int cx231xx_set_alt_setting(struct cx231xx *dev, u8 index, u8 alt);
862*4882a593Smuzhiyun int is_fw_load(struct cx231xx *dev);
863*4882a593Smuzhiyun int cx231xx_check_fw(struct cx231xx *dev);
864*4882a593Smuzhiyun int cx231xx_init_isoc(struct cx231xx *dev, int max_packets,
865*4882a593Smuzhiyun int num_bufs, int max_pkt_size,
866*4882a593Smuzhiyun int (*isoc_copy) (struct cx231xx *dev,
867*4882a593Smuzhiyun struct urb *urb));
868*4882a593Smuzhiyun int cx231xx_init_bulk(struct cx231xx *dev, int max_packets,
869*4882a593Smuzhiyun int num_bufs, int max_pkt_size,
870*4882a593Smuzhiyun int (*bulk_copy) (struct cx231xx *dev,
871*4882a593Smuzhiyun struct urb *urb));
872*4882a593Smuzhiyun void cx231xx_stop_TS1(struct cx231xx *dev);
873*4882a593Smuzhiyun void cx231xx_start_TS1(struct cx231xx *dev);
874*4882a593Smuzhiyun void cx231xx_uninit_isoc(struct cx231xx *dev);
875*4882a593Smuzhiyun void cx231xx_uninit_bulk(struct cx231xx *dev);
876*4882a593Smuzhiyun int cx231xx_set_mode(struct cx231xx *dev, enum cx231xx_mode set_mode);
877*4882a593Smuzhiyun int cx231xx_unmute_audio(struct cx231xx *dev);
878*4882a593Smuzhiyun int cx231xx_ep5_bulkout(struct cx231xx *dev, u8 *firmware, u16 size);
879*4882a593Smuzhiyun void cx231xx_disable656(struct cx231xx *dev);
880*4882a593Smuzhiyun void cx231xx_enable656(struct cx231xx *dev);
881*4882a593Smuzhiyun int cx231xx_demod_reset(struct cx231xx *dev);
882*4882a593Smuzhiyun int cx231xx_gpio_set(struct cx231xx *dev, struct cx231xx_reg_seq *gpio);
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun /* Device list functions */
885*4882a593Smuzhiyun void cx231xx_release_resources(struct cx231xx *dev);
886*4882a593Smuzhiyun void cx231xx_release_analog_resources(struct cx231xx *dev);
887*4882a593Smuzhiyun int cx231xx_register_analog_devices(struct cx231xx *dev);
888*4882a593Smuzhiyun void cx231xx_remove_from_devlist(struct cx231xx *dev);
889*4882a593Smuzhiyun void cx231xx_add_into_devlist(struct cx231xx *dev);
890*4882a593Smuzhiyun void cx231xx_init_extension(struct cx231xx *dev);
891*4882a593Smuzhiyun void cx231xx_close_extension(struct cx231xx *dev);
892*4882a593Smuzhiyun
893*4882a593Smuzhiyun /* hardware init functions */
894*4882a593Smuzhiyun int cx231xx_dev_init(struct cx231xx *dev);
895*4882a593Smuzhiyun void cx231xx_dev_uninit(struct cx231xx *dev);
896*4882a593Smuzhiyun void cx231xx_config_i2c(struct cx231xx *dev);
897*4882a593Smuzhiyun int cx231xx_config(struct cx231xx *dev);
898*4882a593Smuzhiyun
899*4882a593Smuzhiyun /* Stream control functions */
900*4882a593Smuzhiyun int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask);
901*4882a593Smuzhiyun int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask);
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type);
904*4882a593Smuzhiyun
905*4882a593Smuzhiyun /* Power control functions */
906*4882a593Smuzhiyun int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode);
907*4882a593Smuzhiyun int cx231xx_power_suspend(struct cx231xx *dev);
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun /* chip specific control functions */
910*4882a593Smuzhiyun int cx231xx_init_ctrl_pin_status(struct cx231xx *dev);
911*4882a593Smuzhiyun int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
912*4882a593Smuzhiyun u8 analog_or_digital);
913*4882a593Smuzhiyun int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3);
914*4882a593Smuzhiyun
915*4882a593Smuzhiyun /* video audio decoder related functions */
916*4882a593Smuzhiyun void video_mux(struct cx231xx *dev, int index);
917*4882a593Smuzhiyun int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input);
918*4882a593Smuzhiyun int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input);
919*4882a593Smuzhiyun int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev);
920*4882a593Smuzhiyun int cx231xx_set_audio_input(struct cx231xx *dev, u8 input);
921*4882a593Smuzhiyun
922*4882a593Smuzhiyun /* Provided by cx231xx-video.c */
923*4882a593Smuzhiyun int cx231xx_register_extension(struct cx231xx_ops *dev);
924*4882a593Smuzhiyun void cx231xx_unregister_extension(struct cx231xx_ops *dev);
925*4882a593Smuzhiyun void cx231xx_init_extension(struct cx231xx *dev);
926*4882a593Smuzhiyun void cx231xx_close_extension(struct cx231xx *dev);
927*4882a593Smuzhiyun void cx231xx_v4l2_create_entities(struct cx231xx *dev);
928*4882a593Smuzhiyun int cx231xx_querycap(struct file *file, void *priv,
929*4882a593Smuzhiyun struct v4l2_capability *cap);
930*4882a593Smuzhiyun int cx231xx_g_tuner(struct file *file, void *priv, struct v4l2_tuner *t);
931*4882a593Smuzhiyun int cx231xx_s_tuner(struct file *file, void *priv, const struct v4l2_tuner *t);
932*4882a593Smuzhiyun int cx231xx_g_frequency(struct file *file, void *priv,
933*4882a593Smuzhiyun struct v4l2_frequency *f);
934*4882a593Smuzhiyun int cx231xx_s_frequency(struct file *file, void *priv,
935*4882a593Smuzhiyun const struct v4l2_frequency *f);
936*4882a593Smuzhiyun int cx231xx_enum_input(struct file *file, void *priv,
937*4882a593Smuzhiyun struct v4l2_input *i);
938*4882a593Smuzhiyun int cx231xx_g_input(struct file *file, void *priv, unsigned int *i);
939*4882a593Smuzhiyun int cx231xx_s_input(struct file *file, void *priv, unsigned int i);
940*4882a593Smuzhiyun int cx231xx_g_chip_info(struct file *file, void *fh, struct v4l2_dbg_chip_info *chip);
941*4882a593Smuzhiyun int cx231xx_g_register(struct file *file, void *priv,
942*4882a593Smuzhiyun struct v4l2_dbg_register *reg);
943*4882a593Smuzhiyun int cx231xx_s_register(struct file *file, void *priv,
944*4882a593Smuzhiyun const struct v4l2_dbg_register *reg);
945*4882a593Smuzhiyun
946*4882a593Smuzhiyun /* Provided by cx231xx-cards.c */
947*4882a593Smuzhiyun extern void cx231xx_pre_card_setup(struct cx231xx *dev);
948*4882a593Smuzhiyun extern void cx231xx_card_setup(struct cx231xx *dev);
949*4882a593Smuzhiyun extern struct cx231xx_board cx231xx_boards[];
950*4882a593Smuzhiyun extern struct usb_device_id cx231xx_id_table[];
951*4882a593Smuzhiyun extern const unsigned int cx231xx_bcount;
952*4882a593Smuzhiyun int cx231xx_tuner_callback(void *ptr, int component, int command, int arg);
953*4882a593Smuzhiyun
954*4882a593Smuzhiyun /* cx23885-417.c */
955*4882a593Smuzhiyun extern int cx231xx_417_register(struct cx231xx *dev);
956*4882a593Smuzhiyun extern void cx231xx_417_unregister(struct cx231xx *dev);
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun /* cx23885-input.c */
959*4882a593Smuzhiyun
960*4882a593Smuzhiyun #if defined(CONFIG_VIDEO_CX231XX_RC)
961*4882a593Smuzhiyun int cx231xx_ir_init(struct cx231xx *dev);
962*4882a593Smuzhiyun void cx231xx_ir_exit(struct cx231xx *dev);
963*4882a593Smuzhiyun #else
cx231xx_ir_init(struct cx231xx * dev)964*4882a593Smuzhiyun static inline int cx231xx_ir_init(struct cx231xx *dev)
965*4882a593Smuzhiyun {
966*4882a593Smuzhiyun return 0;
967*4882a593Smuzhiyun }
cx231xx_ir_exit(struct cx231xx * dev)968*4882a593Smuzhiyun static inline void cx231xx_ir_exit(struct cx231xx *dev) {}
969*4882a593Smuzhiyun #endif
970*4882a593Smuzhiyun
norm_maxw(struct cx231xx * dev)971*4882a593Smuzhiyun static inline unsigned int norm_maxw(struct cx231xx *dev)
972*4882a593Smuzhiyun {
973*4882a593Smuzhiyun if (dev->board.max_range_640_480)
974*4882a593Smuzhiyun return 640;
975*4882a593Smuzhiyun else
976*4882a593Smuzhiyun return 720;
977*4882a593Smuzhiyun }
978*4882a593Smuzhiyun
norm_maxh(struct cx231xx * dev)979*4882a593Smuzhiyun static inline unsigned int norm_maxh(struct cx231xx *dev)
980*4882a593Smuzhiyun {
981*4882a593Smuzhiyun if (dev->board.max_range_640_480)
982*4882a593Smuzhiyun return 480;
983*4882a593Smuzhiyun else
984*4882a593Smuzhiyun return (dev->norm & V4L2_STD_625_50) ? 576 : 480;
985*4882a593Smuzhiyun }
986*4882a593Smuzhiyun #endif
987