1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun cx231xx-reg.h - driver for Conexant Cx23100/101/102 4*4882a593Smuzhiyun USB video capture devices 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun Copyright (C) 2008 <srinivasa.deevi at conexant dot com> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _CX231XX_REG_H 11*4882a593Smuzhiyun #define _CX231XX_REG_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /***************************************************************************** 14*4882a593Smuzhiyun * VBI codes * 15*4882a593Smuzhiyun *****************************************************************************/ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define SAV_ACTIVE_VIDEO_FIELD1 0x80 18*4882a593Smuzhiyun #define EAV_ACTIVE_VIDEO_FIELD1 0x90 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define SAV_ACTIVE_VIDEO_FIELD2 0xc0 21*4882a593Smuzhiyun #define EAV_ACTIVE_VIDEO_FIELD2 0xd0 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define SAV_VBLANK_FIELD1 0xa0 24*4882a593Smuzhiyun #define EAV_VBLANK_FIELD1 0xb0 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define SAV_VBLANK_FIELD2 0xe0 27*4882a593Smuzhiyun #define EAV_VBLANK_FIELD2 0xf0 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define SAV_VBI_FIELD1 0x20 30*4882a593Smuzhiyun #define EAV_VBI_FIELD1 0x30 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define SAV_VBI_FIELD2 0x60 33*4882a593Smuzhiyun #define EAV_VBI_FIELD2 0x70 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /*****************************************************************************/ 36*4882a593Smuzhiyun /* Audio ADC Registers */ 37*4882a593Smuzhiyun #define CH_PWR_CTRL1 0x0000000e 38*4882a593Smuzhiyun #define CH_PWR_CTRL2 0x0000000f 39*4882a593Smuzhiyun /*****************************************************************************/ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define HOST_REG1 0x000 42*4882a593Smuzhiyun #define FLD_FORCE_CHIP_SEL 0x80 43*4882a593Smuzhiyun #define FLD_AUTO_INC_DIS 0x20 44*4882a593Smuzhiyun #define FLD_PREFETCH_EN 0x10 45*4882a593Smuzhiyun /* Reserved [2:3] */ 46*4882a593Smuzhiyun #define FLD_DIGITAL_PWR_DN 0x02 47*4882a593Smuzhiyun #define FLD_SLEEP 0x01 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /*****************************************************************************/ 50*4882a593Smuzhiyun #define HOST_REG2 0x001 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /*****************************************************************************/ 53*4882a593Smuzhiyun #define HOST_REG3 0x002 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /*****************************************************************************/ 56*4882a593Smuzhiyun /* added for polaris */ 57*4882a593Smuzhiyun #define GPIO_PIN_CTL0 0x3 58*4882a593Smuzhiyun #define GPIO_PIN_CTL1 0x4 59*4882a593Smuzhiyun #define GPIO_PIN_CTL2 0x5 60*4882a593Smuzhiyun #define GPIO_PIN_CTL3 0x6 61*4882a593Smuzhiyun #define TS1_PIN_CTL0 0x7 62*4882a593Smuzhiyun #define TS1_PIN_CTL1 0x8 63*4882a593Smuzhiyun /*****************************************************************************/ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define FLD_CLK_IN_EN 0x80 66*4882a593Smuzhiyun #define FLD_XTAL_CTRL 0x70 67*4882a593Smuzhiyun #define FLD_BB_CLK_MODE 0x0C 68*4882a593Smuzhiyun #define FLD_REF_DIV_PLL 0x02 69*4882a593Smuzhiyun #define FLD_REF_SEL_PLL1 0x01 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /*****************************************************************************/ 72*4882a593Smuzhiyun #define CHIP_CTRL 0x100 73*4882a593Smuzhiyun /* Reserved [27] */ 74*4882a593Smuzhiyun /* Reserved [31:21] */ 75*4882a593Smuzhiyun #define FLD_CHIP_ACFG_DIS 0x00100000 76*4882a593Smuzhiyun /* Reserved [19] */ 77*4882a593Smuzhiyun #define FLD_DUAL_MODE_ADC2 0x00040000 78*4882a593Smuzhiyun #define FLD_SIF_EN 0x00020000 79*4882a593Smuzhiyun #define FLD_SOFT_RST 0x00010000 80*4882a593Smuzhiyun #define FLD_DEVICE_ID 0x0000ffff 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /*****************************************************************************/ 83*4882a593Smuzhiyun #define AFE_CTRL 0x104 84*4882a593Smuzhiyun #define AFE_CTRL_C2HH_SRC_CTRL 0x104 85*4882a593Smuzhiyun #define FLD_DIF_OUT_SEL 0xc0000000 86*4882a593Smuzhiyun #define FLD_AUX_PLL_CLK_ALT_SEL 0x3c000000 87*4882a593Smuzhiyun #define FLD_UV_ORDER_MODE 0x02000000 88*4882a593Smuzhiyun #define FLD_FUNC_MODE 0x01800000 89*4882a593Smuzhiyun #define FLD_ROT1_PHASE_CTL 0x007f8000 90*4882a593Smuzhiyun #define FLD_AUD_IN_SEL 0x00004000 91*4882a593Smuzhiyun #define FLD_LUMA_IN_SEL 0x00002000 92*4882a593Smuzhiyun #define FLD_CHROMA_IN_SEL 0x00001000 93*4882a593Smuzhiyun /* reserve [11:10] */ 94*4882a593Smuzhiyun #define FLD_INV_SPEC_DIS 0x00000200 95*4882a593Smuzhiyun #define FLD_VGA_SEL_CH3 0x00000100 96*4882a593Smuzhiyun #define FLD_VGA_SEL_CH2 0x00000080 97*4882a593Smuzhiyun #define FLD_VGA_SEL_CH1 0x00000040 98*4882a593Smuzhiyun #define FLD_DCR_BYP_CH1 0x00000020 99*4882a593Smuzhiyun #define FLD_DCR_BYP_CH2 0x00000010 100*4882a593Smuzhiyun #define FLD_DCR_BYP_CH3 0x00000008 101*4882a593Smuzhiyun #define FLD_EN_12DB_CH3 0x00000004 102*4882a593Smuzhiyun #define FLD_EN_12DB_CH2 0x00000002 103*4882a593Smuzhiyun #define FLD_EN_12DB_CH1 0x00000001 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* redefine in Cx231xx */ 106*4882a593Smuzhiyun /*****************************************************************************/ 107*4882a593Smuzhiyun #define DC_CTRL1 0x108 108*4882a593Smuzhiyun /* reserve [31:30] */ 109*4882a593Smuzhiyun #define FLD_CLAMP_LVL_CH1 0x3fff8000 110*4882a593Smuzhiyun #define FLD_CLAMP_LVL_CH2 0x00007fff 111*4882a593Smuzhiyun /*****************************************************************************/ 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /*****************************************************************************/ 114*4882a593Smuzhiyun #define DC_CTRL2 0x10c 115*4882a593Smuzhiyun /* reserve [31:28] */ 116*4882a593Smuzhiyun #define FLD_CLAMP_LVL_CH3 0x00fffe00 117*4882a593Smuzhiyun #define FLD_CLAMP_WIND_LENTH 0x000001e0 118*4882a593Smuzhiyun #define FLD_C2HH_SAT_MIN 0x0000001e 119*4882a593Smuzhiyun #define FLD_FLT_BYP_SEL 0x00000001 120*4882a593Smuzhiyun /*****************************************************************************/ 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /*****************************************************************************/ 123*4882a593Smuzhiyun #define DC_CTRL3 0x110 124*4882a593Smuzhiyun /* reserve [31:16] */ 125*4882a593Smuzhiyun #define FLD_ERR_GAIN_CTL 0x00070000 126*4882a593Smuzhiyun #define FLD_LPF_MIN 0x0000ffff 127*4882a593Smuzhiyun /*****************************************************************************/ 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /*****************************************************************************/ 130*4882a593Smuzhiyun #define DC_CTRL4 0x114 131*4882a593Smuzhiyun /* reserve [31:31] */ 132*4882a593Smuzhiyun #define FLD_INTG_CH1 0x7fffffff 133*4882a593Smuzhiyun /*****************************************************************************/ 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /*****************************************************************************/ 136*4882a593Smuzhiyun #define DC_CTRL5 0x118 137*4882a593Smuzhiyun /* reserve [31:31] */ 138*4882a593Smuzhiyun #define FLD_INTG_CH2 0x7fffffff 139*4882a593Smuzhiyun /*****************************************************************************/ 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /*****************************************************************************/ 142*4882a593Smuzhiyun #define DC_CTRL6 0x11c 143*4882a593Smuzhiyun /* reserve [31:31] */ 144*4882a593Smuzhiyun #define FLD_INTG_CH3 0x7fffffff 145*4882a593Smuzhiyun /*****************************************************************************/ 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun /*****************************************************************************/ 148*4882a593Smuzhiyun #define PIN_CTRL 0x120 149*4882a593Smuzhiyun #define FLD_OEF_AGC_RF 0x00000001 150*4882a593Smuzhiyun #define FLD_OEF_AGC_IFVGA 0x00000002 151*4882a593Smuzhiyun #define FLD_OEF_AGC_IF 0x00000004 152*4882a593Smuzhiyun #define FLD_REG_BO_PUD 0x80000000 153*4882a593Smuzhiyun #define FLD_IR_IRQ_STAT 0x40000000 154*4882a593Smuzhiyun #define FLD_AUD_IRQ_STAT 0x20000000 155*4882a593Smuzhiyun #define FLD_VID_IRQ_STAT 0x10000000 156*4882a593Smuzhiyun /* Reserved [27:26] */ 157*4882a593Smuzhiyun #define FLD_IRQ_N_OUT_EN 0x02000000 158*4882a593Smuzhiyun #define FLD_IRQ_N_POLAR 0x01000000 159*4882a593Smuzhiyun /* Reserved [23:6] */ 160*4882a593Smuzhiyun #define FLD_OE_AUX_PLL_CLK 0x00000020 161*4882a593Smuzhiyun #define FLD_OE_I2S_BCLK 0x00000010 162*4882a593Smuzhiyun #define FLD_OE_I2S_WCLK 0x00000008 163*4882a593Smuzhiyun #define FLD_OE_AGC_IF 0x00000004 164*4882a593Smuzhiyun #define FLD_OE_AGC_IFVGA 0x00000002 165*4882a593Smuzhiyun #define FLD_OE_AGC_RF 0x00000001 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /*****************************************************************************/ 168*4882a593Smuzhiyun #define AUD_IO_CTRL 0x124 169*4882a593Smuzhiyun /* Reserved [31:8] */ 170*4882a593Smuzhiyun #define FLD_I2S_PORT_DIR 0x00000080 171*4882a593Smuzhiyun #define FLD_I2S_OUT_SRC 0x00000040 172*4882a593Smuzhiyun #define FLD_AUD_CHAN3_SRC 0x00000030 173*4882a593Smuzhiyun #define FLD_AUD_CHAN2_SRC 0x0000000c 174*4882a593Smuzhiyun #define FLD_AUD_CHAN1_SRC 0x00000003 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /*****************************************************************************/ 177*4882a593Smuzhiyun #define AUD_LOCK1 0x128 178*4882a593Smuzhiyun #define FLD_AUD_LOCK_KI_SHIFT 0xc0000000 179*4882a593Smuzhiyun #define FLD_AUD_LOCK_KD_SHIFT 0x30000000 180*4882a593Smuzhiyun /* Reserved [27:25] */ 181*4882a593Smuzhiyun #define FLD_EN_AV_LOCK 0x01000000 182*4882a593Smuzhiyun #define FLD_VID_COUNT 0x00ffffff 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun /*****************************************************************************/ 185*4882a593Smuzhiyun #define AUD_LOCK2 0x12c 186*4882a593Smuzhiyun #define FLD_AUD_LOCK_KI_MULT 0xf0000000 187*4882a593Smuzhiyun #define FLD_AUD_LOCK_KD_MULT 0x0F000000 188*4882a593Smuzhiyun /* Reserved [23:22] */ 189*4882a593Smuzhiyun #define FLD_AUD_LOCK_FREQ_SHIFT 0x00300000 190*4882a593Smuzhiyun #define FLD_AUD_COUNT 0x000fffff 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun /*****************************************************************************/ 193*4882a593Smuzhiyun #define AFE_DIAG_CTRL1 0x134 194*4882a593Smuzhiyun /* Reserved [31:16] */ 195*4882a593Smuzhiyun #define FLD_CUV_DLY_LENGTH 0x0000ff00 196*4882a593Smuzhiyun #define FLD_YC_DLY_LENGTH 0x000000ff 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun /*****************************************************************************/ 199*4882a593Smuzhiyun /* Poalris redefine */ 200*4882a593Smuzhiyun #define AFE_DIAG_CTRL3 0x138 201*4882a593Smuzhiyun /* Reserved [31:26] */ 202*4882a593Smuzhiyun #define FLD_AUD_DUAL_FLAG_POL 0x02000000 203*4882a593Smuzhiyun #define FLD_VID_DUAL_FLAG_POL 0x01000000 204*4882a593Smuzhiyun /* Reserved [23:23] */ 205*4882a593Smuzhiyun #define FLD_COL_CLAMP_DIS_CH1 0x00400000 206*4882a593Smuzhiyun #define FLD_COL_CLAMP_DIS_CH2 0x00200000 207*4882a593Smuzhiyun #define FLD_COL_CLAMP_DIS_CH3 0x00100000 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun #define TEST_CTRL1 0x144 210*4882a593Smuzhiyun /* Reserved [31:29] */ 211*4882a593Smuzhiyun #define FLD_LBIST_EN 0x10000000 212*4882a593Smuzhiyun /* Reserved [27:10] */ 213*4882a593Smuzhiyun #define FLD_FI_BIST_INTR_R 0x0000200 214*4882a593Smuzhiyun #define FLD_FI_BIST_INTR_L 0x0000100 215*4882a593Smuzhiyun #define FLD_BIST_FAIL_AUD_PLL 0x0000080 216*4882a593Smuzhiyun #define FLD_BIST_INTR_AUD_PLL 0x0000040 217*4882a593Smuzhiyun #define FLD_BIST_FAIL_VID_PLL 0x0000020 218*4882a593Smuzhiyun #define FLD_BIST_INTR_VID_PLL 0x0000010 219*4882a593Smuzhiyun /* Reserved [3:1] */ 220*4882a593Smuzhiyun #define FLD_CIR_TEST_DIS 0x00000001 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun /*****************************************************************************/ 223*4882a593Smuzhiyun #define TEST_CTRL2 0x148 224*4882a593Smuzhiyun #define FLD_TSXCLK_POL_CTL 0x80000000 225*4882a593Smuzhiyun #define FLD_ISO_CTL_SEL 0x40000000 226*4882a593Smuzhiyun #define FLD_ISO_CTL_EN 0x20000000 227*4882a593Smuzhiyun #define FLD_BIST_DEBUGZ 0x10000000 228*4882a593Smuzhiyun #define FLD_AUD_BIST_TEST_H 0x0f000000 229*4882a593Smuzhiyun /* Reserved [23:22] */ 230*4882a593Smuzhiyun #define FLD_FLTRN_BIST_TEST_H 0x00020000 231*4882a593Smuzhiyun #define FLD_VID_BIST_TEST_H 0x00010000 232*4882a593Smuzhiyun /* Reserved [19:17] */ 233*4882a593Smuzhiyun #define FLD_BIST_TEST_H 0x00010000 234*4882a593Smuzhiyun /* Reserved [15:13] */ 235*4882a593Smuzhiyun #define FLD_TAB_EN 0x00001000 236*4882a593Smuzhiyun /* Reserved [11:0] */ 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun /*****************************************************************************/ 239*4882a593Smuzhiyun #define BIST_STAT 0x14c 240*4882a593Smuzhiyun #define FLD_AUD_BIST_FAIL_H 0xfff00000 241*4882a593Smuzhiyun #define FLD_FLTRN_BIST_FAIL_H 0x00180000 242*4882a593Smuzhiyun #define FLD_VID_BIST_FAIL_H 0x00070000 243*4882a593Smuzhiyun #define FLD_AUD_BIST_TST_DONE 0x0000fff0 244*4882a593Smuzhiyun #define FLD_FLTRN_BIST_TST_DONE 0x00000008 245*4882a593Smuzhiyun #define FLD_VID_BIST_TST_DONE 0x00000007 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun /*****************************************************************************/ 248*4882a593Smuzhiyun /* DirectIF registers definition have been moved to DIF_reg.h */ 249*4882a593Smuzhiyun /*****************************************************************************/ 250*4882a593Smuzhiyun #define MODE_CTRL 0x400 251*4882a593Smuzhiyun #define FLD_AFD_PAL60_DIS 0x20000000 252*4882a593Smuzhiyun #define FLD_AFD_FORCE_SECAM 0x10000000 253*4882a593Smuzhiyun #define FLD_AFD_FORCE_PALNC 0x08000000 254*4882a593Smuzhiyun #define FLD_AFD_FORCE_PAL 0x04000000 255*4882a593Smuzhiyun #define FLD_AFD_PALM_SEL 0x03000000 256*4882a593Smuzhiyun #define FLD_CKILL_MODE 0x00300000 257*4882a593Smuzhiyun #define FLD_COMB_NOTCH_MODE 0x00c00000 /* bit[19:18] */ 258*4882a593Smuzhiyun #define FLD_CLR_LOCK_STAT 0x00020000 259*4882a593Smuzhiyun #define FLD_FAST_LOCK_MD 0x00010000 260*4882a593Smuzhiyun #define FLD_WCEN 0x00008000 261*4882a593Smuzhiyun #define FLD_CAGCEN 0x00004000 262*4882a593Smuzhiyun #define FLD_CKILLEN 0x00002000 263*4882a593Smuzhiyun #define FLD_AUTO_SC_LOCK 0x00001000 264*4882a593Smuzhiyun #define FLD_MAN_SC_FAST_LOCK 0x00000800 265*4882a593Smuzhiyun #define FLD_INPUT_MODE 0x00000600 266*4882a593Smuzhiyun #define FLD_AFD_ACQUIRE 0x00000100 267*4882a593Smuzhiyun #define FLD_AFD_NTSC_SEL 0x00000080 268*4882a593Smuzhiyun #define FLD_AFD_PAL_SEL 0x00000040 269*4882a593Smuzhiyun #define FLD_ACFG_DIS 0x00000020 270*4882a593Smuzhiyun #define FLD_SQ_PIXEL 0x00000010 271*4882a593Smuzhiyun #define FLD_VID_FMT_SEL 0x0000000f 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun /*****************************************************************************/ 274*4882a593Smuzhiyun #define OUT_CTRL1 0x404 275*4882a593Smuzhiyun #define FLD_POLAR 0x7f000000 276*4882a593Smuzhiyun /* Reserved [23] */ 277*4882a593Smuzhiyun #define FLD_RND_MODE 0x00600000 278*4882a593Smuzhiyun #define FLD_VIPCLAMP_EN 0x00100000 279*4882a593Smuzhiyun #define FLD_VIPBLANK_EN 0x00080000 280*4882a593Smuzhiyun #define FLD_VIP_OPT_AL 0x00040000 281*4882a593Smuzhiyun #define FLD_IDID0_SOURCE 0x00020000 282*4882a593Smuzhiyun #define FLD_DCMODE 0x00010000 283*4882a593Smuzhiyun #define FLD_CLK_GATING 0x0000c000 284*4882a593Smuzhiyun #define FLD_CLK_INVERT 0x00002000 285*4882a593Smuzhiyun #define FLD_HSFMT 0x00001000 286*4882a593Smuzhiyun #define FLD_VALIDFMT 0x00000800 287*4882a593Smuzhiyun #define FLD_ACTFMT 0x00000400 288*4882a593Smuzhiyun #define FLD_SWAPRAW 0x00000200 289*4882a593Smuzhiyun #define FLD_CLAMPRAW_EN 0x00000100 290*4882a593Smuzhiyun #define FLD_BLUE_FIELD_EN 0x00000080 291*4882a593Smuzhiyun #define FLD_BLUE_FIELD_ACT 0x00000040 292*4882a593Smuzhiyun #define FLD_TASKBIT_VAL 0x00000020 293*4882a593Smuzhiyun #define FLD_ANC_DATA_EN 0x00000010 294*4882a593Smuzhiyun #define FLD_VBIHACTRAW_EN 0x00000008 295*4882a593Smuzhiyun #define FLD_MODE10B 0x00000004 296*4882a593Smuzhiyun #define FLD_OUT_MODE 0x00000003 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun /*****************************************************************************/ 299*4882a593Smuzhiyun #define OUT_CTRL2 0x408 300*4882a593Smuzhiyun #define FLD_AUD_GRP 0xc0000000 301*4882a593Smuzhiyun #define FLD_SAMPLE_RATE 0x30000000 302*4882a593Smuzhiyun #define FLD_AUD_ANC_EN 0x08000000 303*4882a593Smuzhiyun #define FLD_EN_C 0x04000000 304*4882a593Smuzhiyun #define FLD_EN_B 0x02000000 305*4882a593Smuzhiyun #define FLD_EN_A 0x01000000 306*4882a593Smuzhiyun /* Reserved [23:20] */ 307*4882a593Smuzhiyun #define FLD_IDID1_LSB 0x000c0000 308*4882a593Smuzhiyun #define FLD_IDID0_LSB 0x00030000 309*4882a593Smuzhiyun #define FLD_IDID1_MSB 0x0000ff00 310*4882a593Smuzhiyun #define FLD_IDID0_MSB 0x000000ff 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun /*****************************************************************************/ 313*4882a593Smuzhiyun #define GEN_STAT 0x40c 314*4882a593Smuzhiyun #define FLD_VCR_DETECT 0x00800000 315*4882a593Smuzhiyun #define FLD_SPECIAL_PLAY_N 0x00400000 316*4882a593Smuzhiyun #define FLD_VPRES 0x00200000 317*4882a593Smuzhiyun #define FLD_AGC_LOCK 0x00100000 318*4882a593Smuzhiyun #define FLD_CSC_LOCK 0x00080000 319*4882a593Smuzhiyun #define FLD_VLOCK 0x00040000 320*4882a593Smuzhiyun #define FLD_SRC_LOCK 0x00020000 321*4882a593Smuzhiyun #define FLD_HLOCK 0x00010000 322*4882a593Smuzhiyun #define FLD_VSYNC_N 0x00008000 323*4882a593Smuzhiyun #define FLD_SRC_FIFO_UFLOW 0x00004000 324*4882a593Smuzhiyun #define FLD_SRC_FIFO_OFLOW 0x00002000 325*4882a593Smuzhiyun #define FLD_FIELD 0x00001000 326*4882a593Smuzhiyun #define FLD_AFD_FMT_STAT 0x00000f00 327*4882a593Smuzhiyun #define FLD_MV_TYPE2_PAIR 0x00000080 328*4882a593Smuzhiyun #define FLD_MV_T3CS 0x00000040 329*4882a593Smuzhiyun #define FLD_MV_CS 0x00000020 330*4882a593Smuzhiyun #define FLD_MV_PSP 0x00000010 331*4882a593Smuzhiyun /* Reserved [3] */ 332*4882a593Smuzhiyun #define FLD_MV_CDAT 0x00000003 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun /*****************************************************************************/ 335*4882a593Smuzhiyun #define INT_STAT_MASK 0x410 336*4882a593Smuzhiyun #define FLD_COMB_3D_FIFO_MSK 0x80000000 337*4882a593Smuzhiyun #define FLD_WSS_DAT_AVAIL_MSK 0x40000000 338*4882a593Smuzhiyun #define FLD_GS2_DAT_AVAIL_MSK 0x20000000 339*4882a593Smuzhiyun #define FLD_GS1_DAT_AVAIL_MSK 0x10000000 340*4882a593Smuzhiyun #define FLD_CC_DAT_AVAIL_MSK 0x08000000 341*4882a593Smuzhiyun #define FLD_VPRES_CHANGE_MSK 0x04000000 342*4882a593Smuzhiyun #define FLD_MV_CHANGE_MSK 0x02000000 343*4882a593Smuzhiyun #define FLD_END_VBI_EVEN_MSK 0x01000000 344*4882a593Smuzhiyun #define FLD_END_VBI_ODD_MSK 0x00800000 345*4882a593Smuzhiyun #define FLD_FMT_CHANGE_MSK 0x00400000 346*4882a593Smuzhiyun #define FLD_VSYNC_TRAIL_MSK 0x00200000 347*4882a593Smuzhiyun #define FLD_HLOCK_CHANGE_MSK 0x00100000 348*4882a593Smuzhiyun #define FLD_VLOCK_CHANGE_MSK 0x00080000 349*4882a593Smuzhiyun #define FLD_CSC_LOCK_CHANGE_MSK 0x00040000 350*4882a593Smuzhiyun #define FLD_SRC_FIFO_UFLOW_MSK 0x00020000 351*4882a593Smuzhiyun #define FLD_SRC_FIFO_OFLOW_MSK 0x00010000 352*4882a593Smuzhiyun #define FLD_COMB_3D_FIFO_STAT 0x00008000 353*4882a593Smuzhiyun #define FLD_WSS_DAT_AVAIL_STAT 0x00004000 354*4882a593Smuzhiyun #define FLD_GS2_DAT_AVAIL_STAT 0x00002000 355*4882a593Smuzhiyun #define FLD_GS1_DAT_AVAIL_STAT 0x00001000 356*4882a593Smuzhiyun #define FLD_CC_DAT_AVAIL_STAT 0x00000800 357*4882a593Smuzhiyun #define FLD_VPRES_CHANGE_STAT 0x00000400 358*4882a593Smuzhiyun #define FLD_MV_CHANGE_STAT 0x00000200 359*4882a593Smuzhiyun #define FLD_END_VBI_EVEN_STAT 0x00000100 360*4882a593Smuzhiyun #define FLD_END_VBI_ODD_STAT 0x00000080 361*4882a593Smuzhiyun #define FLD_FMT_CHANGE_STAT 0x00000040 362*4882a593Smuzhiyun #define FLD_VSYNC_TRAIL_STAT 0x00000020 363*4882a593Smuzhiyun #define FLD_HLOCK_CHANGE_STAT 0x00000010 364*4882a593Smuzhiyun #define FLD_VLOCK_CHANGE_STAT 0x00000008 365*4882a593Smuzhiyun #define FLD_CSC_LOCK_CHANGE_STAT 0x00000004 366*4882a593Smuzhiyun #define FLD_SRC_FIFO_UFLOW_STAT 0x00000002 367*4882a593Smuzhiyun #define FLD_SRC_FIFO_OFLOW_STAT 0x00000001 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun /*****************************************************************************/ 370*4882a593Smuzhiyun #define LUMA_CTRL 0x414 371*4882a593Smuzhiyun #define BRIGHTNESS_CTRL_BYTE 0x414 372*4882a593Smuzhiyun #define CONTRAST_CTRL_BYTE 0x415 373*4882a593Smuzhiyun #define LUMA_CTRL_BYTE_3 0x416 374*4882a593Smuzhiyun #define FLD_LUMA_CORE_SEL 0x00c00000 375*4882a593Smuzhiyun #define FLD_RANGE 0x00300000 376*4882a593Smuzhiyun /* Reserved [19] */ 377*4882a593Smuzhiyun #define FLD_PEAK_EN 0x00040000 378*4882a593Smuzhiyun #define FLD_PEAK_SEL 0x00030000 379*4882a593Smuzhiyun #define FLD_CNTRST 0x0000ff00 380*4882a593Smuzhiyun #define FLD_BRITE 0x000000ff 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun /*****************************************************************************/ 383*4882a593Smuzhiyun #define HSCALE_CTRL 0x418 384*4882a593Smuzhiyun #define FLD_HFILT 0x03000000 385*4882a593Smuzhiyun #define FLD_HSCALE 0x00ffffff 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun /*****************************************************************************/ 388*4882a593Smuzhiyun #define VSCALE_CTRL 0x41c 389*4882a593Smuzhiyun #define FLD_LINE_AVG_DIS 0x01000000 390*4882a593Smuzhiyun /* Reserved [23:20] */ 391*4882a593Smuzhiyun #define FLD_VS_INTRLACE 0x00080000 392*4882a593Smuzhiyun #define FLD_VFILT 0x00070000 393*4882a593Smuzhiyun /* Reserved [15:13] */ 394*4882a593Smuzhiyun #define FLD_VSCALE 0x00001fff 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun /*****************************************************************************/ 397*4882a593Smuzhiyun #define CHROMA_CTRL 0x420 398*4882a593Smuzhiyun #define USAT_CTRL_BYTE 0x420 399*4882a593Smuzhiyun #define VSAT_CTRL_BYTE 0x421 400*4882a593Smuzhiyun #define HUE_CTRL_BYTE 0x422 401*4882a593Smuzhiyun #define FLD_C_LPF_EN 0x20000000 402*4882a593Smuzhiyun #define FLD_CHR_DELAY 0x1c000000 403*4882a593Smuzhiyun #define FLD_C_CORE_SEL 0x03000000 404*4882a593Smuzhiyun #define FLD_HUE 0x00ff0000 405*4882a593Smuzhiyun #define FLD_VSAT 0x0000ff00 406*4882a593Smuzhiyun #define FLD_USAT 0x000000ff 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun /*****************************************************************************/ 409*4882a593Smuzhiyun #define VBI_LINE_CTRL1 0x424 410*4882a593Smuzhiyun #define FLD_VBI_MD_LINE4 0xff000000 411*4882a593Smuzhiyun #define FLD_VBI_MD_LINE3 0x00ff0000 412*4882a593Smuzhiyun #define FLD_VBI_MD_LINE2 0x0000ff00 413*4882a593Smuzhiyun #define FLD_VBI_MD_LINE1 0x000000ff 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun /*****************************************************************************/ 416*4882a593Smuzhiyun #define VBI_LINE_CTRL2 0x428 417*4882a593Smuzhiyun #define FLD_VBI_MD_LINE8 0xff000000 418*4882a593Smuzhiyun #define FLD_VBI_MD_LINE7 0x00ff0000 419*4882a593Smuzhiyun #define FLD_VBI_MD_LINE6 0x0000ff00 420*4882a593Smuzhiyun #define FLD_VBI_MD_LINE5 0x000000ff 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun /*****************************************************************************/ 423*4882a593Smuzhiyun #define VBI_LINE_CTRL3 0x42c 424*4882a593Smuzhiyun #define FLD_VBI_MD_LINE12 0xff000000 425*4882a593Smuzhiyun #define FLD_VBI_MD_LINE11 0x00ff0000 426*4882a593Smuzhiyun #define FLD_VBI_MD_LINE10 0x0000ff00 427*4882a593Smuzhiyun #define FLD_VBI_MD_LINE9 0x000000ff 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun /*****************************************************************************/ 430*4882a593Smuzhiyun #define VBI_LINE_CTRL4 0x430 431*4882a593Smuzhiyun #define FLD_VBI_MD_LINE16 0xff000000 432*4882a593Smuzhiyun #define FLD_VBI_MD_LINE15 0x00ff0000 433*4882a593Smuzhiyun #define FLD_VBI_MD_LINE14 0x0000ff00 434*4882a593Smuzhiyun #define FLD_VBI_MD_LINE13 0x000000ff 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun /*****************************************************************************/ 437*4882a593Smuzhiyun #define VBI_LINE_CTRL5 0x434 438*4882a593Smuzhiyun #define FLD_VBI_MD_LINE17 0x000000ff 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun /*****************************************************************************/ 441*4882a593Smuzhiyun #define VBI_FC_CFG 0x438 442*4882a593Smuzhiyun #define FLD_FC_ALT2 0xff000000 443*4882a593Smuzhiyun #define FLD_FC_ALT1 0x00ff0000 444*4882a593Smuzhiyun #define FLD_FC_ALT2_TYPE 0x0000f000 445*4882a593Smuzhiyun #define FLD_FC_ALT1_TYPE 0x00000f00 446*4882a593Smuzhiyun /* Reserved [7:1] */ 447*4882a593Smuzhiyun #define FLD_FC_SEARCH_MODE 0x00000001 448*4882a593Smuzhiyun 449*4882a593Smuzhiyun /*****************************************************************************/ 450*4882a593Smuzhiyun #define VBI_MISC_CFG1 0x43c 451*4882a593Smuzhiyun #define FLD_TTX_PKTADRU 0xfff00000 452*4882a593Smuzhiyun #define FLD_TTX_PKTADRL 0x000fff00 453*4882a593Smuzhiyun /* Reserved [7:6] */ 454*4882a593Smuzhiyun #define FLD_MOJI_PACK_DIS 0x00000020 455*4882a593Smuzhiyun #define FLD_VPS_DEC_DIS 0x00000010 456*4882a593Smuzhiyun #define FLD_CRI_MARG_SCALE 0x0000000c 457*4882a593Smuzhiyun #define FLD_EDGE_RESYNC_EN 0x00000002 458*4882a593Smuzhiyun #define FLD_ADAPT_SLICE_DIS 0x00000001 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun /*****************************************************************************/ 461*4882a593Smuzhiyun #define VBI_MISC_CFG2 0x440 462*4882a593Smuzhiyun #define FLD_HAMMING_TYPE 0x0f000000 463*4882a593Smuzhiyun /* Reserved [23:20] */ 464*4882a593Smuzhiyun #define FLD_WSS_FIFO_RST 0x00080000 465*4882a593Smuzhiyun #define FLD_GS2_FIFO_RST 0x00040000 466*4882a593Smuzhiyun #define FLD_GS1_FIFO_RST 0x00020000 467*4882a593Smuzhiyun #define FLD_CC_FIFO_RST 0x00010000 468*4882a593Smuzhiyun /* Reserved [15:12] */ 469*4882a593Smuzhiyun #define FLD_VBI3_SDID 0x00000f00 470*4882a593Smuzhiyun #define FLD_VBI2_SDID 0x000000f0 471*4882a593Smuzhiyun #define FLD_VBI1_SDID 0x0000000f 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun /*****************************************************************************/ 474*4882a593Smuzhiyun #define VBI_PAY1 0x444 475*4882a593Smuzhiyun #define FLD_GS1_FIFO_DAT 0xFF000000 476*4882a593Smuzhiyun #define FLD_GS1_STAT 0x00FF0000 477*4882a593Smuzhiyun #define FLD_CC_FIFO_DAT 0x0000FF00 478*4882a593Smuzhiyun #define FLD_CC_STAT 0x000000FF 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun /*****************************************************************************/ 481*4882a593Smuzhiyun #define VBI_PAY2 0x448 482*4882a593Smuzhiyun #define FLD_WSS_FIFO_DAT 0xff000000 483*4882a593Smuzhiyun #define FLD_WSS_STAT 0x00ff0000 484*4882a593Smuzhiyun #define FLD_GS2_FIFO_DAT 0x0000ff00 485*4882a593Smuzhiyun #define FLD_GS2_STAT 0x000000ff 486*4882a593Smuzhiyun 487*4882a593Smuzhiyun /*****************************************************************************/ 488*4882a593Smuzhiyun #define VBI_CUST1_CFG1 0x44c 489*4882a593Smuzhiyun /* Reserved [31] */ 490*4882a593Smuzhiyun #define FLD_VBI1_CRIWIN 0x7f000000 491*4882a593Smuzhiyun #define FLD_VBI1_SLICE_DIST 0x00f00000 492*4882a593Smuzhiyun #define FLD_VBI1_BITINC 0x000fff00 493*4882a593Smuzhiyun #define FLD_VBI1_HDELAY 0x000000ff 494*4882a593Smuzhiyun 495*4882a593Smuzhiyun /*****************************************************************************/ 496*4882a593Smuzhiyun #define VBI_CUST1_CFG2 0x450 497*4882a593Smuzhiyun #define FLD_VBI1_FC_LENGTH 0x1f000000 498*4882a593Smuzhiyun #define FLD_VBI1_FRAME_CODE 0x00ffffff 499*4882a593Smuzhiyun 500*4882a593Smuzhiyun /*****************************************************************************/ 501*4882a593Smuzhiyun #define VBI_CUST1_CFG3 0x454 502*4882a593Smuzhiyun #define FLD_VBI1_HAM_EN 0x80000000 503*4882a593Smuzhiyun #define FLD_VBI1_FIFO_MODE 0x70000000 504*4882a593Smuzhiyun #define FLD_VBI1_FORMAT_TYPE 0x0f000000 505*4882a593Smuzhiyun #define FLD_VBI1_PAYLD_LENGTH 0x00ff0000 506*4882a593Smuzhiyun #define FLD_VBI1_CRI_LENGTH 0x0000f000 507*4882a593Smuzhiyun #define FLD_VBI1_CRI_MARGIN 0x00000f00 508*4882a593Smuzhiyun #define FLD_VBI1_CRI_TIME 0x000000ff 509*4882a593Smuzhiyun 510*4882a593Smuzhiyun /*****************************************************************************/ 511*4882a593Smuzhiyun #define VBI_CUST2_CFG1 0x458 512*4882a593Smuzhiyun /* Reserved [31] */ 513*4882a593Smuzhiyun #define FLD_VBI2_CRIWIN 0x7f000000 514*4882a593Smuzhiyun #define FLD_VBI2_SLICE_DIST 0x00f00000 515*4882a593Smuzhiyun #define FLD_VBI2_BITINC 0x000fff00 516*4882a593Smuzhiyun #define FLD_VBI2_HDELAY 0x000000ff 517*4882a593Smuzhiyun 518*4882a593Smuzhiyun /*****************************************************************************/ 519*4882a593Smuzhiyun #define VBI_CUST2_CFG2 0x45c 520*4882a593Smuzhiyun #define FLD_VBI2_FC_LENGTH 0x1f000000 521*4882a593Smuzhiyun #define FLD_VBI2_FRAME_CODE 0x00ffffff 522*4882a593Smuzhiyun 523*4882a593Smuzhiyun /*****************************************************************************/ 524*4882a593Smuzhiyun #define VBI_CUST2_CFG3 0x460 525*4882a593Smuzhiyun #define FLD_VBI2_HAM_EN 0x80000000 526*4882a593Smuzhiyun #define FLD_VBI2_FIFO_MODE 0x70000000 527*4882a593Smuzhiyun #define FLD_VBI2_FORMAT_TYPE 0x0f000000 528*4882a593Smuzhiyun #define FLD_VBI2_PAYLD_LENGTH 0x00ff0000 529*4882a593Smuzhiyun #define FLD_VBI2_CRI_LENGTH 0x0000f000 530*4882a593Smuzhiyun #define FLD_VBI2_CRI_MARGIN 0x00000f00 531*4882a593Smuzhiyun #define FLD_VBI2_CRI_TIME 0x000000ff 532*4882a593Smuzhiyun 533*4882a593Smuzhiyun /*****************************************************************************/ 534*4882a593Smuzhiyun #define VBI_CUST3_CFG1 0x464 535*4882a593Smuzhiyun /* Reserved [31] */ 536*4882a593Smuzhiyun #define FLD_VBI3_CRIWIN 0x7f000000 537*4882a593Smuzhiyun #define FLD_VBI3_SLICE_DIST 0x00f00000 538*4882a593Smuzhiyun #define FLD_VBI3_BITINC 0x000fff00 539*4882a593Smuzhiyun #define FLD_VBI3_HDELAY 0x000000ff 540*4882a593Smuzhiyun 541*4882a593Smuzhiyun /*****************************************************************************/ 542*4882a593Smuzhiyun #define VBI_CUST3_CFG2 0x468 543*4882a593Smuzhiyun #define FLD_VBI3_FC_LENGTH 0x1f000000 544*4882a593Smuzhiyun #define FLD_VBI3_FRAME_CODE 0x00ffffff 545*4882a593Smuzhiyun 546*4882a593Smuzhiyun /*****************************************************************************/ 547*4882a593Smuzhiyun #define VBI_CUST3_CFG3 0x46c 548*4882a593Smuzhiyun #define FLD_VBI3_HAM_EN 0x80000000 549*4882a593Smuzhiyun #define FLD_VBI3_FIFO_MODE 0x70000000 550*4882a593Smuzhiyun #define FLD_VBI3_FORMAT_TYPE 0x0f000000 551*4882a593Smuzhiyun #define FLD_VBI3_PAYLD_LENGTH 0x00ff0000 552*4882a593Smuzhiyun #define FLD_VBI3_CRI_LENGTH 0x0000f000 553*4882a593Smuzhiyun #define FLD_VBI3_CRI_MARGIN 0x00000f00 554*4882a593Smuzhiyun #define FLD_VBI3_CRI_TIME 0x000000ff 555*4882a593Smuzhiyun 556*4882a593Smuzhiyun /*****************************************************************************/ 557*4882a593Smuzhiyun #define HORIZ_TIM_CTRL 0x470 558*4882a593Smuzhiyun #define FLD_BGDEL_CNT 0xff000000 559*4882a593Smuzhiyun /* Reserved [23:22] */ 560*4882a593Smuzhiyun #define FLD_HACTIVE_CNT 0x003ff000 561*4882a593Smuzhiyun /* Reserved [11:10] */ 562*4882a593Smuzhiyun #define FLD_HBLANK_CNT 0x000003ff 563*4882a593Smuzhiyun 564*4882a593Smuzhiyun /*****************************************************************************/ 565*4882a593Smuzhiyun #define VERT_TIM_CTRL 0x474 566*4882a593Smuzhiyun #define FLD_V656BLANK_CNT 0xff000000 567*4882a593Smuzhiyun /* Reserved [23:22] */ 568*4882a593Smuzhiyun #define FLD_VACTIVE_CNT 0x003ff000 569*4882a593Smuzhiyun /* Reserved [11:10] */ 570*4882a593Smuzhiyun #define FLD_VBLANK_CNT 0x000003ff 571*4882a593Smuzhiyun 572*4882a593Smuzhiyun /*****************************************************************************/ 573*4882a593Smuzhiyun #define SRC_COMB_CFG 0x478 574*4882a593Smuzhiyun #define FLD_CCOMB_2LN_CHECK 0x80000000 575*4882a593Smuzhiyun #define FLD_CCOMB_3LN_EN 0x40000000 576*4882a593Smuzhiyun #define FLD_CCOMB_2LN_EN 0x20000000 577*4882a593Smuzhiyun #define FLD_CCOMB_3D_EN 0x10000000 578*4882a593Smuzhiyun /* Reserved [27] */ 579*4882a593Smuzhiyun #define FLD_LCOMB_3LN_EN 0x04000000 580*4882a593Smuzhiyun #define FLD_LCOMB_2LN_EN 0x02000000 581*4882a593Smuzhiyun #define FLD_LCOMB_3D_EN 0x01000000 582*4882a593Smuzhiyun #define FLD_LUMA_LPF_SEL 0x00c00000 583*4882a593Smuzhiyun #define FLD_UV_LPF_SEL 0x00300000 584*4882a593Smuzhiyun #define FLD_BLEND_SLOPE 0x000f0000 585*4882a593Smuzhiyun #define FLD_CCOMB_REDUCE_EN 0x00008000 586*4882a593Smuzhiyun /* Reserved [14:10] */ 587*4882a593Smuzhiyun #define FLD_SRC_DECIM_RATIO 0x000003ff 588*4882a593Smuzhiyun 589*4882a593Smuzhiyun /*****************************************************************************/ 590*4882a593Smuzhiyun #define CHROMA_VBIOFF_CFG 0x47c 591*4882a593Smuzhiyun #define FLD_VBI_VOFFSET 0x1f000000 592*4882a593Smuzhiyun /* Reserved [23:20] */ 593*4882a593Smuzhiyun #define FLD_SC_STEP 0x000fffff 594*4882a593Smuzhiyun 595*4882a593Smuzhiyun /*****************************************************************************/ 596*4882a593Smuzhiyun #define FIELD_COUNT 0x480 597*4882a593Smuzhiyun #define FLD_FIELD_COUNT_FLD 0x000003ff 598*4882a593Smuzhiyun 599*4882a593Smuzhiyun /*****************************************************************************/ 600*4882a593Smuzhiyun #define MISC_TIM_CTRL 0x484 601*4882a593Smuzhiyun #define FLD_DEBOUNCE_COUNT 0xc0000000 602*4882a593Smuzhiyun #define FLD_VT_LINE_CNT_HYST 0x30000000 603*4882a593Smuzhiyun /* Reserved [27] */ 604*4882a593Smuzhiyun #define FLD_AFD_STAT 0x07ff0000 605*4882a593Smuzhiyun #define FLD_VPRES_VERT_EN 0x00008000 606*4882a593Smuzhiyun /* Reserved [14:12] */ 607*4882a593Smuzhiyun #define FLD_HR32 0x00000800 608*4882a593Smuzhiyun #define FLD_TDALGN 0x00000400 609*4882a593Smuzhiyun #define FLD_TDFIELD 0x00000200 610*4882a593Smuzhiyun /* Reserved [8:6] */ 611*4882a593Smuzhiyun #define FLD_TEMPDEC 0x0000003f 612*4882a593Smuzhiyun 613*4882a593Smuzhiyun /*****************************************************************************/ 614*4882a593Smuzhiyun #define DFE_CTRL1 0x488 615*4882a593Smuzhiyun #define FLD_CLAMP_AUTO_EN 0x80000000 616*4882a593Smuzhiyun #define FLD_AGC_AUTO_EN 0x40000000 617*4882a593Smuzhiyun #define FLD_VGA_CRUSH_EN 0x20000000 618*4882a593Smuzhiyun #define FLD_VGA_AUTO_EN 0x10000000 619*4882a593Smuzhiyun #define FLD_VBI_GATE_EN 0x08000000 620*4882a593Smuzhiyun #define FLD_CLAMP_LEVEL 0x07000000 621*4882a593Smuzhiyun /* Reserved [23:22] */ 622*4882a593Smuzhiyun #define FLD_CLAMP_SKIP_CNT 0x00300000 623*4882a593Smuzhiyun #define FLD_AGC_GAIN 0x000fff00 624*4882a593Smuzhiyun /* Reserved [7:6] */ 625*4882a593Smuzhiyun #define FLD_VGA_GAIN 0x0000003f 626*4882a593Smuzhiyun 627*4882a593Smuzhiyun /*****************************************************************************/ 628*4882a593Smuzhiyun #define DFE_CTRL2 0x48c 629*4882a593Smuzhiyun #define FLD_VGA_ACQUIRE_RANGE 0x00ff0000 630*4882a593Smuzhiyun #define FLD_VGA_TRACK_RANGE 0x0000ff00 631*4882a593Smuzhiyun #define FLD_VGA_SYNC 0x000000ff 632*4882a593Smuzhiyun 633*4882a593Smuzhiyun /*****************************************************************************/ 634*4882a593Smuzhiyun #define DFE_CTRL3 0x490 635*4882a593Smuzhiyun #define FLD_BP_PERCENT 0xff000000 636*4882a593Smuzhiyun #define FLD_DFT_THRESHOLD 0x00ff0000 637*4882a593Smuzhiyun /* Reserved [15:12] */ 638*4882a593Smuzhiyun #define FLD_SYNC_WIDTH_SEL 0x00000600 639*4882a593Smuzhiyun #define FLD_BP_LOOP_GAIN 0x00000300 640*4882a593Smuzhiyun #define FLD_SYNC_LOOP_GAIN 0x000000c0 641*4882a593Smuzhiyun /* Reserved [5:4] */ 642*4882a593Smuzhiyun #define FLD_AGC_LOOP_GAIN 0x0000000c 643*4882a593Smuzhiyun #define FLD_DCC_LOOP_GAIN 0x00000003 644*4882a593Smuzhiyun 645*4882a593Smuzhiyun /*****************************************************************************/ 646*4882a593Smuzhiyun #define PLL_CTRL 0x494 647*4882a593Smuzhiyun #define FLD_PLL_KD 0xff000000 648*4882a593Smuzhiyun #define FLD_PLL_KI 0x00ff0000 649*4882a593Smuzhiyun #define FLD_PLL_MAX_OFFSET 0x0000ffff 650*4882a593Smuzhiyun 651*4882a593Smuzhiyun /*****************************************************************************/ 652*4882a593Smuzhiyun #define HTL_CTRL 0x498 653*4882a593Smuzhiyun /* Reserved [31:24] */ 654*4882a593Smuzhiyun #define FLD_AUTO_LOCK_SPD 0x00080000 655*4882a593Smuzhiyun #define FLD_MAN_FAST_LOCK 0x00040000 656*4882a593Smuzhiyun #define FLD_HTL_15K_EN 0x00020000 657*4882a593Smuzhiyun #define FLD_HTL_500K_EN 0x00010000 658*4882a593Smuzhiyun #define FLD_HTL_KD 0x0000ff00 659*4882a593Smuzhiyun #define FLD_HTL_KI 0x000000ff 660*4882a593Smuzhiyun 661*4882a593Smuzhiyun /*****************************************************************************/ 662*4882a593Smuzhiyun #define COMB_CTRL 0x49c 663*4882a593Smuzhiyun #define FLD_COMB_PHASE_LIMIT 0xff000000 664*4882a593Smuzhiyun #define FLD_CCOMB_ERR_LIMIT 0x00ff0000 665*4882a593Smuzhiyun #define FLD_LUMA_THRESHOLD 0x0000ff00 666*4882a593Smuzhiyun #define FLD_LCOMB_ERR_LIMIT 0x000000ff 667*4882a593Smuzhiyun 668*4882a593Smuzhiyun /*****************************************************************************/ 669*4882a593Smuzhiyun #define CRUSH_CTRL 0x4a0 670*4882a593Smuzhiyun #define FLD_WTW_EN 0x00400000 671*4882a593Smuzhiyun #define FLD_CRUSH_FREQ 0x00200000 672*4882a593Smuzhiyun #define FLD_MAJ_SEL_EN 0x00100000 673*4882a593Smuzhiyun #define FLD_MAJ_SEL 0x000c0000 674*4882a593Smuzhiyun /* Reserved [17:15] */ 675*4882a593Smuzhiyun #define FLD_SYNC_TIP_REDUCE 0x00007e00 676*4882a593Smuzhiyun /* Reserved [8:6] */ 677*4882a593Smuzhiyun #define FLD_SYNC_TIP_INC 0x0000003f 678*4882a593Smuzhiyun 679*4882a593Smuzhiyun /*****************************************************************************/ 680*4882a593Smuzhiyun #define SOFT_RST_CTRL 0x4a4 681*4882a593Smuzhiyun #define FLD_VD_SOFT_RST 0x00008000 682*4882a593Smuzhiyun /* Reserved [14:12] */ 683*4882a593Smuzhiyun #define FLD_REG_RST_MSK 0x00000800 684*4882a593Smuzhiyun #define FLD_VOF_RST_MSK 0x00000400 685*4882a593Smuzhiyun #define FLD_MVDET_RST_MSK 0x00000200 686*4882a593Smuzhiyun #define FLD_VBI_RST_MSK 0x00000100 687*4882a593Smuzhiyun #define FLD_SCALE_RST_MSK 0x00000080 688*4882a593Smuzhiyun #define FLD_CHROMA_RST_MSK 0x00000040 689*4882a593Smuzhiyun #define FLD_LUMA_RST_MSK 0x00000020 690*4882a593Smuzhiyun #define FLD_VTG_RST_MSK 0x00000010 691*4882a593Smuzhiyun #define FLD_YCSEP_RST_MSK 0x00000008 692*4882a593Smuzhiyun #define FLD_SRC_RST_MSK 0x00000004 693*4882a593Smuzhiyun #define FLD_DFE_RST_MSK 0x00000002 694*4882a593Smuzhiyun /* Reserved [0] */ 695*4882a593Smuzhiyun 696*4882a593Smuzhiyun /*****************************************************************************/ 697*4882a593Smuzhiyun #define MV_DT_CTRL1 0x4a8 698*4882a593Smuzhiyun /* Reserved [31:29] */ 699*4882a593Smuzhiyun #define FLD_PSP_STOP_LINE 0x1f000000 700*4882a593Smuzhiyun /* Reserved [23:21] */ 701*4882a593Smuzhiyun #define FLD_PSP_STRT_LINE 0x001f0000 702*4882a593Smuzhiyun /* Reserved [15] */ 703*4882a593Smuzhiyun #define FLD_PSP_LLIMW 0x00007f00 704*4882a593Smuzhiyun /* Reserved [7] */ 705*4882a593Smuzhiyun #define FLD_PSP_ULIMW 0x0000007f 706*4882a593Smuzhiyun 707*4882a593Smuzhiyun /*****************************************************************************/ 708*4882a593Smuzhiyun #define MV_DT_CTRL2 0x4aC 709*4882a593Smuzhiyun #define FLD_CS_STOPWIN 0xff000000 710*4882a593Smuzhiyun #define FLD_CS_STRTWIN 0x00ff0000 711*4882a593Smuzhiyun #define FLD_CS_WIDTH 0x0000ff00 712*4882a593Smuzhiyun #define FLD_PSP_SPEC_VAL 0x000000ff 713*4882a593Smuzhiyun 714*4882a593Smuzhiyun /*****************************************************************************/ 715*4882a593Smuzhiyun #define MV_DT_CTRL3 0x4B0 716*4882a593Smuzhiyun #define FLD_AUTO_RATE_DIS 0x80000000 717*4882a593Smuzhiyun #define FLD_HLOCK_DIS 0x40000000 718*4882a593Smuzhiyun #define FLD_SEL_FIELD_CNT 0x20000000 719*4882a593Smuzhiyun #define FLD_CS_TYPE2_SEL 0x10000000 720*4882a593Smuzhiyun #define FLD_CS_LINE_THRSH_SEL 0x08000000 721*4882a593Smuzhiyun #define FLD_CS_ATHRESH_SEL 0x04000000 722*4882a593Smuzhiyun #define FLD_PSP_SPEC_SEL 0x02000000 723*4882a593Smuzhiyun #define FLD_PSP_LINES_SEL 0x01000000 724*4882a593Smuzhiyun #define FLD_FIELD_CNT 0x00f00000 725*4882a593Smuzhiyun #define FLD_CS_TYPE2_CNT 0x000fc000 726*4882a593Smuzhiyun #define FLD_CS_LINE_CNT 0x00003f00 727*4882a593Smuzhiyun #define FLD_CS_ATHRESH_LEV 0x000000ff 728*4882a593Smuzhiyun 729*4882a593Smuzhiyun /*****************************************************************************/ 730*4882a593Smuzhiyun #define CHIP_VERSION 0x4b4 731*4882a593Smuzhiyun /* Cx231xx redefine */ 732*4882a593Smuzhiyun #define VERSION 0x4b4 733*4882a593Smuzhiyun #define FLD_REV_ID 0x000000ff 734*4882a593Smuzhiyun 735*4882a593Smuzhiyun /*****************************************************************************/ 736*4882a593Smuzhiyun #define MISC_DIAG_CTRL 0x4b8 737*4882a593Smuzhiyun /* Reserved [31:24] */ 738*4882a593Smuzhiyun #define FLD_SC_CONVERGE_THRESH 0x00ff0000 739*4882a593Smuzhiyun #define FLD_CCOMB_ERR_LIMIT_3D 0x0000ff00 740*4882a593Smuzhiyun #define FLD_LCOMB_ERR_LIMIT_3D 0x000000ff 741*4882a593Smuzhiyun 742*4882a593Smuzhiyun /*****************************************************************************/ 743*4882a593Smuzhiyun #define VBI_PASS_CTRL 0x4bc 744*4882a593Smuzhiyun #define FLD_VBI_PASS_MD 0x00200000 745*4882a593Smuzhiyun #define FLD_VBI_SETUP_DIS 0x00100000 746*4882a593Smuzhiyun #define FLD_PASS_LINE_CTRL 0x000fffff 747*4882a593Smuzhiyun 748*4882a593Smuzhiyun /*****************************************************************************/ 749*4882a593Smuzhiyun /* Cx231xx redefine */ 750*4882a593Smuzhiyun #define VCR_DET_CTRL 0x4c0 751*4882a593Smuzhiyun #define FLD_EN_FIELD_PHASE_DET 0x80000000 752*4882a593Smuzhiyun #define FLD_EN_HEAD_SW_DET 0x40000000 753*4882a593Smuzhiyun #define FLD_FIELD_PHASE_LENGTH 0x01ff0000 754*4882a593Smuzhiyun /* Reserved [29:25] */ 755*4882a593Smuzhiyun #define FLD_FIELD_PHASE_DELAY 0x0000ff00 756*4882a593Smuzhiyun #define FLD_FIELD_PHASE_LIMIT 0x000000f0 757*4882a593Smuzhiyun #define FLD_HEAD_SW_DET_LIMIT 0x0000000f 758*4882a593Smuzhiyun 759*4882a593Smuzhiyun /*****************************************************************************/ 760*4882a593Smuzhiyun #define DL_CTL 0x800 761*4882a593Smuzhiyun #define DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */ 762*4882a593Smuzhiyun #define DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */ 763*4882a593Smuzhiyun #define DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */ 764*4882a593Smuzhiyun #define DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */ 765*4882a593Smuzhiyun /* Reserved [31:5] */ 766*4882a593Smuzhiyun #define FLD_START_8051 0x10000000 767*4882a593Smuzhiyun #define FLD_DL_ENABLE 0x08000000 768*4882a593Smuzhiyun #define FLD_DL_AUTO_INC 0x04000000 769*4882a593Smuzhiyun #define FLD_DL_MAP 0x03000000 770*4882a593Smuzhiyun 771*4882a593Smuzhiyun /*****************************************************************************/ 772*4882a593Smuzhiyun #define STD_DET_STATUS 0x804 773*4882a593Smuzhiyun #define FLD_SPARE_STATUS1 0xff000000 774*4882a593Smuzhiyun #define FLD_SPARE_STATUS0 0x00ff0000 775*4882a593Smuzhiyun #define FLD_MOD_DET_STATUS1 0x0000ff00 776*4882a593Smuzhiyun #define FLD_MOD_DET_STATUS0 0x000000ff 777*4882a593Smuzhiyun 778*4882a593Smuzhiyun /*****************************************************************************/ 779*4882a593Smuzhiyun #define AUD_BUILD_NUM 0x806 780*4882a593Smuzhiyun #define AUD_VER_NUM 0x807 781*4882a593Smuzhiyun #define STD_DET_CTL 0x808 782*4882a593Smuzhiyun #define STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */ 783*4882a593Smuzhiyun #define STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */ 784*4882a593Smuzhiyun #define FLD_SPARE_CTL0 0xff000000 785*4882a593Smuzhiyun #define FLD_DIS_DBX 0x00800000 786*4882a593Smuzhiyun #define FLD_DIS_BTSC 0x00400000 787*4882a593Smuzhiyun #define FLD_DIS_NICAM_A2 0x00200000 788*4882a593Smuzhiyun #define FLD_VIDEO_PRESENT 0x00100000 789*4882a593Smuzhiyun #define FLD_DW8051_VIDEO_FORMAT 0x000f0000 790*4882a593Smuzhiyun #define FLD_PREF_DEC_MODE 0x0000ff00 791*4882a593Smuzhiyun #define FLD_AUD_CONFIG 0x000000ff 792*4882a593Smuzhiyun 793*4882a593Smuzhiyun /*****************************************************************************/ 794*4882a593Smuzhiyun #define DW8051_INT 0x80c 795*4882a593Smuzhiyun #define FLD_VIDEO_PRESENT_CHANGE 0x80000000 796*4882a593Smuzhiyun #define FLD_VIDEO_CHANGE 0x40000000 797*4882a593Smuzhiyun #define FLD_RDS_READY 0x20000000 798*4882a593Smuzhiyun #define FLD_AC97_INT 0x10000000 799*4882a593Smuzhiyun #define FLD_NICAM_BIT_ERROR_TOO_HIGH 0x08000000 800*4882a593Smuzhiyun #define FLD_NICAM_LOCK 0x04000000 801*4882a593Smuzhiyun #define FLD_NICAM_UNLOCK 0x02000000 802*4882a593Smuzhiyun #define FLD_DFT4_TH_CMP 0x01000000 803*4882a593Smuzhiyun /* Reserved [23:22] */ 804*4882a593Smuzhiyun #define FLD_LOCK_IND_INT 0x00200000 805*4882a593Smuzhiyun #define FLD_DFT3_TH_CMP 0x00100000 806*4882a593Smuzhiyun #define FLD_DFT2_TH_CMP 0x00080000 807*4882a593Smuzhiyun #define FLD_DFT1_TH_CMP 0x00040000 808*4882a593Smuzhiyun #define FLD_FM2_DFT_TH_CMP 0x00020000 809*4882a593Smuzhiyun #define FLD_FM1_DFT_TH_CMP 0x00010000 810*4882a593Smuzhiyun #define FLD_VIDEO_PRESENT_EN 0x00008000 811*4882a593Smuzhiyun #define FLD_VIDEO_CHANGE_EN 0x00004000 812*4882a593Smuzhiyun #define FLD_RDS_READY_EN 0x00002000 813*4882a593Smuzhiyun #define FLD_AC97_INT_EN 0x00001000 814*4882a593Smuzhiyun #define FLD_NICAM_BIT_ERROR_TOO_HIGH_EN 0x00000800 815*4882a593Smuzhiyun #define FLD_NICAM_LOCK_EN 0x00000400 816*4882a593Smuzhiyun #define FLD_NICAM_UNLOCK_EN 0x00000200 817*4882a593Smuzhiyun #define FLD_DFT4_TH_CMP_EN 0x00000100 818*4882a593Smuzhiyun /* Reserved [7] */ 819*4882a593Smuzhiyun #define FLD_DW8051_INT6_CTL1 0x00000040 820*4882a593Smuzhiyun #define FLD_DW8051_INT5_CTL1 0x00000020 821*4882a593Smuzhiyun #define FLD_DW8051_INT4_CTL1 0x00000010 822*4882a593Smuzhiyun #define FLD_DW8051_INT3_CTL1 0x00000008 823*4882a593Smuzhiyun #define FLD_DW8051_INT2_CTL1 0x00000004 824*4882a593Smuzhiyun #define FLD_DW8051_INT1_CTL1 0x00000002 825*4882a593Smuzhiyun #define FLD_DW8051_INT0_CTL1 0x00000001 826*4882a593Smuzhiyun 827*4882a593Smuzhiyun /*****************************************************************************/ 828*4882a593Smuzhiyun #define GENERAL_CTL 0x810 829*4882a593Smuzhiyun #define FLD_RDS_INT 0x80000000 830*4882a593Smuzhiyun #define FLD_NBER_INT 0x40000000 831*4882a593Smuzhiyun #define FLD_NLL_INT 0x20000000 832*4882a593Smuzhiyun #define FLD_IFL_INT 0x10000000 833*4882a593Smuzhiyun #define FLD_FDL_INT 0x08000000 834*4882a593Smuzhiyun #define FLD_AFC_INT 0x04000000 835*4882a593Smuzhiyun #define FLD_AMC_INT 0x02000000 836*4882a593Smuzhiyun #define FLD_AC97_INT_CTL 0x01000000 837*4882a593Smuzhiyun #define FLD_RDS_INT_DIS 0x00800000 838*4882a593Smuzhiyun #define FLD_NBER_INT_DIS 0x00400000 839*4882a593Smuzhiyun #define FLD_NLL_INT_DIS 0x00200000 840*4882a593Smuzhiyun #define FLD_IFL_INT_DIS 0x00100000 841*4882a593Smuzhiyun #define FLD_FDL_INT_DIS 0x00080000 842*4882a593Smuzhiyun #define FLD_FC_INT_DIS 0x00040000 843*4882a593Smuzhiyun #define FLD_AMC_INT_DIS 0x00020000 844*4882a593Smuzhiyun #define FLD_AC97_INT_DIS 0x00010000 845*4882a593Smuzhiyun #define FLD_REV_NUM 0x0000ff00 846*4882a593Smuzhiyun /* Reserved [7:5] */ 847*4882a593Smuzhiyun #define FLD_DBX_SOFT_RESET_REG 0x00000010 848*4882a593Smuzhiyun #define FLD_AD_SOFT_RESET_REG 0x00000008 849*4882a593Smuzhiyun #define FLD_SRC_SOFT_RESET_REG 0x00000004 850*4882a593Smuzhiyun #define FLD_CDMOD_SOFT_RESET 0x00000002 851*4882a593Smuzhiyun #define FLD_8051_SOFT_RESET 0x00000001 852*4882a593Smuzhiyun 853*4882a593Smuzhiyun /*****************************************************************************/ 854*4882a593Smuzhiyun #define AAGC_CTL 0x814 855*4882a593Smuzhiyun #define FLD_AFE_12DB_EN 0x80000000 856*4882a593Smuzhiyun #define FLD_AAGC_DEFAULT_EN 0x40000000 857*4882a593Smuzhiyun #define FLD_AAGC_DEFAULT 0x3f000000 858*4882a593Smuzhiyun /* Reserved [23] */ 859*4882a593Smuzhiyun #define FLD_AAGC_GAIN 0x00600000 860*4882a593Smuzhiyun #define FLD_AAGC_TH 0x001f0000 861*4882a593Smuzhiyun /* Reserved [15:14] */ 862*4882a593Smuzhiyun #define FLD_AAGC_HYST2 0x00003f00 863*4882a593Smuzhiyun /* Reserved [7:6] */ 864*4882a593Smuzhiyun #define FLD_AAGC_HYST1 0x0000003f 865*4882a593Smuzhiyun 866*4882a593Smuzhiyun /*****************************************************************************/ 867*4882a593Smuzhiyun #define IF_SRC_CTL 0x818 868*4882a593Smuzhiyun #define FLD_DBX_BYPASS 0x80000000 869*4882a593Smuzhiyun /* Reserved [30:25] */ 870*4882a593Smuzhiyun #define FLD_IF_SRC_MODE 0x01000000 871*4882a593Smuzhiyun /* Reserved [23:18] */ 872*4882a593Smuzhiyun #define FLD_IF_SRC_PHASE_INC 0x0001ffff 873*4882a593Smuzhiyun 874*4882a593Smuzhiyun /*****************************************************************************/ 875*4882a593Smuzhiyun #define ANALOG_DEMOD_CTL 0x81c 876*4882a593Smuzhiyun #define FLD_ROT1_PHACC_PROG 0xffff0000 877*4882a593Smuzhiyun /* Reserved [15] */ 878*4882a593Smuzhiyun #define FLD_FM1_DELAY_FIX 0x00007000 879*4882a593Smuzhiyun #define FLD_PDF4_SHIFT 0x00000c00 880*4882a593Smuzhiyun #define FLD_PDF3_SHIFT 0x00000300 881*4882a593Smuzhiyun #define FLD_PDF2_SHIFT 0x000000c0 882*4882a593Smuzhiyun #define FLD_PDF1_SHIFT 0x00000030 883*4882a593Smuzhiyun #define FLD_FMBYPASS_MODE2 0x00000008 884*4882a593Smuzhiyun #define FLD_FMBYPASS_MODE1 0x00000004 885*4882a593Smuzhiyun #define FLD_NICAM_MODE 0x00000002 886*4882a593Smuzhiyun #define FLD_BTSC_FMRADIO_MODE 0x00000001 887*4882a593Smuzhiyun 888*4882a593Smuzhiyun /*****************************************************************************/ 889*4882a593Smuzhiyun #define ROT_FREQ_CTL 0x820 890*4882a593Smuzhiyun #define FLD_ROT3_PHACC_PROG 0xffff0000 891*4882a593Smuzhiyun #define FLD_ROT2_PHACC_PROG 0x0000ffff 892*4882a593Smuzhiyun 893*4882a593Smuzhiyun /*****************************************************************************/ 894*4882a593Smuzhiyun #define FM_CTL 0x824 895*4882a593Smuzhiyun #define FLD_FM2_DC_FB_SHIFT 0xf0000000 896*4882a593Smuzhiyun #define FLD_FM2_DC_INT_SHIFT 0x0f000000 897*4882a593Smuzhiyun #define FLD_FM2_AFC_RESET 0x00800000 898*4882a593Smuzhiyun #define FLD_FM2_DC_PASS_IN 0x00400000 899*4882a593Smuzhiyun #define FLD_FM2_DAGC_SHIFT 0x00380000 900*4882a593Smuzhiyun #define FLD_FM2_CORDIC_SHIFT 0x00070000 901*4882a593Smuzhiyun #define FLD_FM1_DC_FB_SHIFT 0x0000f000 902*4882a593Smuzhiyun #define FLD_FM1_DC_INT_SHIFT 0x00000f00 903*4882a593Smuzhiyun #define FLD_FM1_AFC_RESET 0x00000080 904*4882a593Smuzhiyun #define FLD_FM1_DC_PASS_IN 0x00000040 905*4882a593Smuzhiyun #define FLD_FM1_DAGC_SHIFT 0x00000038 906*4882a593Smuzhiyun #define FLD_FM1_CORDIC_SHIFT 0x00000007 907*4882a593Smuzhiyun 908*4882a593Smuzhiyun /*****************************************************************************/ 909*4882a593Smuzhiyun #define LPF_PDF_CTL 0x828 910*4882a593Smuzhiyun /* Reserved [31:30] */ 911*4882a593Smuzhiyun #define FLD_LPF32_SHIFT1 0x30000000 912*4882a593Smuzhiyun #define FLD_LPF32_SHIFT2 0x0c000000 913*4882a593Smuzhiyun #define FLD_LPF160_SHIFTA 0x03000000 914*4882a593Smuzhiyun #define FLD_LPF160_SHIFTB 0x00c00000 915*4882a593Smuzhiyun #define FLD_LPF160_SHIFTC 0x00300000 916*4882a593Smuzhiyun #define FLD_LPF32_COEF_SEL2 0x000c0000 917*4882a593Smuzhiyun #define FLD_LPF32_COEF_SEL1 0x00030000 918*4882a593Smuzhiyun #define FLD_LPF160_COEF_SELC 0x0000c000 919*4882a593Smuzhiyun #define FLD_LPF160_COEF_SELB 0x00003000 920*4882a593Smuzhiyun #define FLD_LPF160_COEF_SELA 0x00000c00 921*4882a593Smuzhiyun #define FLD_LPF160_IN_EN_REG 0x00000300 922*4882a593Smuzhiyun #define FLD_PDF4_PDF_SEL 0x000000c0 923*4882a593Smuzhiyun #define FLD_PDF3_PDF_SEL 0x00000030 924*4882a593Smuzhiyun #define FLD_PDF2_PDF_SEL 0x0000000c 925*4882a593Smuzhiyun #define FLD_PDF1_PDF_SEL 0x00000003 926*4882a593Smuzhiyun 927*4882a593Smuzhiyun /*****************************************************************************/ 928*4882a593Smuzhiyun #define DFT1_CTL1 0x82c 929*4882a593Smuzhiyun #define FLD_DFT1_DWELL 0xffff0000 930*4882a593Smuzhiyun #define FLD_DFT1_FREQ 0x0000ffff 931*4882a593Smuzhiyun 932*4882a593Smuzhiyun /*****************************************************************************/ 933*4882a593Smuzhiyun #define DFT1_CTL2 0x830 934*4882a593Smuzhiyun #define FLD_DFT1_THRESHOLD 0xffffff00 935*4882a593Smuzhiyun #define FLD_DFT1_CMP_CTL 0x00000080 936*4882a593Smuzhiyun #define FLD_DFT1_AVG 0x00000070 937*4882a593Smuzhiyun /* Reserved [3:1] */ 938*4882a593Smuzhiyun #define FLD_DFT1_START 0x00000001 939*4882a593Smuzhiyun 940*4882a593Smuzhiyun /*****************************************************************************/ 941*4882a593Smuzhiyun #define DFT1_STATUS 0x834 942*4882a593Smuzhiyun #define FLD_DFT1_DONE 0x80000000 943*4882a593Smuzhiyun #define FLD_DFT1_TH_CMP_STAT 0x40000000 944*4882a593Smuzhiyun #define FLD_DFT1_RESULT 0x3fffffff 945*4882a593Smuzhiyun 946*4882a593Smuzhiyun /*****************************************************************************/ 947*4882a593Smuzhiyun #define DFT2_CTL1 0x838 948*4882a593Smuzhiyun #define FLD_DFT2_DWELL 0xffff0000 949*4882a593Smuzhiyun #define FLD_DFT2_FREQ 0x0000ffff 950*4882a593Smuzhiyun 951*4882a593Smuzhiyun /*****************************************************************************/ 952*4882a593Smuzhiyun #define DFT2_CTL2 0x83C 953*4882a593Smuzhiyun #define FLD_DFT2_THRESHOLD 0xffffff00 954*4882a593Smuzhiyun #define FLD_DFT2_CMP_CTL 0x00000080 955*4882a593Smuzhiyun #define FLD_DFT2_AVG 0x00000070 956*4882a593Smuzhiyun /* Reserved [3:1] */ 957*4882a593Smuzhiyun #define FLD_DFT2_START 0x00000001 958*4882a593Smuzhiyun 959*4882a593Smuzhiyun /*****************************************************************************/ 960*4882a593Smuzhiyun #define DFT2_STATUS 0x840 961*4882a593Smuzhiyun #define FLD_DFT2_DONE 0x80000000 962*4882a593Smuzhiyun #define FLD_DFT2_TH_CMP_STAT 0x40000000 963*4882a593Smuzhiyun #define FLD_DFT2_RESULT 0x3fffffff 964*4882a593Smuzhiyun 965*4882a593Smuzhiyun /*****************************************************************************/ 966*4882a593Smuzhiyun #define DFT3_CTL1 0x844 967*4882a593Smuzhiyun #define FLD_DFT3_DWELL 0xffff0000 968*4882a593Smuzhiyun #define FLD_DFT3_FREQ 0x0000ffff 969*4882a593Smuzhiyun 970*4882a593Smuzhiyun /*****************************************************************************/ 971*4882a593Smuzhiyun #define DFT3_CTL2 0x848 972*4882a593Smuzhiyun #define FLD_DFT3_THRESHOLD 0xffffff00 973*4882a593Smuzhiyun #define FLD_DFT3_CMP_CTL 0x00000080 974*4882a593Smuzhiyun #define FLD_DFT3_AVG 0x00000070 975*4882a593Smuzhiyun /* Reserved [3:1] */ 976*4882a593Smuzhiyun #define FLD_DFT3_START 0x00000001 977*4882a593Smuzhiyun 978*4882a593Smuzhiyun /*****************************************************************************/ 979*4882a593Smuzhiyun #define DFT3_STATUS 0x84c 980*4882a593Smuzhiyun #define FLD_DFT3_DONE 0x80000000 981*4882a593Smuzhiyun #define FLD_DFT3_TH_CMP_STAT 0x40000000 982*4882a593Smuzhiyun #define FLD_DFT3_RESULT 0x3fffffff 983*4882a593Smuzhiyun 984*4882a593Smuzhiyun /*****************************************************************************/ 985*4882a593Smuzhiyun #define DFT4_CTL1 0x850 986*4882a593Smuzhiyun #define FLD_DFT4_DWELL 0xffff0000 987*4882a593Smuzhiyun #define FLD_DFT4_FREQ 0x0000ffff 988*4882a593Smuzhiyun 989*4882a593Smuzhiyun /*****************************************************************************/ 990*4882a593Smuzhiyun #define DFT4_CTL2 0x854 991*4882a593Smuzhiyun #define FLD_DFT4_THRESHOLD 0xffffff00 992*4882a593Smuzhiyun #define FLD_DFT4_CMP_CTL 0x00000080 993*4882a593Smuzhiyun #define FLD_DFT4_AVG 0x00000070 994*4882a593Smuzhiyun /* Reserved [3:1] */ 995*4882a593Smuzhiyun #define FLD_DFT4_START 0x00000001 996*4882a593Smuzhiyun 997*4882a593Smuzhiyun /*****************************************************************************/ 998*4882a593Smuzhiyun #define DFT4_STATUS 0x858 999*4882a593Smuzhiyun #define FLD_DFT4_DONE 0x80000000 1000*4882a593Smuzhiyun #define FLD_DFT4_TH_CMP_STAT 0x40000000 1001*4882a593Smuzhiyun #define FLD_DFT4_RESULT 0x3fffffff 1002*4882a593Smuzhiyun 1003*4882a593Smuzhiyun /*****************************************************************************/ 1004*4882a593Smuzhiyun #define AM_MTS_DET 0x85c 1005*4882a593Smuzhiyun #define FLD_AM_MTS_MODE 0x80000000 1006*4882a593Smuzhiyun /* Reserved [30:26] */ 1007*4882a593Smuzhiyun #define FLD_AM_SUB 0x02000000 1008*4882a593Smuzhiyun #define FLD_AM_GAIN_EN 0x01000000 1009*4882a593Smuzhiyun /* Reserved [23:16] */ 1010*4882a593Smuzhiyun #define FLD_AMMTS_GAIN_SCALE 0x0000e000 1011*4882a593Smuzhiyun #define FLD_MTS_PDF_SHIFT 0x00001800 1012*4882a593Smuzhiyun #define FLD_AM_REG_GAIN 0x00000700 1013*4882a593Smuzhiyun #define FLD_AGC_REF 0x000000ff 1014*4882a593Smuzhiyun 1015*4882a593Smuzhiyun /*****************************************************************************/ 1016*4882a593Smuzhiyun #define ANALOG_MUX_CTL 0x860 1017*4882a593Smuzhiyun /* Reserved [31:29] */ 1018*4882a593Smuzhiyun #define FLD_MUX21_SEL 0x10000000 1019*4882a593Smuzhiyun #define FLD_MUX20_SEL 0x08000000 1020*4882a593Smuzhiyun #define FLD_MUX19_SEL 0x04000000 1021*4882a593Smuzhiyun #define FLD_MUX18_SEL 0x02000000 1022*4882a593Smuzhiyun #define FLD_MUX17_SEL 0x01000000 1023*4882a593Smuzhiyun #define FLD_MUX16_SEL 0x00800000 1024*4882a593Smuzhiyun #define FLD_MUX15_SEL 0x00400000 1025*4882a593Smuzhiyun #define FLD_MUX14_SEL 0x00300000 1026*4882a593Smuzhiyun #define FLD_MUX13_SEL 0x000C0000 1027*4882a593Smuzhiyun #define FLD_MUX12_SEL 0x00020000 1028*4882a593Smuzhiyun #define FLD_MUX11_SEL 0x00018000 1029*4882a593Smuzhiyun #define FLD_MUX10_SEL 0x00004000 1030*4882a593Smuzhiyun #define FLD_MUX9_SEL 0x00002000 1031*4882a593Smuzhiyun #define FLD_MUX8_SEL 0x00001000 1032*4882a593Smuzhiyun #define FLD_MUX7_SEL 0x00000800 1033*4882a593Smuzhiyun #define FLD_MUX6_SEL 0x00000600 1034*4882a593Smuzhiyun #define FLD_MUX5_SEL 0x00000100 1035*4882a593Smuzhiyun #define FLD_MUX4_SEL 0x000000c0 1036*4882a593Smuzhiyun #define FLD_MUX3_SEL 0x00000030 1037*4882a593Smuzhiyun #define FLD_MUX2_SEL 0x0000000c 1038*4882a593Smuzhiyun #define FLD_MUX1_SEL 0x00000003 1039*4882a593Smuzhiyun 1040*4882a593Smuzhiyun /*****************************************************************************/ 1041*4882a593Smuzhiyun /* Cx231xx redefine */ 1042*4882a593Smuzhiyun #define DPLL_CTRL1 0x864 1043*4882a593Smuzhiyun #define DIG_PLL_CTL1 0x864 1044*4882a593Smuzhiyun 1045*4882a593Smuzhiyun #define FLD_PLL_STATUS 0x07000000 1046*4882a593Smuzhiyun #define FLD_BANDWIDTH_SELECT 0x00030000 1047*4882a593Smuzhiyun #define FLD_PLL_SHIFT_REG 0x00007000 1048*4882a593Smuzhiyun #define FLD_PHASE_SHIFT 0x000007ff 1049*4882a593Smuzhiyun 1050*4882a593Smuzhiyun /*****************************************************************************/ 1051*4882a593Smuzhiyun /* Cx231xx redefine */ 1052*4882a593Smuzhiyun #define DPLL_CTRL2 0x868 1053*4882a593Smuzhiyun #define DIG_PLL_CTL2 0x868 1054*4882a593Smuzhiyun #define FLD_PLL_UNLOCK_THR 0xff000000 1055*4882a593Smuzhiyun #define FLD_PLL_LOCK_THR 0x00ff0000 1056*4882a593Smuzhiyun /* Reserved [15:8] */ 1057*4882a593Smuzhiyun #define FLD_AM_PDF_SEL2 0x000000c0 1058*4882a593Smuzhiyun #define FLD_AM_PDF_SEL1 0x00000030 1059*4882a593Smuzhiyun #define FLD_DPLL_FSM_CTRL 0x0000000c 1060*4882a593Smuzhiyun /* Reserved [1] */ 1061*4882a593Smuzhiyun #define FLD_PLL_PILOT_DET 0x00000001 1062*4882a593Smuzhiyun 1063*4882a593Smuzhiyun /*****************************************************************************/ 1064*4882a593Smuzhiyun /* Cx231xx redefine */ 1065*4882a593Smuzhiyun #define DPLL_CTRL3 0x86c 1066*4882a593Smuzhiyun #define DIG_PLL_CTL3 0x86c 1067*4882a593Smuzhiyun #define FLD_DISABLE_LOOP 0x01000000 1068*4882a593Smuzhiyun #define FLD_A1_DS1_SEL 0x000c0000 1069*4882a593Smuzhiyun #define FLD_A1_DS2_SEL 0x00030000 1070*4882a593Smuzhiyun #define FLD_A1_KI 0x0000ff00 1071*4882a593Smuzhiyun #define FLD_A1_KD 0x000000ff 1072*4882a593Smuzhiyun 1073*4882a593Smuzhiyun /*****************************************************************************/ 1074*4882a593Smuzhiyun /* Cx231xx redefine */ 1075*4882a593Smuzhiyun #define DPLL_CTRL4 0x870 1076*4882a593Smuzhiyun #define DIG_PLL_CTL4 0x870 1077*4882a593Smuzhiyun #define FLD_A2_DS1_SEL 0x000c0000 1078*4882a593Smuzhiyun #define FLD_A2_DS2_SEL 0x00030000 1079*4882a593Smuzhiyun #define FLD_A2_KI 0x0000ff00 1080*4882a593Smuzhiyun #define FLD_A2_KD 0x000000ff 1081*4882a593Smuzhiyun 1082*4882a593Smuzhiyun /*****************************************************************************/ 1083*4882a593Smuzhiyun /* Cx231xx redefine */ 1084*4882a593Smuzhiyun #define DPLL_CTRL5 0x874 1085*4882a593Smuzhiyun #define DIG_PLL_CTL5 0x874 1086*4882a593Smuzhiyun #define FLD_TRK_DS1_SEL 0x000c0000 1087*4882a593Smuzhiyun #define FLD_TRK_DS2_SEL 0x00030000 1088*4882a593Smuzhiyun #define FLD_TRK_KI 0x0000ff00 1089*4882a593Smuzhiyun #define FLD_TRK_KD 0x000000ff 1090*4882a593Smuzhiyun 1091*4882a593Smuzhiyun /*****************************************************************************/ 1092*4882a593Smuzhiyun #define DEEMPH_GAIN_CTL 0x878 1093*4882a593Smuzhiyun #define FLD_DEEMPH2_GAIN 0xFFFF0000 1094*4882a593Smuzhiyun #define FLD_DEEMPH1_GAIN 0x0000FFFF 1095*4882a593Smuzhiyun 1096*4882a593Smuzhiyun /*****************************************************************************/ 1097*4882a593Smuzhiyun /* Cx231xx redefine */ 1098*4882a593Smuzhiyun #define DEEMPH_COEFF1 0x87c 1099*4882a593Smuzhiyun #define DEEMPH_COEF1 0x87c 1100*4882a593Smuzhiyun #define FLD_DEEMPH_B0 0xffff0000 1101*4882a593Smuzhiyun #define FLD_DEEMPH_A0 0x0000ffff 1102*4882a593Smuzhiyun 1103*4882a593Smuzhiyun /*****************************************************************************/ 1104*4882a593Smuzhiyun /* Cx231xx redefine */ 1105*4882a593Smuzhiyun #define DEEMPH_COEFF2 0x880 1106*4882a593Smuzhiyun #define DEEMPH_COEF2 0x880 1107*4882a593Smuzhiyun #define FLD_DEEMPH_B1 0xFFFF0000 1108*4882a593Smuzhiyun #define FLD_DEEMPH_A1 0x0000FFFF 1109*4882a593Smuzhiyun 1110*4882a593Smuzhiyun /*****************************************************************************/ 1111*4882a593Smuzhiyun #define DBX1_CTL1 0x884 1112*4882a593Smuzhiyun #define FLD_DBX1_WBE_GAIN 0xffff0000 1113*4882a593Smuzhiyun #define FLD_DBX1_IN_GAIN 0x0000ffff 1114*4882a593Smuzhiyun 1115*4882a593Smuzhiyun /*****************************************************************************/ 1116*4882a593Smuzhiyun #define DBX1_CTL2 0x888 1117*4882a593Smuzhiyun #define FLD_DBX1_SE_BYPASS 0xffff0000 1118*4882a593Smuzhiyun #define FLD_DBX1_SE_GAIN 0x0000ffff 1119*4882a593Smuzhiyun 1120*4882a593Smuzhiyun /*****************************************************************************/ 1121*4882a593Smuzhiyun #define DBX1_RMS_SE 0x88C 1122*4882a593Smuzhiyun #define FLD_DBX1_RMS_WBE 0xffff0000 1123*4882a593Smuzhiyun #define FLD_DBX1_RMS_SE_FLD 0x0000ffff 1124*4882a593Smuzhiyun 1125*4882a593Smuzhiyun /*****************************************************************************/ 1126*4882a593Smuzhiyun #define DBX2_CTL1 0x890 1127*4882a593Smuzhiyun #define FLD_DBX2_WBE_GAIN 0xffff0000 1128*4882a593Smuzhiyun #define FLD_DBX2_IN_GAIN 0x0000ffff 1129*4882a593Smuzhiyun 1130*4882a593Smuzhiyun /*****************************************************************************/ 1131*4882a593Smuzhiyun #define DBX2_CTL2 0x894 1132*4882a593Smuzhiyun #define FLD_DBX2_SE_BYPASS 0xffff0000 1133*4882a593Smuzhiyun #define FLD_DBX2_SE_GAIN 0x0000ffff 1134*4882a593Smuzhiyun 1135*4882a593Smuzhiyun /*****************************************************************************/ 1136*4882a593Smuzhiyun #define DBX2_RMS_SE 0x898 1137*4882a593Smuzhiyun #define FLD_DBX2_RMS_WBE 0xffff0000 1138*4882a593Smuzhiyun #define FLD_DBX2_RMS_SE_FLD 0x0000ffff 1139*4882a593Smuzhiyun 1140*4882a593Smuzhiyun /*****************************************************************************/ 1141*4882a593Smuzhiyun #define AM_FM_DIFF 0x89c 1142*4882a593Smuzhiyun /* Reserved [31] */ 1143*4882a593Smuzhiyun #define FLD_FM_DIFF_OUT 0x7fff0000 1144*4882a593Smuzhiyun /* Reserved [15] */ 1145*4882a593Smuzhiyun #define FLD_AM_DIFF_OUT 0x00007fff 1146*4882a593Smuzhiyun 1147*4882a593Smuzhiyun /*****************************************************************************/ 1148*4882a593Smuzhiyun #define NICAM_FAW 0x8a0 1149*4882a593Smuzhiyun #define FLD_FAWDETWINEND 0xFc000000 1150*4882a593Smuzhiyun #define FLD_FAWDETWINSTR 0x03ff0000 1151*4882a593Smuzhiyun /* Reserved [15:12] */ 1152*4882a593Smuzhiyun #define FLD_FAWDETTHRSHLD3 0x00000f00 1153*4882a593Smuzhiyun #define FLD_FAWDETTHRSHLD2 0x000000f0 1154*4882a593Smuzhiyun #define FLD_FAWDETTHRSHLD1 0x0000000f 1155*4882a593Smuzhiyun 1156*4882a593Smuzhiyun /*****************************************************************************/ 1157*4882a593Smuzhiyun /* Cx231xx redefine */ 1158*4882a593Smuzhiyun #define DEEMPH_GAIN 0x8a4 1159*4882a593Smuzhiyun #define NICAM_DEEMPHGAIN 0x8a4 1160*4882a593Smuzhiyun /* Reserved [31:18] */ 1161*4882a593Smuzhiyun #define FLD_DEEMPHGAIN 0x0003ffff 1162*4882a593Smuzhiyun 1163*4882a593Smuzhiyun /*****************************************************************************/ 1164*4882a593Smuzhiyun /* Cx231xx redefine */ 1165*4882a593Smuzhiyun #define DEEMPH_NUMER1 0x8a8 1166*4882a593Smuzhiyun #define NICAM_DEEMPHNUMER1 0x8a8 1167*4882a593Smuzhiyun /* Reserved [31:18] */ 1168*4882a593Smuzhiyun #define FLD_DEEMPHNUMER1 0x0003ffff 1169*4882a593Smuzhiyun 1170*4882a593Smuzhiyun /*****************************************************************************/ 1171*4882a593Smuzhiyun /* Cx231xx redefine */ 1172*4882a593Smuzhiyun #define DEEMPH_NUMER2 0x8ac 1173*4882a593Smuzhiyun #define NICAM_DEEMPHNUMER2 0x8ac 1174*4882a593Smuzhiyun /* Reserved [31:18] */ 1175*4882a593Smuzhiyun #define FLD_DEEMPHNUMER2 0x0003ffff 1176*4882a593Smuzhiyun 1177*4882a593Smuzhiyun /*****************************************************************************/ 1178*4882a593Smuzhiyun /* Cx231xx redefine */ 1179*4882a593Smuzhiyun #define DEEMPH_DENOM1 0x8b0 1180*4882a593Smuzhiyun #define NICAM_DEEMPHDENOM1 0x8b0 1181*4882a593Smuzhiyun /* Reserved [31:18] */ 1182*4882a593Smuzhiyun #define FLD_DEEMPHDENOM1 0x0003ffff 1183*4882a593Smuzhiyun 1184*4882a593Smuzhiyun /*****************************************************************************/ 1185*4882a593Smuzhiyun /* Cx231xx redefine */ 1186*4882a593Smuzhiyun #define DEEMPH_DENOM2 0x8b4 1187*4882a593Smuzhiyun #define NICAM_DEEMPHDENOM2 0x8b4 1188*4882a593Smuzhiyun /* Reserved [31:18] */ 1189*4882a593Smuzhiyun #define FLD_DEEMPHDENOM2 0x0003ffff 1190*4882a593Smuzhiyun 1191*4882a593Smuzhiyun /*****************************************************************************/ 1192*4882a593Smuzhiyun #define NICAM_ERRLOG_CTL1 0x8B8 1193*4882a593Smuzhiyun /* Reserved [31:28] */ 1194*4882a593Smuzhiyun #define FLD_ERRINTRPTTHSHLD1 0x0fff0000 1195*4882a593Smuzhiyun /* Reserved [15:12] */ 1196*4882a593Smuzhiyun #define FLD_ERRLOGPERIOD 0x00000fff 1197*4882a593Smuzhiyun 1198*4882a593Smuzhiyun /*****************************************************************************/ 1199*4882a593Smuzhiyun #define NICAM_ERRLOG_CTL2 0x8bc 1200*4882a593Smuzhiyun /* Reserved [31:28] */ 1201*4882a593Smuzhiyun #define FLD_ERRINTRPTTHSHLD3 0x0fff0000 1202*4882a593Smuzhiyun /* Reserved [15:12] */ 1203*4882a593Smuzhiyun #define FLD_ERRINTRPTTHSHLD2 0x00000fff 1204*4882a593Smuzhiyun 1205*4882a593Smuzhiyun /*****************************************************************************/ 1206*4882a593Smuzhiyun #define NICAM_ERRLOG_STS1 0x8c0 1207*4882a593Smuzhiyun /* Reserved [31:28] */ 1208*4882a593Smuzhiyun #define FLD_ERRLOG2 0x0fff0000 1209*4882a593Smuzhiyun /* Reserved [15:12] */ 1210*4882a593Smuzhiyun #define FLD_ERRLOG1 0x00000fff 1211*4882a593Smuzhiyun 1212*4882a593Smuzhiyun /*****************************************************************************/ 1213*4882a593Smuzhiyun #define NICAM_ERRLOG_STS2 0x8c4 1214*4882a593Smuzhiyun /* Reserved [31:12] */ 1215*4882a593Smuzhiyun #define FLD_ERRLOG3 0x00000fff 1216*4882a593Smuzhiyun 1217*4882a593Smuzhiyun /*****************************************************************************/ 1218*4882a593Smuzhiyun #define NICAM_STATUS 0x8c8 1219*4882a593Smuzhiyun /* Reserved [31:20] */ 1220*4882a593Smuzhiyun #define FLD_NICAM_CIB 0x000c0000 1221*4882a593Smuzhiyun #define FLD_NICAM_LOCK_STAT 0x00020000 1222*4882a593Smuzhiyun #define FLD_NICAM_MUTE 0x00010000 1223*4882a593Smuzhiyun #define FLD_NICAMADDIT_DATA 0x0000ffe0 1224*4882a593Smuzhiyun #define FLD_NICAMCNTRL 0x0000001f 1225*4882a593Smuzhiyun 1226*4882a593Smuzhiyun /*****************************************************************************/ 1227*4882a593Smuzhiyun #define DEMATRIX_CTL 0x8cc 1228*4882a593Smuzhiyun #define FLD_AC97_IN_SHIFT 0xf0000000 1229*4882a593Smuzhiyun #define FLD_I2S_IN_SHIFT 0x0f000000 1230*4882a593Smuzhiyun #define FLD_DEMATRIX_SEL_CTL 0x00ff0000 1231*4882a593Smuzhiyun /* Reserved [15:11] */ 1232*4882a593Smuzhiyun #define FLD_DMTRX_BYPASS 0x00000400 1233*4882a593Smuzhiyun #define FLD_DEMATRIX_MODE 0x00000300 1234*4882a593Smuzhiyun /* Reserved [7:6] */ 1235*4882a593Smuzhiyun #define FLD_PH_DBX_SEL 0x00000020 1236*4882a593Smuzhiyun #define FLD_PH_CH_SEL 0x00000010 1237*4882a593Smuzhiyun #define FLD_PHASE_FIX 0x0000000f 1238*4882a593Smuzhiyun 1239*4882a593Smuzhiyun /*****************************************************************************/ 1240*4882a593Smuzhiyun #define PATH1_CTL1 0x8d0 1241*4882a593Smuzhiyun /* Reserved [31:29] */ 1242*4882a593Smuzhiyun #define FLD_PATH1_MUTE_CTL 0x1f000000 1243*4882a593Smuzhiyun /* Reserved [23:22] */ 1244*4882a593Smuzhiyun #define FLD_PATH1_AVC_CG 0x00300000 1245*4882a593Smuzhiyun #define FLD_PATH1_AVC_RT 0x000f0000 1246*4882a593Smuzhiyun #define FLD_PATH1_AVC_AT 0x0000f000 1247*4882a593Smuzhiyun #define FLD_PATH1_AVC_STEREO 0x00000800 1248*4882a593Smuzhiyun #define FLD_PATH1_AVC_CR 0x00000700 1249*4882a593Smuzhiyun #define FLD_PATH1_AVC_RMS_CON 0x000000f0 1250*4882a593Smuzhiyun #define FLD_PATH1_SEL_CTL 0x0000000f 1251*4882a593Smuzhiyun 1252*4882a593Smuzhiyun /*****************************************************************************/ 1253*4882a593Smuzhiyun #define PATH1_VOL_CTL 0x8d4 1254*4882a593Smuzhiyun #define FLD_PATH1_AVC_THRESHOLD 0x7fff0000 1255*4882a593Smuzhiyun #define FLD_PATH1_BAL_LEFT 0x00008000 1256*4882a593Smuzhiyun #define FLD_PATH1_BAL_LEVEL 0x00007f00 1257*4882a593Smuzhiyun #define FLD_PATH1_VOLUME 0x000000ff 1258*4882a593Smuzhiyun 1259*4882a593Smuzhiyun /*****************************************************************************/ 1260*4882a593Smuzhiyun #define PATH1_EQ_CTL 0x8d8 1261*4882a593Smuzhiyun /* Reserved [31:30] */ 1262*4882a593Smuzhiyun #define FLD_PATH1_EQ_TREBLE_VOL 0x3f000000 1263*4882a593Smuzhiyun /* Reserved [23:22] */ 1264*4882a593Smuzhiyun #define FLD_PATH1_EQ_MID_VOL 0x003f0000 1265*4882a593Smuzhiyun /* Reserved [15:14] */ 1266*4882a593Smuzhiyun #define FLD_PATH1_EQ_BASS_VOL 0x00003f00 1267*4882a593Smuzhiyun /* Reserved [7:1] */ 1268*4882a593Smuzhiyun #define FLD_PATH1_EQ_BAND_SEL 0x00000001 1269*4882a593Smuzhiyun 1270*4882a593Smuzhiyun /*****************************************************************************/ 1271*4882a593Smuzhiyun #define PATH1_SC_CTL 0x8dc 1272*4882a593Smuzhiyun #define FLD_PATH1_SC_THRESHOLD 0x7fff0000 1273*4882a593Smuzhiyun #define FLD_PATH1_SC_RT 0x0000f000 1274*4882a593Smuzhiyun #define FLD_PATH1_SC_AT 0x00000f00 1275*4882a593Smuzhiyun #define FLD_PATH1_SC_STEREO 0x00000080 1276*4882a593Smuzhiyun #define FLD_PATH1_SC_CR 0x00000070 1277*4882a593Smuzhiyun #define FLD_PATH1_SC_RMS_CON 0x0000000f 1278*4882a593Smuzhiyun 1279*4882a593Smuzhiyun /*****************************************************************************/ 1280*4882a593Smuzhiyun #define PATH2_CTL1 0x8e0 1281*4882a593Smuzhiyun /* Reserved [31:26] */ 1282*4882a593Smuzhiyun #define FLD_PATH2_MUTE_CTL 0x03000000 1283*4882a593Smuzhiyun /* Reserved [23:22] */ 1284*4882a593Smuzhiyun #define FLD_PATH2_AVC_CG 0x00300000 1285*4882a593Smuzhiyun #define FLD_PATH2_AVC_RT 0x000f0000 1286*4882a593Smuzhiyun #define FLD_PATH2_AVC_AT 0x0000f000 1287*4882a593Smuzhiyun #define FLD_PATH2_AVC_STEREO 0x00000800 1288*4882a593Smuzhiyun #define FLD_PATH2_AVC_CR 0x00000700 1289*4882a593Smuzhiyun #define FLD_PATH2_AVC_RMS_CON 0x000000f0 1290*4882a593Smuzhiyun #define FLD_PATH2_SEL_CTL 0x0000000f 1291*4882a593Smuzhiyun 1292*4882a593Smuzhiyun /*****************************************************************************/ 1293*4882a593Smuzhiyun #define PATH2_VOL_CTL 0x8e4 1294*4882a593Smuzhiyun #define FLD_PATH2_AVC_THRESHOLD 0xffff0000 1295*4882a593Smuzhiyun #define FLD_PATH2_BAL_LEFT 0x00008000 1296*4882a593Smuzhiyun #define FLD_PATH2_BAL_LEVEL 0x00007f00 1297*4882a593Smuzhiyun #define FLD_PATH2_VOLUME 0x000000ff 1298*4882a593Smuzhiyun 1299*4882a593Smuzhiyun /*****************************************************************************/ 1300*4882a593Smuzhiyun #define PATH2_EQ_CTL 0x8e8 1301*4882a593Smuzhiyun /* Reserved [31:30] */ 1302*4882a593Smuzhiyun #define FLD_PATH2_EQ_TREBLE_VOL 0x3f000000 1303*4882a593Smuzhiyun /* Reserved [23:22] */ 1304*4882a593Smuzhiyun #define FLD_PATH2_EQ_MID_VOL 0x003f0000 1305*4882a593Smuzhiyun /* Reserved [15:14] */ 1306*4882a593Smuzhiyun #define FLD_PATH2_EQ_BASS_VOL 0x00003f00 1307*4882a593Smuzhiyun /* Reserved [7:1] */ 1308*4882a593Smuzhiyun #define FLD_PATH2_EQ_BAND_SEL 0x00000001 1309*4882a593Smuzhiyun 1310*4882a593Smuzhiyun /*****************************************************************************/ 1311*4882a593Smuzhiyun #define PATH2_SC_CTL 0x8eC 1312*4882a593Smuzhiyun #define FLD_PATH2_SC_THRESHOLD 0xffff0000 1313*4882a593Smuzhiyun #define FLD_PATH2_SC_RT 0x0000f000 1314*4882a593Smuzhiyun #define FLD_PATH2_SC_AT 0x00000f00 1315*4882a593Smuzhiyun #define FLD_PATH2_SC_STEREO 0x00000080 1316*4882a593Smuzhiyun #define FLD_PATH2_SC_CR 0x00000070 1317*4882a593Smuzhiyun #define FLD_PATH2_SC_RMS_CON 0x0000000f 1318*4882a593Smuzhiyun 1319*4882a593Smuzhiyun /*****************************************************************************/ 1320*4882a593Smuzhiyun #define SRC_CTL 0x8f0 1321*4882a593Smuzhiyun #define FLD_SRC_STATUS 0xffffff00 1322*4882a593Smuzhiyun #define FLD_FIFO_LF_EN 0x000000fc 1323*4882a593Smuzhiyun #define FLD_BYPASS_LI 0x00000002 1324*4882a593Smuzhiyun #define FLD_BYPASS_PF 0x00000001 1325*4882a593Smuzhiyun 1326*4882a593Smuzhiyun /*****************************************************************************/ 1327*4882a593Smuzhiyun #define SRC_LF_COEF 0x8f4 1328*4882a593Smuzhiyun #define FLD_LOOP_FILTER_COEF2 0xffff0000 1329*4882a593Smuzhiyun #define FLD_LOOP_FILTER_COEF1 0x0000ffff 1330*4882a593Smuzhiyun 1331*4882a593Smuzhiyun /*****************************************************************************/ 1332*4882a593Smuzhiyun #define SRC1_CTL 0x8f8 1333*4882a593Smuzhiyun /* Reserved [31:28] */ 1334*4882a593Smuzhiyun #define FLD_SRC1_FIFO_RD_TH 0x0f000000 1335*4882a593Smuzhiyun /* Reserved [23:18] */ 1336*4882a593Smuzhiyun #define FLD_SRC1_PHASE_INC 0x0003ffff 1337*4882a593Smuzhiyun 1338*4882a593Smuzhiyun /*****************************************************************************/ 1339*4882a593Smuzhiyun #define SRC2_CTL 0x8fc 1340*4882a593Smuzhiyun /* Reserved [31:28] */ 1341*4882a593Smuzhiyun #define FLD_SRC2_FIFO_RD_TH 0x0f000000 1342*4882a593Smuzhiyun /* Reserved [23:18] */ 1343*4882a593Smuzhiyun #define FLD_SRC2_PHASE_INC 0x0003ffff 1344*4882a593Smuzhiyun 1345*4882a593Smuzhiyun /*****************************************************************************/ 1346*4882a593Smuzhiyun #define SRC3_CTL 0x900 1347*4882a593Smuzhiyun /* Reserved [31:28] */ 1348*4882a593Smuzhiyun #define FLD_SRC3_FIFO_RD_TH 0x0f000000 1349*4882a593Smuzhiyun /* Reserved [23:18] */ 1350*4882a593Smuzhiyun #define FLD_SRC3_PHASE_INC 0x0003ffff 1351*4882a593Smuzhiyun 1352*4882a593Smuzhiyun /*****************************************************************************/ 1353*4882a593Smuzhiyun #define SRC4_CTL 0x904 1354*4882a593Smuzhiyun /* Reserved [31:28] */ 1355*4882a593Smuzhiyun #define FLD_SRC4_FIFO_RD_TH 0x0f000000 1356*4882a593Smuzhiyun /* Reserved [23:18] */ 1357*4882a593Smuzhiyun #define FLD_SRC4_PHASE_INC 0x0003ffff 1358*4882a593Smuzhiyun 1359*4882a593Smuzhiyun /*****************************************************************************/ 1360*4882a593Smuzhiyun #define SRC5_CTL 0x908 1361*4882a593Smuzhiyun /* Reserved [31:28] */ 1362*4882a593Smuzhiyun #define FLD_SRC5_FIFO_RD_TH 0x0f000000 1363*4882a593Smuzhiyun /* Reserved [23:18] */ 1364*4882a593Smuzhiyun #define FLD_SRC5_PHASE_INC 0x0003ffff 1365*4882a593Smuzhiyun 1366*4882a593Smuzhiyun /*****************************************************************************/ 1367*4882a593Smuzhiyun #define SRC6_CTL 0x90c 1368*4882a593Smuzhiyun /* Reserved [31:28] */ 1369*4882a593Smuzhiyun #define FLD_SRC6_FIFO_RD_TH 0x0f000000 1370*4882a593Smuzhiyun /* Reserved [23:18] */ 1371*4882a593Smuzhiyun #define FLD_SRC6_PHASE_INC 0x0003ffff 1372*4882a593Smuzhiyun 1373*4882a593Smuzhiyun /*****************************************************************************/ 1374*4882a593Smuzhiyun #define BAND_OUT_SEL 0x910 1375*4882a593Smuzhiyun #define FLD_SRC6_IN_SEL 0xc0000000 1376*4882a593Smuzhiyun #define FLD_SRC6_CLK_SEL 0x30000000 1377*4882a593Smuzhiyun #define FLD_SRC5_IN_SEL 0x0c000000 1378*4882a593Smuzhiyun #define FLD_SRC5_CLK_SEL 0x03000000 1379*4882a593Smuzhiyun #define FLD_SRC4_IN_SEL 0x00c00000 1380*4882a593Smuzhiyun #define FLD_SRC4_CLK_SEL 0x00300000 1381*4882a593Smuzhiyun #define FLD_SRC3_IN_SEL 0x000c0000 1382*4882a593Smuzhiyun #define FLD_SRC3_CLK_SEL 0x00030000 1383*4882a593Smuzhiyun #define FLD_BASEBAND_BYPASS_CTL 0x0000ff00 1384*4882a593Smuzhiyun #define FLD_AC97_SRC_SEL 0x000000c0 1385*4882a593Smuzhiyun #define FLD_I2S_SRC_SEL 0x00000030 1386*4882a593Smuzhiyun #define FLD_PARALLEL2_SRC_SEL 0x0000000c 1387*4882a593Smuzhiyun #define FLD_PARALLEL1_SRC_SEL 0x00000003 1388*4882a593Smuzhiyun 1389*4882a593Smuzhiyun /*****************************************************************************/ 1390*4882a593Smuzhiyun #define I2S_IN_CTL 0x914 1391*4882a593Smuzhiyun /* Reserved [31:11] */ 1392*4882a593Smuzhiyun #define FLD_I2S_UP2X_BW20K 0x00000400 1393*4882a593Smuzhiyun #define FLD_I2S_UP2X_BYPASS 0x00000200 1394*4882a593Smuzhiyun #define FLD_I2S_IN_MASTER_MODE 0x00000100 1395*4882a593Smuzhiyun #define FLD_I2S_IN_SONY_MODE 0x00000080 1396*4882a593Smuzhiyun #define FLD_I2S_IN_RIGHT_JUST 0x00000040 1397*4882a593Smuzhiyun #define FLD_I2S_IN_WS_SEL 0x00000020 1398*4882a593Smuzhiyun #define FLD_I2S_IN_BCN_DEL 0x0000001f 1399*4882a593Smuzhiyun 1400*4882a593Smuzhiyun /*****************************************************************************/ 1401*4882a593Smuzhiyun #define I2S_OUT_CTL 0x918 1402*4882a593Smuzhiyun /* Reserved [31:17] */ 1403*4882a593Smuzhiyun #define FLD_I2S_OUT_SOFT_RESET_EN 0x00010000 1404*4882a593Smuzhiyun /* Reserved [15:9] */ 1405*4882a593Smuzhiyun #define FLD_I2S_OUT_MASTER_MODE 0x00000100 1406*4882a593Smuzhiyun #define FLD_I2S_OUT_SONY_MODE 0x00000080 1407*4882a593Smuzhiyun #define FLD_I2S_OUT_RIGHT_JUST 0x00000040 1408*4882a593Smuzhiyun #define FLD_I2S_OUT_WS_SEL 0x00000020 1409*4882a593Smuzhiyun #define FLD_I2S_OUT_BCN_DEL 0x0000001f 1410*4882a593Smuzhiyun 1411*4882a593Smuzhiyun /*****************************************************************************/ 1412*4882a593Smuzhiyun #define AC97_CTL 0x91c 1413*4882a593Smuzhiyun /* Reserved [31:26] */ 1414*4882a593Smuzhiyun #define FLD_AC97_UP2X_BW20K 0x02000000 1415*4882a593Smuzhiyun #define FLD_AC97_UP2X_BYPASS 0x01000000 1416*4882a593Smuzhiyun /* Reserved [23:17] */ 1417*4882a593Smuzhiyun #define FLD_AC97_RST_ACL 0x00010000 1418*4882a593Smuzhiyun /* Reserved [15:9] */ 1419*4882a593Smuzhiyun #define FLD_AC97_WAKE_UP_SYNC 0x00000100 1420*4882a593Smuzhiyun /* Reserved [7:1] */ 1421*4882a593Smuzhiyun #define FLD_AC97_SHUTDOWN 0x00000001 1422*4882a593Smuzhiyun 1423*4882a593Smuzhiyun /* Cx231xx redefine */ 1424*4882a593Smuzhiyun #define QPSK_IAGC_CTL1 0x94c 1425*4882a593Smuzhiyun #define QPSK_IAGC_CTL2 0x950 1426*4882a593Smuzhiyun #define QPSK_FEPR_FREQ 0x954 1427*4882a593Smuzhiyun #define QPSK_BTL_CTL1 0x958 1428*4882a593Smuzhiyun #define QPSK_BTL_CTL2 0x95c 1429*4882a593Smuzhiyun #define QPSK_CTL_CTL1 0x960 1430*4882a593Smuzhiyun #define QPSK_CTL_CTL2 0x964 1431*4882a593Smuzhiyun #define QPSK_MF_FAGC_CTL 0x968 1432*4882a593Smuzhiyun #define QPSK_EQ_CTL 0x96c 1433*4882a593Smuzhiyun #define QPSK_LOCK_CTL 0x970 1434*4882a593Smuzhiyun 1435*4882a593Smuzhiyun /*****************************************************************************/ 1436*4882a593Smuzhiyun #define FM1_DFT_CTL 0x9a8 1437*4882a593Smuzhiyun #define FLD_FM1_DFT_THRESHOLD 0xffff0000 1438*4882a593Smuzhiyun /* Reserved [15:8] */ 1439*4882a593Smuzhiyun #define FLD_FM1_DFT_CMP_CTL 0x00000080 1440*4882a593Smuzhiyun #define FLD_FM1_DFT_AVG 0x00000070 1441*4882a593Smuzhiyun /* Reserved [3:1] */ 1442*4882a593Smuzhiyun #define FLD_FM1_DFT_START 0x00000001 1443*4882a593Smuzhiyun 1444*4882a593Smuzhiyun /*****************************************************************************/ 1445*4882a593Smuzhiyun #define FM1_DFT_STATUS 0x9ac 1446*4882a593Smuzhiyun #define FLD_FM1_DFT_DONE 0x80000000 1447*4882a593Smuzhiyun /* Reserved [30:19] */ 1448*4882a593Smuzhiyun #define FLD_FM_DFT_TH_CMP 0x00040000 1449*4882a593Smuzhiyun #define FLD_FM1_DFT 0x0003ffff 1450*4882a593Smuzhiyun 1451*4882a593Smuzhiyun /*****************************************************************************/ 1452*4882a593Smuzhiyun #define FM2_DFT_CTL 0x9b0 1453*4882a593Smuzhiyun #define FLD_FM2_DFT_THRESHOLD 0xffff0000 1454*4882a593Smuzhiyun /* Reserved [15:8] */ 1455*4882a593Smuzhiyun #define FLD_FM2_DFT_CMP_CTL 0x00000080 1456*4882a593Smuzhiyun #define FLD_FM2_DFT_AVG 0x00000070 1457*4882a593Smuzhiyun /* Reserved [3:1] */ 1458*4882a593Smuzhiyun #define FLD_FM2_DFT_START 0x00000001 1459*4882a593Smuzhiyun 1460*4882a593Smuzhiyun /*****************************************************************************/ 1461*4882a593Smuzhiyun #define FM2_DFT_STATUS 0x9b4 1462*4882a593Smuzhiyun #define FLD_FM2_DFT_DONE 0x80000000 1463*4882a593Smuzhiyun /* Reserved [30:19] */ 1464*4882a593Smuzhiyun #define FLD_FM2_DFT_TH_CMP_STAT 0x00040000 1465*4882a593Smuzhiyun #define FLD_FM2_DFT 0x0003ffff 1466*4882a593Smuzhiyun 1467*4882a593Smuzhiyun /*****************************************************************************/ 1468*4882a593Smuzhiyun /* Cx231xx redefine */ 1469*4882a593Smuzhiyun #define AAGC_STATUS_REG 0x9b8 1470*4882a593Smuzhiyun #define AAGC_STATUS 0x9b8 1471*4882a593Smuzhiyun /* Reserved [31:27] */ 1472*4882a593Smuzhiyun #define FLD_FM2_DAGC_OUT 0x07000000 1473*4882a593Smuzhiyun /* Reserved [23:19] */ 1474*4882a593Smuzhiyun #define FLD_FM1_DAGC_OUT 0x00070000 1475*4882a593Smuzhiyun /* Reserved [15:6] */ 1476*4882a593Smuzhiyun #define FLD_AFE_VGA_OUT 0x0000003f 1477*4882a593Smuzhiyun 1478*4882a593Smuzhiyun /*****************************************************************************/ 1479*4882a593Smuzhiyun #define MTS_GAIN_STATUS 0x9bc 1480*4882a593Smuzhiyun /* Reserved [31:14] */ 1481*4882a593Smuzhiyun #define FLD_MTS_GAIN 0x00003fff 1482*4882a593Smuzhiyun 1483*4882a593Smuzhiyun #define RDS_OUT 0x9c0 1484*4882a593Smuzhiyun #define FLD_RDS_Q 0xffff0000 1485*4882a593Smuzhiyun #define FLD_RDS_I 0x0000ffff 1486*4882a593Smuzhiyun 1487*4882a593Smuzhiyun /*****************************************************************************/ 1488*4882a593Smuzhiyun #define AUTOCONFIG_REG 0x9c4 1489*4882a593Smuzhiyun /* Reserved [31:4] */ 1490*4882a593Smuzhiyun #define FLD_AUTOCONFIG_MODE 0x0000000f 1491*4882a593Smuzhiyun 1492*4882a593Smuzhiyun #define FM_AFC 0x9c8 1493*4882a593Smuzhiyun #define FLD_FM2_AFC 0xffff0000 1494*4882a593Smuzhiyun #define FLD_FM1_AFC 0x0000ffff 1495*4882a593Smuzhiyun 1496*4882a593Smuzhiyun /*****************************************************************************/ 1497*4882a593Smuzhiyun /* Cx231xx redefine */ 1498*4882a593Smuzhiyun #define NEW_SPARE 0x9cc 1499*4882a593Smuzhiyun #define NEW_SPARE_REG 0x9cc 1500*4882a593Smuzhiyun 1501*4882a593Smuzhiyun /*****************************************************************************/ 1502*4882a593Smuzhiyun #define DBX_ADJ 0x9d0 1503*4882a593Smuzhiyun /* Reserved [31:28] */ 1504*4882a593Smuzhiyun #define FLD_DBX2_ADJ 0x0fff0000 1505*4882a593Smuzhiyun /* Reserved [15:12] */ 1506*4882a593Smuzhiyun #define FLD_DBX1_ADJ 0x00000fff 1507*4882a593Smuzhiyun 1508*4882a593Smuzhiyun #define VID_FMT_AUTO 0 1509*4882a593Smuzhiyun #define VID_FMT_NTSC_M 1 1510*4882a593Smuzhiyun #define VID_FMT_NTSC_J 2 1511*4882a593Smuzhiyun #define VID_FMT_NTSC_443 3 1512*4882a593Smuzhiyun #define VID_FMT_PAL_BDGHI 4 1513*4882a593Smuzhiyun #define VID_FMT_PAL_M 5 1514*4882a593Smuzhiyun #define VID_FMT_PAL_N 6 1515*4882a593Smuzhiyun #define VID_FMT_PAL_NC 7 1516*4882a593Smuzhiyun #define VID_FMT_PAL_60 8 1517*4882a593Smuzhiyun #define VID_FMT_SECAM 12 1518*4882a593Smuzhiyun #define VID_FMT_SECAM_60 13 1519*4882a593Smuzhiyun 1520*4882a593Smuzhiyun #define INPUT_MODE_CVBS_0 0 /* INPUT_MODE_VALUE(0) */ 1521*4882a593Smuzhiyun #define INPUT_MODE_YC_1 1 /* INPUT_MODE_VALUE(1) */ 1522*4882a593Smuzhiyun #define INPUT_MODE_YC2_2 2 /* INPUT_MODE_VALUE(2) */ 1523*4882a593Smuzhiyun #define INPUT_MODE_YUV_3 3 /* INPUT_MODE_VALUE(3) */ 1524*4882a593Smuzhiyun 1525*4882a593Smuzhiyun #define LUMA_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */ 1526*4882a593Smuzhiyun #define LUMA_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */ 1527*4882a593Smuzhiyun #define LUMA_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */ 1528*4882a593Smuzhiyun 1529*4882a593Smuzhiyun #define UV_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */ 1530*4882a593Smuzhiyun #define UV_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */ 1531*4882a593Smuzhiyun #define UV_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */ 1532*4882a593Smuzhiyun 1533*4882a593Smuzhiyun #define TWO_TAP_FILT 0 1534*4882a593Smuzhiyun #define THREE_TAP_FILT 1 1535*4882a593Smuzhiyun #define FOUR_TAP_FILT 2 1536*4882a593Smuzhiyun #define FIVE_TAP_FILT 3 1537*4882a593Smuzhiyun 1538*4882a593Smuzhiyun #define AUD_CHAN_SRC_PARALLEL 0 1539*4882a593Smuzhiyun #define AUD_CHAN_SRC_I2S_INPUT 1 1540*4882a593Smuzhiyun #define AUD_CHAN_SRC_FLATIRON 2 1541*4882a593Smuzhiyun #define AUD_CHAN_SRC_PARALLEL3 3 1542*4882a593Smuzhiyun 1543*4882a593Smuzhiyun #define OUT_MODE_601 0 1544*4882a593Smuzhiyun #define OUT_MODE_656 1 1545*4882a593Smuzhiyun #define OUT_MODE_VIP11 2 1546*4882a593Smuzhiyun #define OUT_MODE_VIP20 3 1547*4882a593Smuzhiyun 1548*4882a593Smuzhiyun #define PHASE_INC_49MHZ 0x0df22 1549*4882a593Smuzhiyun #define PHASE_INC_56MHZ 0x0fa5b 1550*4882a593Smuzhiyun #define PHASE_INC_28MHZ 0x010000 1551*4882a593Smuzhiyun 1552*4882a593Smuzhiyun #endif 1553