1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun cx231xx_conf-reg.h - driver for Conexant Cx23100/101/102 USB 4*4882a593Smuzhiyun video capture devices 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun Copyright (C) 2008 <srinivasa.deevi at conexant dot com> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _POLARIS_REG_H_ 11*4882a593Smuzhiyun #define _POLARIS_REG_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define BOARD_CFG_STAT 0x0 14*4882a593Smuzhiyun #define TS_MODE_REG 0x4 15*4882a593Smuzhiyun #define TS1_CFG_REG 0x8 16*4882a593Smuzhiyun #define TS1_LENGTH_REG 0xc 17*4882a593Smuzhiyun #define TS2_CFG_REG 0x10 18*4882a593Smuzhiyun #define TS2_LENGTH_REG 0x14 19*4882a593Smuzhiyun #define EP_MODE_SET 0x18 20*4882a593Smuzhiyun #define CIR_PWR_PTN1 0x1c 21*4882a593Smuzhiyun #define CIR_PWR_PTN2 0x20 22*4882a593Smuzhiyun #define CIR_PWR_PTN3 0x24 23*4882a593Smuzhiyun #define CIR_PWR_MASK0 0x28 24*4882a593Smuzhiyun #define CIR_PWR_MASK1 0x2c 25*4882a593Smuzhiyun #define CIR_PWR_MASK2 0x30 26*4882a593Smuzhiyun #define CIR_GAIN 0x34 27*4882a593Smuzhiyun #define CIR_CAR_REG 0x38 28*4882a593Smuzhiyun #define CIR_OT_CFG1 0x40 29*4882a593Smuzhiyun #define CIR_OT_CFG2 0x44 30*4882a593Smuzhiyun #define GBULK_BIT_EN 0x68 31*4882a593Smuzhiyun #define PWR_CTL_EN 0x74 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Polaris Endpoints capture mask for register EP_MODE_SET */ 34*4882a593Smuzhiyun #define ENABLE_EP1 0x01 /* Bit[0]=1 */ 35*4882a593Smuzhiyun #define ENABLE_EP2 0x02 /* Bit[1]=1 */ 36*4882a593Smuzhiyun #define ENABLE_EP3 0x04 /* Bit[2]=1 */ 37*4882a593Smuzhiyun #define ENABLE_EP4 0x08 /* Bit[3]=1 */ 38*4882a593Smuzhiyun #define ENABLE_EP5 0x10 /* Bit[4]=1 */ 39*4882a593Smuzhiyun #define ENABLE_EP6 0x20 /* Bit[5]=1 */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Bit definition for register PWR_CTL_EN */ 42*4882a593Smuzhiyun #define PWR_MODE_MASK 0x17f 43*4882a593Smuzhiyun #define PWR_AV_EN 0x08 /* bit3 */ 44*4882a593Smuzhiyun #define PWR_ISO_EN 0x40 /* bit6 */ 45*4882a593Smuzhiyun #define PWR_AV_MODE 0x30 /* bit4,5 */ 46*4882a593Smuzhiyun #define PWR_TUNER_EN 0x04 /* bit2 */ 47*4882a593Smuzhiyun #define PWR_DEMOD_EN 0x02 /* bit1 */ 48*4882a593Smuzhiyun #define I2C_DEMOD_EN 0x01 /* bit0 */ 49*4882a593Smuzhiyun #define PWR_RESETOUT_EN 0x100 /* bit8 */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun enum AV_MODE{ 52*4882a593Smuzhiyun POLARIS_AVMODE_DEFAULT = 0, 53*4882a593Smuzhiyun POLARIS_AVMODE_DIGITAL = 0x10, 54*4882a593Smuzhiyun POLARIS_AVMODE_ANALOGT_TV = 0x20, 55*4882a593Smuzhiyun POLARIS_AVMODE_ENXTERNAL_AV = 0x30, 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Colibri Registers */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define SINGLE_ENDED 0x0 62*4882a593Smuzhiyun #define LOW_IF 0x4 63*4882a593Smuzhiyun #define EU_IF 0x9 64*4882a593Smuzhiyun #define US_IF 0xa 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define SUP_BLK_TUNE1 0x00 67*4882a593Smuzhiyun #define SUP_BLK_TUNE2 0x01 68*4882a593Smuzhiyun #define SUP_BLK_TUNE3 0x02 69*4882a593Smuzhiyun #define SUP_BLK_XTAL 0x03 70*4882a593Smuzhiyun #define SUP_BLK_PLL1 0x04 71*4882a593Smuzhiyun #define SUP_BLK_PLL2 0x05 72*4882a593Smuzhiyun #define SUP_BLK_PLL3 0x06 73*4882a593Smuzhiyun #define SUP_BLK_REF 0x07 74*4882a593Smuzhiyun #define SUP_BLK_PWRDN 0x08 75*4882a593Smuzhiyun #define SUP_BLK_TESTPAD 0x09 76*4882a593Smuzhiyun #define ADC_COM_INT5_STAB_REF 0x0a 77*4882a593Smuzhiyun #define ADC_COM_QUANT 0x0b 78*4882a593Smuzhiyun #define ADC_COM_BIAS1 0x0c 79*4882a593Smuzhiyun #define ADC_COM_BIAS2 0x0d 80*4882a593Smuzhiyun #define ADC_COM_BIAS3 0x0e 81*4882a593Smuzhiyun #define TESTBUS_CTRL 0x12 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define FLD_PWRDN_TUNING_BIAS 0x10 84*4882a593Smuzhiyun #define FLD_PWRDN_ENABLE_PLL 0x08 85*4882a593Smuzhiyun #define FLD_PWRDN_PD_BANDGAP 0x04 86*4882a593Smuzhiyun #define FLD_PWRDN_PD_BIAS 0x02 87*4882a593Smuzhiyun #define FLD_PWRDN_PD_TUNECK 0x01 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define ADC_STATUS_CH1 0x20 91*4882a593Smuzhiyun #define ADC_STATUS_CH2 0x40 92*4882a593Smuzhiyun #define ADC_STATUS_CH3 0x60 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define ADC_STATUS2_CH1 0x21 95*4882a593Smuzhiyun #define ADC_STATUS2_CH2 0x41 96*4882a593Smuzhiyun #define ADC_STATUS2_CH3 0x61 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define ADC_CAL_ATEST_CH1 0x22 99*4882a593Smuzhiyun #define ADC_CAL_ATEST_CH2 0x42 100*4882a593Smuzhiyun #define ADC_CAL_ATEST_CH3 0x62 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define ADC_PWRDN_CLAMP_CH1 0x23 103*4882a593Smuzhiyun #define ADC_PWRDN_CLAMP_CH2 0x43 104*4882a593Smuzhiyun #define ADC_PWRDN_CLAMP_CH3 0x63 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define ADC_CTRL_DAC23_CH1 0x24 107*4882a593Smuzhiyun #define ADC_CTRL_DAC23_CH2 0x44 108*4882a593Smuzhiyun #define ADC_CTRL_DAC23_CH3 0x64 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define ADC_CTRL_DAC1_CH1 0x25 111*4882a593Smuzhiyun #define ADC_CTRL_DAC1_CH2 0x45 112*4882a593Smuzhiyun #define ADC_CTRL_DAC1_CH3 0x65 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define ADC_DCSERVO_DEM_CH1 0x26 115*4882a593Smuzhiyun #define ADC_DCSERVO_DEM_CH2 0x46 116*4882a593Smuzhiyun #define ADC_DCSERVO_DEM_CH3 0x66 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define ADC_FB_FRCRST_CH1 0x27 119*4882a593Smuzhiyun #define ADC_FB_FRCRST_CH2 0x47 120*4882a593Smuzhiyun #define ADC_FB_FRCRST_CH3 0x67 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define ADC_INPUT_CH1 0x28 123*4882a593Smuzhiyun #define ADC_INPUT_CH2 0x48 124*4882a593Smuzhiyun #define ADC_INPUT_CH3 0x68 125*4882a593Smuzhiyun #define INPUT_SEL_MASK 0x30 /* [5:4] in_sel */ 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define ADC_NTF_PRECLMP_EN_CH1 0x29 128*4882a593Smuzhiyun #define ADC_NTF_PRECLMP_EN_CH2 0x49 129*4882a593Smuzhiyun #define ADC_NTF_PRECLMP_EN_CH3 0x69 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define ADC_QGAIN_RES_TRM_CH1 0x2a 132*4882a593Smuzhiyun #define ADC_QGAIN_RES_TRM_CH2 0x4a 133*4882a593Smuzhiyun #define ADC_QGAIN_RES_TRM_CH3 0x6a 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define ADC_SOC_PRECLMP_TERM_CH1 0x2b 136*4882a593Smuzhiyun #define ADC_SOC_PRECLMP_TERM_CH2 0x4b 137*4882a593Smuzhiyun #define ADC_SOC_PRECLMP_TERM_CH3 0x6b 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #define TESTBUS_CTRL_CH1 0x32 140*4882a593Smuzhiyun #define TESTBUS_CTRL_CH2 0x52 141*4882a593Smuzhiyun #define TESTBUS_CTRL_CH3 0x72 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /****************************************************************************** 144*4882a593Smuzhiyun * DIF registers * 145*4882a593Smuzhiyun ******************************************************************************/ 146*4882a593Smuzhiyun #define DIRECT_IF_REVB_BASE 0x00300 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /*****************************************************************************/ 149*4882a593Smuzhiyun #define DIF_PLL_FREQ_WORD (DIRECT_IF_REVB_BASE + 0x00000000) 150*4882a593Smuzhiyun /*****************************************************************************/ 151*4882a593Smuzhiyun #define FLD_DIF_PLL_LOCK 0x80000000 152*4882a593Smuzhiyun /* Reserved [30:29] */ 153*4882a593Smuzhiyun #define FLD_DIF_PLL_FREE_RUN 0x10000000 154*4882a593Smuzhiyun #define FLD_DIF_PLL_FREQ 0x0fffffff 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /*****************************************************************************/ 157*4882a593Smuzhiyun #define DIF_PLL_CTRL (DIRECT_IF_REVB_BASE + 0x00000004) 158*4882a593Smuzhiyun /*****************************************************************************/ 159*4882a593Smuzhiyun #define FLD_DIF_KD_PD 0xff000000 160*4882a593Smuzhiyun /* Reserved [23:20] */ 161*4882a593Smuzhiyun #define FLD_DIF_KDS_PD 0x000f0000 162*4882a593Smuzhiyun #define FLD_DIF_KI_PD 0x0000ff00 163*4882a593Smuzhiyun /* Reserved [7:4] */ 164*4882a593Smuzhiyun #define FLD_DIF_KIS_PD 0x0000000f 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /*****************************************************************************/ 167*4882a593Smuzhiyun #define DIF_PLL_CTRL1 (DIRECT_IF_REVB_BASE + 0x00000008) 168*4882a593Smuzhiyun /*****************************************************************************/ 169*4882a593Smuzhiyun #define FLD_DIF_KD_FD 0xff000000 170*4882a593Smuzhiyun /* Reserved [23:20] */ 171*4882a593Smuzhiyun #define FLD_DIF_KDS_FD 0x000f0000 172*4882a593Smuzhiyun #define FLD_DIF_KI_FD 0x0000ff00 173*4882a593Smuzhiyun #define FLD_DIF_SIG_PROP_SZ 0x000000f0 174*4882a593Smuzhiyun #define FLD_DIF_KIS_FD 0x0000000f 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /*****************************************************************************/ 177*4882a593Smuzhiyun #define DIF_PLL_CTRL2 (DIRECT_IF_REVB_BASE + 0x0000000c) 178*4882a593Smuzhiyun /*****************************************************************************/ 179*4882a593Smuzhiyun #define FLD_DIF_PLL_AGC_REF 0xfff00000 180*4882a593Smuzhiyun #define FLD_DIF_PLL_AGC_KI 0x000f0000 181*4882a593Smuzhiyun /* Reserved [15] */ 182*4882a593Smuzhiyun #define FLD_DIF_FREQ_LIMIT 0x00007000 183*4882a593Smuzhiyun #define FLD_DIF_K_FD 0x00000f00 184*4882a593Smuzhiyun #define FLD_DIF_DOWNSMPL_FD 0x000000ff 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun /*****************************************************************************/ 187*4882a593Smuzhiyun #define DIF_PLL_CTRL3 (DIRECT_IF_REVB_BASE + 0x00000010) 188*4882a593Smuzhiyun /*****************************************************************************/ 189*4882a593Smuzhiyun /* Reserved [31:16] */ 190*4882a593Smuzhiyun #define FLD_DIF_PLL_AGC_EN 0x00008000 191*4882a593Smuzhiyun /* Reserved [14:12] */ 192*4882a593Smuzhiyun #define FLD_DIF_PLL_MAN_GAIN 0x00000fff 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /*****************************************************************************/ 195*4882a593Smuzhiyun #define DIF_AGC_IF_REF (DIRECT_IF_REVB_BASE + 0x00000014) 196*4882a593Smuzhiyun /*****************************************************************************/ 197*4882a593Smuzhiyun #define FLD_DIF_K_AGC_RF 0xf0000000 198*4882a593Smuzhiyun #define FLD_DIF_K_AGC_IF 0x0f000000 199*4882a593Smuzhiyun #define FLD_DIF_K_AGC_INT 0x00f00000 200*4882a593Smuzhiyun /* Reserved [19:12] */ 201*4882a593Smuzhiyun #define FLD_DIF_IF_REF 0x00000fff 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun /*****************************************************************************/ 204*4882a593Smuzhiyun #define DIF_AGC_CTRL_IF (DIRECT_IF_REVB_BASE + 0x00000018) 205*4882a593Smuzhiyun /*****************************************************************************/ 206*4882a593Smuzhiyun #define FLD_DIF_IF_MAX 0xff000000 207*4882a593Smuzhiyun #define FLD_DIF_IF_MIN 0x00ff0000 208*4882a593Smuzhiyun #define FLD_DIF_IF_AGC 0x0000ffff 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun /*****************************************************************************/ 211*4882a593Smuzhiyun #define DIF_AGC_CTRL_INT (DIRECT_IF_REVB_BASE + 0x0000001c) 212*4882a593Smuzhiyun /*****************************************************************************/ 213*4882a593Smuzhiyun #define FLD_DIF_INT_MAX 0xff000000 214*4882a593Smuzhiyun #define FLD_DIF_INT_MIN 0x00ff0000 215*4882a593Smuzhiyun #define FLD_DIF_INT_AGC 0x0000ffff 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun /*****************************************************************************/ 218*4882a593Smuzhiyun #define DIF_AGC_CTRL_RF (DIRECT_IF_REVB_BASE + 0x00000020) 219*4882a593Smuzhiyun /*****************************************************************************/ 220*4882a593Smuzhiyun #define FLD_DIF_RF_MAX 0xff000000 221*4882a593Smuzhiyun #define FLD_DIF_RF_MIN 0x00ff0000 222*4882a593Smuzhiyun #define FLD_DIF_RF_AGC 0x0000ffff 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun /*****************************************************************************/ 225*4882a593Smuzhiyun #define DIF_AGC_IF_INT_CURRENT (DIRECT_IF_REVB_BASE + 0x00000024) 226*4882a593Smuzhiyun /*****************************************************************************/ 227*4882a593Smuzhiyun #define FLD_DIF_IF_AGC_IN 0xffff0000 228*4882a593Smuzhiyun #define FLD_DIF_INT_AGC_IN 0x0000ffff 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun /*****************************************************************************/ 231*4882a593Smuzhiyun #define DIF_AGC_RF_CURRENT (DIRECT_IF_REVB_BASE + 0x00000028) 232*4882a593Smuzhiyun /*****************************************************************************/ 233*4882a593Smuzhiyun /* Reserved [31:16] */ 234*4882a593Smuzhiyun #define FLD_DIF_RF_AGC_IN 0x0000ffff 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun /*****************************************************************************/ 237*4882a593Smuzhiyun #define DIF_VIDEO_AGC_CTRL (DIRECT_IF_REVB_BASE + 0x0000002c) 238*4882a593Smuzhiyun /*****************************************************************************/ 239*4882a593Smuzhiyun #define FLD_DIF_AFD 0xc0000000 240*4882a593Smuzhiyun #define FLD_DIF_K_VID_AGC 0x30000000 241*4882a593Smuzhiyun #define FLD_DIF_LINE_LENGTH 0x0fff0000 242*4882a593Smuzhiyun #define FLD_DIF_AGC_GAIN 0x0000ffff 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun /*****************************************************************************/ 245*4882a593Smuzhiyun #define DIF_VID_AUD_OVERRIDE (DIRECT_IF_REVB_BASE + 0x00000030) 246*4882a593Smuzhiyun /*****************************************************************************/ 247*4882a593Smuzhiyun #define FLD_DIF_AUDIO_AGC_OVERRIDE 0x80000000 248*4882a593Smuzhiyun /* Reserved [30:30] */ 249*4882a593Smuzhiyun #define FLD_DIF_AUDIO_MAN_GAIN 0x3f000000 250*4882a593Smuzhiyun /* Reserved [23:17] */ 251*4882a593Smuzhiyun #define FLD_DIF_VID_AGC_OVERRIDE 0x00010000 252*4882a593Smuzhiyun #define FLD_DIF_VID_MAN_GAIN 0x0000ffff 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun /*****************************************************************************/ 255*4882a593Smuzhiyun #define DIF_AV_SEP_CTRL (DIRECT_IF_REVB_BASE + 0x00000034) 256*4882a593Smuzhiyun /*****************************************************************************/ 257*4882a593Smuzhiyun #define FLD_DIF_LPF_FREQ 0xc0000000 258*4882a593Smuzhiyun #define FLD_DIF_AV_PHASE_INC 0x3f000000 259*4882a593Smuzhiyun #define FLD_DIF_AUDIO_FREQ 0x00ffffff 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun /*****************************************************************************/ 262*4882a593Smuzhiyun #define DIF_COMP_FLT_CTRL (DIRECT_IF_REVB_BASE + 0x00000038) 263*4882a593Smuzhiyun /*****************************************************************************/ 264*4882a593Smuzhiyun /* Reserved [31:24] */ 265*4882a593Smuzhiyun #define FLD_DIF_IIR23_R2 0x00ff0000 266*4882a593Smuzhiyun #define FLD_DIF_IIR23_R1 0x0000ff00 267*4882a593Smuzhiyun #define FLD_DIF_IIR1_R1 0x000000ff 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun /*****************************************************************************/ 270*4882a593Smuzhiyun #define DIF_MISC_CTRL (DIRECT_IF_REVB_BASE + 0x0000003c) 271*4882a593Smuzhiyun /*****************************************************************************/ 272*4882a593Smuzhiyun #define FLD_DIF_DIF_BYPASS 0x80000000 273*4882a593Smuzhiyun #define FLD_DIF_FM_NYQ_GAIN 0x40000000 274*4882a593Smuzhiyun #define FLD_DIF_RF_AGC_ENA 0x20000000 275*4882a593Smuzhiyun #define FLD_DIF_INT_AGC_ENA 0x10000000 276*4882a593Smuzhiyun #define FLD_DIF_IF_AGC_ENA 0x08000000 277*4882a593Smuzhiyun #define FLD_DIF_FORCE_RF_IF_LOCK 0x04000000 278*4882a593Smuzhiyun #define FLD_DIF_VIDEO_AGC_ENA 0x02000000 279*4882a593Smuzhiyun #define FLD_DIF_RF_AGC_INV 0x01000000 280*4882a593Smuzhiyun #define FLD_DIF_INT_AGC_INV 0x00800000 281*4882a593Smuzhiyun #define FLD_DIF_IF_AGC_INV 0x00400000 282*4882a593Smuzhiyun #define FLD_DIF_SPEC_INV 0x00200000 283*4882a593Smuzhiyun #define FLD_DIF_AUD_FULL_BW 0x00100000 284*4882a593Smuzhiyun #define FLD_DIF_AUD_SRC_SEL 0x00080000 285*4882a593Smuzhiyun /* Reserved [18] */ 286*4882a593Smuzhiyun #define FLD_DIF_IF_FREQ 0x00030000 287*4882a593Smuzhiyun /* Reserved [15:14] */ 288*4882a593Smuzhiyun #define FLD_DIF_TIP_OFFSET 0x00003f00 289*4882a593Smuzhiyun /* Reserved [7:5] */ 290*4882a593Smuzhiyun #define FLD_DIF_DITHER_ENA 0x00000010 291*4882a593Smuzhiyun /* Reserved [3:1] */ 292*4882a593Smuzhiyun #define FLD_DIF_RF_IF_LOCK 0x00000001 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun /*****************************************************************************/ 295*4882a593Smuzhiyun #define DIF_SRC_PHASE_INC (DIRECT_IF_REVB_BASE + 0x00000040) 296*4882a593Smuzhiyun /*****************************************************************************/ 297*4882a593Smuzhiyun /* Reserved [31:29] */ 298*4882a593Smuzhiyun #define FLD_DIF_PHASE_INC 0x1fffffff 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun /*****************************************************************************/ 301*4882a593Smuzhiyun #define DIF_SRC_GAIN_CONTROL (DIRECT_IF_REVB_BASE + 0x00000044) 302*4882a593Smuzhiyun /*****************************************************************************/ 303*4882a593Smuzhiyun /* Reserved [31:16] */ 304*4882a593Smuzhiyun #define FLD_DIF_SRC_KI 0x0000ff00 305*4882a593Smuzhiyun #define FLD_DIF_SRC_KD 0x000000ff 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun /*****************************************************************************/ 308*4882a593Smuzhiyun #define DIF_BPF_COEFF01 (DIRECT_IF_REVB_BASE + 0x00000048) 309*4882a593Smuzhiyun /*****************************************************************************/ 310*4882a593Smuzhiyun /* Reserved [31:19] */ 311*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_0 0x00070000 312*4882a593Smuzhiyun /* Reserved [15:4] */ 313*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_1 0x0000000f 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun /*****************************************************************************/ 316*4882a593Smuzhiyun #define DIF_BPF_COEFF23 (DIRECT_IF_REVB_BASE + 0x0000004c) 317*4882a593Smuzhiyun /*****************************************************************************/ 318*4882a593Smuzhiyun /* Reserved [31:22] */ 319*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_2 0x003f0000 320*4882a593Smuzhiyun /* Reserved [15:7] */ 321*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_3 0x0000007f 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun /*****************************************************************************/ 324*4882a593Smuzhiyun #define DIF_BPF_COEFF45 (DIRECT_IF_REVB_BASE + 0x00000050) 325*4882a593Smuzhiyun /*****************************************************************************/ 326*4882a593Smuzhiyun /* Reserved [31:24] */ 327*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_4 0x00ff0000 328*4882a593Smuzhiyun /* Reserved [15:8] */ 329*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_5 0x000000ff 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun /*****************************************************************************/ 332*4882a593Smuzhiyun #define DIF_BPF_COEFF67 (DIRECT_IF_REVB_BASE + 0x00000054) 333*4882a593Smuzhiyun /*****************************************************************************/ 334*4882a593Smuzhiyun /* Reserved [31:25] */ 335*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_6 0x01ff0000 336*4882a593Smuzhiyun /* Reserved [15:9] */ 337*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_7 0x000001ff 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun /*****************************************************************************/ 340*4882a593Smuzhiyun #define DIF_BPF_COEFF89 (DIRECT_IF_REVB_BASE + 0x00000058) 341*4882a593Smuzhiyun /*****************************************************************************/ 342*4882a593Smuzhiyun /* Reserved [31:26] */ 343*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_8 0x03ff0000 344*4882a593Smuzhiyun /* Reserved [15:10] */ 345*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_9 0x000003ff 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun /*****************************************************************************/ 348*4882a593Smuzhiyun #define DIF_BPF_COEFF1011 (DIRECT_IF_REVB_BASE + 0x0000005c) 349*4882a593Smuzhiyun /*****************************************************************************/ 350*4882a593Smuzhiyun /* Reserved [31:27] */ 351*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_10 0x07ff0000 352*4882a593Smuzhiyun /* Reserved [15:11] */ 353*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_11 0x000007ff 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun /*****************************************************************************/ 356*4882a593Smuzhiyun #define DIF_BPF_COEFF1213 (DIRECT_IF_REVB_BASE + 0x00000060) 357*4882a593Smuzhiyun /*****************************************************************************/ 358*4882a593Smuzhiyun /* Reserved [31:27] */ 359*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_12 0x07ff0000 360*4882a593Smuzhiyun /* Reserved [15:12] */ 361*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_13 0x00000fff 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun /*****************************************************************************/ 364*4882a593Smuzhiyun #define DIF_BPF_COEFF1415 (DIRECT_IF_REVB_BASE + 0x00000064) 365*4882a593Smuzhiyun /*****************************************************************************/ 366*4882a593Smuzhiyun /* Reserved [31:28] */ 367*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_14 0x0fff0000 368*4882a593Smuzhiyun /* Reserved [15:12] */ 369*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_15 0x00000fff 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun /*****************************************************************************/ 372*4882a593Smuzhiyun #define DIF_BPF_COEFF1617 (DIRECT_IF_REVB_BASE + 0x00000068) 373*4882a593Smuzhiyun /*****************************************************************************/ 374*4882a593Smuzhiyun /* Reserved [31:29] */ 375*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_16 0x1fff0000 376*4882a593Smuzhiyun /* Reserved [15:13] */ 377*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_17 0x00001fff 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun /*****************************************************************************/ 380*4882a593Smuzhiyun #define DIF_BPF_COEFF1819 (DIRECT_IF_REVB_BASE + 0x0000006c) 381*4882a593Smuzhiyun /*****************************************************************************/ 382*4882a593Smuzhiyun /* Reserved [31:29] */ 383*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_18 0x1fff0000 384*4882a593Smuzhiyun /* Reserved [15:13] */ 385*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_19 0x00001fff 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun /*****************************************************************************/ 388*4882a593Smuzhiyun #define DIF_BPF_COEFF2021 (DIRECT_IF_REVB_BASE + 0x00000070) 389*4882a593Smuzhiyun /*****************************************************************************/ 390*4882a593Smuzhiyun /* Reserved [31:29] */ 391*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_20 0x1fff0000 392*4882a593Smuzhiyun /* Reserved [15:14] */ 393*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_21 0x00003fff 394*4882a593Smuzhiyun 395*4882a593Smuzhiyun /*****************************************************************************/ 396*4882a593Smuzhiyun #define DIF_BPF_COEFF2223 (DIRECT_IF_REVB_BASE + 0x00000074) 397*4882a593Smuzhiyun /*****************************************************************************/ 398*4882a593Smuzhiyun /* Reserved [31:30] */ 399*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_22 0x3fff0000 400*4882a593Smuzhiyun /* Reserved [15:14] */ 401*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_23 0x00003fff 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun /*****************************************************************************/ 404*4882a593Smuzhiyun #define DIF_BPF_COEFF2425 (DIRECT_IF_REVB_BASE + 0x00000078) 405*4882a593Smuzhiyun /*****************************************************************************/ 406*4882a593Smuzhiyun /* Reserved [31:30] */ 407*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_24 0x3fff0000 408*4882a593Smuzhiyun /* Reserved [15:14] */ 409*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_25 0x00003fff 410*4882a593Smuzhiyun 411*4882a593Smuzhiyun /*****************************************************************************/ 412*4882a593Smuzhiyun #define DIF_BPF_COEFF2627 (DIRECT_IF_REVB_BASE + 0x0000007c) 413*4882a593Smuzhiyun /*****************************************************************************/ 414*4882a593Smuzhiyun /* Reserved [31:30] */ 415*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_26 0x3fff0000 416*4882a593Smuzhiyun /* Reserved [15:14] */ 417*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_27 0x00003fff 418*4882a593Smuzhiyun 419*4882a593Smuzhiyun /*****************************************************************************/ 420*4882a593Smuzhiyun #define DIF_BPF_COEFF2829 (DIRECT_IF_REVB_BASE + 0x00000080) 421*4882a593Smuzhiyun /*****************************************************************************/ 422*4882a593Smuzhiyun /* Reserved [31:30] */ 423*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_28 0x3fff0000 424*4882a593Smuzhiyun /* Reserved [15:14] */ 425*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_29 0x00003fff 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun /*****************************************************************************/ 428*4882a593Smuzhiyun #define DIF_BPF_COEFF3031 (DIRECT_IF_REVB_BASE + 0x00000084) 429*4882a593Smuzhiyun /*****************************************************************************/ 430*4882a593Smuzhiyun /* Reserved [31:30] */ 431*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_30 0x3fff0000 432*4882a593Smuzhiyun /* Reserved [15:14] */ 433*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_31 0x00003fff 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun /*****************************************************************************/ 436*4882a593Smuzhiyun #define DIF_BPF_COEFF3233 (DIRECT_IF_REVB_BASE + 0x00000088) 437*4882a593Smuzhiyun /*****************************************************************************/ 438*4882a593Smuzhiyun /* Reserved [31:30] */ 439*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_32 0x3fff0000 440*4882a593Smuzhiyun /* Reserved [15:14] */ 441*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_33 0x00003fff 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun /*****************************************************************************/ 444*4882a593Smuzhiyun #define DIF_BPF_COEFF3435 (DIRECT_IF_REVB_BASE + 0x0000008c) 445*4882a593Smuzhiyun /*****************************************************************************/ 446*4882a593Smuzhiyun /* Reserved [31:30] */ 447*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_34 0x3fff0000 448*4882a593Smuzhiyun /* Reserved [15:14] */ 449*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_35 0x00003fff 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun /*****************************************************************************/ 452*4882a593Smuzhiyun #define DIF_BPF_COEFF36 (DIRECT_IF_REVB_BASE + 0x00000090) 453*4882a593Smuzhiyun /*****************************************************************************/ 454*4882a593Smuzhiyun /* Reserved [31:30] */ 455*4882a593Smuzhiyun #define FLD_DIF_BPF_COEFF_36 0x3fff0000 456*4882a593Smuzhiyun /* Reserved [15:0] */ 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun /*****************************************************************************/ 459*4882a593Smuzhiyun #define DIF_RPT_VARIANCE (DIRECT_IF_REVB_BASE + 0x00000094) 460*4882a593Smuzhiyun /*****************************************************************************/ 461*4882a593Smuzhiyun /* Reserved [31:20] */ 462*4882a593Smuzhiyun #define FLD_DIF_RPT_VARIANCE 0x000fffff 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun /*****************************************************************************/ 465*4882a593Smuzhiyun #define DIF_SOFT_RST_CTRL_REVB (DIRECT_IF_REVB_BASE + 0x00000098) 466*4882a593Smuzhiyun /*****************************************************************************/ 467*4882a593Smuzhiyun /* Reserved [31:8] */ 468*4882a593Smuzhiyun #define FLD_DIF_DIF_SOFT_RST 0x00000080 469*4882a593Smuzhiyun #define FLD_DIF_DIF_REG_RST_MSK 0x00000040 470*4882a593Smuzhiyun #define FLD_DIF_AGC_RST_MSK 0x00000020 471*4882a593Smuzhiyun #define FLD_DIF_CMP_RST_MSK 0x00000010 472*4882a593Smuzhiyun #define FLD_DIF_AVS_RST_MSK 0x00000008 473*4882a593Smuzhiyun #define FLD_DIF_NYQ_RST_MSK 0x00000004 474*4882a593Smuzhiyun #define FLD_DIF_DIF_SRC_RST_MSK 0x00000002 475*4882a593Smuzhiyun #define FLD_DIF_PLL_RST_MSK 0x00000001 476*4882a593Smuzhiyun 477*4882a593Smuzhiyun /*****************************************************************************/ 478*4882a593Smuzhiyun #define DIF_PLL_FREQ_ERR (DIRECT_IF_REVB_BASE + 0x0000009c) 479*4882a593Smuzhiyun /*****************************************************************************/ 480*4882a593Smuzhiyun /* Reserved [31:25] */ 481*4882a593Smuzhiyun #define FLD_DIF_CTL_IP 0x01ffffff 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun #endif 484