1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /**************************************************************************** 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Filename: cpia2registers.h 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright 2001, STMicrolectronics, Inc. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Description: 9*4882a593Smuzhiyun * Definitions for the CPia2 register set 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun ****************************************************************************/ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef CPIA2_REGISTER_HEADER 14*4882a593Smuzhiyun #define CPIA2_REGISTER_HEADER 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /*** 17*4882a593Smuzhiyun * System register set (Bank 0) 18*4882a593Smuzhiyun ***/ 19*4882a593Smuzhiyun #define CPIA2_SYSTEM_DEVICE_HI 0x00 20*4882a593Smuzhiyun #define CPIA2_SYSTEM_DEVICE_LO 0x01 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define CPIA2_SYSTEM_SYSTEM_CONTROL 0x02 23*4882a593Smuzhiyun #define CPIA2_SYSTEM_CONTROL_LOW_POWER 0x00 24*4882a593Smuzhiyun #define CPIA2_SYSTEM_CONTROL_HIGH_POWER 0x01 25*4882a593Smuzhiyun #define CPIA2_SYSTEM_CONTROL_SUSPEND 0x02 26*4882a593Smuzhiyun #define CPIA2_SYSTEM_CONTROL_V2W_ERR 0x10 27*4882a593Smuzhiyun #define CPIA2_SYSTEM_CONTROL_RB_ERR 0x10 28*4882a593Smuzhiyun #define CPIA2_SYSTEM_CONTROL_CLEAR_ERR 0x80 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define CPIA2_SYSTEM_INT_PACKET_CTRL 0x04 31*4882a593Smuzhiyun #define CPIA2_SYSTEM_INT_PACKET_CTRL_ENABLE_SW_XX 0x01 32*4882a593Smuzhiyun #define CPIA2_SYSTEM_INT_PACKET_CTRL_ENABLE_EOF 0x02 33*4882a593Smuzhiyun #define CPIA2_SYSTEM_INT_PACKET_CTRL_ENABLE_INT1 0x04 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define CPIA2_SYSTEM_CACHE_CTRL 0x05 36*4882a593Smuzhiyun #define CPIA2_SYSTEM_CACHE_CTRL_CACHE_RESET 0x01 37*4882a593Smuzhiyun #define CPIA2_SYSTEM_CACHE_CTRL_CACHE_FLUSH 0x02 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define CPIA2_SYSTEM_SERIAL_CTRL 0x06 40*4882a593Smuzhiyun #define CPIA2_SYSTEM_SERIAL_CTRL_NULL_CMD 0x00 41*4882a593Smuzhiyun #define CPIA2_SYSTEM_SERIAL_CTRL_START_CMD 0x01 42*4882a593Smuzhiyun #define CPIA2_SYSTEM_SERIAL_CTRL_STOP_CMD 0x02 43*4882a593Smuzhiyun #define CPIA2_SYSTEM_SERIAL_CTRL_WRITE_CMD 0x03 44*4882a593Smuzhiyun #define CPIA2_SYSTEM_SERIAL_CTRL_READ_ACK_CMD 0x04 45*4882a593Smuzhiyun #define CPIA2_SYSTEM_SERIAL_CTRL_READ_NACK_CMD 0x05 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define CPIA2_SYSTEM_SERIAL_DATA 0x07 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define CPIA2_SYSTEM_VP_SERIAL_ADDR 0x08 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /*** 52*4882a593Smuzhiyun * I2C addresses for various devices in CPiA2 53*4882a593Smuzhiyun ***/ 54*4882a593Smuzhiyun #define CPIA2_SYSTEM_VP_SERIAL_ADDR_SENSOR 0x20 55*4882a593Smuzhiyun #define CPIA2_SYSTEM_VP_SERIAL_ADDR_VP 0x88 56*4882a593Smuzhiyun #define CPIA2_SYSTEM_VP_SERIAL_ADDR_676_VP 0x8A 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define CPIA2_SYSTEM_SPARE_REG1 0x09 59*4882a593Smuzhiyun #define CPIA2_SYSTEM_SPARE_REG2 0x0A 60*4882a593Smuzhiyun #define CPIA2_SYSTEM_SPARE_REG3 0x0B 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define CPIA2_SYSTEM_MC_PORT_0 0x0C 63*4882a593Smuzhiyun #define CPIA2_SYSTEM_MC_PORT_1 0x0D 64*4882a593Smuzhiyun #define CPIA2_SYSTEM_MC_PORT_2 0x0E 65*4882a593Smuzhiyun #define CPIA2_SYSTEM_MC_PORT_3 0x0F 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define CPIA2_SYSTEM_STATUS_PKT 0x20 68*4882a593Smuzhiyun #define CPIA2_SYSTEM_STATUS_PKT_END 0x27 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define CPIA2_SYSTEM_DESCRIP_VID_HI 0x30 71*4882a593Smuzhiyun #define CPIA2_SYSTEM_DESCRIP_VID_LO 0x31 72*4882a593Smuzhiyun #define CPIA2_SYSTEM_DESCRIP_PID_HI 0x32 73*4882a593Smuzhiyun #define CPIA2_SYSTEM_DESCRIP_PID_LO 0x33 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define CPIA2_SYSTEM_FW_VERSION_HI 0x34 76*4882a593Smuzhiyun #define CPIA2_SYSTEM_FW_VERSION_LO 0x35 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define CPIA2_SYSTEM_CACHE_START_INDEX 0x80 79*4882a593Smuzhiyun #define CPIA2_SYSTEM_CACHE_MAX_WRITES 0x10 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /*** 82*4882a593Smuzhiyun * VC register set (Bank 1) 83*4882a593Smuzhiyun ***/ 84*4882a593Smuzhiyun #define CPIA2_VC_ASIC_ID 0x80 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define CPIA2_VC_ASIC_REV 0x81 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define CPIA2_VC_PW_CTRL 0x82 89*4882a593Smuzhiyun #define CPIA2_VC_PW_CTRL_COLDSTART 0x01 90*4882a593Smuzhiyun #define CPIA2_VC_PW_CTRL_CP_CLK_EN 0x02 91*4882a593Smuzhiyun #define CPIA2_VC_PW_CTRL_VP_RESET_N 0x04 92*4882a593Smuzhiyun #define CPIA2_VC_PW_CTRL_VC_CLK_EN 0x08 93*4882a593Smuzhiyun #define CPIA2_VC_PW_CTRL_VC_RESET_N 0x10 94*4882a593Smuzhiyun #define CPIA2_VC_PW_CTRL_GOTO_SUSPEND 0x20 95*4882a593Smuzhiyun #define CPIA2_VC_PW_CTRL_UDC_SUSPEND 0x40 96*4882a593Smuzhiyun #define CPIA2_VC_PW_CTRL_PWR_DOWN 0x80 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define CPIA2_VC_WAKEUP 0x83 99*4882a593Smuzhiyun #define CPIA2_VC_WAKEUP_SW_ENABLE 0x01 100*4882a593Smuzhiyun #define CPIA2_VC_WAKEUP_XX_ENABLE 0x02 101*4882a593Smuzhiyun #define CPIA2_VC_WAKEUP_SW_ATWAKEUP 0x04 102*4882a593Smuzhiyun #define CPIA2_VC_WAKEUP_XX_ATWAKEUP 0x08 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define CPIA2_VC_CLOCK_CTRL 0x84 105*4882a593Smuzhiyun #define CPIA2_VC_CLOCK_CTRL_TESTUP72 0x01 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define CPIA2_VC_INT_ENABLE 0x88 108*4882a593Smuzhiyun #define CPIA2_VC_INT_ENABLE_XX_IE 0x01 109*4882a593Smuzhiyun #define CPIA2_VC_INT_ENABLE_SW_IE 0x02 110*4882a593Smuzhiyun #define CPIA2_VC_INT_ENABLE_VC_IE 0x04 111*4882a593Smuzhiyun #define CPIA2_VC_INT_ENABLE_USBDATA_IE 0x08 112*4882a593Smuzhiyun #define CPIA2_VC_INT_ENABLE_USBSETUP_IE 0x10 113*4882a593Smuzhiyun #define CPIA2_VC_INT_ENABLE_USBCFG_IE 0x20 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define CPIA2_VC_INT_FLAG 0x89 116*4882a593Smuzhiyun #define CPIA2_VC_INT_ENABLE_XX_FLAG 0x01 117*4882a593Smuzhiyun #define CPIA2_VC_INT_ENABLE_SW_FLAG 0x02 118*4882a593Smuzhiyun #define CPIA2_VC_INT_ENABLE_VC_FLAG 0x04 119*4882a593Smuzhiyun #define CPIA2_VC_INT_ENABLE_USBDATA_FLAG 0x08 120*4882a593Smuzhiyun #define CPIA2_VC_INT_ENABLE_USBSETUP_FLAG 0x10 121*4882a593Smuzhiyun #define CPIA2_VC_INT_ENABLE_USBCFG_FLAG 0x20 122*4882a593Smuzhiyun #define CPIA2_VC_INT_ENABLE_SET_RESET_BIT 0x80 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define CPIA2_VC_INT_STATE 0x8A 125*4882a593Smuzhiyun #define CPIA2_VC_INT_STATE_XX_STATE 0x01 126*4882a593Smuzhiyun #define CPIA2_VC_INT_STATE_SW_STATE 0x02 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #define CPIA2_VC_MP_DIR 0x90 129*4882a593Smuzhiyun #define CPIA2_VC_MP_DIR_INPUT 0x00 130*4882a593Smuzhiyun #define CPIA2_VC_MP_DIR_OUTPUT 0x01 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define CPIA2_VC_MP_DATA 0x91 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define CPIA2_VC_DP_CTRL 0x98 135*4882a593Smuzhiyun #define CPIA2_VC_DP_CTRL_MODE_0 0x00 136*4882a593Smuzhiyun #define CPIA2_VC_DP_CTRL_MODE_A 0x01 137*4882a593Smuzhiyun #define CPIA2_VC_DP_CTRL_MODE_B 0x02 138*4882a593Smuzhiyun #define CPIA2_VC_DP_CTRL_MODE_C 0x03 139*4882a593Smuzhiyun #define CPIA2_VC_DP_CTRL_FAKE_FST 0x04 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define CPIA2_VC_AD_CTRL 0x99 142*4882a593Smuzhiyun #define CPIA2_VC_AD_CTRL_SRC_0 0x00 143*4882a593Smuzhiyun #define CPIA2_VC_AD_CTRL_SRC_DIGI_A 0x01 144*4882a593Smuzhiyun #define CPIA2_VC_AD_CTRL_SRC_REG 0x02 145*4882a593Smuzhiyun #define CPIA2_VC_AD_CTRL_DST_USB 0x00 146*4882a593Smuzhiyun #define CPIA2_VC_AD_CTRL_DST_REG 0x04 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #define CPIA2_VC_AD_TEST_IN 0x9B 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #define CPIA2_VC_AD_TEST_OUT 0x9C 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #define CPIA2_VC_AD_STATUS 0x9D 153*4882a593Smuzhiyun #define CPIA2_VC_AD_STATUS_EMPTY 0x01 154*4882a593Smuzhiyun #define CPIA2_VC_AD_STATUS_FULL 0x02 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #define CPIA2_VC_DP_DATA 0x9E 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun #define CPIA2_VC_ST_CTRL 0xA0 159*4882a593Smuzhiyun #define CPIA2_VC_ST_CTRL_SRC_VC 0x00 160*4882a593Smuzhiyun #define CPIA2_VC_ST_CTRL_SRC_DP 0x01 161*4882a593Smuzhiyun #define CPIA2_VC_ST_CTRL_SRC_REG 0x02 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun #define CPIA2_VC_ST_CTRL_RAW_SELECT 0x04 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun #define CPIA2_VC_ST_CTRL_DST_USB 0x00 166*4882a593Smuzhiyun #define CPIA2_VC_ST_CTRL_DST_DP 0x08 167*4882a593Smuzhiyun #define CPIA2_VC_ST_CTRL_DST_REG 0x10 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun #define CPIA2_VC_ST_CTRL_FIFO_ENABLE 0x20 170*4882a593Smuzhiyun #define CPIA2_VC_ST_CTRL_EOF_DETECT 0x40 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun #define CPIA2_VC_ST_TEST 0xA1 173*4882a593Smuzhiyun #define CPIA2_VC_ST_TEST_MODE_MANUAL 0x00 174*4882a593Smuzhiyun #define CPIA2_VC_ST_TEST_MODE_INCREMENT 0x02 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #define CPIA2_VC_ST_TEST_AUTO_FILL 0x08 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun #define CPIA2_VC_ST_TEST_REPEAT_FIFO 0x10 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun #define CPIA2_VC_ST_TEST_IN 0xA2 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun #define CPIA2_VC_ST_TEST_OUT 0xA3 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #define CPIA2_VC_ST_STATUS 0xA4 185*4882a593Smuzhiyun #define CPIA2_VC_ST_STATUS_EMPTY 0x01 186*4882a593Smuzhiyun #define CPIA2_VC_ST_STATUS_FULL 0x02 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun #define CPIA2_VC_ST_FRAME_DETECT_1 0xA5 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun #define CPIA2_VC_ST_FRAME_DETECT_2 0xA6 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun #define CPIA2_VC_USB_CTRL 0xA8 193*4882a593Smuzhiyun #define CPIA2_VC_USB_CTRL_CMD_STALLED 0x01 194*4882a593Smuzhiyun #define CPIA2_VC_USB_CTRL_CMD_READY 0x02 195*4882a593Smuzhiyun #define CPIA2_VC_USB_CTRL_CMD_STATUS 0x04 196*4882a593Smuzhiyun #define CPIA2_VC_USB_CTRL_CMD_STATUS_DIR 0x08 197*4882a593Smuzhiyun #define CPIA2_VC_USB_CTRL_CMD_NO_CLASH 0x10 198*4882a593Smuzhiyun #define CPIA2_VC_USB_CTRL_CMD_MICRO_ACCESS 0x80 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun #define CPIA2_VC_USB_STRM 0xA9 201*4882a593Smuzhiyun #define CPIA2_VC_USB_STRM_ISO_ENABLE 0x01 202*4882a593Smuzhiyun #define CPIA2_VC_USB_STRM_BLK_ENABLE 0x02 203*4882a593Smuzhiyun #define CPIA2_VC_USB_STRM_INT_ENABLE 0x04 204*4882a593Smuzhiyun #define CPIA2_VC_USB_STRM_AUD_ENABLE 0x08 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun #define CPIA2_VC_USB_STATUS 0xAA 207*4882a593Smuzhiyun #define CPIA2_VC_USB_STATUS_CMD_IN_PROGRESS 0x01 208*4882a593Smuzhiyun #define CPIA2_VC_USB_STATUS_CMD_STATUS_STALL 0x02 209*4882a593Smuzhiyun #define CPIA2_VC_USB_STATUS_CMD_HANDSHAKE 0x04 210*4882a593Smuzhiyun #define CPIA2_VC_USB_STATUS_CMD_OVERRIDE 0x08 211*4882a593Smuzhiyun #define CPIA2_VC_USB_STATUS_CMD_FIFO_BUSY 0x10 212*4882a593Smuzhiyun #define CPIA2_VC_USB_STATUS_BULK_REPEAT_TXN 0x20 213*4882a593Smuzhiyun #define CPIA2_VC_USB_STATUS_CONFIG_DONE 0x40 214*4882a593Smuzhiyun #define CPIA2_VC_USB_STATUS_USB_SUSPEND 0x80 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun #define CPIA2_VC_USB_CMDW 0xAB 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun #define CPIA2_VC_USB_DATARW 0xAC 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun #define CPIA2_VC_USB_INFO 0xAD 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun #define CPIA2_VC_USB_CONFIG 0xAE 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun #define CPIA2_VC_USB_SETTINGS 0xAF 225*4882a593Smuzhiyun #define CPIA2_VC_USB_SETTINGS_CONFIG_MASK 0x03 226*4882a593Smuzhiyun #define CPIA2_VC_USB_SETTINGS_INTERFACE_MASK 0x0C 227*4882a593Smuzhiyun #define CPIA2_VC_USB_SETTINGS_ALTERNATE_MASK 0x70 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun #define CPIA2_VC_USB_ISOLIM 0xB0 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun #define CPIA2_VC_USB_ISOFAILS 0xB1 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun #define CPIA2_VC_USB_ISOMAXPKTHI 0xB2 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun #define CPIA2_VC_USB_ISOMAXPKTLO 0xB3 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun #define CPIA2_VC_V2W_CTRL 0xB8 238*4882a593Smuzhiyun #define CPIA2_VC_V2W_SELECT 0x01 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun #define CPIA2_VC_V2W_SCL 0xB9 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun #define CPIA2_VC_V2W_SDA 0xBA 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun #define CPIA2_VC_VC_CTRL 0xC0 245*4882a593Smuzhiyun #define CPIA2_VC_VC_CTRL_RUN 0x01 246*4882a593Smuzhiyun #define CPIA2_VC_VC_CTRL_SINGLESHOT 0x02 247*4882a593Smuzhiyun #define CPIA2_VC_VC_CTRL_IDLING 0x04 248*4882a593Smuzhiyun #define CPIA2_VC_VC_CTRL_INHIBIT_H_TABLES 0x10 249*4882a593Smuzhiyun #define CPIA2_VC_VC_CTRL_INHIBIT_Q_TABLES 0x20 250*4882a593Smuzhiyun #define CPIA2_VC_VC_CTRL_INHIBIT_PRIVATE 0x40 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun #define CPIA2_VC_VC_RESTART_IVAL_HI 0xC1 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun #define CPIA2_VC_VC_RESTART_IVAL_LO 0xC2 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun #define CPIA2_VC_VC_FORMAT 0xC3 257*4882a593Smuzhiyun #define CPIA2_VC_VC_FORMAT_UFIRST 0x01 258*4882a593Smuzhiyun #define CPIA2_VC_VC_FORMAT_MONO 0x02 259*4882a593Smuzhiyun #define CPIA2_VC_VC_FORMAT_DECIMATING 0x04 260*4882a593Smuzhiyun #define CPIA2_VC_VC_FORMAT_SHORTLINE 0x08 261*4882a593Smuzhiyun #define CPIA2_VC_VC_FORMAT_SELFTEST 0x10 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun #define CPIA2_VC_VC_CLOCKS 0xC4 264*4882a593Smuzhiyun #define CPIA2_VC_VC_CLOCKS_CLKDIV_MASK 0x03 265*4882a593Smuzhiyun #define CPIA2_VC_VC_672_CLOCKS_CIF_DIV_BY_3 0x04 266*4882a593Smuzhiyun #define CPIA2_VC_VC_672_CLOCKS_SCALING 0x08 267*4882a593Smuzhiyun #define CPIA2_VC_VC_CLOCKS_LOGDIV0 0x00 268*4882a593Smuzhiyun #define CPIA2_VC_VC_CLOCKS_LOGDIV1 0x01 269*4882a593Smuzhiyun #define CPIA2_VC_VC_CLOCKS_LOGDIV2 0x02 270*4882a593Smuzhiyun #define CPIA2_VC_VC_CLOCKS_LOGDIV3 0x03 271*4882a593Smuzhiyun #define CPIA2_VC_VC_676_CLOCKS_CIF_DIV_BY_3 0x08 272*4882a593Smuzhiyun #define CPIA2_VC_VC_676_CLOCKS_SCALING 0x10 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun #define CPIA2_VC_VC_IHSIZE_LO 0xC5 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun #define CPIA2_VC_VC_XLIM_HI 0xC6 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun #define CPIA2_VC_VC_XLIM_LO 0xC7 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun #define CPIA2_VC_VC_YLIM_HI 0xC8 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun #define CPIA2_VC_VC_YLIM_LO 0xC9 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun #define CPIA2_VC_VC_OHSIZE 0xCA 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun #define CPIA2_VC_VC_OVSIZE 0xCB 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun #define CPIA2_VC_VC_HCROP 0xCC 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun #define CPIA2_VC_VC_VCROP 0xCD 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun #define CPIA2_VC_VC_HPHASE 0xCE 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun #define CPIA2_VC_VC_VPHASE 0xCF 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun #define CPIA2_VC_VC_HISPAN 0xD0 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun #define CPIA2_VC_VC_VISPAN 0xD1 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun #define CPIA2_VC_VC_HICROP 0xD2 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun #define CPIA2_VC_VC_VICROP 0xD3 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun #define CPIA2_VC_VC_HFRACT 0xD4 305*4882a593Smuzhiyun #define CPIA2_VC_VC_HFRACT_DEN_MASK 0x0F 306*4882a593Smuzhiyun #define CPIA2_VC_VC_HFRACT_NUM_MASK 0xF0 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun #define CPIA2_VC_VC_VFRACT 0xD5 309*4882a593Smuzhiyun #define CPIA2_VC_VC_VFRACT_DEN_MASK 0x0F 310*4882a593Smuzhiyun #define CPIA2_VC_VC_VFRACT_NUM_MASK 0xF0 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun #define CPIA2_VC_VC_JPEG_OPT 0xD6 313*4882a593Smuzhiyun #define CPIA2_VC_VC_JPEG_OPT_DOUBLE_SQUEEZE 0x01 314*4882a593Smuzhiyun #define CPIA2_VC_VC_JPEG_OPT_NO_DC_AUTO_SQUEEZE 0x02 315*4882a593Smuzhiyun #define CPIA2_VC_VC_JPEG_OPT_AUTO_SQUEEZE 0x04 316*4882a593Smuzhiyun #define CPIA2_VC_VC_JPEG_OPT_DEFAULT (CPIA2_VC_VC_JPEG_OPT_DOUBLE_SQUEEZE|\ 317*4882a593Smuzhiyun CPIA2_VC_VC_JPEG_OPT_AUTO_SQUEEZE) 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun #define CPIA2_VC_VC_CREEP_PERIOD 0xD7 321*4882a593Smuzhiyun #define CPIA2_VC_VC_USER_SQUEEZE 0xD8 322*4882a593Smuzhiyun #define CPIA2_VC_VC_TARGET_KB 0xD9 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun #define CPIA2_VC_VC_AUTO_SQUEEZE 0xE6 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun /*** 328*4882a593Smuzhiyun * VP register set (Bank 2) 329*4882a593Smuzhiyun ***/ 330*4882a593Smuzhiyun #define CPIA2_VP_DEVICEH 0 331*4882a593Smuzhiyun #define CPIA2_VP_DEVICEL 1 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun #define CPIA2_VP_SYSTEMSTATE 0x02 334*4882a593Smuzhiyun #define CPIA2_VP_SYSTEMSTATE_HK_ALIVE 0x01 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun #define CPIA2_VP_SYSTEMCTRL 0x03 337*4882a593Smuzhiyun #define CPIA2_VP_SYSTEMCTRL_REQ_CLEAR_ERROR 0x80 338*4882a593Smuzhiyun #define CPIA2_VP_SYSTEMCTRL_POWER_DOWN_PLL 0x20 339*4882a593Smuzhiyun #define CPIA2_VP_SYSTEMCTRL_REQ_SUSPEND_STATE 0x10 340*4882a593Smuzhiyun #define CPIA2_VP_SYSTEMCTRL_REQ_SERIAL_WAKEUP 0x08 341*4882a593Smuzhiyun #define CPIA2_VP_SYSTEMCTRL_REQ_AUTOLOAD 0x04 342*4882a593Smuzhiyun #define CPIA2_VP_SYSTEMCTRL_HK_CONTROL 0x02 343*4882a593Smuzhiyun #define CPIA2_VP_SYSTEMCTRL_POWER_CONTROL 0x01 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun #define CPIA2_VP_SENSOR_FLAGS 0x05 346*4882a593Smuzhiyun #define CPIA2_VP_SENSOR_FLAGS_404 0x01 347*4882a593Smuzhiyun #define CPIA2_VP_SENSOR_FLAGS_407 0x02 348*4882a593Smuzhiyun #define CPIA2_VP_SENSOR_FLAGS_409 0x04 349*4882a593Smuzhiyun #define CPIA2_VP_SENSOR_FLAGS_410 0x08 350*4882a593Smuzhiyun #define CPIA2_VP_SENSOR_FLAGS_500 0x10 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun #define CPIA2_VP_SENSOR_REV 0x06 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun #define CPIA2_VP_DEVICE_CONFIG 0x07 355*4882a593Smuzhiyun #define CPIA2_VP_DEVICE_CONFIG_SERIAL_BRIDGE 0x01 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun #define CPIA2_VP_GPIO_DIRECTION 0x08 358*4882a593Smuzhiyun #define CPIA2_VP_GPIO_READ 0xFF 359*4882a593Smuzhiyun #define CPIA2_VP_GPIO_WRITE 0x00 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun #define CPIA2_VP_GPIO_DATA 0x09 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun #define CPIA2_VP_RAM_ADDR_H 0x0A 364*4882a593Smuzhiyun #define CPIA2_VP_RAM_ADDR_L 0x0B 365*4882a593Smuzhiyun #define CPIA2_VP_RAM_DATA 0x0C 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun #define CPIA2_VP_PATCH_REV 0x0F 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun #define CPIA2_VP4_USER_MODE 0x10 370*4882a593Smuzhiyun #define CPIA2_VP5_USER_MODE 0x13 371*4882a593Smuzhiyun #define CPIA2_VP_USER_MODE_CIF 0x01 372*4882a593Smuzhiyun #define CPIA2_VP_USER_MODE_QCIFDS 0x02 373*4882a593Smuzhiyun #define CPIA2_VP_USER_MODE_QCIFPTC 0x04 374*4882a593Smuzhiyun #define CPIA2_VP_USER_MODE_QVGADS 0x08 375*4882a593Smuzhiyun #define CPIA2_VP_USER_MODE_QVGAPTC 0x10 376*4882a593Smuzhiyun #define CPIA2_VP_USER_MODE_VGA 0x20 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun #define CPIA2_VP4_FRAMERATE_REQUEST 0x11 379*4882a593Smuzhiyun #define CPIA2_VP5_FRAMERATE_REQUEST 0x14 380*4882a593Smuzhiyun #define CPIA2_VP_FRAMERATE_60 0x80 381*4882a593Smuzhiyun #define CPIA2_VP_FRAMERATE_50 0x40 382*4882a593Smuzhiyun #define CPIA2_VP_FRAMERATE_30 0x20 383*4882a593Smuzhiyun #define CPIA2_VP_FRAMERATE_25 0x10 384*4882a593Smuzhiyun #define CPIA2_VP_FRAMERATE_15 0x08 385*4882a593Smuzhiyun #define CPIA2_VP_FRAMERATE_12_5 0x04 386*4882a593Smuzhiyun #define CPIA2_VP_FRAMERATE_7_5 0x02 387*4882a593Smuzhiyun #define CPIA2_VP_FRAMERATE_6_25 0x01 388*4882a593Smuzhiyun 389*4882a593Smuzhiyun #define CPIA2_VP4_USER_EFFECTS 0x12 390*4882a593Smuzhiyun #define CPIA2_VP5_USER_EFFECTS 0x15 391*4882a593Smuzhiyun #define CPIA2_VP_USER_EFFECTS_COLBARS 0x01 392*4882a593Smuzhiyun #define CPIA2_VP_USER_EFFECTS_COLBARS_GRAD 0x02 393*4882a593Smuzhiyun #define CPIA2_VP_USER_EFFECTS_MIRROR 0x04 394*4882a593Smuzhiyun #define CPIA2_VP_USER_EFFECTS_FLIP 0x40 // VP5 only 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun /* NOTE: CPIA2_VP_EXPOSURE_MODES shares the same register as VP5 User 397*4882a593Smuzhiyun * Effects */ 398*4882a593Smuzhiyun #define CPIA2_VP_EXPOSURE_MODES 0x15 399*4882a593Smuzhiyun #define CPIA2_VP_EXPOSURE_MODES_INHIBIT_FLICKER 0x20 400*4882a593Smuzhiyun #define CPIA2_VP_EXPOSURE_MODES_COMPILE_EXP 0x10 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun #define CPIA2_VP4_EXPOSURE_TARGET 0x16 // VP4 403*4882a593Smuzhiyun #define CPIA2_VP5_EXPOSURE_TARGET 0x20 // VP5 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun #define CPIA2_VP_FLICKER_MODES 0x1B 406*4882a593Smuzhiyun #define CPIA2_VP_FLICKER_MODES_50HZ 0x80 407*4882a593Smuzhiyun #define CPIA2_VP_FLICKER_MODES_CUSTOM_FLT_FFREQ 0x40 408*4882a593Smuzhiyun #define CPIA2_VP_FLICKER_MODES_NEVER_FLICKER 0x20 409*4882a593Smuzhiyun #define CPIA2_VP_FLICKER_MODES_INHIBIT_RUB 0x10 410*4882a593Smuzhiyun #define CPIA2_VP_FLICKER_MODES_ADJUST_LINE_FREQ 0x08 411*4882a593Smuzhiyun #define CPIA2_VP_FLICKER_MODES_CUSTOM_INT_FFREQ 0x04 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun #define CPIA2_VP_UMISC 0x1D 414*4882a593Smuzhiyun #define CPIA2_VP_UMISC_FORCE_MONO 0x80 415*4882a593Smuzhiyun #define CPIA2_VP_UMISC_FORCE_ID_MASK 0x40 416*4882a593Smuzhiyun #define CPIA2_VP_UMISC_INHIBIT_AUTO_FGS 0x20 417*4882a593Smuzhiyun #define CPIA2_VP_UMISC_INHIBIT_AUTO_DIMS 0x08 418*4882a593Smuzhiyun #define CPIA2_VP_UMISC_OPT_FOR_SENSOR_DS 0x04 419*4882a593Smuzhiyun #define CPIA2_VP_UMISC_INHIBIT_AUTO_MODE_INT 0x02 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun #define CPIA2_VP5_ANTIFLKRSETUP 0x22 //34 422*4882a593Smuzhiyun 423*4882a593Smuzhiyun #define CPIA2_VP_INTERPOLATION 0x24 424*4882a593Smuzhiyun #define CPIA2_VP_INTERPOLATION_EVEN_FIRST 0x40 425*4882a593Smuzhiyun #define CPIA2_VP_INTERPOLATION_HJOG 0x20 426*4882a593Smuzhiyun #define CPIA2_VP_INTERPOLATION_VJOG 0x10 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun #define CPIA2_VP_GAMMA 0x25 429*4882a593Smuzhiyun #define CPIA2_VP_DEFAULT_GAMMA 0x10 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun #define CPIA2_VP_YRANGE 0x26 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun #define CPIA2_VP_SATURATION 0x27 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun #define CPIA2_VP5_MYBLACK_LEVEL 0x3A //58 436*4882a593Smuzhiyun #define CPIA2_VP5_MCYRANGE 0x3B //59 437*4882a593Smuzhiyun #define CPIA2_VP5_MYCEILING 0x3C //60 438*4882a593Smuzhiyun #define CPIA2_VP5_MCUVSATURATION 0x3D //61 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun #define CPIA2_VP_REHASH_VALUES 0x60 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun /*** 445*4882a593Smuzhiyun * Common sensor registers 446*4882a593Smuzhiyun ***/ 447*4882a593Smuzhiyun #define CPIA2_SENSOR_DEVICE_H 0x00 448*4882a593Smuzhiyun #define CPIA2_SENSOR_DEVICE_L 0x01 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun #define CPIA2_SENSOR_DATA_FORMAT 0x16 451*4882a593Smuzhiyun #define CPIA2_SENSOR_DATA_FORMAT_HMIRROR 0x08 452*4882a593Smuzhiyun #define CPIA2_SENSOR_DATA_FORMAT_VMIRROR 0x10 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun #define CPIA2_SENSOR_CR1 0x76 455*4882a593Smuzhiyun #define CPIA2_SENSOR_CR1_STAND_BY 0x01 456*4882a593Smuzhiyun #define CPIA2_SENSOR_CR1_DOWN_RAMP_GEN 0x02 457*4882a593Smuzhiyun #define CPIA2_SENSOR_CR1_DOWN_COLUMN_ADC 0x04 458*4882a593Smuzhiyun #define CPIA2_SENSOR_CR1_DOWN_CAB_REGULATOR 0x08 459*4882a593Smuzhiyun #define CPIA2_SENSOR_CR1_DOWN_AUDIO_REGULATOR 0x10 460*4882a593Smuzhiyun #define CPIA2_SENSOR_CR1_DOWN_VRT_AMP 0x20 461*4882a593Smuzhiyun #define CPIA2_SENSOR_CR1_DOWN_BAND_GAP 0x40 462*4882a593Smuzhiyun 463*4882a593Smuzhiyun #endif 464