1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Driver for the Auvitek USB bridge 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2008 Steven Toth <stoth@linuxtv.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* We'll start to rename these registers once we have a better 9*4882a593Smuzhiyun * understanding of their meaning. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #define REG_000 0x000 12*4882a593Smuzhiyun #define REG_001 0x001 13*4882a593Smuzhiyun #define REG_002 0x002 14*4882a593Smuzhiyun #define REG_003 0x003 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define AU0828_SENSORCTRL_100 0x100 17*4882a593Smuzhiyun #define AU0828_SENSORCTRL_VBI_103 0x103 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* I2C registers */ 20*4882a593Smuzhiyun #define AU0828_I2C_TRIGGER_200 0x200 21*4882a593Smuzhiyun #define AU0828_I2C_STATUS_201 0x201 22*4882a593Smuzhiyun #define AU0828_I2C_CLK_DIVIDER_202 0x202 23*4882a593Smuzhiyun #define AU0828_I2C_DEST_ADDR_203 0x203 24*4882a593Smuzhiyun #define AU0828_I2C_WRITE_FIFO_205 0x205 25*4882a593Smuzhiyun #define AU0828_I2C_READ_FIFO_209 0x209 26*4882a593Smuzhiyun #define AU0828_I2C_MULTIBYTE_MODE_2FF 0x2ff 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Audio registers */ 29*4882a593Smuzhiyun #define AU0828_AUDIOCTRL_50C 0x50C 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define REG_600 0x600 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /*********************************************************************/ 34*4882a593Smuzhiyun /* Here are constants for values associated with the above registers */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* I2C Trigger (Reg 0x200) */ 37*4882a593Smuzhiyun #define AU0828_I2C_TRIGGER_WRITE 0x01 38*4882a593Smuzhiyun #define AU0828_I2C_TRIGGER_READ 0x20 39*4882a593Smuzhiyun #define AU0828_I2C_TRIGGER_HOLD 0x40 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* I2C Status (Reg 0x201) */ 42*4882a593Smuzhiyun #define AU0828_I2C_STATUS_READ_DONE 0x01 43*4882a593Smuzhiyun #define AU0828_I2C_STATUS_NO_READ_ACK 0x02 44*4882a593Smuzhiyun #define AU0828_I2C_STATUS_WRITE_DONE 0x04 45*4882a593Smuzhiyun #define AU0828_I2C_STATUS_NO_WRITE_ACK 0x08 46*4882a593Smuzhiyun #define AU0828_I2C_STATUS_BUSY 0x10 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* I2C Clock Divider (Reg 0x202) */ 49*4882a593Smuzhiyun #define AU0828_I2C_CLK_250KHZ 0x07 50*4882a593Smuzhiyun #define AU0828_I2C_CLK_100KHZ 0x14 51*4882a593Smuzhiyun #define AU0828_I2C_CLK_30KHZ 0x40 52*4882a593Smuzhiyun #define AU0828_I2C_CLK_20KHZ 0x60 53