1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Driver for Quantek QT1010 silicon tuner 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2006 Antti Palosaari <crope@iki.fi> 6*4882a593Smuzhiyun * Aapo Tahkola <aet@rasterburn.org> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef QT1010_PRIV_H 10*4882a593Smuzhiyun #define QT1010_PRIV_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun reg def meaning 14*4882a593Smuzhiyun === === ======= 15*4882a593Smuzhiyun 00 00 ? 16*4882a593Smuzhiyun 01 a0 ? operation start/stop; start=80, stop=00 17*4882a593Smuzhiyun 02 00 ? 18*4882a593Smuzhiyun 03 19 ? 19*4882a593Smuzhiyun 04 00 ? 20*4882a593Smuzhiyun 05 00 ? maybe band selection 21*4882a593Smuzhiyun 06 00 ? 22*4882a593Smuzhiyun 07 2b set frequency: 32 MHz scale, n*32 MHz 23*4882a593Smuzhiyun 08 0b ? 24*4882a593Smuzhiyun 09 10 ? changes every 8/24 MHz; values 1d/1c 25*4882a593Smuzhiyun 0a 08 set frequency: 4 MHz scale, n*4 MHz 26*4882a593Smuzhiyun 0b 41 ? changes every 2/2 MHz; values 45/45 27*4882a593Smuzhiyun 0c e1 ? 28*4882a593Smuzhiyun 0d 94 ? 29*4882a593Smuzhiyun 0e b6 ? 30*4882a593Smuzhiyun 0f 2c ? 31*4882a593Smuzhiyun 10 10 ? 32*4882a593Smuzhiyun 11 f1 ? maybe device specified adjustment 33*4882a593Smuzhiyun 12 11 ? maybe device specified adjustment 34*4882a593Smuzhiyun 13 3f ? 35*4882a593Smuzhiyun 14 1f ? 36*4882a593Smuzhiyun 15 3f ? 37*4882a593Smuzhiyun 16 ff ? 38*4882a593Smuzhiyun 17 ff ? 39*4882a593Smuzhiyun 18 f7 ? 40*4882a593Smuzhiyun 19 80 ? 41*4882a593Smuzhiyun 1a d0 set frequency: 125 kHz scale, n*125 kHz 42*4882a593Smuzhiyun 1b 00 ? 43*4882a593Smuzhiyun 1c 89 ? 44*4882a593Smuzhiyun 1d 00 ? 45*4882a593Smuzhiyun 1e 00 ? looks like operation register; write cmd here, read result from 1f-26 46*4882a593Smuzhiyun 1f 20 ? chip initialization 47*4882a593Smuzhiyun 20 e0 ? chip initialization 48*4882a593Smuzhiyun 21 20 ? 49*4882a593Smuzhiyun 22 d0 ? 50*4882a593Smuzhiyun 23 d0 ? 51*4882a593Smuzhiyun 24 d0 ? 52*4882a593Smuzhiyun 25 40 ? chip initialization 53*4882a593Smuzhiyun 26 08 ? 54*4882a593Smuzhiyun 27 29 ? 55*4882a593Smuzhiyun 28 55 ? 56*4882a593Smuzhiyun 29 39 ? 57*4882a593Smuzhiyun 2a 13 ? 58*4882a593Smuzhiyun 2b 01 ? 59*4882a593Smuzhiyun 2c ea ? 60*4882a593Smuzhiyun 2d 00 ? 61*4882a593Smuzhiyun 2e 00 ? not used? 62*4882a593Smuzhiyun 2f 00 ? not used? 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define QT1010_STEP (125 * kHz) /* 66*4882a593Smuzhiyun * used by Windows drivers, 67*4882a593Smuzhiyun * hw could be more precise but we don't 68*4882a593Smuzhiyun * know how to use 69*4882a593Smuzhiyun */ 70*4882a593Smuzhiyun #define QT1010_MIN_FREQ (48 * MHz) 71*4882a593Smuzhiyun #define QT1010_MAX_FREQ (860 * MHz) 72*4882a593Smuzhiyun #define QT1010_OFFSET (1246 * MHz) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define QT1010_WR 0 75*4882a593Smuzhiyun #define QT1010_RD 1 76*4882a593Smuzhiyun #define QT1010_M1 3 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun typedef struct { 79*4882a593Smuzhiyun u8 oper, reg, val; 80*4882a593Smuzhiyun } qt1010_i2c_oper_t; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun struct qt1010_priv { 83*4882a593Smuzhiyun struct qt1010_config *cfg; 84*4882a593Smuzhiyun struct i2c_adapter *i2c; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun u8 reg1f_init_val; 87*4882a593Smuzhiyun u8 reg20_init_val; 88*4882a593Smuzhiyun u8 reg25_init_val; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun u32 frequency; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #endif 94