1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for Microtune MT2131 "QAM/8VSB single chip tuner"
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/dvb/frontend.h>
11*4882a593Smuzhiyun #include <linux/i2c.h>
12*4882a593Smuzhiyun #include <linux/slab.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <media/dvb_frontend.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "mt2131.h"
17*4882a593Smuzhiyun #include "mt2131_priv.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun static int debug;
20*4882a593Smuzhiyun module_param(debug, int, 0644);
21*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define dprintk(level,fmt, arg...) if (debug >= level) \
24*4882a593Smuzhiyun printk(KERN_INFO "%s: " fmt, "mt2131", ## arg)
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static u8 mt2131_config1[] = {
27*4882a593Smuzhiyun 0x01,
28*4882a593Smuzhiyun 0x50, 0x00, 0x50, 0x80, 0x00, 0x49, 0xfa, 0x88,
29*4882a593Smuzhiyun 0x08, 0x77, 0x41, 0x04, 0x00, 0x00, 0x00, 0x32,
30*4882a593Smuzhiyun 0x7f, 0xda, 0x4c, 0x00, 0x10, 0xaa, 0x78, 0x80,
31*4882a593Smuzhiyun 0xff, 0x68, 0xa0, 0xff, 0xdd, 0x00, 0x00
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static u8 mt2131_config2[] = {
35*4882a593Smuzhiyun 0x10,
36*4882a593Smuzhiyun 0x7f, 0xc8, 0x0a, 0x5f, 0x00, 0x04
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
mt2131_readreg(struct mt2131_priv * priv,u8 reg,u8 * val)39*4882a593Smuzhiyun static int mt2131_readreg(struct mt2131_priv *priv, u8 reg, u8 *val)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun struct i2c_msg msg[2] = {
42*4882a593Smuzhiyun { .addr = priv->cfg->i2c_address, .flags = 0,
43*4882a593Smuzhiyun .buf = ®, .len = 1 },
44*4882a593Smuzhiyun { .addr = priv->cfg->i2c_address, .flags = I2C_M_RD,
45*4882a593Smuzhiyun .buf = val, .len = 1 },
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun if (i2c_transfer(priv->i2c, msg, 2) != 2) {
49*4882a593Smuzhiyun printk(KERN_WARNING "mt2131 I2C read failed\n");
50*4882a593Smuzhiyun return -EREMOTEIO;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun return 0;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
mt2131_writereg(struct mt2131_priv * priv,u8 reg,u8 val)55*4882a593Smuzhiyun static int mt2131_writereg(struct mt2131_priv *priv, u8 reg, u8 val)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun u8 buf[2] = { reg, val };
58*4882a593Smuzhiyun struct i2c_msg msg = { .addr = priv->cfg->i2c_address, .flags = 0,
59*4882a593Smuzhiyun .buf = buf, .len = 2 };
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
62*4882a593Smuzhiyun printk(KERN_WARNING "mt2131 I2C write failed\n");
63*4882a593Smuzhiyun return -EREMOTEIO;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun return 0;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
mt2131_writeregs(struct mt2131_priv * priv,u8 * buf,u8 len)68*4882a593Smuzhiyun static int mt2131_writeregs(struct mt2131_priv *priv,u8 *buf, u8 len)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun struct i2c_msg msg = { .addr = priv->cfg->i2c_address,
71*4882a593Smuzhiyun .flags = 0, .buf = buf, .len = len };
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
74*4882a593Smuzhiyun printk(KERN_WARNING "mt2131 I2C write failed (len=%i)\n",
75*4882a593Smuzhiyun (int)len);
76*4882a593Smuzhiyun return -EREMOTEIO;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun return 0;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
mt2131_set_params(struct dvb_frontend * fe)81*4882a593Smuzhiyun static int mt2131_set_params(struct dvb_frontend *fe)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun struct dtv_frontend_properties *c = &fe->dtv_property_cache;
84*4882a593Smuzhiyun struct mt2131_priv *priv;
85*4882a593Smuzhiyun int ret=0, i;
86*4882a593Smuzhiyun u32 freq;
87*4882a593Smuzhiyun u8 if_band_center;
88*4882a593Smuzhiyun u32 f_lo1, f_lo2;
89*4882a593Smuzhiyun u32 div1, num1, div2, num2;
90*4882a593Smuzhiyun u8 b[8];
91*4882a593Smuzhiyun u8 lockval = 0;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun priv = fe->tuner_priv;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun freq = c->frequency / 1000; /* Hz -> kHz */
96*4882a593Smuzhiyun dprintk(1, "%s() freq=%d\n", __func__, freq);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun f_lo1 = freq + MT2131_IF1 * 1000;
99*4882a593Smuzhiyun f_lo1 = (f_lo1 / 250) * 250;
100*4882a593Smuzhiyun f_lo2 = f_lo1 - freq - MT2131_IF2;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun priv->frequency = (f_lo1 - f_lo2 - MT2131_IF2) * 1000;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* Frequency LO1 = 16MHz * (DIV1 + NUM1/8192 ) */
105*4882a593Smuzhiyun num1 = f_lo1 * 64 / (MT2131_FREF / 128);
106*4882a593Smuzhiyun div1 = num1 / 8192;
107*4882a593Smuzhiyun num1 &= 0x1fff;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* Frequency LO2 = 16MHz * (DIV2 + NUM2/8192 ) */
110*4882a593Smuzhiyun num2 = f_lo2 * 64 / (MT2131_FREF / 128);
111*4882a593Smuzhiyun div2 = num2 / 8192;
112*4882a593Smuzhiyun num2 &= 0x1fff;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun if (freq <= 82500) if_band_center = 0x00; else
115*4882a593Smuzhiyun if (freq <= 137500) if_band_center = 0x01; else
116*4882a593Smuzhiyun if (freq <= 192500) if_band_center = 0x02; else
117*4882a593Smuzhiyun if (freq <= 247500) if_band_center = 0x03; else
118*4882a593Smuzhiyun if (freq <= 302500) if_band_center = 0x04; else
119*4882a593Smuzhiyun if (freq <= 357500) if_band_center = 0x05; else
120*4882a593Smuzhiyun if (freq <= 412500) if_band_center = 0x06; else
121*4882a593Smuzhiyun if (freq <= 467500) if_band_center = 0x07; else
122*4882a593Smuzhiyun if (freq <= 522500) if_band_center = 0x08; else
123*4882a593Smuzhiyun if (freq <= 577500) if_band_center = 0x09; else
124*4882a593Smuzhiyun if (freq <= 632500) if_band_center = 0x0A; else
125*4882a593Smuzhiyun if (freq <= 687500) if_band_center = 0x0B; else
126*4882a593Smuzhiyun if (freq <= 742500) if_band_center = 0x0C; else
127*4882a593Smuzhiyun if (freq <= 797500) if_band_center = 0x0D; else
128*4882a593Smuzhiyun if (freq <= 852500) if_band_center = 0x0E; else
129*4882a593Smuzhiyun if (freq <= 907500) if_band_center = 0x0F; else
130*4882a593Smuzhiyun if (freq <= 962500) if_band_center = 0x10; else
131*4882a593Smuzhiyun if (freq <= 1017500) if_band_center = 0x11; else
132*4882a593Smuzhiyun if (freq <= 1072500) if_band_center = 0x12; else if_band_center = 0x13;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun b[0] = 1;
135*4882a593Smuzhiyun b[1] = (num1 >> 5) & 0xFF;
136*4882a593Smuzhiyun b[2] = (num1 & 0x1F);
137*4882a593Smuzhiyun b[3] = div1;
138*4882a593Smuzhiyun b[4] = (num2 >> 5) & 0xFF;
139*4882a593Smuzhiyun b[5] = num2 & 0x1F;
140*4882a593Smuzhiyun b[6] = div2;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun dprintk(1, "IF1: %dMHz IF2: %dMHz\n", MT2131_IF1, MT2131_IF2);
143*4882a593Smuzhiyun dprintk(1, "PLL freq=%dkHz band=%d\n", (int)freq, (int)if_band_center);
144*4882a593Smuzhiyun dprintk(1, "PLL f_lo1=%dkHz f_lo2=%dkHz\n", (int)f_lo1, (int)f_lo2);
145*4882a593Smuzhiyun dprintk(1, "PLL div1=%d num1=%d div2=%d num2=%d\n",
146*4882a593Smuzhiyun (int)div1, (int)num1, (int)div2, (int)num2);
147*4882a593Smuzhiyun dprintk(1, "PLL [1..6]: %2x %2x %2x %2x %2x %2x\n",
148*4882a593Smuzhiyun (int)b[1], (int)b[2], (int)b[3], (int)b[4], (int)b[5],
149*4882a593Smuzhiyun (int)b[6]);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun ret = mt2131_writeregs(priv,b,7);
152*4882a593Smuzhiyun if (ret < 0)
153*4882a593Smuzhiyun return ret;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun mt2131_writereg(priv, 0x0b, if_band_center);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /* Wait for lock */
158*4882a593Smuzhiyun i = 0;
159*4882a593Smuzhiyun do {
160*4882a593Smuzhiyun mt2131_readreg(priv, 0x08, &lockval);
161*4882a593Smuzhiyun if ((lockval & 0x88) == 0x88)
162*4882a593Smuzhiyun break;
163*4882a593Smuzhiyun msleep(4);
164*4882a593Smuzhiyun i++;
165*4882a593Smuzhiyun } while (i < 10);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun return ret;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
mt2131_get_frequency(struct dvb_frontend * fe,u32 * frequency)170*4882a593Smuzhiyun static int mt2131_get_frequency(struct dvb_frontend *fe, u32 *frequency)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun struct mt2131_priv *priv = fe->tuner_priv;
173*4882a593Smuzhiyun dprintk(1, "%s()\n", __func__);
174*4882a593Smuzhiyun *frequency = priv->frequency;
175*4882a593Smuzhiyun return 0;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
mt2131_get_status(struct dvb_frontend * fe,u32 * status)178*4882a593Smuzhiyun static int mt2131_get_status(struct dvb_frontend *fe, u32 *status)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun struct mt2131_priv *priv = fe->tuner_priv;
181*4882a593Smuzhiyun u8 lock_status = 0;
182*4882a593Smuzhiyun u8 afc_status = 0;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun *status = 0;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun mt2131_readreg(priv, 0x08, &lock_status);
187*4882a593Smuzhiyun if ((lock_status & 0x88) == 0x88)
188*4882a593Smuzhiyun *status = TUNER_STATUS_LOCKED;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun mt2131_readreg(priv, 0x09, &afc_status);
191*4882a593Smuzhiyun dprintk(1, "%s() - LO Status = 0x%x, AFC Status = 0x%x\n",
192*4882a593Smuzhiyun __func__, lock_status, afc_status);
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun return 0;
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun
mt2131_init(struct dvb_frontend * fe)197*4882a593Smuzhiyun static int mt2131_init(struct dvb_frontend *fe)
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun struct mt2131_priv *priv = fe->tuner_priv;
200*4882a593Smuzhiyun int ret;
201*4882a593Smuzhiyun dprintk(1, "%s()\n", __func__);
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun if ((ret = mt2131_writeregs(priv, mt2131_config1,
204*4882a593Smuzhiyun sizeof(mt2131_config1))) < 0)
205*4882a593Smuzhiyun return ret;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun mt2131_writereg(priv, 0x0b, 0x09);
208*4882a593Smuzhiyun mt2131_writereg(priv, 0x15, 0x47);
209*4882a593Smuzhiyun mt2131_writereg(priv, 0x07, 0xf2);
210*4882a593Smuzhiyun mt2131_writereg(priv, 0x0b, 0x01);
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun if ((ret = mt2131_writeregs(priv, mt2131_config2,
213*4882a593Smuzhiyun sizeof(mt2131_config2))) < 0)
214*4882a593Smuzhiyun return ret;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun return ret;
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun
mt2131_release(struct dvb_frontend * fe)219*4882a593Smuzhiyun static void mt2131_release(struct dvb_frontend *fe)
220*4882a593Smuzhiyun {
221*4882a593Smuzhiyun dprintk(1, "%s()\n", __func__);
222*4882a593Smuzhiyun kfree(fe->tuner_priv);
223*4882a593Smuzhiyun fe->tuner_priv = NULL;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun static const struct dvb_tuner_ops mt2131_tuner_ops = {
227*4882a593Smuzhiyun .info = {
228*4882a593Smuzhiyun .name = "Microtune MT2131",
229*4882a593Smuzhiyun .frequency_min_hz = 48 * MHz,
230*4882a593Smuzhiyun .frequency_max_hz = 860 * MHz,
231*4882a593Smuzhiyun .frequency_step_hz = 50 * kHz,
232*4882a593Smuzhiyun },
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun .release = mt2131_release,
235*4882a593Smuzhiyun .init = mt2131_init,
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun .set_params = mt2131_set_params,
238*4882a593Smuzhiyun .get_frequency = mt2131_get_frequency,
239*4882a593Smuzhiyun .get_status = mt2131_get_status
240*4882a593Smuzhiyun };
241*4882a593Smuzhiyun
mt2131_attach(struct dvb_frontend * fe,struct i2c_adapter * i2c,struct mt2131_config * cfg,u16 if1)242*4882a593Smuzhiyun struct dvb_frontend * mt2131_attach(struct dvb_frontend *fe,
243*4882a593Smuzhiyun struct i2c_adapter *i2c,
244*4882a593Smuzhiyun struct mt2131_config *cfg, u16 if1)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun struct mt2131_priv *priv = NULL;
247*4882a593Smuzhiyun u8 id = 0;
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun dprintk(1, "%s()\n", __func__);
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun priv = kzalloc(sizeof(struct mt2131_priv), GFP_KERNEL);
252*4882a593Smuzhiyun if (priv == NULL)
253*4882a593Smuzhiyun return NULL;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun priv->cfg = cfg;
256*4882a593Smuzhiyun priv->i2c = i2c;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun if (mt2131_readreg(priv, 0, &id) != 0) {
259*4882a593Smuzhiyun kfree(priv);
260*4882a593Smuzhiyun return NULL;
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun if ( (id != 0x3E) && (id != 0x3F) ) {
263*4882a593Smuzhiyun printk(KERN_ERR "MT2131: Device not found at addr 0x%02x\n",
264*4882a593Smuzhiyun cfg->i2c_address);
265*4882a593Smuzhiyun kfree(priv);
266*4882a593Smuzhiyun return NULL;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun printk(KERN_INFO "MT2131: successfully identified at address 0x%02x\n",
270*4882a593Smuzhiyun cfg->i2c_address);
271*4882a593Smuzhiyun memcpy(&fe->ops.tuner_ops, &mt2131_tuner_ops,
272*4882a593Smuzhiyun sizeof(struct dvb_tuner_ops));
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun fe->tuner_priv = priv;
275*4882a593Smuzhiyun return fe;
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun EXPORT_SYMBOL(mt2131_attach);
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun MODULE_AUTHOR("Steven Toth");
280*4882a593Smuzhiyun MODULE_DESCRIPTION("Microtune MT2131 silicon tuner driver");
281*4882a593Smuzhiyun MODULE_LICENSE("GPL");
282