1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Driver for Microtune MT2060 "Single chip dual conversion broadband tuner" 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2006 Olivier DANET <odanet@caramail.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef MT2060_PRIV_H 9*4882a593Smuzhiyun #define MT2060_PRIV_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun // Uncomment the #define below to enable spurs checking. The results where quite unconvincing. 12*4882a593Smuzhiyun // #define MT2060_SPURCHECK 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* This driver is based on the information available in the datasheet of the 15*4882a593Smuzhiyun "Comtech SDVBT-3K6M" tuner ( K1000737843.pdf ) which features the MT2060 register map : 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun I2C Address : 0x60 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun Reg.No | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 | ( defaults ) 20*4882a593Smuzhiyun -------------------------------------------------------------------------------- 21*4882a593Smuzhiyun 00 | [ PART ] | [ REV ] | R = 0x63 22*4882a593Smuzhiyun 01 | [ LNABAND ] | [ NUM1(5:2) ] | RW = 0x3F 23*4882a593Smuzhiyun 02 | [ DIV1 ] | RW = 0x74 24*4882a593Smuzhiyun 03 | FM1CA | FM1SS | [ NUM1(1:0) ] | [ NUM2(3:0) ] | RW = 0x00 25*4882a593Smuzhiyun 04 | NUM2(11:4) ] | RW = 0x08 26*4882a593Smuzhiyun 05 | [ DIV2 ] |NUM2(12)| RW = 0x93 27*4882a593Smuzhiyun 06 | L1LK | [ TAD1 ] | L2LK | [ TAD2 ] | R 28*4882a593Smuzhiyun 07 | [ FMF ] | R 29*4882a593Smuzhiyun 08 | ? | FMCAL | ? | ? | ? | ? | ? | TEMP | R 30*4882a593Smuzhiyun 09 | 0 | 0 | [ FMGC ] | 0 | GP02 | GP01 | 0 | RW = 0x20 31*4882a593Smuzhiyun 0A | ?? 32*4882a593Smuzhiyun 0B | 0 | 0 | 1 | 1 | 0 | 0 | [ VGAG ] | RW = 0x30 33*4882a593Smuzhiyun 0C | V1CSE | 1 | 1 | 1 | 1 | 1 | 1 | 1 | RW = 0xFF 34*4882a593Smuzhiyun 0D | 1 | 0 | [ V1CS ] | RW = 0xB0 35*4882a593Smuzhiyun 0E | ?? 36*4882a593Smuzhiyun 0F | ?? 37*4882a593Smuzhiyun 10 | ?? 38*4882a593Smuzhiyun 11 | [ LOTO ] | 0 | 0 | 1 | 0 | RW = 0x42 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun PART : Part code : 6 for MT2060 41*4882a593Smuzhiyun REV : Revision code : 3 for current revision 42*4882a593Smuzhiyun LNABAND : Input frequency range : ( See code for details ) 43*4882a593Smuzhiyun NUM1 / DIV1 / NUM2 / DIV2 : Frequencies programming ( See code for details ) 44*4882a593Smuzhiyun FM1CA : Calibration Start Bit 45*4882a593Smuzhiyun FM1SS : Calibration Single Step bit 46*4882a593Smuzhiyun L1LK : LO1 Lock Detect 47*4882a593Smuzhiyun TAD1 : Tune Line ADC ( ? ) 48*4882a593Smuzhiyun L2LK : LO2 Lock Detect 49*4882a593Smuzhiyun TAD2 : Tune Line ADC ( ? ) 50*4882a593Smuzhiyun FMF : Estimated first IF Center frequency Offset ( ? ) 51*4882a593Smuzhiyun FM1CAL : Calibration done bit 52*4882a593Smuzhiyun TEMP : On chip temperature sensor 53*4882a593Smuzhiyun FMCG : Mixer 1 Cap Gain ( ? ) 54*4882a593Smuzhiyun GP01 / GP02 : Programmable digital outputs. Unconnected pins ? 55*4882a593Smuzhiyun V1CSE : LO1 VCO Automatic Capacitor Select Enable ( ? ) 56*4882a593Smuzhiyun V1CS : LO1 Capacitor Selection Value ( ? ) 57*4882a593Smuzhiyun LOTO : LO Timeout ( ? ) 58*4882a593Smuzhiyun VGAG : Tuner Output gain 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define I2C_ADDRESS 0x60 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define REG_PART_REV 0 64*4882a593Smuzhiyun #define REG_LO1C1 1 65*4882a593Smuzhiyun #define REG_LO1C2 2 66*4882a593Smuzhiyun #define REG_LO2C1 3 67*4882a593Smuzhiyun #define REG_LO2C2 4 68*4882a593Smuzhiyun #define REG_LO2C3 5 69*4882a593Smuzhiyun #define REG_LO_STATUS 6 70*4882a593Smuzhiyun #define REG_FM_FREQ 7 71*4882a593Smuzhiyun #define REG_MISC_STAT 8 72*4882a593Smuzhiyun #define REG_MISC_CTRL 9 73*4882a593Smuzhiyun #define REG_RESERVED_A 0x0A 74*4882a593Smuzhiyun #define REG_VGAG 0x0B 75*4882a593Smuzhiyun #define REG_LO1B1 0x0C 76*4882a593Smuzhiyun #define REG_LO1B2 0x0D 77*4882a593Smuzhiyun #define REG_LOTO 0x11 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define PART_REV 0x63 // The current driver works only with PART=6 and REV=3 chips 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun struct mt2060_priv { 82*4882a593Smuzhiyun struct mt2060_config *cfg; 83*4882a593Smuzhiyun struct i2c_adapter *i2c; 84*4882a593Smuzhiyun struct i2c_client *client; 85*4882a593Smuzhiyun struct mt2060_config config; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun u8 i2c_max_regs; 88*4882a593Smuzhiyun u32 frequency; 89*4882a593Smuzhiyun u16 if1_freq; 90*4882a593Smuzhiyun u8 fmfreq; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* 93*4882a593Smuzhiyun * Use REG_MISC_CTRL register for sleep. That drops sleep power usage 94*4882a593Smuzhiyun * about 0.9W (huge!). Register bit meanings are unknown, so let it be 95*4882a593Smuzhiyun * disabled by default to avoid possible regression. Convert driver to 96*4882a593Smuzhiyun * i2c model in order to enable it. 97*4882a593Smuzhiyun */ 98*4882a593Smuzhiyun bool sleep; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #endif 102