xref: /OK3568_Linux_fs/kernel/drivers/media/tuners/mt2060.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  Driver for Microtune MT2060 "Single chip dual conversion broadband tuner"
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Copyright (c) 2006 Olivier DANET <odanet@caramail.com>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun /* In that file, frequencies are expressed in kiloHertz to avoid 32 bits overflows */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/dvb/frontend.h>
13*4882a593Smuzhiyun #include <linux/i2c.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include <media/dvb_frontend.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include "mt2060.h"
19*4882a593Smuzhiyun #include "mt2060_priv.h"
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun static int debug;
22*4882a593Smuzhiyun module_param(debug, int, 0644);
23*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #define dprintk(args...) do { if (debug) {printk(KERN_DEBUG "MT2060: " args); printk("\n"); }} while (0)
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun // Reads a single register
mt2060_readreg(struct mt2060_priv * priv,u8 reg,u8 * val)28*4882a593Smuzhiyun static int mt2060_readreg(struct mt2060_priv *priv, u8 reg, u8 *val)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun 	struct i2c_msg msg[2] = {
31*4882a593Smuzhiyun 		{ .addr = priv->cfg->i2c_address, .flags = 0, .len = 1 },
32*4882a593Smuzhiyun 		{ .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, .len = 1 },
33*4882a593Smuzhiyun 	};
34*4882a593Smuzhiyun 	int rc = 0;
35*4882a593Smuzhiyun 	u8 *b;
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun 	b = kmalloc(2, GFP_KERNEL);
38*4882a593Smuzhiyun 	if (!b)
39*4882a593Smuzhiyun 		return -ENOMEM;
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun 	b[0] = reg;
42*4882a593Smuzhiyun 	b[1] = 0;
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun 	msg[0].buf = b;
45*4882a593Smuzhiyun 	msg[1].buf = b + 1;
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun 	if (i2c_transfer(priv->i2c, msg, 2) != 2) {
48*4882a593Smuzhiyun 		printk(KERN_WARNING "mt2060 I2C read failed\n");
49*4882a593Smuzhiyun 		rc = -EREMOTEIO;
50*4882a593Smuzhiyun 	}
51*4882a593Smuzhiyun 	*val = b[1];
52*4882a593Smuzhiyun 	kfree(b);
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	return rc;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun // Writes a single register
mt2060_writereg(struct mt2060_priv * priv,u8 reg,u8 val)58*4882a593Smuzhiyun static int mt2060_writereg(struct mt2060_priv *priv, u8 reg, u8 val)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun 	struct i2c_msg msg = {
61*4882a593Smuzhiyun 		.addr = priv->cfg->i2c_address, .flags = 0, .len = 2
62*4882a593Smuzhiyun 	};
63*4882a593Smuzhiyun 	u8 *buf;
64*4882a593Smuzhiyun 	int rc = 0;
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	buf = kmalloc(2, GFP_KERNEL);
67*4882a593Smuzhiyun 	if (!buf)
68*4882a593Smuzhiyun 		return -ENOMEM;
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	buf[0] = reg;
71*4882a593Smuzhiyun 	buf[1] = val;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	msg.buf = buf;
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
76*4882a593Smuzhiyun 		printk(KERN_WARNING "mt2060 I2C write failed\n");
77*4882a593Smuzhiyun 		rc = -EREMOTEIO;
78*4882a593Smuzhiyun 	}
79*4882a593Smuzhiyun 	kfree(buf);
80*4882a593Smuzhiyun 	return rc;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun // Writes a set of consecutive registers
mt2060_writeregs(struct mt2060_priv * priv,u8 * buf,u8 len)84*4882a593Smuzhiyun static int mt2060_writeregs(struct mt2060_priv *priv,u8 *buf, u8 len)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun 	int rem, val_len;
87*4882a593Smuzhiyun 	u8 *xfer_buf;
88*4882a593Smuzhiyun 	int rc = 0;
89*4882a593Smuzhiyun 	struct i2c_msg msg = {
90*4882a593Smuzhiyun 		.addr = priv->cfg->i2c_address, .flags = 0
91*4882a593Smuzhiyun 	};
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	xfer_buf = kmalloc(16, GFP_KERNEL);
94*4882a593Smuzhiyun 	if (!xfer_buf)
95*4882a593Smuzhiyun 		return -ENOMEM;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	msg.buf = xfer_buf;
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	for (rem = len - 1; rem > 0; rem -= priv->i2c_max_regs) {
100*4882a593Smuzhiyun 		val_len = min_t(int, rem, priv->i2c_max_regs);
101*4882a593Smuzhiyun 		msg.len = 1 + val_len;
102*4882a593Smuzhiyun 		xfer_buf[0] = buf[0] + len - 1 - rem;
103*4882a593Smuzhiyun 		memcpy(&xfer_buf[1], &buf[1 + len - 1 - rem], val_len);
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 		if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
106*4882a593Smuzhiyun 			printk(KERN_WARNING "mt2060 I2C write failed (len=%i)\n", val_len);
107*4882a593Smuzhiyun 			rc = -EREMOTEIO;
108*4882a593Smuzhiyun 			break;
109*4882a593Smuzhiyun 		}
110*4882a593Smuzhiyun 	}
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	kfree(xfer_buf);
113*4882a593Smuzhiyun 	return rc;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun // Initialisation sequences
117*4882a593Smuzhiyun // LNABAND=3, NUM1=0x3C, DIV1=0x74, NUM2=0x1080, DIV2=0x49
118*4882a593Smuzhiyun static u8 mt2060_config1[] = {
119*4882a593Smuzhiyun 	REG_LO1C1,
120*4882a593Smuzhiyun 	0x3F,	0x74,	0x00,	0x08,	0x93
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun // FMCG=2, GP2=0, GP1=0
124*4882a593Smuzhiyun static u8 mt2060_config2[] = {
125*4882a593Smuzhiyun 	REG_MISC_CTRL,
126*4882a593Smuzhiyun 	0x20,	0x1E,	0x30,	0xff,	0x80,	0xff,	0x00,	0x2c,	0x42
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun //  VGAG=3, V1CSE=1
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun #ifdef  MT2060_SPURCHECK
132*4882a593Smuzhiyun /* The function below calculates the frequency offset between the output frequency if2
133*4882a593Smuzhiyun  and the closer cross modulation subcarrier between lo1 and lo2 up to the tenth harmonic */
mt2060_spurcalc(u32 lo1,u32 lo2,u32 if2)134*4882a593Smuzhiyun static int mt2060_spurcalc(u32 lo1,u32 lo2,u32 if2)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun 	int I,J;
137*4882a593Smuzhiyun 	int dia,diamin,diff;
138*4882a593Smuzhiyun 	diamin=1000000;
139*4882a593Smuzhiyun 	for (I = 1; I < 10; I++) {
140*4882a593Smuzhiyun 		J = ((2*I*lo1)/lo2+1)/2;
141*4882a593Smuzhiyun 		diff = I*(int)lo1-J*(int)lo2;
142*4882a593Smuzhiyun 		if (diff < 0) diff=-diff;
143*4882a593Smuzhiyun 		dia = (diff-(int)if2);
144*4882a593Smuzhiyun 		if (dia < 0) dia=-dia;
145*4882a593Smuzhiyun 		if (diamin > dia) diamin=dia;
146*4882a593Smuzhiyun 	}
147*4882a593Smuzhiyun 	return diamin;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun #define BANDWIDTH 4000 // kHz
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun /* Calculates the frequency offset to add to avoid spurs. Returns 0 if no offset is needed */
mt2060_spurcheck(u32 lo1,u32 lo2,u32 if2)153*4882a593Smuzhiyun static int mt2060_spurcheck(u32 lo1,u32 lo2,u32 if2)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun 	u32 Spur,Sp1,Sp2;
156*4882a593Smuzhiyun 	int I,J;
157*4882a593Smuzhiyun 	I=0;
158*4882a593Smuzhiyun 	J=1000;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	Spur=mt2060_spurcalc(lo1,lo2,if2);
161*4882a593Smuzhiyun 	if (Spur < BANDWIDTH) {
162*4882a593Smuzhiyun 		/* Potential spurs detected */
163*4882a593Smuzhiyun 		dprintk("Spurs before : f_lo1: %d  f_lo2: %d  (kHz)",
164*4882a593Smuzhiyun 			(int)lo1,(int)lo2);
165*4882a593Smuzhiyun 		I=1000;
166*4882a593Smuzhiyun 		Sp1 = mt2060_spurcalc(lo1+I,lo2+I,if2);
167*4882a593Smuzhiyun 		Sp2 = mt2060_spurcalc(lo1-I,lo2-I,if2);
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 		if (Sp1 < Sp2) {
170*4882a593Smuzhiyun 			J=-J; I=-I; Spur=Sp2;
171*4882a593Smuzhiyun 		} else
172*4882a593Smuzhiyun 			Spur=Sp1;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 		while (Spur < BANDWIDTH) {
175*4882a593Smuzhiyun 			I += J;
176*4882a593Smuzhiyun 			Spur = mt2060_spurcalc(lo1+I,lo2+I,if2);
177*4882a593Smuzhiyun 		}
178*4882a593Smuzhiyun 		dprintk("Spurs after  : f_lo1: %d  f_lo2: %d  (kHz)",
179*4882a593Smuzhiyun 			(int)(lo1+I),(int)(lo2+I));
180*4882a593Smuzhiyun 	}
181*4882a593Smuzhiyun 	return I;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun #endif
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun #define IF2  36150       // IF2 frequency = 36.150 MHz
186*4882a593Smuzhiyun #define FREF 16000       // Quartz oscillator 16 MHz
187*4882a593Smuzhiyun 
mt2060_set_params(struct dvb_frontend * fe)188*4882a593Smuzhiyun static int mt2060_set_params(struct dvb_frontend *fe)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
191*4882a593Smuzhiyun 	struct mt2060_priv *priv;
192*4882a593Smuzhiyun 	int i=0;
193*4882a593Smuzhiyun 	u32 freq;
194*4882a593Smuzhiyun 	u8  lnaband;
195*4882a593Smuzhiyun 	u32 f_lo1,f_lo2;
196*4882a593Smuzhiyun 	u32 div1,num1,div2,num2;
197*4882a593Smuzhiyun 	u8  b[8];
198*4882a593Smuzhiyun 	u32 if1;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	priv = fe->tuner_priv;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	if1 = priv->if1_freq;
203*4882a593Smuzhiyun 	b[0] = REG_LO1B1;
204*4882a593Smuzhiyun 	b[1] = 0xFF;
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	if (fe->ops.i2c_gate_ctrl)
207*4882a593Smuzhiyun 		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	mt2060_writeregs(priv,b,2);
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	freq = c->frequency / 1000; /* Hz -> kHz */
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	f_lo1 = freq + if1 * 1000;
214*4882a593Smuzhiyun 	f_lo1 = (f_lo1 / 250) * 250;
215*4882a593Smuzhiyun 	f_lo2 = f_lo1 - freq - IF2;
216*4882a593Smuzhiyun 	// From the Comtech datasheet, the step used is 50kHz. The tuner chip could be more precise
217*4882a593Smuzhiyun 	f_lo2 = ((f_lo2 + 25) / 50) * 50;
218*4882a593Smuzhiyun 	priv->frequency =  (f_lo1 - f_lo2 - IF2) * 1000,
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun #ifdef MT2060_SPURCHECK
221*4882a593Smuzhiyun 	// LO-related spurs detection and correction
222*4882a593Smuzhiyun 	num1   = mt2060_spurcheck(f_lo1,f_lo2,IF2);
223*4882a593Smuzhiyun 	f_lo1 += num1;
224*4882a593Smuzhiyun 	f_lo2 += num1;
225*4882a593Smuzhiyun #endif
226*4882a593Smuzhiyun 	//Frequency LO1 = 16MHz * (DIV1 + NUM1/64 )
227*4882a593Smuzhiyun 	num1 = f_lo1 / (FREF / 64);
228*4882a593Smuzhiyun 	div1 = num1 / 64;
229*4882a593Smuzhiyun 	num1 &= 0x3f;
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	// Frequency LO2 = 16MHz * (DIV2 + NUM2/8192 )
232*4882a593Smuzhiyun 	num2 = f_lo2 * 64 / (FREF / 128);
233*4882a593Smuzhiyun 	div2 = num2 / 8192;
234*4882a593Smuzhiyun 	num2 &= 0x1fff;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	if (freq <=  95000) lnaband = 0xB0; else
237*4882a593Smuzhiyun 	if (freq <= 180000) lnaband = 0xA0; else
238*4882a593Smuzhiyun 	if (freq <= 260000) lnaband = 0x90; else
239*4882a593Smuzhiyun 	if (freq <= 335000) lnaband = 0x80; else
240*4882a593Smuzhiyun 	if (freq <= 425000) lnaband = 0x70; else
241*4882a593Smuzhiyun 	if (freq <= 480000) lnaband = 0x60; else
242*4882a593Smuzhiyun 	if (freq <= 570000) lnaband = 0x50; else
243*4882a593Smuzhiyun 	if (freq <= 645000) lnaband = 0x40; else
244*4882a593Smuzhiyun 	if (freq <= 730000) lnaband = 0x30; else
245*4882a593Smuzhiyun 	if (freq <= 810000) lnaband = 0x20; else lnaband = 0x10;
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	b[0] = REG_LO1C1;
248*4882a593Smuzhiyun 	b[1] = lnaband | ((num1 >>2) & 0x0F);
249*4882a593Smuzhiyun 	b[2] = div1;
250*4882a593Smuzhiyun 	b[3] = (num2 & 0x0F)  | ((num1 & 3) << 4);
251*4882a593Smuzhiyun 	b[4] = num2 >> 4;
252*4882a593Smuzhiyun 	b[5] = ((num2 >>12) & 1) | (div2 << 1);
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	dprintk("IF1: %dMHz",(int)if1);
255*4882a593Smuzhiyun 	dprintk("PLL freq=%dkHz  f_lo1=%dkHz  f_lo2=%dkHz",(int)freq,(int)f_lo1,(int)f_lo2);
256*4882a593Smuzhiyun 	dprintk("PLL div1=%d  num1=%d  div2=%d  num2=%d",(int)div1,(int)num1,(int)div2,(int)num2);
257*4882a593Smuzhiyun 	dprintk("PLL [1..5]: %2x %2x %2x %2x %2x",(int)b[1],(int)b[2],(int)b[3],(int)b[4],(int)b[5]);
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	mt2060_writeregs(priv,b,6);
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	//Waits for pll lock or timeout
262*4882a593Smuzhiyun 	i = 0;
263*4882a593Smuzhiyun 	do {
264*4882a593Smuzhiyun 		mt2060_readreg(priv,REG_LO_STATUS,b);
265*4882a593Smuzhiyun 		if ((b[0] & 0x88)==0x88)
266*4882a593Smuzhiyun 			break;
267*4882a593Smuzhiyun 		msleep(4);
268*4882a593Smuzhiyun 		i++;
269*4882a593Smuzhiyun 	} while (i<10);
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	if (fe->ops.i2c_gate_ctrl)
272*4882a593Smuzhiyun 		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	return 0;
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun 
mt2060_calibrate(struct mt2060_priv * priv)277*4882a593Smuzhiyun static void mt2060_calibrate(struct mt2060_priv *priv)
278*4882a593Smuzhiyun {
279*4882a593Smuzhiyun 	u8 b = 0;
280*4882a593Smuzhiyun 	int i = 0;
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 	if (mt2060_writeregs(priv,mt2060_config1,sizeof(mt2060_config1)))
283*4882a593Smuzhiyun 		return;
284*4882a593Smuzhiyun 	if (mt2060_writeregs(priv,mt2060_config2,sizeof(mt2060_config2)))
285*4882a593Smuzhiyun 		return;
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	/* initialize the clock output */
288*4882a593Smuzhiyun 	mt2060_writereg(priv, REG_VGAG, (priv->cfg->clock_out << 6) | 0x30);
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	do {
291*4882a593Smuzhiyun 		b |= (1 << 6); // FM1SS;
292*4882a593Smuzhiyun 		mt2060_writereg(priv, REG_LO2C1,b);
293*4882a593Smuzhiyun 		msleep(20);
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 		if (i == 0) {
296*4882a593Smuzhiyun 			b |= (1 << 7); // FM1CA;
297*4882a593Smuzhiyun 			mt2060_writereg(priv, REG_LO2C1,b);
298*4882a593Smuzhiyun 			b &= ~(1 << 7); // FM1CA;
299*4882a593Smuzhiyun 			msleep(20);
300*4882a593Smuzhiyun 		}
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 		b &= ~(1 << 6); // FM1SS
303*4882a593Smuzhiyun 		mt2060_writereg(priv, REG_LO2C1,b);
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 		msleep(20);
306*4882a593Smuzhiyun 		i++;
307*4882a593Smuzhiyun 	} while (i < 9);
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	i = 0;
310*4882a593Smuzhiyun 	while (i++ < 10 && mt2060_readreg(priv, REG_MISC_STAT, &b) == 0 && (b & (1 << 6)) == 0)
311*4882a593Smuzhiyun 		msleep(20);
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	if (i <= 10) {
314*4882a593Smuzhiyun 		mt2060_readreg(priv, REG_FM_FREQ, &priv->fmfreq); // now find out, what is fmreq used for :)
315*4882a593Smuzhiyun 		dprintk("calibration was successful: %d", (int)priv->fmfreq);
316*4882a593Smuzhiyun 	} else
317*4882a593Smuzhiyun 		dprintk("FMCAL timed out");
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun 
mt2060_get_frequency(struct dvb_frontend * fe,u32 * frequency)320*4882a593Smuzhiyun static int mt2060_get_frequency(struct dvb_frontend *fe, u32 *frequency)
321*4882a593Smuzhiyun {
322*4882a593Smuzhiyun 	struct mt2060_priv *priv = fe->tuner_priv;
323*4882a593Smuzhiyun 	*frequency = priv->frequency;
324*4882a593Smuzhiyun 	return 0;
325*4882a593Smuzhiyun }
326*4882a593Smuzhiyun 
mt2060_get_if_frequency(struct dvb_frontend * fe,u32 * frequency)327*4882a593Smuzhiyun static int mt2060_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
328*4882a593Smuzhiyun {
329*4882a593Smuzhiyun 	*frequency = IF2 * 1000;
330*4882a593Smuzhiyun 	return 0;
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun 
mt2060_init(struct dvb_frontend * fe)333*4882a593Smuzhiyun static int mt2060_init(struct dvb_frontend *fe)
334*4882a593Smuzhiyun {
335*4882a593Smuzhiyun 	struct mt2060_priv *priv = fe->tuner_priv;
336*4882a593Smuzhiyun 	int ret;
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 	if (fe->ops.i2c_gate_ctrl)
339*4882a593Smuzhiyun 		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 	if (priv->sleep) {
342*4882a593Smuzhiyun 		ret = mt2060_writereg(priv, REG_MISC_CTRL, 0x20);
343*4882a593Smuzhiyun 		if (ret)
344*4882a593Smuzhiyun 			goto err_i2c_gate_ctrl;
345*4882a593Smuzhiyun 	}
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	ret = mt2060_writereg(priv, REG_VGAG,
348*4882a593Smuzhiyun 			      (priv->cfg->clock_out << 6) | 0x33);
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun err_i2c_gate_ctrl:
351*4882a593Smuzhiyun 	if (fe->ops.i2c_gate_ctrl)
352*4882a593Smuzhiyun 		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun 	return ret;
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun 
mt2060_sleep(struct dvb_frontend * fe)357*4882a593Smuzhiyun static int mt2060_sleep(struct dvb_frontend *fe)
358*4882a593Smuzhiyun {
359*4882a593Smuzhiyun 	struct mt2060_priv *priv = fe->tuner_priv;
360*4882a593Smuzhiyun 	int ret;
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	if (fe->ops.i2c_gate_ctrl)
363*4882a593Smuzhiyun 		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	ret = mt2060_writereg(priv, REG_VGAG,
366*4882a593Smuzhiyun 			      (priv->cfg->clock_out << 6) | 0x30);
367*4882a593Smuzhiyun 	if (ret)
368*4882a593Smuzhiyun 		goto err_i2c_gate_ctrl;
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun 	if (priv->sleep)
371*4882a593Smuzhiyun 		ret = mt2060_writereg(priv, REG_MISC_CTRL, 0xe8);
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun err_i2c_gate_ctrl:
374*4882a593Smuzhiyun 	if (fe->ops.i2c_gate_ctrl)
375*4882a593Smuzhiyun 		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 	return ret;
378*4882a593Smuzhiyun }
379*4882a593Smuzhiyun 
mt2060_release(struct dvb_frontend * fe)380*4882a593Smuzhiyun static void mt2060_release(struct dvb_frontend *fe)
381*4882a593Smuzhiyun {
382*4882a593Smuzhiyun 	kfree(fe->tuner_priv);
383*4882a593Smuzhiyun 	fe->tuner_priv = NULL;
384*4882a593Smuzhiyun }
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun static const struct dvb_tuner_ops mt2060_tuner_ops = {
387*4882a593Smuzhiyun 	.info = {
388*4882a593Smuzhiyun 		.name              = "Microtune MT2060",
389*4882a593Smuzhiyun 		.frequency_min_hz  =  48 * MHz,
390*4882a593Smuzhiyun 		.frequency_max_hz  = 860 * MHz,
391*4882a593Smuzhiyun 		.frequency_step_hz =  50 * kHz,
392*4882a593Smuzhiyun 	},
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	.release       = mt2060_release,
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	.init          = mt2060_init,
397*4882a593Smuzhiyun 	.sleep         = mt2060_sleep,
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun 	.set_params    = mt2060_set_params,
400*4882a593Smuzhiyun 	.get_frequency = mt2060_get_frequency,
401*4882a593Smuzhiyun 	.get_if_frequency = mt2060_get_if_frequency,
402*4882a593Smuzhiyun };
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun /* This functions tries to identify a MT2060 tuner by reading the PART/REV register. This is hasty. */
mt2060_attach(struct dvb_frontend * fe,struct i2c_adapter * i2c,struct mt2060_config * cfg,u16 if1)405*4882a593Smuzhiyun struct dvb_frontend * mt2060_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2060_config *cfg, u16 if1)
406*4882a593Smuzhiyun {
407*4882a593Smuzhiyun 	struct mt2060_priv *priv = NULL;
408*4882a593Smuzhiyun 	u8 id = 0;
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	priv = kzalloc(sizeof(struct mt2060_priv), GFP_KERNEL);
411*4882a593Smuzhiyun 	if (priv == NULL)
412*4882a593Smuzhiyun 		return NULL;
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	priv->cfg      = cfg;
415*4882a593Smuzhiyun 	priv->i2c      = i2c;
416*4882a593Smuzhiyun 	priv->if1_freq = if1;
417*4882a593Smuzhiyun 	priv->i2c_max_regs = ~0;
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	if (fe->ops.i2c_gate_ctrl)
420*4882a593Smuzhiyun 		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 	if (mt2060_readreg(priv,REG_PART_REV,&id) != 0) {
423*4882a593Smuzhiyun 		kfree(priv);
424*4882a593Smuzhiyun 		return NULL;
425*4882a593Smuzhiyun 	}
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun 	if (id != PART_REV) {
428*4882a593Smuzhiyun 		kfree(priv);
429*4882a593Smuzhiyun 		return NULL;
430*4882a593Smuzhiyun 	}
431*4882a593Smuzhiyun 	printk(KERN_INFO "MT2060: successfully identified (IF1 = %d)\n", if1);
432*4882a593Smuzhiyun 	memcpy(&fe->ops.tuner_ops, &mt2060_tuner_ops, sizeof(struct dvb_tuner_ops));
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	fe->tuner_priv = priv;
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 	mt2060_calibrate(priv);
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun 	if (fe->ops.i2c_gate_ctrl)
439*4882a593Smuzhiyun 		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun 	return fe;
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun EXPORT_SYMBOL(mt2060_attach);
444*4882a593Smuzhiyun 
mt2060_probe(struct i2c_client * client,const struct i2c_device_id * id)445*4882a593Smuzhiyun static int mt2060_probe(struct i2c_client *client,
446*4882a593Smuzhiyun 			const struct i2c_device_id *id)
447*4882a593Smuzhiyun {
448*4882a593Smuzhiyun 	struct mt2060_platform_data *pdata = client->dev.platform_data;
449*4882a593Smuzhiyun 	struct dvb_frontend *fe;
450*4882a593Smuzhiyun 	struct mt2060_priv *dev;
451*4882a593Smuzhiyun 	int ret;
452*4882a593Smuzhiyun 	u8 chip_id;
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun 	dev_dbg(&client->dev, "\n");
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	if (!pdata) {
457*4882a593Smuzhiyun 		dev_err(&client->dev, "Cannot proceed without platform data\n");
458*4882a593Smuzhiyun 		ret = -EINVAL;
459*4882a593Smuzhiyun 		goto err;
460*4882a593Smuzhiyun 	}
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 	dev = devm_kzalloc(&client->dev, sizeof(*dev), GFP_KERNEL);
463*4882a593Smuzhiyun 	if (!dev) {
464*4882a593Smuzhiyun 		ret = -ENOMEM;
465*4882a593Smuzhiyun 		goto err;
466*4882a593Smuzhiyun 	}
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun 	fe = pdata->dvb_frontend;
469*4882a593Smuzhiyun 	dev->config.i2c_address = client->addr;
470*4882a593Smuzhiyun 	dev->config.clock_out = pdata->clock_out;
471*4882a593Smuzhiyun 	dev->cfg = &dev->config;
472*4882a593Smuzhiyun 	dev->i2c = client->adapter;
473*4882a593Smuzhiyun 	dev->if1_freq = pdata->if1 ? pdata->if1 : 1220;
474*4882a593Smuzhiyun 	dev->client = client;
475*4882a593Smuzhiyun 	dev->i2c_max_regs = pdata->i2c_write_max ? pdata->i2c_write_max - 1 : ~0;
476*4882a593Smuzhiyun 	dev->sleep = true;
477*4882a593Smuzhiyun 
478*4882a593Smuzhiyun 	ret = mt2060_readreg(dev, REG_PART_REV, &chip_id);
479*4882a593Smuzhiyun 	if (ret) {
480*4882a593Smuzhiyun 		ret = -ENODEV;
481*4882a593Smuzhiyun 		goto err;
482*4882a593Smuzhiyun 	}
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun 	dev_dbg(&client->dev, "chip id=%02x\n", chip_id);
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 	if (chip_id != PART_REV) {
487*4882a593Smuzhiyun 		ret = -ENODEV;
488*4882a593Smuzhiyun 		goto err;
489*4882a593Smuzhiyun 	}
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun 	/* Power on, calibrate, sleep */
492*4882a593Smuzhiyun 	ret = mt2060_writereg(dev, REG_MISC_CTRL, 0x20);
493*4882a593Smuzhiyun 	if (ret)
494*4882a593Smuzhiyun 		goto err;
495*4882a593Smuzhiyun 	mt2060_calibrate(dev);
496*4882a593Smuzhiyun 	ret = mt2060_writereg(dev, REG_MISC_CTRL, 0xe8);
497*4882a593Smuzhiyun 	if (ret)
498*4882a593Smuzhiyun 		goto err;
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun 	dev_info(&client->dev, "Microtune MT2060 successfully identified\n");
501*4882a593Smuzhiyun 	memcpy(&fe->ops.tuner_ops, &mt2060_tuner_ops, sizeof(fe->ops.tuner_ops));
502*4882a593Smuzhiyun 	fe->ops.tuner_ops.release = NULL;
503*4882a593Smuzhiyun 	fe->tuner_priv = dev;
504*4882a593Smuzhiyun 	i2c_set_clientdata(client, dev);
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun 	return 0;
507*4882a593Smuzhiyun err:
508*4882a593Smuzhiyun 	dev_dbg(&client->dev, "failed=%d\n", ret);
509*4882a593Smuzhiyun 	return ret;
510*4882a593Smuzhiyun }
511*4882a593Smuzhiyun 
mt2060_remove(struct i2c_client * client)512*4882a593Smuzhiyun static int mt2060_remove(struct i2c_client *client)
513*4882a593Smuzhiyun {
514*4882a593Smuzhiyun 	dev_dbg(&client->dev, "\n");
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun 	return 0;
517*4882a593Smuzhiyun }
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun static const struct i2c_device_id mt2060_id_table[] = {
520*4882a593Smuzhiyun 	{"mt2060", 0},
521*4882a593Smuzhiyun 	{}
522*4882a593Smuzhiyun };
523*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, mt2060_id_table);
524*4882a593Smuzhiyun 
525*4882a593Smuzhiyun static struct i2c_driver mt2060_driver = {
526*4882a593Smuzhiyun 	.driver = {
527*4882a593Smuzhiyun 		.name = "mt2060",
528*4882a593Smuzhiyun 		.suppress_bind_attrs = true,
529*4882a593Smuzhiyun 	},
530*4882a593Smuzhiyun 	.probe		= mt2060_probe,
531*4882a593Smuzhiyun 	.remove		= mt2060_remove,
532*4882a593Smuzhiyun 	.id_table	= mt2060_id_table,
533*4882a593Smuzhiyun };
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun module_i2c_driver(mt2060_driver);
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun MODULE_AUTHOR("Olivier DANET");
538*4882a593Smuzhiyun MODULE_DESCRIPTION("Microtune MT2060 silicon tuner driver");
539*4882a593Smuzhiyun MODULE_LICENSE("GPL");
540