xref: /OK3568_Linux_fs/kernel/drivers/media/tuners/msi001.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Mirics MSi001 silicon tuner driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
6*4882a593Smuzhiyun  * Copyright (C) 2014 Antti Palosaari <crope@iki.fi>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/gcd.h>
11*4882a593Smuzhiyun #include <media/v4l2-device.h>
12*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun static const struct v4l2_frequency_band bands[] = {
15*4882a593Smuzhiyun 	{
16*4882a593Smuzhiyun 		.type = V4L2_TUNER_RF,
17*4882a593Smuzhiyun 		.index = 0,
18*4882a593Smuzhiyun 		.capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
19*4882a593Smuzhiyun 		.rangelow   =   49000000,
20*4882a593Smuzhiyun 		.rangehigh  =  263000000,
21*4882a593Smuzhiyun 	}, {
22*4882a593Smuzhiyun 		.type = V4L2_TUNER_RF,
23*4882a593Smuzhiyun 		.index = 1,
24*4882a593Smuzhiyun 		.capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
25*4882a593Smuzhiyun 		.rangelow   =  390000000,
26*4882a593Smuzhiyun 		.rangehigh  =  960000000,
27*4882a593Smuzhiyun 	},
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun struct msi001_dev {
31*4882a593Smuzhiyun 	struct spi_device *spi;
32*4882a593Smuzhiyun 	struct v4l2_subdev sd;
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun 	/* Controls */
35*4882a593Smuzhiyun 	struct v4l2_ctrl_handler hdl;
36*4882a593Smuzhiyun 	struct v4l2_ctrl *bandwidth_auto;
37*4882a593Smuzhiyun 	struct v4l2_ctrl *bandwidth;
38*4882a593Smuzhiyun 	struct v4l2_ctrl *lna_gain;
39*4882a593Smuzhiyun 	struct v4l2_ctrl *mixer_gain;
40*4882a593Smuzhiyun 	struct v4l2_ctrl *if_gain;
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 	unsigned int f_tuner;
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun 
sd_to_msi001_dev(struct v4l2_subdev * sd)45*4882a593Smuzhiyun static inline struct msi001_dev *sd_to_msi001_dev(struct v4l2_subdev *sd)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun 	return container_of(sd, struct msi001_dev, sd);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun 
msi001_wreg(struct msi001_dev * dev,u32 data)50*4882a593Smuzhiyun static int msi001_wreg(struct msi001_dev *dev, u32 data)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun 	/* Register format: 4 bits addr + 20 bits value */
53*4882a593Smuzhiyun 	return spi_write(dev->spi, &data, 3);
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun 
msi001_set_gain(struct msi001_dev * dev,int lna_gain,int mixer_gain,int if_gain)56*4882a593Smuzhiyun static int msi001_set_gain(struct msi001_dev *dev, int lna_gain, int mixer_gain,
57*4882a593Smuzhiyun 			   int if_gain)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun 	struct spi_device *spi = dev->spi;
60*4882a593Smuzhiyun 	int ret;
61*4882a593Smuzhiyun 	u32 reg;
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	dev_dbg(&spi->dev, "lna=%d mixer=%d if=%d\n",
64*4882a593Smuzhiyun 		lna_gain, mixer_gain, if_gain);
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	reg = 1 << 0;
67*4882a593Smuzhiyun 	reg |= (59 - if_gain) << 4;
68*4882a593Smuzhiyun 	reg |= 0 << 10;
69*4882a593Smuzhiyun 	reg |= (1 - mixer_gain) << 12;
70*4882a593Smuzhiyun 	reg |= (1 - lna_gain) << 13;
71*4882a593Smuzhiyun 	reg |= 4 << 14;
72*4882a593Smuzhiyun 	reg |= 0 << 17;
73*4882a593Smuzhiyun 	ret = msi001_wreg(dev, reg);
74*4882a593Smuzhiyun 	if (ret)
75*4882a593Smuzhiyun 		goto err;
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	return 0;
78*4882a593Smuzhiyun err:
79*4882a593Smuzhiyun 	dev_dbg(&spi->dev, "failed %d\n", ret);
80*4882a593Smuzhiyun 	return ret;
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun 
msi001_set_tuner(struct msi001_dev * dev)83*4882a593Smuzhiyun static int msi001_set_tuner(struct msi001_dev *dev)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun 	struct spi_device *spi = dev->spi;
86*4882a593Smuzhiyun 	int ret, i;
87*4882a593Smuzhiyun 	unsigned int uitmp, div_n, k, k_thresh, k_frac, div_lo, f_if1;
88*4882a593Smuzhiyun 	u32 reg;
89*4882a593Smuzhiyun 	u64 f_vco;
90*4882a593Smuzhiyun 	u8 mode, filter_mode;
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	static const struct {
93*4882a593Smuzhiyun 		u32 rf;
94*4882a593Smuzhiyun 		u8 mode;
95*4882a593Smuzhiyun 		u8 div_lo;
96*4882a593Smuzhiyun 	} band_lut[] = {
97*4882a593Smuzhiyun 		{ 50000000, 0xe1, 16}, /* AM_MODE2, antenna 2 */
98*4882a593Smuzhiyun 		{108000000, 0x42, 32}, /* VHF_MODE */
99*4882a593Smuzhiyun 		{330000000, 0x44, 16}, /* B3_MODE */
100*4882a593Smuzhiyun 		{960000000, 0x48,  4}, /* B45_MODE */
101*4882a593Smuzhiyun 		{      ~0U, 0x50,  2}, /* BL_MODE */
102*4882a593Smuzhiyun 	};
103*4882a593Smuzhiyun 	static const struct {
104*4882a593Smuzhiyun 		u32 freq;
105*4882a593Smuzhiyun 		u8 filter_mode;
106*4882a593Smuzhiyun 	} if_freq_lut[] = {
107*4882a593Smuzhiyun 		{      0, 0x03}, /* Zero IF */
108*4882a593Smuzhiyun 		{ 450000, 0x02}, /* 450 kHz IF */
109*4882a593Smuzhiyun 		{1620000, 0x01}, /* 1.62 MHz IF */
110*4882a593Smuzhiyun 		{2048000, 0x00}, /* 2.048 MHz IF */
111*4882a593Smuzhiyun 	};
112*4882a593Smuzhiyun 	static const struct {
113*4882a593Smuzhiyun 		u32 freq;
114*4882a593Smuzhiyun 		u8 val;
115*4882a593Smuzhiyun 	} bandwidth_lut[] = {
116*4882a593Smuzhiyun 		{ 200000, 0x00}, /* 200 kHz */
117*4882a593Smuzhiyun 		{ 300000, 0x01}, /* 300 kHz */
118*4882a593Smuzhiyun 		{ 600000, 0x02}, /* 600 kHz */
119*4882a593Smuzhiyun 		{1536000, 0x03}, /* 1.536 MHz */
120*4882a593Smuzhiyun 		{5000000, 0x04}, /* 5 MHz */
121*4882a593Smuzhiyun 		{6000000, 0x05}, /* 6 MHz */
122*4882a593Smuzhiyun 		{7000000, 0x06}, /* 7 MHz */
123*4882a593Smuzhiyun 		{8000000, 0x07}, /* 8 MHz */
124*4882a593Smuzhiyun 	};
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	unsigned int f_rf = dev->f_tuner;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	/*
129*4882a593Smuzhiyun 	 * bandwidth (Hz)
130*4882a593Smuzhiyun 	 * 200000, 300000, 600000, 1536000, 5000000, 6000000, 7000000, 8000000
131*4882a593Smuzhiyun 	 */
132*4882a593Smuzhiyun 	unsigned int bandwidth;
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	/*
135*4882a593Smuzhiyun 	 * intermediate frequency (Hz)
136*4882a593Smuzhiyun 	 * 0, 450000, 1620000, 2048000
137*4882a593Smuzhiyun 	 */
138*4882a593Smuzhiyun 	unsigned int f_if = 0;
139*4882a593Smuzhiyun 	#define F_REF 24000000
140*4882a593Smuzhiyun 	#define DIV_PRE_N 4
141*4882a593Smuzhiyun 	#define	F_VCO_STEP div_lo
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	dev_dbg(&spi->dev, "f_rf=%d f_if=%d\n", f_rf, f_if);
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(band_lut); i++) {
146*4882a593Smuzhiyun 		if (f_rf <= band_lut[i].rf) {
147*4882a593Smuzhiyun 			mode = band_lut[i].mode;
148*4882a593Smuzhiyun 			div_lo = band_lut[i].div_lo;
149*4882a593Smuzhiyun 			break;
150*4882a593Smuzhiyun 		}
151*4882a593Smuzhiyun 	}
152*4882a593Smuzhiyun 	if (i == ARRAY_SIZE(band_lut)) {
153*4882a593Smuzhiyun 		ret = -EINVAL;
154*4882a593Smuzhiyun 		goto err;
155*4882a593Smuzhiyun 	}
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	/* AM_MODE is upconverted */
158*4882a593Smuzhiyun 	if ((mode >> 0) & 0x1)
159*4882a593Smuzhiyun 		f_if1 =  5 * F_REF;
160*4882a593Smuzhiyun 	else
161*4882a593Smuzhiyun 		f_if1 =  0;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(if_freq_lut); i++) {
164*4882a593Smuzhiyun 		if (f_if == if_freq_lut[i].freq) {
165*4882a593Smuzhiyun 			filter_mode = if_freq_lut[i].filter_mode;
166*4882a593Smuzhiyun 			break;
167*4882a593Smuzhiyun 		}
168*4882a593Smuzhiyun 	}
169*4882a593Smuzhiyun 	if (i == ARRAY_SIZE(if_freq_lut)) {
170*4882a593Smuzhiyun 		ret = -EINVAL;
171*4882a593Smuzhiyun 		goto err;
172*4882a593Smuzhiyun 	}
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	/* filters */
175*4882a593Smuzhiyun 	bandwidth = dev->bandwidth->val;
176*4882a593Smuzhiyun 	bandwidth = clamp(bandwidth, 200000U, 8000000U);
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(bandwidth_lut); i++) {
179*4882a593Smuzhiyun 		if (bandwidth <= bandwidth_lut[i].freq) {
180*4882a593Smuzhiyun 			bandwidth = bandwidth_lut[i].val;
181*4882a593Smuzhiyun 			break;
182*4882a593Smuzhiyun 		}
183*4882a593Smuzhiyun 	}
184*4882a593Smuzhiyun 	if (i == ARRAY_SIZE(bandwidth_lut)) {
185*4882a593Smuzhiyun 		ret = -EINVAL;
186*4882a593Smuzhiyun 		goto err;
187*4882a593Smuzhiyun 	}
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	dev->bandwidth->val = bandwidth_lut[i].freq;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	dev_dbg(&spi->dev, "bandwidth selected=%d\n", bandwidth_lut[i].freq);
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	/*
194*4882a593Smuzhiyun 	 * Fractional-N synthesizer
195*4882a593Smuzhiyun 	 *
196*4882a593Smuzhiyun 	 *           +---------------------------------------+
197*4882a593Smuzhiyun 	 *           v                                       |
198*4882a593Smuzhiyun 	 *  Fref   +----+     +-------+         +----+     +------+     +---+
199*4882a593Smuzhiyun 	 * ------> | PD | --> |  VCO  | ------> | /4 | --> | /N.F | <-- | K |
200*4882a593Smuzhiyun 	 *         +----+     +-------+         +----+     +------+     +---+
201*4882a593Smuzhiyun 	 *                      |
202*4882a593Smuzhiyun 	 *                      |
203*4882a593Smuzhiyun 	 *                      v
204*4882a593Smuzhiyun 	 *                    +-------+  Fout
205*4882a593Smuzhiyun 	 *                    | /Rout | ------>
206*4882a593Smuzhiyun 	 *                    +-------+
207*4882a593Smuzhiyun 	 */
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	/* Calculate PLL integer and fractional control word. */
210*4882a593Smuzhiyun 	f_vco = (u64) (f_rf + f_if + f_if1) * div_lo;
211*4882a593Smuzhiyun 	div_n = div_u64_rem(f_vco, DIV_PRE_N * F_REF, &k);
212*4882a593Smuzhiyun 	k_thresh = (DIV_PRE_N * F_REF) / F_VCO_STEP;
213*4882a593Smuzhiyun 	k_frac = div_u64((u64) k * k_thresh, (DIV_PRE_N * F_REF));
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	/* Find out greatest common divisor and divide to smaller. */
216*4882a593Smuzhiyun 	uitmp = gcd(k_thresh, k_frac);
217*4882a593Smuzhiyun 	k_thresh /= uitmp;
218*4882a593Smuzhiyun 	k_frac /= uitmp;
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	/* Force divide to reg max. Resolution will be reduced. */
221*4882a593Smuzhiyun 	uitmp = DIV_ROUND_UP(k_thresh, 4095);
222*4882a593Smuzhiyun 	k_thresh = DIV_ROUND_CLOSEST(k_thresh, uitmp);
223*4882a593Smuzhiyun 	k_frac = DIV_ROUND_CLOSEST(k_frac, uitmp);
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	/* Calculate real RF set. */
226*4882a593Smuzhiyun 	uitmp = (unsigned int) F_REF * DIV_PRE_N * div_n;
227*4882a593Smuzhiyun 	uitmp += (unsigned int) F_REF * DIV_PRE_N * k_frac / k_thresh;
228*4882a593Smuzhiyun 	uitmp /= div_lo;
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 	dev_dbg(&spi->dev,
231*4882a593Smuzhiyun 		"f_rf=%u:%u f_vco=%llu div_n=%u k_thresh=%u k_frac=%u div_lo=%u\n",
232*4882a593Smuzhiyun 		f_rf, uitmp, f_vco, div_n, k_thresh, k_frac, div_lo);
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	ret = msi001_wreg(dev, 0x00000e);
235*4882a593Smuzhiyun 	if (ret)
236*4882a593Smuzhiyun 		goto err;
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	ret = msi001_wreg(dev, 0x000003);
239*4882a593Smuzhiyun 	if (ret)
240*4882a593Smuzhiyun 		goto err;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	reg = 0 << 0;
243*4882a593Smuzhiyun 	reg |= mode << 4;
244*4882a593Smuzhiyun 	reg |= filter_mode << 12;
245*4882a593Smuzhiyun 	reg |= bandwidth << 14;
246*4882a593Smuzhiyun 	reg |= 0x02 << 17;
247*4882a593Smuzhiyun 	reg |= 0x00 << 20;
248*4882a593Smuzhiyun 	ret = msi001_wreg(dev, reg);
249*4882a593Smuzhiyun 	if (ret)
250*4882a593Smuzhiyun 		goto err;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	reg = 5 << 0;
253*4882a593Smuzhiyun 	reg |= k_thresh << 4;
254*4882a593Smuzhiyun 	reg |= 1 << 19;
255*4882a593Smuzhiyun 	reg |= 1 << 21;
256*4882a593Smuzhiyun 	ret = msi001_wreg(dev, reg);
257*4882a593Smuzhiyun 	if (ret)
258*4882a593Smuzhiyun 		goto err;
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun 	reg = 2 << 0;
261*4882a593Smuzhiyun 	reg |= k_frac << 4;
262*4882a593Smuzhiyun 	reg |= div_n << 16;
263*4882a593Smuzhiyun 	ret = msi001_wreg(dev, reg);
264*4882a593Smuzhiyun 	if (ret)
265*4882a593Smuzhiyun 		goto err;
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	ret = msi001_set_gain(dev, dev->lna_gain->cur.val,
268*4882a593Smuzhiyun 			      dev->mixer_gain->cur.val, dev->if_gain->cur.val);
269*4882a593Smuzhiyun 	if (ret)
270*4882a593Smuzhiyun 		goto err;
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	reg = 6 << 0;
273*4882a593Smuzhiyun 	reg |= 63 << 4;
274*4882a593Smuzhiyun 	reg |= 4095 << 10;
275*4882a593Smuzhiyun 	ret = msi001_wreg(dev, reg);
276*4882a593Smuzhiyun 	if (ret)
277*4882a593Smuzhiyun 		goto err;
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	return 0;
280*4882a593Smuzhiyun err:
281*4882a593Smuzhiyun 	dev_dbg(&spi->dev, "failed %d\n", ret);
282*4882a593Smuzhiyun 	return ret;
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun 
msi001_standby(struct v4l2_subdev * sd)285*4882a593Smuzhiyun static int msi001_standby(struct v4l2_subdev *sd)
286*4882a593Smuzhiyun {
287*4882a593Smuzhiyun 	struct msi001_dev *dev = sd_to_msi001_dev(sd);
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	return msi001_wreg(dev, 0x000000);
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun 
msi001_g_tuner(struct v4l2_subdev * sd,struct v4l2_tuner * v)292*4882a593Smuzhiyun static int msi001_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *v)
293*4882a593Smuzhiyun {
294*4882a593Smuzhiyun 	struct msi001_dev *dev = sd_to_msi001_dev(sd);
295*4882a593Smuzhiyun 	struct spi_device *spi = dev->spi;
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 	dev_dbg(&spi->dev, "index=%d\n", v->index);
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun 	strscpy(v->name, "Mirics MSi001", sizeof(v->name));
300*4882a593Smuzhiyun 	v->type = V4L2_TUNER_RF;
301*4882a593Smuzhiyun 	v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
302*4882a593Smuzhiyun 	v->rangelow =    49000000;
303*4882a593Smuzhiyun 	v->rangehigh =  960000000;
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	return 0;
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun 
msi001_s_tuner(struct v4l2_subdev * sd,const struct v4l2_tuner * v)308*4882a593Smuzhiyun static int msi001_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *v)
309*4882a593Smuzhiyun {
310*4882a593Smuzhiyun 	struct msi001_dev *dev = sd_to_msi001_dev(sd);
311*4882a593Smuzhiyun 	struct spi_device *spi = dev->spi;
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	dev_dbg(&spi->dev, "index=%d\n", v->index);
314*4882a593Smuzhiyun 	return 0;
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun 
msi001_g_frequency(struct v4l2_subdev * sd,struct v4l2_frequency * f)317*4882a593Smuzhiyun static int msi001_g_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *f)
318*4882a593Smuzhiyun {
319*4882a593Smuzhiyun 	struct msi001_dev *dev = sd_to_msi001_dev(sd);
320*4882a593Smuzhiyun 	struct spi_device *spi = dev->spi;
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	dev_dbg(&spi->dev, "tuner=%d\n", f->tuner);
323*4882a593Smuzhiyun 	f->frequency = dev->f_tuner;
324*4882a593Smuzhiyun 	return 0;
325*4882a593Smuzhiyun }
326*4882a593Smuzhiyun 
msi001_s_frequency(struct v4l2_subdev * sd,const struct v4l2_frequency * f)327*4882a593Smuzhiyun static int msi001_s_frequency(struct v4l2_subdev *sd,
328*4882a593Smuzhiyun 			      const struct v4l2_frequency *f)
329*4882a593Smuzhiyun {
330*4882a593Smuzhiyun 	struct msi001_dev *dev = sd_to_msi001_dev(sd);
331*4882a593Smuzhiyun 	struct spi_device *spi = dev->spi;
332*4882a593Smuzhiyun 	unsigned int band;
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 	dev_dbg(&spi->dev, "tuner=%d type=%d frequency=%u\n",
335*4882a593Smuzhiyun 		f->tuner, f->type, f->frequency);
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	if (f->frequency < ((bands[0].rangehigh + bands[1].rangelow) / 2))
338*4882a593Smuzhiyun 		band = 0;
339*4882a593Smuzhiyun 	else
340*4882a593Smuzhiyun 		band = 1;
341*4882a593Smuzhiyun 	dev->f_tuner = clamp_t(unsigned int, f->frequency,
342*4882a593Smuzhiyun 			       bands[band].rangelow, bands[band].rangehigh);
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 	return msi001_set_tuner(dev);
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun 
msi001_enum_freq_bands(struct v4l2_subdev * sd,struct v4l2_frequency_band * band)347*4882a593Smuzhiyun static int msi001_enum_freq_bands(struct v4l2_subdev *sd,
348*4882a593Smuzhiyun 				  struct v4l2_frequency_band *band)
349*4882a593Smuzhiyun {
350*4882a593Smuzhiyun 	struct msi001_dev *dev = sd_to_msi001_dev(sd);
351*4882a593Smuzhiyun 	struct spi_device *spi = dev->spi;
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	dev_dbg(&spi->dev, "tuner=%d type=%d index=%d\n",
354*4882a593Smuzhiyun 		band->tuner, band->type, band->index);
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 	if (band->index >= ARRAY_SIZE(bands))
357*4882a593Smuzhiyun 		return -EINVAL;
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 	band->capability = bands[band->index].capability;
360*4882a593Smuzhiyun 	band->rangelow = bands[band->index].rangelow;
361*4882a593Smuzhiyun 	band->rangehigh = bands[band->index].rangehigh;
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	return 0;
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun static const struct v4l2_subdev_tuner_ops msi001_tuner_ops = {
367*4882a593Smuzhiyun 	.standby                  = msi001_standby,
368*4882a593Smuzhiyun 	.g_tuner                  = msi001_g_tuner,
369*4882a593Smuzhiyun 	.s_tuner                  = msi001_s_tuner,
370*4882a593Smuzhiyun 	.g_frequency              = msi001_g_frequency,
371*4882a593Smuzhiyun 	.s_frequency              = msi001_s_frequency,
372*4882a593Smuzhiyun 	.enum_freq_bands          = msi001_enum_freq_bands,
373*4882a593Smuzhiyun };
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun static const struct v4l2_subdev_ops msi001_ops = {
376*4882a593Smuzhiyun 	.tuner                    = &msi001_tuner_ops,
377*4882a593Smuzhiyun };
378*4882a593Smuzhiyun 
msi001_s_ctrl(struct v4l2_ctrl * ctrl)379*4882a593Smuzhiyun static int msi001_s_ctrl(struct v4l2_ctrl *ctrl)
380*4882a593Smuzhiyun {
381*4882a593Smuzhiyun 	struct msi001_dev *dev = container_of(ctrl->handler, struct msi001_dev, hdl);
382*4882a593Smuzhiyun 	struct spi_device *spi = dev->spi;
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	int ret;
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun 	dev_dbg(&spi->dev, "id=%d name=%s val=%d min=%lld max=%lld step=%lld\n",
387*4882a593Smuzhiyun 		ctrl->id, ctrl->name, ctrl->val, ctrl->minimum, ctrl->maximum,
388*4882a593Smuzhiyun 		ctrl->step);
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	switch (ctrl->id) {
391*4882a593Smuzhiyun 	case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO:
392*4882a593Smuzhiyun 	case V4L2_CID_RF_TUNER_BANDWIDTH:
393*4882a593Smuzhiyun 		ret = msi001_set_tuner(dev);
394*4882a593Smuzhiyun 		break;
395*4882a593Smuzhiyun 	case  V4L2_CID_RF_TUNER_LNA_GAIN:
396*4882a593Smuzhiyun 		ret = msi001_set_gain(dev, dev->lna_gain->val,
397*4882a593Smuzhiyun 				      dev->mixer_gain->cur.val,
398*4882a593Smuzhiyun 				      dev->if_gain->cur.val);
399*4882a593Smuzhiyun 		break;
400*4882a593Smuzhiyun 	case  V4L2_CID_RF_TUNER_MIXER_GAIN:
401*4882a593Smuzhiyun 		ret = msi001_set_gain(dev, dev->lna_gain->cur.val,
402*4882a593Smuzhiyun 				      dev->mixer_gain->val,
403*4882a593Smuzhiyun 				      dev->if_gain->cur.val);
404*4882a593Smuzhiyun 		break;
405*4882a593Smuzhiyun 	case  V4L2_CID_RF_TUNER_IF_GAIN:
406*4882a593Smuzhiyun 		ret = msi001_set_gain(dev, dev->lna_gain->cur.val,
407*4882a593Smuzhiyun 				      dev->mixer_gain->cur.val,
408*4882a593Smuzhiyun 				      dev->if_gain->val);
409*4882a593Smuzhiyun 		break;
410*4882a593Smuzhiyun 	default:
411*4882a593Smuzhiyun 		dev_dbg(&spi->dev, "unknown control %d\n", ctrl->id);
412*4882a593Smuzhiyun 		ret = -EINVAL;
413*4882a593Smuzhiyun 	}
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	return ret;
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun 
418*4882a593Smuzhiyun static const struct v4l2_ctrl_ops msi001_ctrl_ops = {
419*4882a593Smuzhiyun 	.s_ctrl                   = msi001_s_ctrl,
420*4882a593Smuzhiyun };
421*4882a593Smuzhiyun 
msi001_probe(struct spi_device * spi)422*4882a593Smuzhiyun static int msi001_probe(struct spi_device *spi)
423*4882a593Smuzhiyun {
424*4882a593Smuzhiyun 	struct msi001_dev *dev;
425*4882a593Smuzhiyun 	int ret;
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun 	dev_dbg(&spi->dev, "\n");
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
430*4882a593Smuzhiyun 	if (!dev) {
431*4882a593Smuzhiyun 		ret = -ENOMEM;
432*4882a593Smuzhiyun 		goto err;
433*4882a593Smuzhiyun 	}
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 	dev->spi = spi;
436*4882a593Smuzhiyun 	dev->f_tuner = bands[0].rangelow;
437*4882a593Smuzhiyun 	v4l2_spi_subdev_init(&dev->sd, spi, &msi001_ops);
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun 	/* Register controls */
440*4882a593Smuzhiyun 	v4l2_ctrl_handler_init(&dev->hdl, 5);
441*4882a593Smuzhiyun 	dev->bandwidth_auto = v4l2_ctrl_new_std(&dev->hdl, &msi001_ctrl_ops,
442*4882a593Smuzhiyun 			V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1);
443*4882a593Smuzhiyun 	dev->bandwidth = v4l2_ctrl_new_std(&dev->hdl, &msi001_ctrl_ops,
444*4882a593Smuzhiyun 			V4L2_CID_RF_TUNER_BANDWIDTH, 200000, 8000000, 1, 200000);
445*4882a593Smuzhiyun 	if (dev->hdl.error) {
446*4882a593Smuzhiyun 		ret = dev->hdl.error;
447*4882a593Smuzhiyun 		dev_err(&spi->dev, "Could not initialize controls\n");
448*4882a593Smuzhiyun 		/* control init failed, free handler */
449*4882a593Smuzhiyun 		goto err_ctrl_handler_free;
450*4882a593Smuzhiyun 	}
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun 	v4l2_ctrl_auto_cluster(2, &dev->bandwidth_auto, 0, false);
453*4882a593Smuzhiyun 	dev->lna_gain = v4l2_ctrl_new_std(&dev->hdl, &msi001_ctrl_ops,
454*4882a593Smuzhiyun 			V4L2_CID_RF_TUNER_LNA_GAIN, 0, 1, 1, 1);
455*4882a593Smuzhiyun 	dev->mixer_gain = v4l2_ctrl_new_std(&dev->hdl, &msi001_ctrl_ops,
456*4882a593Smuzhiyun 			V4L2_CID_RF_TUNER_MIXER_GAIN, 0, 1, 1, 1);
457*4882a593Smuzhiyun 	dev->if_gain = v4l2_ctrl_new_std(&dev->hdl, &msi001_ctrl_ops,
458*4882a593Smuzhiyun 			V4L2_CID_RF_TUNER_IF_GAIN, 0, 59, 1, 0);
459*4882a593Smuzhiyun 	if (dev->hdl.error) {
460*4882a593Smuzhiyun 		ret = dev->hdl.error;
461*4882a593Smuzhiyun 		dev_err(&spi->dev, "Could not initialize controls\n");
462*4882a593Smuzhiyun 		/* control init failed, free handler */
463*4882a593Smuzhiyun 		goto err_ctrl_handler_free;
464*4882a593Smuzhiyun 	}
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun 	dev->sd.ctrl_handler = &dev->hdl;
467*4882a593Smuzhiyun 	return 0;
468*4882a593Smuzhiyun err_ctrl_handler_free:
469*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&dev->hdl);
470*4882a593Smuzhiyun 	kfree(dev);
471*4882a593Smuzhiyun err:
472*4882a593Smuzhiyun 	return ret;
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun 
msi001_remove(struct spi_device * spi)475*4882a593Smuzhiyun static int msi001_remove(struct spi_device *spi)
476*4882a593Smuzhiyun {
477*4882a593Smuzhiyun 	struct v4l2_subdev *sd = spi_get_drvdata(spi);
478*4882a593Smuzhiyun 	struct msi001_dev *dev = sd_to_msi001_dev(sd);
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	dev_dbg(&spi->dev, "\n");
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun 	/*
483*4882a593Smuzhiyun 	 * Registered by v4l2_spi_new_subdev() from master driver, but we must
484*4882a593Smuzhiyun 	 * unregister it from here. Weird.
485*4882a593Smuzhiyun 	 */
486*4882a593Smuzhiyun 	v4l2_device_unregister_subdev(&dev->sd);
487*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&dev->hdl);
488*4882a593Smuzhiyun 	kfree(dev);
489*4882a593Smuzhiyun 	return 0;
490*4882a593Smuzhiyun }
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun static const struct spi_device_id msi001_id_table[] = {
493*4882a593Smuzhiyun 	{"msi001", 0},
494*4882a593Smuzhiyun 	{}
495*4882a593Smuzhiyun };
496*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, msi001_id_table);
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun static struct spi_driver msi001_driver = {
499*4882a593Smuzhiyun 	.driver = {
500*4882a593Smuzhiyun 		.name	= "msi001",
501*4882a593Smuzhiyun 		.suppress_bind_attrs = true,
502*4882a593Smuzhiyun 	},
503*4882a593Smuzhiyun 	.probe		= msi001_probe,
504*4882a593Smuzhiyun 	.remove		= msi001_remove,
505*4882a593Smuzhiyun 	.id_table	= msi001_id_table,
506*4882a593Smuzhiyun };
507*4882a593Smuzhiyun module_spi_driver(msi001_driver);
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
510*4882a593Smuzhiyun MODULE_DESCRIPTION("Mirics MSi001");
511*4882a593Smuzhiyun MODULE_LICENSE("GPL");
512