1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Driver for Freescale MC44S803 Low Power CMOS Broadband Tuner 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2009 Jochen Friedrich <jochen@scram.de> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef MC44S803_PRIV_H 9*4882a593Smuzhiyun #define MC44S803_PRIV_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* This driver is based on the information available in the datasheet 12*4882a593Smuzhiyun http://www.freescale.com/files/rf_if/doc/data_sheet/MC44S803.pdf 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun SPI or I2C Address : 0xc0-0xc6 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun Reg.No | Function 17*4882a593Smuzhiyun ------------------------------------------- 18*4882a593Smuzhiyun 00 | Power Down 19*4882a593Smuzhiyun 01 | Reference Oszillator 20*4882a593Smuzhiyun 02 | Reference Dividers 21*4882a593Smuzhiyun 03 | Mixer and Reference Buffer 22*4882a593Smuzhiyun 04 | Reset/Serial Out 23*4882a593Smuzhiyun 05 | LO 1 24*4882a593Smuzhiyun 06 | LO 2 25*4882a593Smuzhiyun 07 | Circuit Adjust 26*4882a593Smuzhiyun 08 | Test 27*4882a593Smuzhiyun 09 | Digital Tune 28*4882a593Smuzhiyun 0A | LNA AGC 29*4882a593Smuzhiyun 0B | Data Register Address 30*4882a593Smuzhiyun 0C | Regulator Test 31*4882a593Smuzhiyun 0D | VCO Test 32*4882a593Smuzhiyun 0E | LNA Gain/Input Power 33*4882a593Smuzhiyun 0F | ID Bits 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define MC44S803_OSC 26000000 /* 26 MHz */ 38*4882a593Smuzhiyun #define MC44S803_IF1 1086000000 /* 1086 MHz */ 39*4882a593Smuzhiyun #define MC44S803_IF2 36125000 /* 36.125 MHz */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define MC44S803_REG_POWER 0 42*4882a593Smuzhiyun #define MC44S803_REG_REFOSC 1 43*4882a593Smuzhiyun #define MC44S803_REG_REFDIV 2 44*4882a593Smuzhiyun #define MC44S803_REG_MIXER 3 45*4882a593Smuzhiyun #define MC44S803_REG_RESET 4 46*4882a593Smuzhiyun #define MC44S803_REG_LO1 5 47*4882a593Smuzhiyun #define MC44S803_REG_LO2 6 48*4882a593Smuzhiyun #define MC44S803_REG_CIRCADJ 7 49*4882a593Smuzhiyun #define MC44S803_REG_TEST 8 50*4882a593Smuzhiyun #define MC44S803_REG_DIGTUNE 9 51*4882a593Smuzhiyun #define MC44S803_REG_LNAAGC 0x0A 52*4882a593Smuzhiyun #define MC44S803_REG_DATAREG 0x0B 53*4882a593Smuzhiyun #define MC44S803_REG_REGTEST 0x0C 54*4882a593Smuzhiyun #define MC44S803_REG_VCOTEST 0x0D 55*4882a593Smuzhiyun #define MC44S803_REG_LNAGAIN 0x0E 56*4882a593Smuzhiyun #define MC44S803_REG_ID 0x0F 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Register definitions */ 59*4882a593Smuzhiyun #define MC44S803_ADDR 0x0F 60*4882a593Smuzhiyun #define MC44S803_ADDR_S 0 61*4882a593Smuzhiyun /* REG_POWER */ 62*4882a593Smuzhiyun #define MC44S803_POWER 0xFFFFF0 63*4882a593Smuzhiyun #define MC44S803_POWER_S 4 64*4882a593Smuzhiyun /* REG_REFOSC */ 65*4882a593Smuzhiyun #define MC44S803_REFOSC 0x1FF0 66*4882a593Smuzhiyun #define MC44S803_REFOSC_S 4 67*4882a593Smuzhiyun #define MC44S803_OSCSEL 0x2000 68*4882a593Smuzhiyun #define MC44S803_OSCSEL_S 13 69*4882a593Smuzhiyun /* REG_REFDIV */ 70*4882a593Smuzhiyun #define MC44S803_R2 0x1FF0 71*4882a593Smuzhiyun #define MC44S803_R2_S 4 72*4882a593Smuzhiyun #define MC44S803_REFBUF_EN 0x2000 73*4882a593Smuzhiyun #define MC44S803_REFBUF_EN_S 13 74*4882a593Smuzhiyun #define MC44S803_R1 0x7C000 75*4882a593Smuzhiyun #define MC44S803_R1_S 14 76*4882a593Smuzhiyun /* REG_MIXER */ 77*4882a593Smuzhiyun #define MC44S803_R3 0x70 78*4882a593Smuzhiyun #define MC44S803_R3_S 4 79*4882a593Smuzhiyun #define MC44S803_MUX3 0x80 80*4882a593Smuzhiyun #define MC44S803_MUX3_S 7 81*4882a593Smuzhiyun #define MC44S803_MUX4 0x100 82*4882a593Smuzhiyun #define MC44S803_MUX4_S 8 83*4882a593Smuzhiyun #define MC44S803_OSC_SCR 0x200 84*4882a593Smuzhiyun #define MC44S803_OSC_SCR_S 9 85*4882a593Smuzhiyun #define MC44S803_TRI_STATE 0x400 86*4882a593Smuzhiyun #define MC44S803_TRI_STATE_S 10 87*4882a593Smuzhiyun #define MC44S803_BUF_GAIN 0x800 88*4882a593Smuzhiyun #define MC44S803_BUF_GAIN_S 11 89*4882a593Smuzhiyun #define MC44S803_BUF_IO 0x1000 90*4882a593Smuzhiyun #define MC44S803_BUF_IO_S 12 91*4882a593Smuzhiyun #define MC44S803_MIXER_RES 0xFE000 92*4882a593Smuzhiyun #define MC44S803_MIXER_RES_S 13 93*4882a593Smuzhiyun /* REG_RESET */ 94*4882a593Smuzhiyun #define MC44S803_RS 0x10 95*4882a593Smuzhiyun #define MC44S803_RS_S 4 96*4882a593Smuzhiyun #define MC44S803_SO 0x20 97*4882a593Smuzhiyun #define MC44S803_SO_S 5 98*4882a593Smuzhiyun /* REG_LO1 */ 99*4882a593Smuzhiyun #define MC44S803_LO1 0xFFF0 100*4882a593Smuzhiyun #define MC44S803_LO1_S 4 101*4882a593Smuzhiyun /* REG_LO2 */ 102*4882a593Smuzhiyun #define MC44S803_LO2 0x7FFF0 103*4882a593Smuzhiyun #define MC44S803_LO2_S 4 104*4882a593Smuzhiyun /* REG_CIRCADJ */ 105*4882a593Smuzhiyun #define MC44S803_G1 0x20 106*4882a593Smuzhiyun #define MC44S803_G1_S 5 107*4882a593Smuzhiyun #define MC44S803_G3 0x80 108*4882a593Smuzhiyun #define MC44S803_G3_S 7 109*4882a593Smuzhiyun #define MC44S803_CIRCADJ_RES 0x300 110*4882a593Smuzhiyun #define MC44S803_CIRCADJ_RES_S 8 111*4882a593Smuzhiyun #define MC44S803_G6 0x400 112*4882a593Smuzhiyun #define MC44S803_G6_S 10 113*4882a593Smuzhiyun #define MC44S803_G7 0x800 114*4882a593Smuzhiyun #define MC44S803_G7_S 11 115*4882a593Smuzhiyun #define MC44S803_S1 0x1000 116*4882a593Smuzhiyun #define MC44S803_S1_S 12 117*4882a593Smuzhiyun #define MC44S803_LP 0x7E000 118*4882a593Smuzhiyun #define MC44S803_LP_S 13 119*4882a593Smuzhiyun #define MC44S803_CLRF 0x80000 120*4882a593Smuzhiyun #define MC44S803_CLRF_S 19 121*4882a593Smuzhiyun #define MC44S803_CLIF 0x100000 122*4882a593Smuzhiyun #define MC44S803_CLIF_S 20 123*4882a593Smuzhiyun /* REG_TEST */ 124*4882a593Smuzhiyun /* REG_DIGTUNE */ 125*4882a593Smuzhiyun #define MC44S803_DA 0xF0 126*4882a593Smuzhiyun #define MC44S803_DA_S 4 127*4882a593Smuzhiyun #define MC44S803_XOD 0x300 128*4882a593Smuzhiyun #define MC44S803_XOD_S 8 129*4882a593Smuzhiyun #define MC44S803_RST 0x10000 130*4882a593Smuzhiyun #define MC44S803_RST_S 16 131*4882a593Smuzhiyun #define MC44S803_LO_REF 0x1FFF00 132*4882a593Smuzhiyun #define MC44S803_LO_REF_S 8 133*4882a593Smuzhiyun #define MC44S803_AT 0x200000 134*4882a593Smuzhiyun #define MC44S803_AT_S 21 135*4882a593Smuzhiyun #define MC44S803_MT 0x400000 136*4882a593Smuzhiyun #define MC44S803_MT_S 22 137*4882a593Smuzhiyun /* REG_LNAAGC */ 138*4882a593Smuzhiyun #define MC44S803_G 0x3F0 139*4882a593Smuzhiyun #define MC44S803_G_S 4 140*4882a593Smuzhiyun #define MC44S803_AT1 0x400 141*4882a593Smuzhiyun #define MC44S803_AT1_S 10 142*4882a593Smuzhiyun #define MC44S803_AT2 0x800 143*4882a593Smuzhiyun #define MC44S803_AT2_S 11 144*4882a593Smuzhiyun #define MC44S803_HL_GR_EN 0x8000 145*4882a593Smuzhiyun #define MC44S803_HL_GR_EN_S 15 146*4882a593Smuzhiyun #define MC44S803_AGC_AN_DIG 0x10000 147*4882a593Smuzhiyun #define MC44S803_AGC_AN_DIG_S 16 148*4882a593Smuzhiyun #define MC44S803_ATTEN_EN 0x20000 149*4882a593Smuzhiyun #define MC44S803_ATTEN_EN_S 17 150*4882a593Smuzhiyun #define MC44S803_AGC_READ_EN 0x40000 151*4882a593Smuzhiyun #define MC44S803_AGC_READ_EN_S 18 152*4882a593Smuzhiyun #define MC44S803_LNA0 0x80000 153*4882a593Smuzhiyun #define MC44S803_LNA0_S 19 154*4882a593Smuzhiyun #define MC44S803_AGC_SEL 0x100000 155*4882a593Smuzhiyun #define MC44S803_AGC_SEL_S 20 156*4882a593Smuzhiyun #define MC44S803_AT0 0x200000 157*4882a593Smuzhiyun #define MC44S803_AT0_S 21 158*4882a593Smuzhiyun #define MC44S803_B 0xC00000 159*4882a593Smuzhiyun #define MC44S803_B_S 22 160*4882a593Smuzhiyun /* REG_DATAREG */ 161*4882a593Smuzhiyun #define MC44S803_D 0xF0 162*4882a593Smuzhiyun #define MC44S803_D_S 4 163*4882a593Smuzhiyun /* REG_REGTEST */ 164*4882a593Smuzhiyun /* REG_VCOTEST */ 165*4882a593Smuzhiyun /* REG_LNAGAIN */ 166*4882a593Smuzhiyun #define MC44S803_IF_PWR 0x700 167*4882a593Smuzhiyun #define MC44S803_IF_PWR_S 8 168*4882a593Smuzhiyun #define MC44S803_RF_PWR 0x3800 169*4882a593Smuzhiyun #define MC44S803_RF_PWR_S 11 170*4882a593Smuzhiyun #define MC44S803_LNA_GAIN 0xFC000 171*4882a593Smuzhiyun #define MC44S803_LNA_GAIN_S 14 172*4882a593Smuzhiyun /* REG_ID */ 173*4882a593Smuzhiyun #define MC44S803_ID 0x3E00 174*4882a593Smuzhiyun #define MC44S803_ID_S 9 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* Some macros to read/write fields */ 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun /* First shift, then mask */ 179*4882a593Smuzhiyun #define MC44S803_REG_SM(_val, _reg) \ 180*4882a593Smuzhiyun (((_val) << _reg##_S) & (_reg)) 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun /* First mask, then shift */ 183*4882a593Smuzhiyun #define MC44S803_REG_MS(_val, _reg) \ 184*4882a593Smuzhiyun (((_val) & (_reg)) >> _reg##_S) 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun struct mc44s803_priv { 187*4882a593Smuzhiyun struct mc44s803_config *cfg; 188*4882a593Smuzhiyun struct i2c_adapter *i2c; 189*4882a593Smuzhiyun struct dvb_frontend *fe; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun u32 frequency; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun #endif 195