1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for Freescale MC44S803 Low Power CMOS Broadband Tuner
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2009 Jochen Friedrich <jochen@scram.de>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/dvb/frontend.h>
11*4882a593Smuzhiyun #include <linux/i2c.h>
12*4882a593Smuzhiyun #include <linux/slab.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <media/dvb_frontend.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "mc44s803.h"
17*4882a593Smuzhiyun #include "mc44s803_priv.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define mc_printk(level, format, arg...) \
20*4882a593Smuzhiyun printk(level "mc44s803: " format , ## arg)
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* Writes a single register */
mc44s803_writereg(struct mc44s803_priv * priv,u32 val)23*4882a593Smuzhiyun static int mc44s803_writereg(struct mc44s803_priv *priv, u32 val)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun u8 buf[3];
26*4882a593Smuzhiyun struct i2c_msg msg = {
27*4882a593Smuzhiyun .addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 3
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun buf[0] = (val & 0xff0000) >> 16;
31*4882a593Smuzhiyun buf[1] = (val & 0xff00) >> 8;
32*4882a593Smuzhiyun buf[2] = (val & 0xff);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
35*4882a593Smuzhiyun mc_printk(KERN_WARNING, "I2C write failed\n");
36*4882a593Smuzhiyun return -EREMOTEIO;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun return 0;
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* Reads a single register */
mc44s803_readreg(struct mc44s803_priv * priv,u8 reg,u32 * val)42*4882a593Smuzhiyun static int mc44s803_readreg(struct mc44s803_priv *priv, u8 reg, u32 *val)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun u32 wval;
45*4882a593Smuzhiyun u8 buf[3];
46*4882a593Smuzhiyun int ret;
47*4882a593Smuzhiyun struct i2c_msg msg[] = {
48*4882a593Smuzhiyun { .addr = priv->cfg->i2c_address, .flags = I2C_M_RD,
49*4882a593Smuzhiyun .buf = buf, .len = 3 },
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun wval = MC44S803_REG_SM(MC44S803_REG_DATAREG, MC44S803_ADDR) |
53*4882a593Smuzhiyun MC44S803_REG_SM(reg, MC44S803_D);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun ret = mc44s803_writereg(priv, wval);
56*4882a593Smuzhiyun if (ret)
57*4882a593Smuzhiyun return ret;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun if (i2c_transfer(priv->i2c, msg, 1) != 1) {
60*4882a593Smuzhiyun mc_printk(KERN_WARNING, "I2C read failed\n");
61*4882a593Smuzhiyun return -EREMOTEIO;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun *val = (buf[0] << 16) | (buf[1] << 8) | buf[2];
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun return 0;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
mc44s803_release(struct dvb_frontend * fe)69*4882a593Smuzhiyun static void mc44s803_release(struct dvb_frontend *fe)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun struct mc44s803_priv *priv = fe->tuner_priv;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun fe->tuner_priv = NULL;
74*4882a593Smuzhiyun kfree(priv);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
mc44s803_init(struct dvb_frontend * fe)77*4882a593Smuzhiyun static int mc44s803_init(struct dvb_frontend *fe)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun struct mc44s803_priv *priv = fe->tuner_priv;
80*4882a593Smuzhiyun u32 val;
81*4882a593Smuzhiyun int err;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun if (fe->ops.i2c_gate_ctrl)
84*4882a593Smuzhiyun fe->ops.i2c_gate_ctrl(fe, 1);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /* Reset chip */
87*4882a593Smuzhiyun val = MC44S803_REG_SM(MC44S803_REG_RESET, MC44S803_ADDR) |
88*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_RS);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun err = mc44s803_writereg(priv, val);
91*4882a593Smuzhiyun if (err)
92*4882a593Smuzhiyun goto exit;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun val = MC44S803_REG_SM(MC44S803_REG_RESET, MC44S803_ADDR);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun err = mc44s803_writereg(priv, val);
97*4882a593Smuzhiyun if (err)
98*4882a593Smuzhiyun goto exit;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* Power Up and Start Osc */
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun val = MC44S803_REG_SM(MC44S803_REG_REFOSC, MC44S803_ADDR) |
103*4882a593Smuzhiyun MC44S803_REG_SM(0xC0, MC44S803_REFOSC) |
104*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_OSCSEL);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun err = mc44s803_writereg(priv, val);
107*4882a593Smuzhiyun if (err)
108*4882a593Smuzhiyun goto exit;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun val = MC44S803_REG_SM(MC44S803_REG_POWER, MC44S803_ADDR) |
111*4882a593Smuzhiyun MC44S803_REG_SM(0x200, MC44S803_POWER);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun err = mc44s803_writereg(priv, val);
114*4882a593Smuzhiyun if (err)
115*4882a593Smuzhiyun goto exit;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun msleep(10);
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun val = MC44S803_REG_SM(MC44S803_REG_REFOSC, MC44S803_ADDR) |
120*4882a593Smuzhiyun MC44S803_REG_SM(0x40, MC44S803_REFOSC) |
121*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_OSCSEL);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun err = mc44s803_writereg(priv, val);
124*4882a593Smuzhiyun if (err)
125*4882a593Smuzhiyun goto exit;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun msleep(20);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /* Setup Mixer */
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun val = MC44S803_REG_SM(MC44S803_REG_MIXER, MC44S803_ADDR) |
132*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_TRI_STATE) |
133*4882a593Smuzhiyun MC44S803_REG_SM(0x7F, MC44S803_MIXER_RES);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun err = mc44s803_writereg(priv, val);
136*4882a593Smuzhiyun if (err)
137*4882a593Smuzhiyun goto exit;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun /* Setup Cirquit Adjust */
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun val = MC44S803_REG_SM(MC44S803_REG_CIRCADJ, MC44S803_ADDR) |
142*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_G1) |
143*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_G3) |
144*4882a593Smuzhiyun MC44S803_REG_SM(0x3, MC44S803_CIRCADJ_RES) |
145*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_G6) |
146*4882a593Smuzhiyun MC44S803_REG_SM(priv->cfg->dig_out, MC44S803_S1) |
147*4882a593Smuzhiyun MC44S803_REG_SM(0x3, MC44S803_LP) |
148*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_CLRF) |
149*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_CLIF);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun err = mc44s803_writereg(priv, val);
152*4882a593Smuzhiyun if (err)
153*4882a593Smuzhiyun goto exit;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun val = MC44S803_REG_SM(MC44S803_REG_CIRCADJ, MC44S803_ADDR) |
156*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_G1) |
157*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_G3) |
158*4882a593Smuzhiyun MC44S803_REG_SM(0x3, MC44S803_CIRCADJ_RES) |
159*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_G6) |
160*4882a593Smuzhiyun MC44S803_REG_SM(priv->cfg->dig_out, MC44S803_S1) |
161*4882a593Smuzhiyun MC44S803_REG_SM(0x3, MC44S803_LP);
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun err = mc44s803_writereg(priv, val);
164*4882a593Smuzhiyun if (err)
165*4882a593Smuzhiyun goto exit;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun /* Setup Digtune */
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun val = MC44S803_REG_SM(MC44S803_REG_DIGTUNE, MC44S803_ADDR) |
170*4882a593Smuzhiyun MC44S803_REG_SM(3, MC44S803_XOD);
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun err = mc44s803_writereg(priv, val);
173*4882a593Smuzhiyun if (err)
174*4882a593Smuzhiyun goto exit;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun /* Setup AGC */
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun val = MC44S803_REG_SM(MC44S803_REG_LNAAGC, MC44S803_ADDR) |
179*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_AT1) |
180*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_AT2) |
181*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_AGC_AN_DIG) |
182*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_AGC_READ_EN) |
183*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_LNA0);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun err = mc44s803_writereg(priv, val);
186*4882a593Smuzhiyun if (err)
187*4882a593Smuzhiyun goto exit;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun if (fe->ops.i2c_gate_ctrl)
190*4882a593Smuzhiyun fe->ops.i2c_gate_ctrl(fe, 0);
191*4882a593Smuzhiyun return 0;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun exit:
194*4882a593Smuzhiyun if (fe->ops.i2c_gate_ctrl)
195*4882a593Smuzhiyun fe->ops.i2c_gate_ctrl(fe, 0);
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun mc_printk(KERN_WARNING, "I/O Error\n");
198*4882a593Smuzhiyun return err;
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun
mc44s803_set_params(struct dvb_frontend * fe)201*4882a593Smuzhiyun static int mc44s803_set_params(struct dvb_frontend *fe)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun struct mc44s803_priv *priv = fe->tuner_priv;
204*4882a593Smuzhiyun struct dtv_frontend_properties *c = &fe->dtv_property_cache;
205*4882a593Smuzhiyun u32 r1, r2, n1, n2, lo1, lo2, freq, val;
206*4882a593Smuzhiyun int err;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun priv->frequency = c->frequency;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun r1 = MC44S803_OSC / 1000000;
211*4882a593Smuzhiyun r2 = MC44S803_OSC / 100000;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun n1 = (c->frequency + MC44S803_IF1 + 500000) / 1000000;
214*4882a593Smuzhiyun freq = MC44S803_OSC / r1 * n1;
215*4882a593Smuzhiyun lo1 = ((60 * n1) + (r1 / 2)) / r1;
216*4882a593Smuzhiyun freq = freq - c->frequency;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun n2 = (freq - MC44S803_IF2 + 50000) / 100000;
219*4882a593Smuzhiyun lo2 = ((60 * n2) + (r2 / 2)) / r2;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun if (fe->ops.i2c_gate_ctrl)
222*4882a593Smuzhiyun fe->ops.i2c_gate_ctrl(fe, 1);
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun val = MC44S803_REG_SM(MC44S803_REG_REFDIV, MC44S803_ADDR) |
225*4882a593Smuzhiyun MC44S803_REG_SM(r1-1, MC44S803_R1) |
226*4882a593Smuzhiyun MC44S803_REG_SM(r2-1, MC44S803_R2) |
227*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_REFBUF_EN);
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun err = mc44s803_writereg(priv, val);
230*4882a593Smuzhiyun if (err)
231*4882a593Smuzhiyun goto exit;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun val = MC44S803_REG_SM(MC44S803_REG_LO1, MC44S803_ADDR) |
234*4882a593Smuzhiyun MC44S803_REG_SM(n1-2, MC44S803_LO1);
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun err = mc44s803_writereg(priv, val);
237*4882a593Smuzhiyun if (err)
238*4882a593Smuzhiyun goto exit;
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun val = MC44S803_REG_SM(MC44S803_REG_LO2, MC44S803_ADDR) |
241*4882a593Smuzhiyun MC44S803_REG_SM(n2-2, MC44S803_LO2);
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun err = mc44s803_writereg(priv, val);
244*4882a593Smuzhiyun if (err)
245*4882a593Smuzhiyun goto exit;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun val = MC44S803_REG_SM(MC44S803_REG_DIGTUNE, MC44S803_ADDR) |
248*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_DA) |
249*4882a593Smuzhiyun MC44S803_REG_SM(lo1, MC44S803_LO_REF) |
250*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_AT);
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun err = mc44s803_writereg(priv, val);
253*4882a593Smuzhiyun if (err)
254*4882a593Smuzhiyun goto exit;
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun val = MC44S803_REG_SM(MC44S803_REG_DIGTUNE, MC44S803_ADDR) |
257*4882a593Smuzhiyun MC44S803_REG_SM(2, MC44S803_DA) |
258*4882a593Smuzhiyun MC44S803_REG_SM(lo2, MC44S803_LO_REF) |
259*4882a593Smuzhiyun MC44S803_REG_SM(1, MC44S803_AT);
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun err = mc44s803_writereg(priv, val);
262*4882a593Smuzhiyun if (err)
263*4882a593Smuzhiyun goto exit;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun if (fe->ops.i2c_gate_ctrl)
266*4882a593Smuzhiyun fe->ops.i2c_gate_ctrl(fe, 0);
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun return 0;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun exit:
271*4882a593Smuzhiyun if (fe->ops.i2c_gate_ctrl)
272*4882a593Smuzhiyun fe->ops.i2c_gate_ctrl(fe, 0);
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun mc_printk(KERN_WARNING, "I/O Error\n");
275*4882a593Smuzhiyun return err;
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun
mc44s803_get_frequency(struct dvb_frontend * fe,u32 * frequency)278*4882a593Smuzhiyun static int mc44s803_get_frequency(struct dvb_frontend *fe, u32 *frequency)
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun struct mc44s803_priv *priv = fe->tuner_priv;
281*4882a593Smuzhiyun *frequency = priv->frequency;
282*4882a593Smuzhiyun return 0;
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun
mc44s803_get_if_frequency(struct dvb_frontend * fe,u32 * frequency)285*4882a593Smuzhiyun static int mc44s803_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
286*4882a593Smuzhiyun {
287*4882a593Smuzhiyun *frequency = MC44S803_IF2; /* 36.125 MHz */
288*4882a593Smuzhiyun return 0;
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun static const struct dvb_tuner_ops mc44s803_tuner_ops = {
292*4882a593Smuzhiyun .info = {
293*4882a593Smuzhiyun .name = "Freescale MC44S803",
294*4882a593Smuzhiyun .frequency_min_hz = 48 * MHz,
295*4882a593Smuzhiyun .frequency_max_hz = 1000 * MHz,
296*4882a593Smuzhiyun .frequency_step_hz = 100 * kHz,
297*4882a593Smuzhiyun },
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun .release = mc44s803_release,
300*4882a593Smuzhiyun .init = mc44s803_init,
301*4882a593Smuzhiyun .set_params = mc44s803_set_params,
302*4882a593Smuzhiyun .get_frequency = mc44s803_get_frequency,
303*4882a593Smuzhiyun .get_if_frequency = mc44s803_get_if_frequency,
304*4882a593Smuzhiyun };
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun /* This functions tries to identify a MC44S803 tuner by reading the ID
307*4882a593Smuzhiyun register. This is hasty. */
mc44s803_attach(struct dvb_frontend * fe,struct i2c_adapter * i2c,struct mc44s803_config * cfg)308*4882a593Smuzhiyun struct dvb_frontend *mc44s803_attach(struct dvb_frontend *fe,
309*4882a593Smuzhiyun struct i2c_adapter *i2c, struct mc44s803_config *cfg)
310*4882a593Smuzhiyun {
311*4882a593Smuzhiyun struct mc44s803_priv *priv;
312*4882a593Smuzhiyun u32 reg;
313*4882a593Smuzhiyun u8 id;
314*4882a593Smuzhiyun int ret;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun reg = 0;
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun priv = kzalloc(sizeof(struct mc44s803_priv), GFP_KERNEL);
319*4882a593Smuzhiyun if (priv == NULL)
320*4882a593Smuzhiyun return NULL;
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun priv->cfg = cfg;
323*4882a593Smuzhiyun priv->i2c = i2c;
324*4882a593Smuzhiyun priv->fe = fe;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun if (fe->ops.i2c_gate_ctrl)
327*4882a593Smuzhiyun fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun ret = mc44s803_readreg(priv, MC44S803_REG_ID, ®);
330*4882a593Smuzhiyun if (ret)
331*4882a593Smuzhiyun goto error;
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun id = MC44S803_REG_MS(reg, MC44S803_ID);
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun if (id != 0x14) {
336*4882a593Smuzhiyun mc_printk(KERN_ERR, "unsupported ID (%x should be 0x14)\n",
337*4882a593Smuzhiyun id);
338*4882a593Smuzhiyun goto error;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun mc_printk(KERN_INFO, "successfully identified (ID = %x)\n", id);
342*4882a593Smuzhiyun memcpy(&fe->ops.tuner_ops, &mc44s803_tuner_ops,
343*4882a593Smuzhiyun sizeof(struct dvb_tuner_ops));
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun fe->tuner_priv = priv;
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun if (fe->ops.i2c_gate_ctrl)
348*4882a593Smuzhiyun fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun return fe;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun error:
353*4882a593Smuzhiyun if (fe->ops.i2c_gate_ctrl)
354*4882a593Smuzhiyun fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun kfree(priv);
357*4882a593Smuzhiyun return NULL;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun EXPORT_SYMBOL(mc44s803_attach);
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun MODULE_AUTHOR("Jochen Friedrich");
362*4882a593Smuzhiyun MODULE_DESCRIPTION("Freescale MC44S803 silicon tuner driver");
363*4882a593Smuzhiyun MODULE_LICENSE("GPL");
364