1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Driver for Maxim MAX2165 silicon tuner 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2009 David T. L. Wong <davidtlwong@gmail.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __MAX2165_PRIV_H__ 9*4882a593Smuzhiyun #define __MAX2165_PRIV_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define REG_NDIV_INT 0x00 12*4882a593Smuzhiyun #define REG_NDIV_FRAC2 0x01 13*4882a593Smuzhiyun #define REG_NDIV_FRAC1 0x02 14*4882a593Smuzhiyun #define REG_NDIV_FRAC0 0x03 15*4882a593Smuzhiyun #define REG_TRACK_FILTER 0x04 16*4882a593Smuzhiyun #define REG_LNA 0x05 17*4882a593Smuzhiyun #define REG_PLL_CFG 0x06 18*4882a593Smuzhiyun #define REG_TEST 0x07 19*4882a593Smuzhiyun #define REG_SHUTDOWN 0x08 20*4882a593Smuzhiyun #define REG_VCO_CTRL 0x09 21*4882a593Smuzhiyun #define REG_BASEBAND_CTRL 0x0A 22*4882a593Smuzhiyun #define REG_DC_OFFSET_CTRL 0x0B 23*4882a593Smuzhiyun #define REG_DC_OFFSET_DAC 0x0C 24*4882a593Smuzhiyun #define REG_ROM_TABLE_ADDR 0x0D 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Read Only Registers */ 27*4882a593Smuzhiyun #define REG_ROM_TABLE_DATA 0x10 28*4882a593Smuzhiyun #define REG_STATUS 0x11 29*4882a593Smuzhiyun #define REG_AUTOTUNE 0x12 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun struct max2165_priv { 32*4882a593Smuzhiyun struct max2165_config *config; 33*4882a593Smuzhiyun struct i2c_adapter *i2c; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun u32 frequency; 36*4882a593Smuzhiyun u32 bandwidth; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun u8 tf_ntch_low_cfg; 39*4882a593Smuzhiyun u8 tf_ntch_hi_cfg; 40*4882a593Smuzhiyun u8 tf_balun_low_ref; 41*4882a593Smuzhiyun u8 tf_balun_hi_ref; 42*4882a593Smuzhiyun u8 bb_filter_7mhz_cfg; 43*4882a593Smuzhiyun u8 bb_filter_8mhz_cfg; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #endif 47