1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Elonics E4000 silicon tuner driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include "e4000_priv.h"
9*4882a593Smuzhiyun
e4000_init(struct e4000_dev * dev)10*4882a593Smuzhiyun static int e4000_init(struct e4000_dev *dev)
11*4882a593Smuzhiyun {
12*4882a593Smuzhiyun struct i2c_client *client = dev->client;
13*4882a593Smuzhiyun int ret;
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun dev_dbg(&client->dev, "\n");
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* reset */
18*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x00, 0x01);
19*4882a593Smuzhiyun if (ret)
20*4882a593Smuzhiyun goto err;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* disable output clock */
23*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x06, 0x00);
24*4882a593Smuzhiyun if (ret)
25*4882a593Smuzhiyun goto err;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x7a, 0x96);
28*4882a593Smuzhiyun if (ret)
29*4882a593Smuzhiyun goto err;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* configure gains */
32*4882a593Smuzhiyun ret = regmap_bulk_write(dev->regmap, 0x7e, "\x01\xfe", 2);
33*4882a593Smuzhiyun if (ret)
34*4882a593Smuzhiyun goto err;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x82, 0x00);
37*4882a593Smuzhiyun if (ret)
38*4882a593Smuzhiyun goto err;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x24, 0x05);
41*4882a593Smuzhiyun if (ret)
42*4882a593Smuzhiyun goto err;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun ret = regmap_bulk_write(dev->regmap, 0x87, "\x20\x01", 2);
45*4882a593Smuzhiyun if (ret)
46*4882a593Smuzhiyun goto err;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun ret = regmap_bulk_write(dev->regmap, 0x9f, "\x7f\x07", 2);
49*4882a593Smuzhiyun if (ret)
50*4882a593Smuzhiyun goto err;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* DC offset control */
53*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x2d, 0x1f);
54*4882a593Smuzhiyun if (ret)
55*4882a593Smuzhiyun goto err;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun ret = regmap_bulk_write(dev->regmap, 0x70, "\x01\x01", 2);
58*4882a593Smuzhiyun if (ret)
59*4882a593Smuzhiyun goto err;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* gain control */
62*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x1a, 0x17);
63*4882a593Smuzhiyun if (ret)
64*4882a593Smuzhiyun goto err;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x1f, 0x1a);
67*4882a593Smuzhiyun if (ret)
68*4882a593Smuzhiyun goto err;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun dev->active = true;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun return 0;
73*4882a593Smuzhiyun err:
74*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
75*4882a593Smuzhiyun return ret;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
e4000_sleep(struct e4000_dev * dev)78*4882a593Smuzhiyun static int e4000_sleep(struct e4000_dev *dev)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun struct i2c_client *client = dev->client;
81*4882a593Smuzhiyun int ret;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun dev_dbg(&client->dev, "\n");
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun dev->active = false;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x00, 0x00);
88*4882a593Smuzhiyun if (ret)
89*4882a593Smuzhiyun goto err;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun return 0;
92*4882a593Smuzhiyun err:
93*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
94*4882a593Smuzhiyun return ret;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
e4000_set_params(struct e4000_dev * dev)97*4882a593Smuzhiyun static int e4000_set_params(struct e4000_dev *dev)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun struct i2c_client *client = dev->client;
100*4882a593Smuzhiyun int ret, i;
101*4882a593Smuzhiyun unsigned int div_n, k, k_cw, div_out;
102*4882a593Smuzhiyun u64 f_vco;
103*4882a593Smuzhiyun u8 buf[5], i_data[4], q_data[4];
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun if (!dev->active) {
106*4882a593Smuzhiyun dev_dbg(&client->dev, "tuner is sleeping\n");
107*4882a593Smuzhiyun return 0;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* gain control manual */
111*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x1a, 0x00);
112*4882a593Smuzhiyun if (ret)
113*4882a593Smuzhiyun goto err;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /*
116*4882a593Smuzhiyun * Fractional-N synthesizer
117*4882a593Smuzhiyun *
118*4882a593Smuzhiyun * +----------------------------+
119*4882a593Smuzhiyun * v |
120*4882a593Smuzhiyun * Fref +----+ +-------+ +------+ +---+
121*4882a593Smuzhiyun * ------> | PD | --> | VCO | ------> | /N.F | <-- | K |
122*4882a593Smuzhiyun * +----+ +-------+ +------+ +---+
123*4882a593Smuzhiyun * |
124*4882a593Smuzhiyun * |
125*4882a593Smuzhiyun * v
126*4882a593Smuzhiyun * +-------+ Fout
127*4882a593Smuzhiyun * | /Rout | ------>
128*4882a593Smuzhiyun * +-------+
129*4882a593Smuzhiyun */
130*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(e4000_pll_lut); i++) {
131*4882a593Smuzhiyun if (dev->f_frequency <= e4000_pll_lut[i].freq)
132*4882a593Smuzhiyun break;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun if (i == ARRAY_SIZE(e4000_pll_lut)) {
135*4882a593Smuzhiyun ret = -EINVAL;
136*4882a593Smuzhiyun goto err;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun #define F_REF dev->clk
140*4882a593Smuzhiyun div_out = e4000_pll_lut[i].div_out;
141*4882a593Smuzhiyun f_vco = (u64) dev->f_frequency * div_out;
142*4882a593Smuzhiyun /* calculate PLL integer and fractional control word */
143*4882a593Smuzhiyun div_n = div_u64_rem(f_vco, F_REF, &k);
144*4882a593Smuzhiyun k_cw = div_u64((u64) k * 0x10000, F_REF);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun dev_dbg(&client->dev,
147*4882a593Smuzhiyun "frequency=%u bandwidth=%u f_vco=%llu F_REF=%u div_n=%u k=%u k_cw=%04x div_out=%u\n",
148*4882a593Smuzhiyun dev->f_frequency, dev->f_bandwidth, f_vco, F_REF, div_n, k,
149*4882a593Smuzhiyun k_cw, div_out);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun buf[0] = div_n;
152*4882a593Smuzhiyun buf[1] = (k_cw >> 0) & 0xff;
153*4882a593Smuzhiyun buf[2] = (k_cw >> 8) & 0xff;
154*4882a593Smuzhiyun buf[3] = 0x00;
155*4882a593Smuzhiyun buf[4] = e4000_pll_lut[i].div_out_reg;
156*4882a593Smuzhiyun ret = regmap_bulk_write(dev->regmap, 0x09, buf, 5);
157*4882a593Smuzhiyun if (ret)
158*4882a593Smuzhiyun goto err;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun /* LNA filter (RF filter) */
161*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(e400_lna_filter_lut); i++) {
162*4882a593Smuzhiyun if (dev->f_frequency <= e400_lna_filter_lut[i].freq)
163*4882a593Smuzhiyun break;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun if (i == ARRAY_SIZE(e400_lna_filter_lut)) {
166*4882a593Smuzhiyun ret = -EINVAL;
167*4882a593Smuzhiyun goto err;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x10, e400_lna_filter_lut[i].val);
171*4882a593Smuzhiyun if (ret)
172*4882a593Smuzhiyun goto err;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun /* IF filters */
175*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(e4000_if_filter_lut); i++) {
176*4882a593Smuzhiyun if (dev->f_bandwidth <= e4000_if_filter_lut[i].freq)
177*4882a593Smuzhiyun break;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun if (i == ARRAY_SIZE(e4000_if_filter_lut)) {
180*4882a593Smuzhiyun ret = -EINVAL;
181*4882a593Smuzhiyun goto err;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun buf[0] = e4000_if_filter_lut[i].reg11_val;
185*4882a593Smuzhiyun buf[1] = e4000_if_filter_lut[i].reg12_val;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun ret = regmap_bulk_write(dev->regmap, 0x11, buf, 2);
188*4882a593Smuzhiyun if (ret)
189*4882a593Smuzhiyun goto err;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun /* frequency band */
192*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(e4000_band_lut); i++) {
193*4882a593Smuzhiyun if (dev->f_frequency <= e4000_band_lut[i].freq)
194*4882a593Smuzhiyun break;
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun if (i == ARRAY_SIZE(e4000_band_lut)) {
197*4882a593Smuzhiyun ret = -EINVAL;
198*4882a593Smuzhiyun goto err;
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x07, e4000_band_lut[i].reg07_val);
202*4882a593Smuzhiyun if (ret)
203*4882a593Smuzhiyun goto err;
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x78, e4000_band_lut[i].reg78_val);
206*4882a593Smuzhiyun if (ret)
207*4882a593Smuzhiyun goto err;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun /* DC offset */
210*4882a593Smuzhiyun for (i = 0; i < 4; i++) {
211*4882a593Smuzhiyun if (i == 0)
212*4882a593Smuzhiyun ret = regmap_bulk_write(dev->regmap, 0x15, "\x00\x7e\x24", 3);
213*4882a593Smuzhiyun else if (i == 1)
214*4882a593Smuzhiyun ret = regmap_bulk_write(dev->regmap, 0x15, "\x00\x7f", 2);
215*4882a593Smuzhiyun else if (i == 2)
216*4882a593Smuzhiyun ret = regmap_bulk_write(dev->regmap, 0x15, "\x01", 1);
217*4882a593Smuzhiyun else
218*4882a593Smuzhiyun ret = regmap_bulk_write(dev->regmap, 0x16, "\x7e", 1);
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun if (ret)
221*4882a593Smuzhiyun goto err;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x29, 0x01);
224*4882a593Smuzhiyun if (ret)
225*4882a593Smuzhiyun goto err;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun ret = regmap_bulk_read(dev->regmap, 0x2a, buf, 3);
228*4882a593Smuzhiyun if (ret)
229*4882a593Smuzhiyun goto err;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun i_data[i] = (((buf[2] >> 0) & 0x3) << 6) | (buf[0] & 0x3f);
232*4882a593Smuzhiyun q_data[i] = (((buf[2] >> 4) & 0x3) << 6) | (buf[1] & 0x3f);
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun swap(q_data[2], q_data[3]);
236*4882a593Smuzhiyun swap(i_data[2], i_data[3]);
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun ret = regmap_bulk_write(dev->regmap, 0x50, q_data, 4);
239*4882a593Smuzhiyun if (ret)
240*4882a593Smuzhiyun goto err;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun ret = regmap_bulk_write(dev->regmap, 0x60, i_data, 4);
243*4882a593Smuzhiyun if (ret)
244*4882a593Smuzhiyun goto err;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun /* gain control auto */
247*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x1a, 0x17);
248*4882a593Smuzhiyun if (ret)
249*4882a593Smuzhiyun goto err;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun return 0;
252*4882a593Smuzhiyun err:
253*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
254*4882a593Smuzhiyun return ret;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun /*
258*4882a593Smuzhiyun * V4L2 API
259*4882a593Smuzhiyun */
260*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_VIDEO_V4L2)
261*4882a593Smuzhiyun static const struct v4l2_frequency_band bands[] = {
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun .type = V4L2_TUNER_RF,
264*4882a593Smuzhiyun .index = 0,
265*4882a593Smuzhiyun .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
266*4882a593Smuzhiyun .rangelow = 59000000,
267*4882a593Smuzhiyun .rangehigh = 1105000000,
268*4882a593Smuzhiyun },
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun .type = V4L2_TUNER_RF,
271*4882a593Smuzhiyun .index = 1,
272*4882a593Smuzhiyun .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
273*4882a593Smuzhiyun .rangelow = 1249000000,
274*4882a593Smuzhiyun .rangehigh = 2208000000UL,
275*4882a593Smuzhiyun },
276*4882a593Smuzhiyun };
277*4882a593Smuzhiyun
e4000_subdev_to_dev(struct v4l2_subdev * sd)278*4882a593Smuzhiyun static inline struct e4000_dev *e4000_subdev_to_dev(struct v4l2_subdev *sd)
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun return container_of(sd, struct e4000_dev, sd);
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun
e4000_standby(struct v4l2_subdev * sd)283*4882a593Smuzhiyun static int e4000_standby(struct v4l2_subdev *sd)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun struct e4000_dev *dev = e4000_subdev_to_dev(sd);
286*4882a593Smuzhiyun int ret;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun ret = e4000_sleep(dev);
289*4882a593Smuzhiyun if (ret)
290*4882a593Smuzhiyun return ret;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun return e4000_set_params(dev);
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun
e4000_g_tuner(struct v4l2_subdev * sd,struct v4l2_tuner * v)295*4882a593Smuzhiyun static int e4000_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *v)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun struct e4000_dev *dev = e4000_subdev_to_dev(sd);
298*4882a593Smuzhiyun struct i2c_client *client = dev->client;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun dev_dbg(&client->dev, "index=%d\n", v->index);
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun strscpy(v->name, "Elonics E4000", sizeof(v->name));
303*4882a593Smuzhiyun v->type = V4L2_TUNER_RF;
304*4882a593Smuzhiyun v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
305*4882a593Smuzhiyun v->rangelow = bands[0].rangelow;
306*4882a593Smuzhiyun v->rangehigh = bands[1].rangehigh;
307*4882a593Smuzhiyun return 0;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
e4000_s_tuner(struct v4l2_subdev * sd,const struct v4l2_tuner * v)310*4882a593Smuzhiyun static int e4000_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *v)
311*4882a593Smuzhiyun {
312*4882a593Smuzhiyun struct e4000_dev *dev = e4000_subdev_to_dev(sd);
313*4882a593Smuzhiyun struct i2c_client *client = dev->client;
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun dev_dbg(&client->dev, "index=%d\n", v->index);
316*4882a593Smuzhiyun return 0;
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun
e4000_g_frequency(struct v4l2_subdev * sd,struct v4l2_frequency * f)319*4882a593Smuzhiyun static int e4000_g_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *f)
320*4882a593Smuzhiyun {
321*4882a593Smuzhiyun struct e4000_dev *dev = e4000_subdev_to_dev(sd);
322*4882a593Smuzhiyun struct i2c_client *client = dev->client;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun dev_dbg(&client->dev, "tuner=%d\n", f->tuner);
325*4882a593Smuzhiyun f->frequency = dev->f_frequency;
326*4882a593Smuzhiyun return 0;
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
e4000_s_frequency(struct v4l2_subdev * sd,const struct v4l2_frequency * f)329*4882a593Smuzhiyun static int e4000_s_frequency(struct v4l2_subdev *sd,
330*4882a593Smuzhiyun const struct v4l2_frequency *f)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun struct e4000_dev *dev = e4000_subdev_to_dev(sd);
333*4882a593Smuzhiyun struct i2c_client *client = dev->client;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun dev_dbg(&client->dev, "tuner=%d type=%d frequency=%u\n",
336*4882a593Smuzhiyun f->tuner, f->type, f->frequency);
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun dev->f_frequency = clamp_t(unsigned int, f->frequency,
339*4882a593Smuzhiyun bands[0].rangelow, bands[1].rangehigh);
340*4882a593Smuzhiyun return e4000_set_params(dev);
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun
e4000_enum_freq_bands(struct v4l2_subdev * sd,struct v4l2_frequency_band * band)343*4882a593Smuzhiyun static int e4000_enum_freq_bands(struct v4l2_subdev *sd,
344*4882a593Smuzhiyun struct v4l2_frequency_band *band)
345*4882a593Smuzhiyun {
346*4882a593Smuzhiyun struct e4000_dev *dev = e4000_subdev_to_dev(sd);
347*4882a593Smuzhiyun struct i2c_client *client = dev->client;
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun dev_dbg(&client->dev, "tuner=%d type=%d index=%d\n",
350*4882a593Smuzhiyun band->tuner, band->type, band->index);
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun if (band->index >= ARRAY_SIZE(bands))
353*4882a593Smuzhiyun return -EINVAL;
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun band->capability = bands[band->index].capability;
356*4882a593Smuzhiyun band->rangelow = bands[band->index].rangelow;
357*4882a593Smuzhiyun band->rangehigh = bands[band->index].rangehigh;
358*4882a593Smuzhiyun return 0;
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun static const struct v4l2_subdev_tuner_ops e4000_subdev_tuner_ops = {
362*4882a593Smuzhiyun .standby = e4000_standby,
363*4882a593Smuzhiyun .g_tuner = e4000_g_tuner,
364*4882a593Smuzhiyun .s_tuner = e4000_s_tuner,
365*4882a593Smuzhiyun .g_frequency = e4000_g_frequency,
366*4882a593Smuzhiyun .s_frequency = e4000_s_frequency,
367*4882a593Smuzhiyun .enum_freq_bands = e4000_enum_freq_bands,
368*4882a593Smuzhiyun };
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun static const struct v4l2_subdev_ops e4000_subdev_ops = {
371*4882a593Smuzhiyun .tuner = &e4000_subdev_tuner_ops,
372*4882a593Smuzhiyun };
373*4882a593Smuzhiyun
e4000_set_lna_gain(struct dvb_frontend * fe)374*4882a593Smuzhiyun static int e4000_set_lna_gain(struct dvb_frontend *fe)
375*4882a593Smuzhiyun {
376*4882a593Smuzhiyun struct e4000_dev *dev = fe->tuner_priv;
377*4882a593Smuzhiyun struct i2c_client *client = dev->client;
378*4882a593Smuzhiyun int ret;
379*4882a593Smuzhiyun u8 u8tmp;
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun dev_dbg(&client->dev, "lna auto=%d->%d val=%d->%d\n",
382*4882a593Smuzhiyun dev->lna_gain_auto->cur.val, dev->lna_gain_auto->val,
383*4882a593Smuzhiyun dev->lna_gain->cur.val, dev->lna_gain->val);
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun if (dev->lna_gain_auto->val && dev->if_gain_auto->cur.val)
386*4882a593Smuzhiyun u8tmp = 0x17;
387*4882a593Smuzhiyun else if (dev->lna_gain_auto->val)
388*4882a593Smuzhiyun u8tmp = 0x19;
389*4882a593Smuzhiyun else if (dev->if_gain_auto->cur.val)
390*4882a593Smuzhiyun u8tmp = 0x16;
391*4882a593Smuzhiyun else
392*4882a593Smuzhiyun u8tmp = 0x10;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x1a, u8tmp);
395*4882a593Smuzhiyun if (ret)
396*4882a593Smuzhiyun goto err;
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun if (dev->lna_gain_auto->val == false) {
399*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x14, dev->lna_gain->val);
400*4882a593Smuzhiyun if (ret)
401*4882a593Smuzhiyun goto err;
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun return 0;
405*4882a593Smuzhiyun err:
406*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
407*4882a593Smuzhiyun return ret;
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun
e4000_set_mixer_gain(struct dvb_frontend * fe)410*4882a593Smuzhiyun static int e4000_set_mixer_gain(struct dvb_frontend *fe)
411*4882a593Smuzhiyun {
412*4882a593Smuzhiyun struct e4000_dev *dev = fe->tuner_priv;
413*4882a593Smuzhiyun struct i2c_client *client = dev->client;
414*4882a593Smuzhiyun int ret;
415*4882a593Smuzhiyun u8 u8tmp;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun dev_dbg(&client->dev, "mixer auto=%d->%d val=%d->%d\n",
418*4882a593Smuzhiyun dev->mixer_gain_auto->cur.val, dev->mixer_gain_auto->val,
419*4882a593Smuzhiyun dev->mixer_gain->cur.val, dev->mixer_gain->val);
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun if (dev->mixer_gain_auto->val)
422*4882a593Smuzhiyun u8tmp = 0x15;
423*4882a593Smuzhiyun else
424*4882a593Smuzhiyun u8tmp = 0x14;
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x20, u8tmp);
427*4882a593Smuzhiyun if (ret)
428*4882a593Smuzhiyun goto err;
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun if (dev->mixer_gain_auto->val == false) {
431*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x15, dev->mixer_gain->val);
432*4882a593Smuzhiyun if (ret)
433*4882a593Smuzhiyun goto err;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun return 0;
437*4882a593Smuzhiyun err:
438*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
439*4882a593Smuzhiyun return ret;
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun
e4000_set_if_gain(struct dvb_frontend * fe)442*4882a593Smuzhiyun static int e4000_set_if_gain(struct dvb_frontend *fe)
443*4882a593Smuzhiyun {
444*4882a593Smuzhiyun struct e4000_dev *dev = fe->tuner_priv;
445*4882a593Smuzhiyun struct i2c_client *client = dev->client;
446*4882a593Smuzhiyun int ret;
447*4882a593Smuzhiyun u8 buf[2];
448*4882a593Smuzhiyun u8 u8tmp;
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun dev_dbg(&client->dev, "if auto=%d->%d val=%d->%d\n",
451*4882a593Smuzhiyun dev->if_gain_auto->cur.val, dev->if_gain_auto->val,
452*4882a593Smuzhiyun dev->if_gain->cur.val, dev->if_gain->val);
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun if (dev->if_gain_auto->val && dev->lna_gain_auto->cur.val)
455*4882a593Smuzhiyun u8tmp = 0x17;
456*4882a593Smuzhiyun else if (dev->lna_gain_auto->cur.val)
457*4882a593Smuzhiyun u8tmp = 0x19;
458*4882a593Smuzhiyun else if (dev->if_gain_auto->val)
459*4882a593Smuzhiyun u8tmp = 0x16;
460*4882a593Smuzhiyun else
461*4882a593Smuzhiyun u8tmp = 0x10;
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x1a, u8tmp);
464*4882a593Smuzhiyun if (ret)
465*4882a593Smuzhiyun goto err;
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun if (dev->if_gain_auto->val == false) {
468*4882a593Smuzhiyun buf[0] = e4000_if_gain_lut[dev->if_gain->val].reg16_val;
469*4882a593Smuzhiyun buf[1] = e4000_if_gain_lut[dev->if_gain->val].reg17_val;
470*4882a593Smuzhiyun ret = regmap_bulk_write(dev->regmap, 0x16, buf, 2);
471*4882a593Smuzhiyun if (ret)
472*4882a593Smuzhiyun goto err;
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun return 0;
476*4882a593Smuzhiyun err:
477*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
478*4882a593Smuzhiyun return ret;
479*4882a593Smuzhiyun }
480*4882a593Smuzhiyun
e4000_pll_lock(struct dvb_frontend * fe)481*4882a593Smuzhiyun static int e4000_pll_lock(struct dvb_frontend *fe)
482*4882a593Smuzhiyun {
483*4882a593Smuzhiyun struct e4000_dev *dev = fe->tuner_priv;
484*4882a593Smuzhiyun struct i2c_client *client = dev->client;
485*4882a593Smuzhiyun int ret;
486*4882a593Smuzhiyun unsigned int uitmp;
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun ret = regmap_read(dev->regmap, 0x07, &uitmp);
489*4882a593Smuzhiyun if (ret)
490*4882a593Smuzhiyun goto err;
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun dev->pll_lock->val = (uitmp & 0x01);
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun return 0;
495*4882a593Smuzhiyun err:
496*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
497*4882a593Smuzhiyun return ret;
498*4882a593Smuzhiyun }
499*4882a593Smuzhiyun
e4000_g_volatile_ctrl(struct v4l2_ctrl * ctrl)500*4882a593Smuzhiyun static int e4000_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
501*4882a593Smuzhiyun {
502*4882a593Smuzhiyun struct e4000_dev *dev = container_of(ctrl->handler, struct e4000_dev, hdl);
503*4882a593Smuzhiyun struct i2c_client *client = dev->client;
504*4882a593Smuzhiyun int ret;
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun if (!dev->active)
507*4882a593Smuzhiyun return 0;
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun switch (ctrl->id) {
510*4882a593Smuzhiyun case V4L2_CID_RF_TUNER_PLL_LOCK:
511*4882a593Smuzhiyun ret = e4000_pll_lock(dev->fe);
512*4882a593Smuzhiyun break;
513*4882a593Smuzhiyun default:
514*4882a593Smuzhiyun dev_dbg(&client->dev, "unknown ctrl: id=%d name=%s\n",
515*4882a593Smuzhiyun ctrl->id, ctrl->name);
516*4882a593Smuzhiyun ret = -EINVAL;
517*4882a593Smuzhiyun }
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun return ret;
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun
e4000_s_ctrl(struct v4l2_ctrl * ctrl)522*4882a593Smuzhiyun static int e4000_s_ctrl(struct v4l2_ctrl *ctrl)
523*4882a593Smuzhiyun {
524*4882a593Smuzhiyun struct e4000_dev *dev = container_of(ctrl->handler, struct e4000_dev, hdl);
525*4882a593Smuzhiyun struct i2c_client *client = dev->client;
526*4882a593Smuzhiyun int ret;
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun if (!dev->active)
529*4882a593Smuzhiyun return 0;
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun switch (ctrl->id) {
532*4882a593Smuzhiyun case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO:
533*4882a593Smuzhiyun case V4L2_CID_RF_TUNER_BANDWIDTH:
534*4882a593Smuzhiyun /*
535*4882a593Smuzhiyun * TODO: Auto logic does not work 100% correctly as tuner driver
536*4882a593Smuzhiyun * do not have information to calculate maximum suitable
537*4882a593Smuzhiyun * bandwidth. Calculating it is responsible of master driver.
538*4882a593Smuzhiyun */
539*4882a593Smuzhiyun dev->f_bandwidth = dev->bandwidth->val;
540*4882a593Smuzhiyun ret = e4000_set_params(dev);
541*4882a593Smuzhiyun break;
542*4882a593Smuzhiyun case V4L2_CID_RF_TUNER_LNA_GAIN_AUTO:
543*4882a593Smuzhiyun case V4L2_CID_RF_TUNER_LNA_GAIN:
544*4882a593Smuzhiyun ret = e4000_set_lna_gain(dev->fe);
545*4882a593Smuzhiyun break;
546*4882a593Smuzhiyun case V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO:
547*4882a593Smuzhiyun case V4L2_CID_RF_TUNER_MIXER_GAIN:
548*4882a593Smuzhiyun ret = e4000_set_mixer_gain(dev->fe);
549*4882a593Smuzhiyun break;
550*4882a593Smuzhiyun case V4L2_CID_RF_TUNER_IF_GAIN_AUTO:
551*4882a593Smuzhiyun case V4L2_CID_RF_TUNER_IF_GAIN:
552*4882a593Smuzhiyun ret = e4000_set_if_gain(dev->fe);
553*4882a593Smuzhiyun break;
554*4882a593Smuzhiyun default:
555*4882a593Smuzhiyun dev_dbg(&client->dev, "unknown ctrl: id=%d name=%s\n",
556*4882a593Smuzhiyun ctrl->id, ctrl->name);
557*4882a593Smuzhiyun ret = -EINVAL;
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun return ret;
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun static const struct v4l2_ctrl_ops e4000_ctrl_ops = {
564*4882a593Smuzhiyun .g_volatile_ctrl = e4000_g_volatile_ctrl,
565*4882a593Smuzhiyun .s_ctrl = e4000_s_ctrl,
566*4882a593Smuzhiyun };
567*4882a593Smuzhiyun #endif
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun /*
570*4882a593Smuzhiyun * DVB API
571*4882a593Smuzhiyun */
e4000_dvb_set_params(struct dvb_frontend * fe)572*4882a593Smuzhiyun static int e4000_dvb_set_params(struct dvb_frontend *fe)
573*4882a593Smuzhiyun {
574*4882a593Smuzhiyun struct e4000_dev *dev = fe->tuner_priv;
575*4882a593Smuzhiyun struct dtv_frontend_properties *c = &fe->dtv_property_cache;
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun dev->f_frequency = c->frequency;
578*4882a593Smuzhiyun dev->f_bandwidth = c->bandwidth_hz;
579*4882a593Smuzhiyun return e4000_set_params(dev);
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun
e4000_dvb_init(struct dvb_frontend * fe)582*4882a593Smuzhiyun static int e4000_dvb_init(struct dvb_frontend *fe)
583*4882a593Smuzhiyun {
584*4882a593Smuzhiyun return e4000_init(fe->tuner_priv);
585*4882a593Smuzhiyun }
586*4882a593Smuzhiyun
e4000_dvb_sleep(struct dvb_frontend * fe)587*4882a593Smuzhiyun static int e4000_dvb_sleep(struct dvb_frontend *fe)
588*4882a593Smuzhiyun {
589*4882a593Smuzhiyun return e4000_sleep(fe->tuner_priv);
590*4882a593Smuzhiyun }
591*4882a593Smuzhiyun
e4000_dvb_get_if_frequency(struct dvb_frontend * fe,u32 * frequency)592*4882a593Smuzhiyun static int e4000_dvb_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
593*4882a593Smuzhiyun {
594*4882a593Smuzhiyun *frequency = 0; /* Zero-IF */
595*4882a593Smuzhiyun return 0;
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun static const struct dvb_tuner_ops e4000_dvb_tuner_ops = {
599*4882a593Smuzhiyun .info = {
600*4882a593Smuzhiyun .name = "Elonics E4000",
601*4882a593Smuzhiyun .frequency_min_hz = 174 * MHz,
602*4882a593Smuzhiyun .frequency_max_hz = 862 * MHz,
603*4882a593Smuzhiyun },
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun .init = e4000_dvb_init,
606*4882a593Smuzhiyun .sleep = e4000_dvb_sleep,
607*4882a593Smuzhiyun .set_params = e4000_dvb_set_params,
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun .get_if_frequency = e4000_dvb_get_if_frequency,
610*4882a593Smuzhiyun };
611*4882a593Smuzhiyun
e4000_probe(struct i2c_client * client,const struct i2c_device_id * id)612*4882a593Smuzhiyun static int e4000_probe(struct i2c_client *client,
613*4882a593Smuzhiyun const struct i2c_device_id *id)
614*4882a593Smuzhiyun {
615*4882a593Smuzhiyun struct e4000_dev *dev;
616*4882a593Smuzhiyun struct e4000_config *cfg = client->dev.platform_data;
617*4882a593Smuzhiyun struct dvb_frontend *fe = cfg->fe;
618*4882a593Smuzhiyun int ret;
619*4882a593Smuzhiyun unsigned int uitmp;
620*4882a593Smuzhiyun static const struct regmap_config regmap_config = {
621*4882a593Smuzhiyun .reg_bits = 8,
622*4882a593Smuzhiyun .val_bits = 8,
623*4882a593Smuzhiyun };
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun dev = kzalloc(sizeof(*dev), GFP_KERNEL);
626*4882a593Smuzhiyun if (!dev) {
627*4882a593Smuzhiyun ret = -ENOMEM;
628*4882a593Smuzhiyun goto err;
629*4882a593Smuzhiyun }
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun dev->clk = cfg->clock;
632*4882a593Smuzhiyun dev->client = client;
633*4882a593Smuzhiyun dev->fe = cfg->fe;
634*4882a593Smuzhiyun dev->regmap = devm_regmap_init_i2c(client, ®map_config);
635*4882a593Smuzhiyun if (IS_ERR(dev->regmap)) {
636*4882a593Smuzhiyun ret = PTR_ERR(dev->regmap);
637*4882a593Smuzhiyun goto err_kfree;
638*4882a593Smuzhiyun }
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun /* check if the tuner is there */
641*4882a593Smuzhiyun ret = regmap_read(dev->regmap, 0x02, &uitmp);
642*4882a593Smuzhiyun if (ret)
643*4882a593Smuzhiyun goto err_kfree;
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun dev_dbg(&client->dev, "chip id=%02x\n", uitmp);
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun if (uitmp != 0x40) {
648*4882a593Smuzhiyun ret = -ENODEV;
649*4882a593Smuzhiyun goto err_kfree;
650*4882a593Smuzhiyun }
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun /* put sleep as chip seems to be in normal mode by default */
653*4882a593Smuzhiyun ret = regmap_write(dev->regmap, 0x00, 0x00);
654*4882a593Smuzhiyun if (ret)
655*4882a593Smuzhiyun goto err_kfree;
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_VIDEO_V4L2)
658*4882a593Smuzhiyun /* Register controls */
659*4882a593Smuzhiyun v4l2_ctrl_handler_init(&dev->hdl, 9);
660*4882a593Smuzhiyun dev->bandwidth_auto = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
661*4882a593Smuzhiyun V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1);
662*4882a593Smuzhiyun dev->bandwidth = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
663*4882a593Smuzhiyun V4L2_CID_RF_TUNER_BANDWIDTH, 4300000, 11000000, 100000, 4300000);
664*4882a593Smuzhiyun v4l2_ctrl_auto_cluster(2, &dev->bandwidth_auto, 0, false);
665*4882a593Smuzhiyun dev->lna_gain_auto = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
666*4882a593Smuzhiyun V4L2_CID_RF_TUNER_LNA_GAIN_AUTO, 0, 1, 1, 1);
667*4882a593Smuzhiyun dev->lna_gain = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
668*4882a593Smuzhiyun V4L2_CID_RF_TUNER_LNA_GAIN, 0, 15, 1, 10);
669*4882a593Smuzhiyun v4l2_ctrl_auto_cluster(2, &dev->lna_gain_auto, 0, false);
670*4882a593Smuzhiyun dev->mixer_gain_auto = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
671*4882a593Smuzhiyun V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO, 0, 1, 1, 1);
672*4882a593Smuzhiyun dev->mixer_gain = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
673*4882a593Smuzhiyun V4L2_CID_RF_TUNER_MIXER_GAIN, 0, 1, 1, 1);
674*4882a593Smuzhiyun v4l2_ctrl_auto_cluster(2, &dev->mixer_gain_auto, 0, false);
675*4882a593Smuzhiyun dev->if_gain_auto = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
676*4882a593Smuzhiyun V4L2_CID_RF_TUNER_IF_GAIN_AUTO, 0, 1, 1, 1);
677*4882a593Smuzhiyun dev->if_gain = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
678*4882a593Smuzhiyun V4L2_CID_RF_TUNER_IF_GAIN, 0, 54, 1, 0);
679*4882a593Smuzhiyun v4l2_ctrl_auto_cluster(2, &dev->if_gain_auto, 0, false);
680*4882a593Smuzhiyun dev->pll_lock = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
681*4882a593Smuzhiyun V4L2_CID_RF_TUNER_PLL_LOCK, 0, 1, 1, 0);
682*4882a593Smuzhiyun if (dev->hdl.error) {
683*4882a593Smuzhiyun ret = dev->hdl.error;
684*4882a593Smuzhiyun dev_err(&client->dev, "Could not initialize controls\n");
685*4882a593Smuzhiyun v4l2_ctrl_handler_free(&dev->hdl);
686*4882a593Smuzhiyun goto err_kfree;
687*4882a593Smuzhiyun }
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun dev->sd.ctrl_handler = &dev->hdl;
690*4882a593Smuzhiyun dev->f_frequency = bands[0].rangelow;
691*4882a593Smuzhiyun dev->f_bandwidth = dev->bandwidth->val;
692*4882a593Smuzhiyun v4l2_i2c_subdev_init(&dev->sd, client, &e4000_subdev_ops);
693*4882a593Smuzhiyun #endif
694*4882a593Smuzhiyun fe->tuner_priv = dev;
695*4882a593Smuzhiyun memcpy(&fe->ops.tuner_ops, &e4000_dvb_tuner_ops,
696*4882a593Smuzhiyun sizeof(fe->ops.tuner_ops));
697*4882a593Smuzhiyun v4l2_set_subdevdata(&dev->sd, client);
698*4882a593Smuzhiyun i2c_set_clientdata(client, &dev->sd);
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun dev_info(&client->dev, "Elonics E4000 successfully identified\n");
701*4882a593Smuzhiyun return 0;
702*4882a593Smuzhiyun err_kfree:
703*4882a593Smuzhiyun kfree(dev);
704*4882a593Smuzhiyun err:
705*4882a593Smuzhiyun dev_dbg(&client->dev, "failed=%d\n", ret);
706*4882a593Smuzhiyun return ret;
707*4882a593Smuzhiyun }
708*4882a593Smuzhiyun
e4000_remove(struct i2c_client * client)709*4882a593Smuzhiyun static int e4000_remove(struct i2c_client *client)
710*4882a593Smuzhiyun {
711*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
712*4882a593Smuzhiyun struct e4000_dev *dev = container_of(sd, struct e4000_dev, sd);
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun dev_dbg(&client->dev, "\n");
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_VIDEO_V4L2)
717*4882a593Smuzhiyun v4l2_ctrl_handler_free(&dev->hdl);
718*4882a593Smuzhiyun #endif
719*4882a593Smuzhiyun kfree(dev);
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun return 0;
722*4882a593Smuzhiyun }
723*4882a593Smuzhiyun
724*4882a593Smuzhiyun static const struct i2c_device_id e4000_id_table[] = {
725*4882a593Smuzhiyun {"e4000", 0},
726*4882a593Smuzhiyun {}
727*4882a593Smuzhiyun };
728*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, e4000_id_table);
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun static struct i2c_driver e4000_driver = {
731*4882a593Smuzhiyun .driver = {
732*4882a593Smuzhiyun .name = "e4000",
733*4882a593Smuzhiyun .suppress_bind_attrs = true,
734*4882a593Smuzhiyun },
735*4882a593Smuzhiyun .probe = e4000_probe,
736*4882a593Smuzhiyun .remove = e4000_remove,
737*4882a593Smuzhiyun .id_table = e4000_id_table,
738*4882a593Smuzhiyun };
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun module_i2c_driver(e4000_driver);
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun MODULE_DESCRIPTION("Elonics E4000 silicon tuner driver");
743*4882a593Smuzhiyun MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
744*4882a593Smuzhiyun MODULE_LICENSE("GPL");
745