1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2017 Sanechips Technology Co., Ltd.
4*4882a593Smuzhiyun * Copyright 2017 Linaro Ltd.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/device.h>
8*4882a593Smuzhiyun #include <linux/err.h>
9*4882a593Smuzhiyun #include <linux/interrupt.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/of_platform.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <media/rc-core.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define DRIVER_NAME "zx-irdec"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define ZX_IR_ENABLE 0x04
20*4882a593Smuzhiyun #define ZX_IREN BIT(0)
21*4882a593Smuzhiyun #define ZX_IR_CTRL 0x08
22*4882a593Smuzhiyun #define ZX_DEGL_MASK GENMASK(21, 20)
23*4882a593Smuzhiyun #define ZX_DEGL_VALUE(x) (((x) << 20) & ZX_DEGL_MASK)
24*4882a593Smuzhiyun #define ZX_WDBEGIN_MASK GENMASK(18, 8)
25*4882a593Smuzhiyun #define ZX_WDBEGIN_VALUE(x) (((x) << 8) & ZX_WDBEGIN_MASK)
26*4882a593Smuzhiyun #define ZX_IR_INTEN 0x10
27*4882a593Smuzhiyun #define ZX_IR_INTSTCLR 0x14
28*4882a593Smuzhiyun #define ZX_IR_CODE 0x30
29*4882a593Smuzhiyun #define ZX_IR_CNUM 0x34
30*4882a593Smuzhiyun #define ZX_NECRPT BIT(16)
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun struct zx_irdec {
33*4882a593Smuzhiyun void __iomem *base;
34*4882a593Smuzhiyun struct rc_dev *rcd;
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
zx_irdec_set_mask(struct zx_irdec * irdec,unsigned int reg,u32 mask,u32 value)37*4882a593Smuzhiyun static void zx_irdec_set_mask(struct zx_irdec *irdec, unsigned int reg,
38*4882a593Smuzhiyun u32 mask, u32 value)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun u32 data;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun data = readl(irdec->base + reg);
43*4882a593Smuzhiyun data &= ~mask;
44*4882a593Smuzhiyun data |= value & mask;
45*4882a593Smuzhiyun writel(data, irdec->base + reg);
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
zx_irdec_irq(int irq,void * dev_id)48*4882a593Smuzhiyun static irqreturn_t zx_irdec_irq(int irq, void *dev_id)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun struct zx_irdec *irdec = dev_id;
51*4882a593Smuzhiyun u8 address, not_address;
52*4882a593Smuzhiyun u8 command, not_command;
53*4882a593Smuzhiyun u32 rawcode, scancode;
54*4882a593Smuzhiyun enum rc_proto rc_proto;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* Clear interrupt */
57*4882a593Smuzhiyun writel(1, irdec->base + ZX_IR_INTSTCLR);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* Check repeat frame */
60*4882a593Smuzhiyun if (readl(irdec->base + ZX_IR_CNUM) & ZX_NECRPT) {
61*4882a593Smuzhiyun rc_repeat(irdec->rcd);
62*4882a593Smuzhiyun goto done;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun rawcode = readl(irdec->base + ZX_IR_CODE);
66*4882a593Smuzhiyun not_command = (rawcode >> 24) & 0xff;
67*4882a593Smuzhiyun command = (rawcode >> 16) & 0xff;
68*4882a593Smuzhiyun not_address = (rawcode >> 8) & 0xff;
69*4882a593Smuzhiyun address = rawcode & 0xff;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun scancode = ir_nec_bytes_to_scancode(address, not_address,
72*4882a593Smuzhiyun command, not_command,
73*4882a593Smuzhiyun &rc_proto);
74*4882a593Smuzhiyun rc_keydown(irdec->rcd, rc_proto, scancode, 0);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun done:
77*4882a593Smuzhiyun return IRQ_HANDLED;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
zx_irdec_probe(struct platform_device * pdev)80*4882a593Smuzhiyun static int zx_irdec_probe(struct platform_device *pdev)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun struct device *dev = &pdev->dev;
83*4882a593Smuzhiyun struct zx_irdec *irdec;
84*4882a593Smuzhiyun struct resource *res;
85*4882a593Smuzhiyun struct rc_dev *rcd;
86*4882a593Smuzhiyun int irq;
87*4882a593Smuzhiyun int ret;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun irdec = devm_kzalloc(dev, sizeof(*irdec), GFP_KERNEL);
90*4882a593Smuzhiyun if (!irdec)
91*4882a593Smuzhiyun return -ENOMEM;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
94*4882a593Smuzhiyun irdec->base = devm_ioremap_resource(dev, res);
95*4882a593Smuzhiyun if (IS_ERR(irdec->base))
96*4882a593Smuzhiyun return PTR_ERR(irdec->base);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun irq = platform_get_irq(pdev, 0);
99*4882a593Smuzhiyun if (irq < 0)
100*4882a593Smuzhiyun return irq;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun rcd = devm_rc_allocate_device(dev, RC_DRIVER_SCANCODE);
103*4882a593Smuzhiyun if (!rcd) {
104*4882a593Smuzhiyun dev_err(dev, "failed to allocate rc device\n");
105*4882a593Smuzhiyun return -ENOMEM;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun irdec->rcd = rcd;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun rcd->priv = irdec;
111*4882a593Smuzhiyun rcd->input_phys = DRIVER_NAME "/input0";
112*4882a593Smuzhiyun rcd->input_id.bustype = BUS_HOST;
113*4882a593Smuzhiyun rcd->map_name = RC_MAP_ZX_IRDEC;
114*4882a593Smuzhiyun rcd->allowed_protocols = RC_PROTO_BIT_NEC | RC_PROTO_BIT_NECX |
115*4882a593Smuzhiyun RC_PROTO_BIT_NEC32;
116*4882a593Smuzhiyun rcd->driver_name = DRIVER_NAME;
117*4882a593Smuzhiyun rcd->device_name = DRIVER_NAME;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun platform_set_drvdata(pdev, irdec);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun ret = devm_rc_register_device(dev, rcd);
122*4882a593Smuzhiyun if (ret) {
123*4882a593Smuzhiyun dev_err(dev, "failed to register rc device\n");
124*4882a593Smuzhiyun return ret;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun ret = devm_request_irq(dev, irq, zx_irdec_irq, 0, NULL, irdec);
128*4882a593Smuzhiyun if (ret) {
129*4882a593Smuzhiyun dev_err(dev, "failed to request irq\n");
130*4882a593Smuzhiyun return ret;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /*
134*4882a593Smuzhiyun * Initialize deglitch level and watchdog counter beginner as
135*4882a593Smuzhiyun * recommended by vendor BSP code.
136*4882a593Smuzhiyun */
137*4882a593Smuzhiyun zx_irdec_set_mask(irdec, ZX_IR_CTRL, ZX_DEGL_MASK, ZX_DEGL_VALUE(0));
138*4882a593Smuzhiyun zx_irdec_set_mask(irdec, ZX_IR_CTRL, ZX_WDBEGIN_MASK,
139*4882a593Smuzhiyun ZX_WDBEGIN_VALUE(0x21c));
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun /* Enable interrupt */
142*4882a593Smuzhiyun writel(1, irdec->base + ZX_IR_INTEN);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun /* Enable the decoder */
145*4882a593Smuzhiyun zx_irdec_set_mask(irdec, ZX_IR_ENABLE, ZX_IREN, ZX_IREN);
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun return 0;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
zx_irdec_remove(struct platform_device * pdev)150*4882a593Smuzhiyun static int zx_irdec_remove(struct platform_device *pdev)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun struct zx_irdec *irdec = platform_get_drvdata(pdev);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun /* Disable the decoder */
155*4882a593Smuzhiyun zx_irdec_set_mask(irdec, ZX_IR_ENABLE, ZX_IREN, 0);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /* Disable interrupt */
158*4882a593Smuzhiyun writel(0, irdec->base + ZX_IR_INTEN);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun return 0;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun static const struct of_device_id zx_irdec_match[] = {
164*4882a593Smuzhiyun { .compatible = "zte,zx296718-irdec" },
165*4882a593Smuzhiyun { },
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, zx_irdec_match);
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun static struct platform_driver zx_irdec_driver = {
170*4882a593Smuzhiyun .probe = zx_irdec_probe,
171*4882a593Smuzhiyun .remove = zx_irdec_remove,
172*4882a593Smuzhiyun .driver = {
173*4882a593Smuzhiyun .name = DRIVER_NAME,
174*4882a593Smuzhiyun .of_match_table = zx_irdec_match,
175*4882a593Smuzhiyun },
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun module_platform_driver(zx_irdec_driver);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun MODULE_DESCRIPTION("ZTE ZX IR remote control driver");
180*4882a593Smuzhiyun MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
181*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
182