xref: /OK3568_Linux_fs/kernel/drivers/media/rc/tango-ir.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2015 Mans Rullgard <mans@mansr.com>
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/input.h>
7*4882a593Smuzhiyun #include <linux/module.h>
8*4882a593Smuzhiyun #include <linux/platform_device.h>
9*4882a593Smuzhiyun #include <linux/interrupt.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/clk.h>
12*4882a593Smuzhiyun #include <linux/of.h>
13*4882a593Smuzhiyun #include <media/rc-core.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define DRIVER_NAME "tango-ir"
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #define IR_NEC_CTRL	0x00
18*4882a593Smuzhiyun #define IR_NEC_DATA	0x04
19*4882a593Smuzhiyun #define IR_CTRL		0x08
20*4882a593Smuzhiyun #define IR_RC5_CLK_DIV	0x0c
21*4882a593Smuzhiyun #define IR_RC5_DATA	0x10
22*4882a593Smuzhiyun #define IR_INT		0x14
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #define NEC_TIME_BASE	560
25*4882a593Smuzhiyun #define RC5_TIME_BASE	1778
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define RC6_CTRL	0x00
28*4882a593Smuzhiyun #define RC6_CLKDIV	0x04
29*4882a593Smuzhiyun #define RC6_DATA0	0x08
30*4882a593Smuzhiyun #define RC6_DATA1	0x0c
31*4882a593Smuzhiyun #define RC6_DATA2	0x10
32*4882a593Smuzhiyun #define RC6_DATA3	0x14
33*4882a593Smuzhiyun #define RC6_DATA4	0x18
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #define RC6_CARRIER	36000
36*4882a593Smuzhiyun #define RC6_TIME_BASE	16
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define NEC_CAP(n)	((n) << 24)
39*4882a593Smuzhiyun #define GPIO_SEL(n)	((n) << 16)
40*4882a593Smuzhiyun #define DISABLE_NEC	(BIT(4) | BIT(8))
41*4882a593Smuzhiyun #define ENABLE_RC5	(BIT(0) | BIT(9))
42*4882a593Smuzhiyun #define ENABLE_RC6	(BIT(0) | BIT(7))
43*4882a593Smuzhiyun #define ACK_IR_INT	(BIT(0) | BIT(1))
44*4882a593Smuzhiyun #define ACK_RC6_INT	(BIT(31))
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun #define NEC_ANY (RC_PROTO_BIT_NEC | RC_PROTO_BIT_NECX | RC_PROTO_BIT_NEC32)
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun struct tango_ir {
49*4882a593Smuzhiyun 	void __iomem *rc5_base;
50*4882a593Smuzhiyun 	void __iomem *rc6_base;
51*4882a593Smuzhiyun 	struct rc_dev *rc;
52*4882a593Smuzhiyun 	struct clk *clk;
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun 
tango_ir_handle_nec(struct tango_ir * ir)55*4882a593Smuzhiyun static void tango_ir_handle_nec(struct tango_ir *ir)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun 	u32 v, code;
58*4882a593Smuzhiyun 	enum rc_proto proto;
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	v = readl_relaxed(ir->rc5_base + IR_NEC_DATA);
61*4882a593Smuzhiyun 	if (!v) {
62*4882a593Smuzhiyun 		rc_repeat(ir->rc);
63*4882a593Smuzhiyun 		return;
64*4882a593Smuzhiyun 	}
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	code = ir_nec_bytes_to_scancode(v, v >> 8, v >> 16, v >> 24, &proto);
67*4882a593Smuzhiyun 	rc_keydown(ir->rc, proto, code, 0);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun 
tango_ir_handle_rc5(struct tango_ir * ir)70*4882a593Smuzhiyun static void tango_ir_handle_rc5(struct tango_ir *ir)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun 	u32 data, field, toggle, addr, cmd, code;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	data = readl_relaxed(ir->rc5_base + IR_RC5_DATA);
75*4882a593Smuzhiyun 	if (data & BIT(31))
76*4882a593Smuzhiyun 		return;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	field = data >> 12 & 1;
79*4882a593Smuzhiyun 	toggle = data >> 11 & 1;
80*4882a593Smuzhiyun 	addr = data >> 6 & 0x1f;
81*4882a593Smuzhiyun 	cmd = (data & 0x3f) | (field ^ 1) << 6;
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	code = RC_SCANCODE_RC5(addr, cmd);
84*4882a593Smuzhiyun 	rc_keydown(ir->rc, RC_PROTO_RC5, code, toggle);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun 
tango_ir_handle_rc6(struct tango_ir * ir)87*4882a593Smuzhiyun static void tango_ir_handle_rc6(struct tango_ir *ir)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun 	u32 data0, data1, toggle, mode, addr, cmd, code;
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	data0 = readl_relaxed(ir->rc6_base + RC6_DATA0);
92*4882a593Smuzhiyun 	data1 = readl_relaxed(ir->rc6_base + RC6_DATA1);
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	mode = data0 >> 1 & 7;
95*4882a593Smuzhiyun 	if (mode != 0)
96*4882a593Smuzhiyun 		return;
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	toggle = data0 & 1;
99*4882a593Smuzhiyun 	addr = data0 >> 16;
100*4882a593Smuzhiyun 	cmd = data1;
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	code = RC_SCANCODE_RC6_0(addr, cmd);
103*4882a593Smuzhiyun 	rc_keydown(ir->rc, RC_PROTO_RC6_0, code, toggle);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun 
tango_ir_irq(int irq,void * dev_id)106*4882a593Smuzhiyun static irqreturn_t tango_ir_irq(int irq, void *dev_id)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun 	struct tango_ir *ir = dev_id;
109*4882a593Smuzhiyun 	unsigned int rc5_stat;
110*4882a593Smuzhiyun 	unsigned int rc6_stat;
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	rc5_stat = readl_relaxed(ir->rc5_base + IR_INT);
113*4882a593Smuzhiyun 	writel_relaxed(rc5_stat, ir->rc5_base + IR_INT);
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	rc6_stat = readl_relaxed(ir->rc6_base + RC6_CTRL);
116*4882a593Smuzhiyun 	writel_relaxed(rc6_stat, ir->rc6_base + RC6_CTRL);
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	if (!(rc5_stat & 3) && !(rc6_stat & BIT(31)))
119*4882a593Smuzhiyun 		return IRQ_NONE;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	if (rc5_stat & BIT(0))
122*4882a593Smuzhiyun 		tango_ir_handle_rc5(ir);
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	if (rc5_stat & BIT(1))
125*4882a593Smuzhiyun 		tango_ir_handle_nec(ir);
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	if (rc6_stat & BIT(31))
128*4882a593Smuzhiyun 		tango_ir_handle_rc6(ir);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	return IRQ_HANDLED;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
tango_change_protocol(struct rc_dev * dev,u64 * rc_type)133*4882a593Smuzhiyun static int tango_change_protocol(struct rc_dev *dev, u64 *rc_type)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun 	struct tango_ir *ir = dev->priv;
136*4882a593Smuzhiyun 	u32 rc5_ctrl = DISABLE_NEC;
137*4882a593Smuzhiyun 	u32 rc6_ctrl = 0;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	if (*rc_type & NEC_ANY)
140*4882a593Smuzhiyun 		rc5_ctrl = 0;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	if (*rc_type & RC_PROTO_BIT_RC5)
143*4882a593Smuzhiyun 		rc5_ctrl |= ENABLE_RC5;
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	if (*rc_type & RC_PROTO_BIT_RC6_0)
146*4882a593Smuzhiyun 		rc6_ctrl = ENABLE_RC6;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	writel_relaxed(rc5_ctrl, ir->rc5_base + IR_CTRL);
149*4882a593Smuzhiyun 	writel_relaxed(rc6_ctrl, ir->rc6_base + RC6_CTRL);
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	return 0;
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun 
tango_ir_probe(struct platform_device * pdev)154*4882a593Smuzhiyun static int tango_ir_probe(struct platform_device *pdev)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun 	const char *map_name = RC_MAP_TANGO;
157*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
158*4882a593Smuzhiyun 	struct rc_dev *rc;
159*4882a593Smuzhiyun 	struct tango_ir *ir;
160*4882a593Smuzhiyun 	u64 clkrate, clkdiv;
161*4882a593Smuzhiyun 	int irq, err;
162*4882a593Smuzhiyun 	u32 val;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	irq = platform_get_irq(pdev, 0);
165*4882a593Smuzhiyun 	if (irq <= 0)
166*4882a593Smuzhiyun 		return -EINVAL;
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	ir = devm_kzalloc(dev, sizeof(*ir), GFP_KERNEL);
169*4882a593Smuzhiyun 	if (!ir)
170*4882a593Smuzhiyun 		return -ENOMEM;
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	ir->rc5_base = devm_platform_ioremap_resource(pdev, 0);
173*4882a593Smuzhiyun 	if (IS_ERR(ir->rc5_base))
174*4882a593Smuzhiyun 		return PTR_ERR(ir->rc5_base);
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	ir->rc6_base = devm_platform_ioremap_resource(pdev, 1);
177*4882a593Smuzhiyun 	if (IS_ERR(ir->rc6_base))
178*4882a593Smuzhiyun 		return PTR_ERR(ir->rc6_base);
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	ir->clk = devm_clk_get(dev, NULL);
181*4882a593Smuzhiyun 	if (IS_ERR(ir->clk))
182*4882a593Smuzhiyun 		return PTR_ERR(ir->clk);
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	rc = devm_rc_allocate_device(dev, RC_DRIVER_SCANCODE);
185*4882a593Smuzhiyun 	if (!rc)
186*4882a593Smuzhiyun 		return -ENOMEM;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	of_property_read_string(dev->of_node, "linux,rc-map-name", &map_name);
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	rc->device_name = DRIVER_NAME;
191*4882a593Smuzhiyun 	rc->driver_name = DRIVER_NAME;
192*4882a593Smuzhiyun 	rc->input_phys = DRIVER_NAME "/input0";
193*4882a593Smuzhiyun 	rc->map_name = map_name;
194*4882a593Smuzhiyun 	rc->allowed_protocols = NEC_ANY | RC_PROTO_BIT_RC5 | RC_PROTO_BIT_RC6_0;
195*4882a593Smuzhiyun 	rc->change_protocol = tango_change_protocol;
196*4882a593Smuzhiyun 	rc->priv = ir;
197*4882a593Smuzhiyun 	ir->rc = rc;
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	err = clk_prepare_enable(ir->clk);
200*4882a593Smuzhiyun 	if (err)
201*4882a593Smuzhiyun 		return err;
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	clkrate = clk_get_rate(ir->clk);
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	clkdiv = clkrate * NEC_TIME_BASE;
206*4882a593Smuzhiyun 	do_div(clkdiv, 1000000);
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	val = NEC_CAP(31) | GPIO_SEL(12) | clkdiv;
209*4882a593Smuzhiyun 	writel_relaxed(val, ir->rc5_base + IR_NEC_CTRL);
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	clkdiv = clkrate * RC5_TIME_BASE;
212*4882a593Smuzhiyun 	do_div(clkdiv, 1000000);
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	writel_relaxed(DISABLE_NEC, ir->rc5_base + IR_CTRL);
215*4882a593Smuzhiyun 	writel_relaxed(clkdiv, ir->rc5_base + IR_RC5_CLK_DIV);
216*4882a593Smuzhiyun 	writel_relaxed(ACK_IR_INT, ir->rc5_base + IR_INT);
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	clkdiv = clkrate * RC6_TIME_BASE;
219*4882a593Smuzhiyun 	do_div(clkdiv, RC6_CARRIER);
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	writel_relaxed(ACK_RC6_INT, ir->rc6_base + RC6_CTRL);
222*4882a593Smuzhiyun 	writel_relaxed((clkdiv >> 2) << 18 | clkdiv, ir->rc6_base + RC6_CLKDIV);
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	err = devm_request_irq(dev, irq, tango_ir_irq, IRQF_SHARED,
225*4882a593Smuzhiyun 			       dev_name(dev), ir);
226*4882a593Smuzhiyun 	if (err)
227*4882a593Smuzhiyun 		goto err_clk;
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	err = devm_rc_register_device(dev, rc);
230*4882a593Smuzhiyun 	if (err)
231*4882a593Smuzhiyun 		goto err_clk;
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	platform_set_drvdata(pdev, ir);
234*4882a593Smuzhiyun 	return 0;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun err_clk:
237*4882a593Smuzhiyun 	clk_disable_unprepare(ir->clk);
238*4882a593Smuzhiyun 	return err;
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun 
tango_ir_remove(struct platform_device * pdev)241*4882a593Smuzhiyun static int tango_ir_remove(struct platform_device *pdev)
242*4882a593Smuzhiyun {
243*4882a593Smuzhiyun 	struct tango_ir *ir = platform_get_drvdata(pdev);
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	clk_disable_unprepare(ir->clk);
246*4882a593Smuzhiyun 	return 0;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun static const struct of_device_id tango_ir_dt_ids[] = {
250*4882a593Smuzhiyun 	{ .compatible = "sigma,smp8642-ir" },
251*4882a593Smuzhiyun 	{ }
252*4882a593Smuzhiyun };
253*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, tango_ir_dt_ids);
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun static struct platform_driver tango_ir_driver = {
256*4882a593Smuzhiyun 	.probe	= tango_ir_probe,
257*4882a593Smuzhiyun 	.remove	= tango_ir_remove,
258*4882a593Smuzhiyun 	.driver	= {
259*4882a593Smuzhiyun 		.name		= DRIVER_NAME,
260*4882a593Smuzhiyun 		.of_match_table	= tango_ir_dt_ids,
261*4882a593Smuzhiyun 	},
262*4882a593Smuzhiyun };
263*4882a593Smuzhiyun module_platform_driver(tango_ir_driver);
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun MODULE_DESCRIPTION("SMP86xx IR decoder driver");
266*4882a593Smuzhiyun MODULE_AUTHOR("Mans Rullgard <mans@mansr.com>");
267*4882a593Smuzhiyun MODULE_LICENSE("GPL");
268