1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for Amlogic Meson IR remote receiver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/device.h>
9*4882a593Smuzhiyun #include <linux/err.h>
10*4882a593Smuzhiyun #include <linux/interrupt.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/of_platform.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/spinlock.h>
16*4882a593Smuzhiyun #include <linux/bitfield.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <media/rc-core.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define DRIVER_NAME "meson-ir"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* valid on all Meson platforms */
23*4882a593Smuzhiyun #define IR_DEC_LDR_ACTIVE 0x00
24*4882a593Smuzhiyun #define IR_DEC_LDR_IDLE 0x04
25*4882a593Smuzhiyun #define IR_DEC_LDR_REPEAT 0x08
26*4882a593Smuzhiyun #define IR_DEC_BIT_0 0x0c
27*4882a593Smuzhiyun #define IR_DEC_REG0 0x10
28*4882a593Smuzhiyun #define IR_DEC_FRAME 0x14
29*4882a593Smuzhiyun #define IR_DEC_STATUS 0x18
30*4882a593Smuzhiyun #define IR_DEC_REG1 0x1c
31*4882a593Smuzhiyun /* only available on Meson 8b and newer */
32*4882a593Smuzhiyun #define IR_DEC_REG2 0x20
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define REG0_RATE_MASK GENMASK(11, 0)
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define DECODE_MODE_NEC 0x0
37*4882a593Smuzhiyun #define DECODE_MODE_RAW 0x2
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* Meson 6b uses REG1 to configure the mode */
40*4882a593Smuzhiyun #define REG1_MODE_MASK GENMASK(8, 7)
41*4882a593Smuzhiyun #define REG1_MODE_SHIFT 7
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* Meson 8b / GXBB use REG2 to configure the mode */
44*4882a593Smuzhiyun #define REG2_MODE_MASK GENMASK(3, 0)
45*4882a593Smuzhiyun #define REG2_MODE_SHIFT 0
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define REG1_TIME_IV_MASK GENMASK(28, 16)
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #define REG1_IRQSEL_MASK GENMASK(3, 2)
50*4882a593Smuzhiyun #define REG1_IRQSEL_NEC_MODE 0
51*4882a593Smuzhiyun #define REG1_IRQSEL_RISE_FALL 1
52*4882a593Smuzhiyun #define REG1_IRQSEL_FALL 2
53*4882a593Smuzhiyun #define REG1_IRQSEL_RISE 3
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define REG1_RESET BIT(0)
56*4882a593Smuzhiyun #define REG1_ENABLE BIT(15)
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define STATUS_IR_DEC_IN BIT(8)
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #define MESON_TRATE 10 /* us */
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun struct meson_ir {
63*4882a593Smuzhiyun void __iomem *reg;
64*4882a593Smuzhiyun struct rc_dev *rc;
65*4882a593Smuzhiyun spinlock_t lock;
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
meson_ir_set_mask(struct meson_ir * ir,unsigned int reg,u32 mask,u32 value)68*4882a593Smuzhiyun static void meson_ir_set_mask(struct meson_ir *ir, unsigned int reg,
69*4882a593Smuzhiyun u32 mask, u32 value)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun u32 data;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun data = readl(ir->reg + reg);
74*4882a593Smuzhiyun data &= ~mask;
75*4882a593Smuzhiyun data |= (value & mask);
76*4882a593Smuzhiyun writel(data, ir->reg + reg);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
meson_ir_irq(int irqno,void * dev_id)79*4882a593Smuzhiyun static irqreturn_t meson_ir_irq(int irqno, void *dev_id)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun struct meson_ir *ir = dev_id;
82*4882a593Smuzhiyun u32 duration, status;
83*4882a593Smuzhiyun struct ir_raw_event rawir = {};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun spin_lock(&ir->lock);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun duration = readl_relaxed(ir->reg + IR_DEC_REG1);
88*4882a593Smuzhiyun duration = FIELD_GET(REG1_TIME_IV_MASK, duration);
89*4882a593Smuzhiyun rawir.duration = duration * MESON_TRATE;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun status = readl_relaxed(ir->reg + IR_DEC_STATUS);
92*4882a593Smuzhiyun rawir.pulse = !!(status & STATUS_IR_DEC_IN);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun ir_raw_event_store_with_timeout(ir->rc, &rawir);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun spin_unlock(&ir->lock);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun return IRQ_HANDLED;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
meson_ir_probe(struct platform_device * pdev)101*4882a593Smuzhiyun static int meson_ir_probe(struct platform_device *pdev)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun struct device *dev = &pdev->dev;
104*4882a593Smuzhiyun struct device_node *node = dev->of_node;
105*4882a593Smuzhiyun struct resource *res;
106*4882a593Smuzhiyun const char *map_name;
107*4882a593Smuzhiyun struct meson_ir *ir;
108*4882a593Smuzhiyun int irq, ret;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun ir = devm_kzalloc(dev, sizeof(struct meson_ir), GFP_KERNEL);
111*4882a593Smuzhiyun if (!ir)
112*4882a593Smuzhiyun return -ENOMEM;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
115*4882a593Smuzhiyun ir->reg = devm_ioremap_resource(dev, res);
116*4882a593Smuzhiyun if (IS_ERR(ir->reg))
117*4882a593Smuzhiyun return PTR_ERR(ir->reg);
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun irq = platform_get_irq(pdev, 0);
120*4882a593Smuzhiyun if (irq < 0)
121*4882a593Smuzhiyun return irq;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
124*4882a593Smuzhiyun if (!ir->rc) {
125*4882a593Smuzhiyun dev_err(dev, "failed to allocate rc device\n");
126*4882a593Smuzhiyun return -ENOMEM;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun ir->rc->priv = ir;
130*4882a593Smuzhiyun ir->rc->device_name = DRIVER_NAME;
131*4882a593Smuzhiyun ir->rc->input_phys = DRIVER_NAME "/input0";
132*4882a593Smuzhiyun ir->rc->input_id.bustype = BUS_HOST;
133*4882a593Smuzhiyun map_name = of_get_property(node, "linux,rc-map-name", NULL);
134*4882a593Smuzhiyun ir->rc->map_name = map_name ? map_name : RC_MAP_EMPTY;
135*4882a593Smuzhiyun ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
136*4882a593Smuzhiyun ir->rc->rx_resolution = MESON_TRATE;
137*4882a593Smuzhiyun ir->rc->min_timeout = 1;
138*4882a593Smuzhiyun ir->rc->timeout = IR_DEFAULT_TIMEOUT;
139*4882a593Smuzhiyun ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
140*4882a593Smuzhiyun ir->rc->driver_name = DRIVER_NAME;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun spin_lock_init(&ir->lock);
143*4882a593Smuzhiyun platform_set_drvdata(pdev, ir);
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun ret = devm_rc_register_device(dev, ir->rc);
146*4882a593Smuzhiyun if (ret) {
147*4882a593Smuzhiyun dev_err(dev, "failed to register rc device\n");
148*4882a593Smuzhiyun return ret;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun ret = devm_request_irq(dev, irq, meson_ir_irq, 0, NULL, ir);
152*4882a593Smuzhiyun if (ret) {
153*4882a593Smuzhiyun dev_err(dev, "failed to request irq\n");
154*4882a593Smuzhiyun return ret;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /* Reset the decoder */
158*4882a593Smuzhiyun meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, REG1_RESET);
159*4882a593Smuzhiyun meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, 0);
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun /* Set general operation mode (= raw/software decoding) */
162*4882a593Smuzhiyun if (of_device_is_compatible(node, "amlogic,meson6-ir"))
163*4882a593Smuzhiyun meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK,
164*4882a593Smuzhiyun FIELD_PREP(REG1_MODE_MASK, DECODE_MODE_RAW));
165*4882a593Smuzhiyun else
166*4882a593Smuzhiyun meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK,
167*4882a593Smuzhiyun FIELD_PREP(REG2_MODE_MASK, DECODE_MODE_RAW));
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun /* Set rate */
170*4882a593Smuzhiyun meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, MESON_TRATE - 1);
171*4882a593Smuzhiyun /* IRQ on rising and falling edges */
172*4882a593Smuzhiyun meson_ir_set_mask(ir, IR_DEC_REG1, REG1_IRQSEL_MASK,
173*4882a593Smuzhiyun FIELD_PREP(REG1_IRQSEL_MASK, REG1_IRQSEL_RISE_FALL));
174*4882a593Smuzhiyun /* Enable the decoder */
175*4882a593Smuzhiyun meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, REG1_ENABLE);
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun dev_info(dev, "receiver initialized\n");
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun return 0;
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun
meson_ir_remove(struct platform_device * pdev)182*4882a593Smuzhiyun static int meson_ir_remove(struct platform_device *pdev)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun struct meson_ir *ir = platform_get_drvdata(pdev);
185*4882a593Smuzhiyun unsigned long flags;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun /* Disable the decoder */
188*4882a593Smuzhiyun spin_lock_irqsave(&ir->lock, flags);
189*4882a593Smuzhiyun meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, 0);
190*4882a593Smuzhiyun spin_unlock_irqrestore(&ir->lock, flags);
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun return 0;
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
meson_ir_shutdown(struct platform_device * pdev)195*4882a593Smuzhiyun static void meson_ir_shutdown(struct platform_device *pdev)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun struct device *dev = &pdev->dev;
198*4882a593Smuzhiyun struct device_node *node = dev->of_node;
199*4882a593Smuzhiyun struct meson_ir *ir = platform_get_drvdata(pdev);
200*4882a593Smuzhiyun unsigned long flags;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun spin_lock_irqsave(&ir->lock, flags);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun /*
205*4882a593Smuzhiyun * Set operation mode to NEC/hardware decoding to give
206*4882a593Smuzhiyun * bootloader a chance to power the system back on
207*4882a593Smuzhiyun */
208*4882a593Smuzhiyun if (of_device_is_compatible(node, "amlogic,meson6-ir"))
209*4882a593Smuzhiyun meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK,
210*4882a593Smuzhiyun DECODE_MODE_NEC << REG1_MODE_SHIFT);
211*4882a593Smuzhiyun else
212*4882a593Smuzhiyun meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK,
213*4882a593Smuzhiyun DECODE_MODE_NEC << REG2_MODE_SHIFT);
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun /* Set rate to default value */
216*4882a593Smuzhiyun meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, 0x13);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun spin_unlock_irqrestore(&ir->lock, flags);
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun static const struct of_device_id meson_ir_match[] = {
222*4882a593Smuzhiyun { .compatible = "amlogic,meson6-ir" },
223*4882a593Smuzhiyun { .compatible = "amlogic,meson8b-ir" },
224*4882a593Smuzhiyun { .compatible = "amlogic,meson-gxbb-ir" },
225*4882a593Smuzhiyun { },
226*4882a593Smuzhiyun };
227*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, meson_ir_match);
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun static struct platform_driver meson_ir_driver = {
230*4882a593Smuzhiyun .probe = meson_ir_probe,
231*4882a593Smuzhiyun .remove = meson_ir_remove,
232*4882a593Smuzhiyun .shutdown = meson_ir_shutdown,
233*4882a593Smuzhiyun .driver = {
234*4882a593Smuzhiyun .name = DRIVER_NAME,
235*4882a593Smuzhiyun .of_match_table = meson_ir_match,
236*4882a593Smuzhiyun },
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun module_platform_driver(meson_ir_driver);
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun MODULE_DESCRIPTION("Amlogic Meson IR remote receiver driver");
242*4882a593Smuzhiyun MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
243*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
244