xref: /OK3568_Linux_fs/kernel/drivers/media/rc/ite-cir.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Driver for ITE Tech Inc. IT8712F/IT8512 CIR
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2010 Juan Jesús García de Soria <skandalfo@gmail.com>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Inspired by the original lirc_it87 and lirc_ite8709 drivers, on top of the
8*4882a593Smuzhiyun  * skeleton provided by the nuvoton-cir driver.
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * The lirc_it87 driver was originally written by Hans-Gunter Lutke Uphues
11*4882a593Smuzhiyun  * <hg_lu@web.de> in 2001, with enhancements by Christoph Bartelmus
12*4882a593Smuzhiyun  * <lirc@bartelmus.de>, Andrew Calkin <r_tay@hotmail.com> and James Edwards
13*4882a593Smuzhiyun  * <jimbo-lirc@edwardsclan.net>.
14*4882a593Smuzhiyun  *
15*4882a593Smuzhiyun  * The lirc_ite8709 driver was written by Grégory Lardière
16*4882a593Smuzhiyun  * <spmf2004-lirc@yahoo.fr> in 2008.
17*4882a593Smuzhiyun  */
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include <linux/kernel.h>
20*4882a593Smuzhiyun #include <linux/module.h>
21*4882a593Smuzhiyun #include <linux/pnp.h>
22*4882a593Smuzhiyun #include <linux/io.h>
23*4882a593Smuzhiyun #include <linux/interrupt.h>
24*4882a593Smuzhiyun #include <linux/sched.h>
25*4882a593Smuzhiyun #include <linux/delay.h>
26*4882a593Smuzhiyun #include <linux/slab.h>
27*4882a593Smuzhiyun #include <linux/input.h>
28*4882a593Smuzhiyun #include <linux/bitops.h>
29*4882a593Smuzhiyun #include <media/rc-core.h>
30*4882a593Smuzhiyun #include <linux/pci_ids.h>
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #include "ite-cir.h"
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun /* module parameters */
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun /* debug level */
37*4882a593Smuzhiyun static int debug;
38*4882a593Smuzhiyun module_param(debug, int, S_IRUGO | S_IWUSR);
39*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Enable debugging output");
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun /* low limit for RX carrier freq, Hz, 0 for no RX demodulation */
42*4882a593Smuzhiyun static int rx_low_carrier_freq;
43*4882a593Smuzhiyun module_param(rx_low_carrier_freq, int, S_IRUGO | S_IWUSR);
44*4882a593Smuzhiyun MODULE_PARM_DESC(rx_low_carrier_freq, "Override low RX carrier frequency, Hz, 0 for no RX demodulation");
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun /* high limit for RX carrier freq, Hz, 0 for no RX demodulation */
47*4882a593Smuzhiyun static int rx_high_carrier_freq;
48*4882a593Smuzhiyun module_param(rx_high_carrier_freq, int, S_IRUGO | S_IWUSR);
49*4882a593Smuzhiyun MODULE_PARM_DESC(rx_high_carrier_freq, "Override high RX carrier frequency, Hz, 0 for no RX demodulation");
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun /* override tx carrier frequency */
52*4882a593Smuzhiyun static int tx_carrier_freq;
53*4882a593Smuzhiyun module_param(tx_carrier_freq, int, S_IRUGO | S_IWUSR);
54*4882a593Smuzhiyun MODULE_PARM_DESC(tx_carrier_freq, "Override TX carrier frequency, Hz");
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun /* override tx duty cycle */
57*4882a593Smuzhiyun static int tx_duty_cycle;
58*4882a593Smuzhiyun module_param(tx_duty_cycle, int, S_IRUGO | S_IWUSR);
59*4882a593Smuzhiyun MODULE_PARM_DESC(tx_duty_cycle, "Override TX duty cycle, 1-100");
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun /* override default sample period */
62*4882a593Smuzhiyun static long sample_period;
63*4882a593Smuzhiyun module_param(sample_period, long, S_IRUGO | S_IWUSR);
64*4882a593Smuzhiyun MODULE_PARM_DESC(sample_period, "Override carrier sample period, us");
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun /* override detected model id */
67*4882a593Smuzhiyun static int model_number = -1;
68*4882a593Smuzhiyun module_param(model_number, int, S_IRUGO | S_IWUSR);
69*4882a593Smuzhiyun MODULE_PARM_DESC(model_number, "Use this model number, don't autodetect");
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun /* HW-independent code functions */
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun /* check whether carrier frequency is high frequency */
ite_is_high_carrier_freq(unsigned int freq)75*4882a593Smuzhiyun static inline bool ite_is_high_carrier_freq(unsigned int freq)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun 	return freq >= ITE_HCF_MIN_CARRIER_FREQ;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun /* get the bits required to program the carrier frequency in CFQ bits,
81*4882a593Smuzhiyun  * unshifted */
ite_get_carrier_freq_bits(unsigned int freq)82*4882a593Smuzhiyun static u8 ite_get_carrier_freq_bits(unsigned int freq)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun 	if (ite_is_high_carrier_freq(freq)) {
85*4882a593Smuzhiyun 		if (freq < 425000)
86*4882a593Smuzhiyun 			return ITE_CFQ_400;
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 		else if (freq < 465000)
89*4882a593Smuzhiyun 			return ITE_CFQ_450;
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 		else if (freq < 490000)
92*4882a593Smuzhiyun 			return ITE_CFQ_480;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 		else
95*4882a593Smuzhiyun 			return ITE_CFQ_500;
96*4882a593Smuzhiyun 	} else {
97*4882a593Smuzhiyun 			/* trim to limits */
98*4882a593Smuzhiyun 		if (freq < ITE_LCF_MIN_CARRIER_FREQ)
99*4882a593Smuzhiyun 			freq = ITE_LCF_MIN_CARRIER_FREQ;
100*4882a593Smuzhiyun 		if (freq > ITE_LCF_MAX_CARRIER_FREQ)
101*4882a593Smuzhiyun 			freq = ITE_LCF_MAX_CARRIER_FREQ;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 		/* convert to kHz and subtract the base freq */
104*4882a593Smuzhiyun 		freq =
105*4882a593Smuzhiyun 		    DIV_ROUND_CLOSEST(freq - ITE_LCF_MIN_CARRIER_FREQ,
106*4882a593Smuzhiyun 				      1000);
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 		return (u8) freq;
109*4882a593Smuzhiyun 	}
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun /* get the bits required to program the pulse with in TXMPW */
ite_get_pulse_width_bits(unsigned int freq,int duty_cycle)113*4882a593Smuzhiyun static u8 ite_get_pulse_width_bits(unsigned int freq, int duty_cycle)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun 	unsigned long period_ns, on_ns;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	/* sanitize freq into range */
118*4882a593Smuzhiyun 	if (freq < ITE_LCF_MIN_CARRIER_FREQ)
119*4882a593Smuzhiyun 		freq = ITE_LCF_MIN_CARRIER_FREQ;
120*4882a593Smuzhiyun 	if (freq > ITE_HCF_MAX_CARRIER_FREQ)
121*4882a593Smuzhiyun 		freq = ITE_HCF_MAX_CARRIER_FREQ;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	period_ns = 1000000000UL / freq;
124*4882a593Smuzhiyun 	on_ns = period_ns * duty_cycle / 100;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	if (ite_is_high_carrier_freq(freq)) {
127*4882a593Smuzhiyun 		if (on_ns < 750)
128*4882a593Smuzhiyun 			return ITE_TXMPW_A;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 		else if (on_ns < 850)
131*4882a593Smuzhiyun 			return ITE_TXMPW_B;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 		else if (on_ns < 950)
134*4882a593Smuzhiyun 			return ITE_TXMPW_C;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 		else if (on_ns < 1080)
137*4882a593Smuzhiyun 			return ITE_TXMPW_D;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 		else
140*4882a593Smuzhiyun 			return ITE_TXMPW_E;
141*4882a593Smuzhiyun 	} else {
142*4882a593Smuzhiyun 		if (on_ns < 6500)
143*4882a593Smuzhiyun 			return ITE_TXMPW_A;
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 		else if (on_ns < 7850)
146*4882a593Smuzhiyun 			return ITE_TXMPW_B;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 		else if (on_ns < 9650)
149*4882a593Smuzhiyun 			return ITE_TXMPW_C;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 		else if (on_ns < 11950)
152*4882a593Smuzhiyun 			return ITE_TXMPW_D;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 		else
155*4882a593Smuzhiyun 			return ITE_TXMPW_E;
156*4882a593Smuzhiyun 	}
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun /* decode raw bytes as received by the hardware, and push them to the ir-core
160*4882a593Smuzhiyun  * layer */
ite_decode_bytes(struct ite_dev * dev,const u8 * data,int length)161*4882a593Smuzhiyun static void ite_decode_bytes(struct ite_dev *dev, const u8 * data, int
162*4882a593Smuzhiyun 			     length)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun 	u32 sample_period;
165*4882a593Smuzhiyun 	unsigned long *ldata;
166*4882a593Smuzhiyun 	unsigned int next_one, next_zero, size;
167*4882a593Smuzhiyun 	struct ir_raw_event ev = {};
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	if (length == 0)
170*4882a593Smuzhiyun 		return;
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	sample_period = dev->params.sample_period;
173*4882a593Smuzhiyun 	ldata = (unsigned long *)data;
174*4882a593Smuzhiyun 	size = length << 3;
175*4882a593Smuzhiyun 	next_one = find_next_bit_le(ldata, size, 0);
176*4882a593Smuzhiyun 	if (next_one > 0) {
177*4882a593Smuzhiyun 		ev.pulse = true;
178*4882a593Smuzhiyun 		ev.duration =
179*4882a593Smuzhiyun 		    ITE_BITS_TO_US(next_one, sample_period);
180*4882a593Smuzhiyun 		ir_raw_event_store_with_filter(dev->rdev, &ev);
181*4882a593Smuzhiyun 	}
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	while (next_one < size) {
184*4882a593Smuzhiyun 		next_zero = find_next_zero_bit_le(ldata, size, next_one + 1);
185*4882a593Smuzhiyun 		ev.pulse = false;
186*4882a593Smuzhiyun 		ev.duration = ITE_BITS_TO_US(next_zero - next_one, sample_period);
187*4882a593Smuzhiyun 		ir_raw_event_store_with_filter(dev->rdev, &ev);
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 		if (next_zero < size) {
190*4882a593Smuzhiyun 			next_one =
191*4882a593Smuzhiyun 			    find_next_bit_le(ldata,
192*4882a593Smuzhiyun 						     size,
193*4882a593Smuzhiyun 						     next_zero + 1);
194*4882a593Smuzhiyun 			ev.pulse = true;
195*4882a593Smuzhiyun 			ev.duration =
196*4882a593Smuzhiyun 			    ITE_BITS_TO_US(next_one - next_zero,
197*4882a593Smuzhiyun 					   sample_period);
198*4882a593Smuzhiyun 			ir_raw_event_store_with_filter
199*4882a593Smuzhiyun 			    (dev->rdev, &ev);
200*4882a593Smuzhiyun 		} else
201*4882a593Smuzhiyun 			next_one = size;
202*4882a593Smuzhiyun 	}
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	ir_raw_event_handle(dev->rdev);
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	ite_dbg_verbose("decoded %d bytes.", length);
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun /* set all the rx/tx carrier parameters; this must be called with the device
210*4882a593Smuzhiyun  * spinlock held */
ite_set_carrier_params(struct ite_dev * dev)211*4882a593Smuzhiyun static void ite_set_carrier_params(struct ite_dev *dev)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun 	unsigned int freq, low_freq, high_freq;
214*4882a593Smuzhiyun 	int allowance;
215*4882a593Smuzhiyun 	bool use_demodulator;
216*4882a593Smuzhiyun 	bool for_tx = dev->transmitting;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	if (for_tx) {
221*4882a593Smuzhiyun 		/* we don't need no stinking calculations */
222*4882a593Smuzhiyun 		freq = dev->params.tx_carrier_freq;
223*4882a593Smuzhiyun 		allowance = ITE_RXDCR_DEFAULT;
224*4882a593Smuzhiyun 		use_demodulator = false;
225*4882a593Smuzhiyun 	} else {
226*4882a593Smuzhiyun 		low_freq = dev->params.rx_low_carrier_freq;
227*4882a593Smuzhiyun 		high_freq = dev->params.rx_high_carrier_freq;
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 		if (low_freq == 0) {
230*4882a593Smuzhiyun 			/* don't demodulate */
231*4882a593Smuzhiyun 			freq =
232*4882a593Smuzhiyun 			ITE_DEFAULT_CARRIER_FREQ;
233*4882a593Smuzhiyun 			allowance = ITE_RXDCR_DEFAULT;
234*4882a593Smuzhiyun 			use_demodulator = false;
235*4882a593Smuzhiyun 		} else {
236*4882a593Smuzhiyun 			/* calculate the middle freq */
237*4882a593Smuzhiyun 			freq = (low_freq + high_freq) / 2;
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 			/* calculate the allowance */
240*4882a593Smuzhiyun 			allowance =
241*4882a593Smuzhiyun 			    DIV_ROUND_CLOSEST(10000 * (high_freq - low_freq),
242*4882a593Smuzhiyun 					      ITE_RXDCR_PER_10000_STEP
243*4882a593Smuzhiyun 					      * (high_freq + low_freq));
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 			if (allowance < 1)
246*4882a593Smuzhiyun 				allowance = 1;
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 			if (allowance > ITE_RXDCR_MAX)
249*4882a593Smuzhiyun 				allowance = ITE_RXDCR_MAX;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 			use_demodulator = true;
252*4882a593Smuzhiyun 		}
253*4882a593Smuzhiyun 	}
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	/* set the carrier parameters in a device-dependent way */
256*4882a593Smuzhiyun 	dev->params.set_carrier_params(dev, ite_is_high_carrier_freq(freq),
257*4882a593Smuzhiyun 		 use_demodulator, ite_get_carrier_freq_bits(freq), allowance,
258*4882a593Smuzhiyun 		 ite_get_pulse_width_bits(freq, dev->params.tx_duty_cycle));
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun /* interrupt service routine for incoming and outgoing CIR data */
ite_cir_isr(int irq,void * data)262*4882a593Smuzhiyun static irqreturn_t ite_cir_isr(int irq, void *data)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun 	struct ite_dev *dev = data;
265*4882a593Smuzhiyun 	unsigned long flags;
266*4882a593Smuzhiyun 	irqreturn_t ret = IRQ_RETVAL(IRQ_NONE);
267*4882a593Smuzhiyun 	u8 rx_buf[ITE_RX_FIFO_LEN];
268*4882a593Smuzhiyun 	int rx_bytes;
269*4882a593Smuzhiyun 	int iflags;
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	ite_dbg_verbose("%s firing", __func__);
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	/* grab the spinlock */
274*4882a593Smuzhiyun 	spin_lock_irqsave(&dev->lock, flags);
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	/* read the interrupt flags */
277*4882a593Smuzhiyun 	iflags = dev->params.get_irq_causes(dev);
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	/* Check for RX overflow */
280*4882a593Smuzhiyun 	if (iflags & ITE_IRQ_RX_FIFO_OVERRUN) {
281*4882a593Smuzhiyun 		dev_warn(&dev->rdev->dev, "receive overflow\n");
282*4882a593Smuzhiyun 		ir_raw_event_reset(dev->rdev);
283*4882a593Smuzhiyun 	}
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	/* check for the receive interrupt */
286*4882a593Smuzhiyun 	if (iflags & (ITE_IRQ_RX_FIFO | ITE_IRQ_RX_FIFO_OVERRUN)) {
287*4882a593Smuzhiyun 		/* read the FIFO bytes */
288*4882a593Smuzhiyun 		rx_bytes =
289*4882a593Smuzhiyun 			dev->params.get_rx_bytes(dev, rx_buf,
290*4882a593Smuzhiyun 					     ITE_RX_FIFO_LEN);
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 		if (rx_bytes > 0) {
293*4882a593Smuzhiyun 			/* drop the spinlock, since the ir-core layer
294*4882a593Smuzhiyun 			 * may call us back again through
295*4882a593Smuzhiyun 			 * ite_s_idle() */
296*4882a593Smuzhiyun 			spin_unlock_irqrestore(&dev->
297*4882a593Smuzhiyun 									 lock,
298*4882a593Smuzhiyun 									 flags);
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 			/* decode the data we've just received */
301*4882a593Smuzhiyun 			ite_decode_bytes(dev, rx_buf,
302*4882a593Smuzhiyun 								   rx_bytes);
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 			/* reacquire the spinlock */
305*4882a593Smuzhiyun 			spin_lock_irqsave(&dev->lock,
306*4882a593Smuzhiyun 								    flags);
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 			/* mark the interrupt as serviced */
309*4882a593Smuzhiyun 			ret = IRQ_RETVAL(IRQ_HANDLED);
310*4882a593Smuzhiyun 		}
311*4882a593Smuzhiyun 	} else if (iflags & ITE_IRQ_TX_FIFO) {
312*4882a593Smuzhiyun 		/* FIFO space available interrupt */
313*4882a593Smuzhiyun 		ite_dbg_verbose("got interrupt for TX FIFO");
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 		/* wake any sleeping transmitter */
316*4882a593Smuzhiyun 		wake_up_interruptible(&dev->tx_queue);
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 		/* mark the interrupt as serviced */
319*4882a593Smuzhiyun 		ret = IRQ_RETVAL(IRQ_HANDLED);
320*4882a593Smuzhiyun 	}
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	/* drop the spinlock */
323*4882a593Smuzhiyun 	spin_unlock_irqrestore(&dev->lock, flags);
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	ite_dbg_verbose("%s done returning %d", __func__, (int)ret);
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	return ret;
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun /* set the rx carrier freq range, guess it's in Hz... */
ite_set_rx_carrier_range(struct rc_dev * rcdev,u32 carrier_low,u32 carrier_high)331*4882a593Smuzhiyun static int ite_set_rx_carrier_range(struct rc_dev *rcdev, u32 carrier_low, u32
332*4882a593Smuzhiyun 				    carrier_high)
333*4882a593Smuzhiyun {
334*4882a593Smuzhiyun 	unsigned long flags;
335*4882a593Smuzhiyun 	struct ite_dev *dev = rcdev->priv;
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	spin_lock_irqsave(&dev->lock, flags);
338*4882a593Smuzhiyun 	dev->params.rx_low_carrier_freq = carrier_low;
339*4882a593Smuzhiyun 	dev->params.rx_high_carrier_freq = carrier_high;
340*4882a593Smuzhiyun 	ite_set_carrier_params(dev);
341*4882a593Smuzhiyun 	spin_unlock_irqrestore(&dev->lock, flags);
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	return 0;
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun /* set the tx carrier freq, guess it's in Hz... */
ite_set_tx_carrier(struct rc_dev * rcdev,u32 carrier)347*4882a593Smuzhiyun static int ite_set_tx_carrier(struct rc_dev *rcdev, u32 carrier)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun 	unsigned long flags;
350*4882a593Smuzhiyun 	struct ite_dev *dev = rcdev->priv;
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun 	spin_lock_irqsave(&dev->lock, flags);
353*4882a593Smuzhiyun 	dev->params.tx_carrier_freq = carrier;
354*4882a593Smuzhiyun 	ite_set_carrier_params(dev);
355*4882a593Smuzhiyun 	spin_unlock_irqrestore(&dev->lock, flags);
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun 	return 0;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun /* set the tx duty cycle by controlling the pulse width */
ite_set_tx_duty_cycle(struct rc_dev * rcdev,u32 duty_cycle)361*4882a593Smuzhiyun static int ite_set_tx_duty_cycle(struct rc_dev *rcdev, u32 duty_cycle)
362*4882a593Smuzhiyun {
363*4882a593Smuzhiyun 	unsigned long flags;
364*4882a593Smuzhiyun 	struct ite_dev *dev = rcdev->priv;
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 	spin_lock_irqsave(&dev->lock, flags);
367*4882a593Smuzhiyun 	dev->params.tx_duty_cycle = duty_cycle;
368*4882a593Smuzhiyun 	ite_set_carrier_params(dev);
369*4882a593Smuzhiyun 	spin_unlock_irqrestore(&dev->lock, flags);
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 	return 0;
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun /* transmit out IR pulses; what you get here is a batch of alternating
375*4882a593Smuzhiyun  * pulse/space/pulse/space lengths that we should write out completely through
376*4882a593Smuzhiyun  * the FIFO, blocking on a full FIFO */
ite_tx_ir(struct rc_dev * rcdev,unsigned * txbuf,unsigned n)377*4882a593Smuzhiyun static int ite_tx_ir(struct rc_dev *rcdev, unsigned *txbuf, unsigned n)
378*4882a593Smuzhiyun {
379*4882a593Smuzhiyun 	unsigned long flags;
380*4882a593Smuzhiyun 	struct ite_dev *dev = rcdev->priv;
381*4882a593Smuzhiyun 	bool is_pulse = false;
382*4882a593Smuzhiyun 	int remaining_us, fifo_avail, fifo_remaining, last_idx = 0;
383*4882a593Smuzhiyun 	int max_rle_us, next_rle_us;
384*4882a593Smuzhiyun 	int ret = n;
385*4882a593Smuzhiyun 	u8 last_sent[ITE_TX_FIFO_LEN];
386*4882a593Smuzhiyun 	u8 val;
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	/* clear the array just in case */
391*4882a593Smuzhiyun 	memset(last_sent, 0, sizeof(last_sent));
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 	spin_lock_irqsave(&dev->lock, flags);
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	/* let everybody know we're now transmitting */
396*4882a593Smuzhiyun 	dev->transmitting = true;
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	/* and set the carrier values for transmission */
399*4882a593Smuzhiyun 	ite_set_carrier_params(dev);
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun 	/* calculate how much time we can send in one byte */
402*4882a593Smuzhiyun 	max_rle_us =
403*4882a593Smuzhiyun 	    (ITE_BAUDRATE_DIVISOR * dev->params.sample_period *
404*4882a593Smuzhiyun 	     ITE_TX_MAX_RLE) / 1000;
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	/* disable the receiver */
407*4882a593Smuzhiyun 	dev->params.disable_rx(dev);
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun 	/* this is where we'll begin filling in the FIFO, until it's full.
410*4882a593Smuzhiyun 	 * then we'll just activate the interrupt, wait for it to wake us up
411*4882a593Smuzhiyun 	 * again, disable it, continue filling the FIFO... until everything
412*4882a593Smuzhiyun 	 * has been pushed out */
413*4882a593Smuzhiyun 	fifo_avail =
414*4882a593Smuzhiyun 	    ITE_TX_FIFO_LEN - dev->params.get_tx_used_slots(dev);
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 	while (n > 0 && dev->in_use) {
417*4882a593Smuzhiyun 		/* transmit the next sample */
418*4882a593Smuzhiyun 		is_pulse = !is_pulse;
419*4882a593Smuzhiyun 		remaining_us = *(txbuf++);
420*4882a593Smuzhiyun 		n--;
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 		ite_dbg("%s: %ld",
423*4882a593Smuzhiyun 				      ((is_pulse) ? "pulse" : "space"),
424*4882a593Smuzhiyun 				      (long int)
425*4882a593Smuzhiyun 				      remaining_us);
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun 		/* repeat while the pulse is non-zero length */
428*4882a593Smuzhiyun 		while (remaining_us > 0 && dev->in_use) {
429*4882a593Smuzhiyun 			if (remaining_us > max_rle_us)
430*4882a593Smuzhiyun 				next_rle_us = max_rle_us;
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 			else
433*4882a593Smuzhiyun 				next_rle_us = remaining_us;
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 			remaining_us -= next_rle_us;
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 			/* check what's the length we have to pump out */
438*4882a593Smuzhiyun 			val = (ITE_TX_MAX_RLE * next_rle_us) / max_rle_us;
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun 			/* put it into the sent buffer */
441*4882a593Smuzhiyun 			last_sent[last_idx++] = val;
442*4882a593Smuzhiyun 			last_idx &= (ITE_TX_FIFO_LEN);
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 			/* encode it for 7 bits */
445*4882a593Smuzhiyun 			val = (val - 1) & ITE_TX_RLE_MASK;
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun 			/* take into account pulse/space prefix */
448*4882a593Smuzhiyun 			if (is_pulse)
449*4882a593Smuzhiyun 				val |= ITE_TX_PULSE;
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun 			else
452*4882a593Smuzhiyun 				val |= ITE_TX_SPACE;
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun 			/*
455*4882a593Smuzhiyun 			 * if we get to 0 available, read again, just in case
456*4882a593Smuzhiyun 			 * some other slot got freed
457*4882a593Smuzhiyun 			 */
458*4882a593Smuzhiyun 			if (fifo_avail <= 0)
459*4882a593Smuzhiyun 				fifo_avail = ITE_TX_FIFO_LEN - dev->params.get_tx_used_slots(dev);
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun 			/* if it's still full */
462*4882a593Smuzhiyun 			if (fifo_avail <= 0) {
463*4882a593Smuzhiyun 				/* enable the tx interrupt */
464*4882a593Smuzhiyun 				dev->params.
465*4882a593Smuzhiyun 				enable_tx_interrupt(dev);
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun 				/* drop the spinlock */
468*4882a593Smuzhiyun 				spin_unlock_irqrestore(&dev->lock, flags);
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 				/* wait for the FIFO to empty enough */
471*4882a593Smuzhiyun 				wait_event_interruptible(dev->tx_queue, (fifo_avail = ITE_TX_FIFO_LEN - dev->params.get_tx_used_slots(dev)) >= 8);
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun 				/* get the spinlock again */
474*4882a593Smuzhiyun 				spin_lock_irqsave(&dev->lock, flags);
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun 				/* disable the tx interrupt again. */
477*4882a593Smuzhiyun 				dev->params.
478*4882a593Smuzhiyun 				disable_tx_interrupt(dev);
479*4882a593Smuzhiyun 			}
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 			/* now send the byte through the FIFO */
482*4882a593Smuzhiyun 			dev->params.put_tx_byte(dev, val);
483*4882a593Smuzhiyun 			fifo_avail--;
484*4882a593Smuzhiyun 		}
485*4882a593Smuzhiyun 	}
486*4882a593Smuzhiyun 
487*4882a593Smuzhiyun 	/* wait and don't return until the whole FIFO has been sent out;
488*4882a593Smuzhiyun 	 * otherwise we could configure the RX carrier params instead of the
489*4882a593Smuzhiyun 	 * TX ones while the transmission is still being performed! */
490*4882a593Smuzhiyun 	fifo_remaining = dev->params.get_tx_used_slots(dev);
491*4882a593Smuzhiyun 	remaining_us = 0;
492*4882a593Smuzhiyun 	while (fifo_remaining > 0) {
493*4882a593Smuzhiyun 		fifo_remaining--;
494*4882a593Smuzhiyun 		last_idx--;
495*4882a593Smuzhiyun 		last_idx &= (ITE_TX_FIFO_LEN - 1);
496*4882a593Smuzhiyun 		remaining_us += last_sent[last_idx];
497*4882a593Smuzhiyun 	}
498*4882a593Smuzhiyun 	remaining_us = (remaining_us * max_rle_us) / (ITE_TX_MAX_RLE);
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun 	/* drop the spinlock while we sleep */
501*4882a593Smuzhiyun 	spin_unlock_irqrestore(&dev->lock, flags);
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun 	/* sleep remaining_us microseconds */
504*4882a593Smuzhiyun 	mdelay(DIV_ROUND_UP(remaining_us, 1000));
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun 	/* reacquire the spinlock */
507*4882a593Smuzhiyun 	spin_lock_irqsave(&dev->lock, flags);
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 	/* now we're not transmitting anymore */
510*4882a593Smuzhiyun 	dev->transmitting = false;
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	/* and set the carrier values for reception */
513*4882a593Smuzhiyun 	ite_set_carrier_params(dev);
514*4882a593Smuzhiyun 
515*4882a593Smuzhiyun 	/* re-enable the receiver */
516*4882a593Smuzhiyun 	if (dev->in_use)
517*4882a593Smuzhiyun 		dev->params.enable_rx(dev);
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun 	/* notify transmission end */
520*4882a593Smuzhiyun 	wake_up_interruptible(&dev->tx_ended);
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	spin_unlock_irqrestore(&dev->lock, flags);
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	return ret;
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun /* idle the receiver if needed */
ite_s_idle(struct rc_dev * rcdev,bool enable)528*4882a593Smuzhiyun static void ite_s_idle(struct rc_dev *rcdev, bool enable)
529*4882a593Smuzhiyun {
530*4882a593Smuzhiyun 	unsigned long flags;
531*4882a593Smuzhiyun 	struct ite_dev *dev = rcdev->priv;
532*4882a593Smuzhiyun 
533*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 	if (enable) {
536*4882a593Smuzhiyun 		spin_lock_irqsave(&dev->lock, flags);
537*4882a593Smuzhiyun 		dev->params.idle_rx(dev);
538*4882a593Smuzhiyun 		spin_unlock_irqrestore(&dev->lock, flags);
539*4882a593Smuzhiyun 	}
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun /* IT8712F HW-specific functions */
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun /* retrieve a bitmask of the current causes for a pending interrupt; this may
546*4882a593Smuzhiyun  * be composed of ITE_IRQ_TX_FIFO, ITE_IRQ_RX_FIFO and ITE_IRQ_RX_FIFO_OVERRUN
547*4882a593Smuzhiyun  * */
it87_get_irq_causes(struct ite_dev * dev)548*4882a593Smuzhiyun static int it87_get_irq_causes(struct ite_dev *dev)
549*4882a593Smuzhiyun {
550*4882a593Smuzhiyun 	u8 iflags;
551*4882a593Smuzhiyun 	int ret = 0;
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun 	/* read the interrupt flags */
556*4882a593Smuzhiyun 	iflags = inb(dev->cir_addr + IT87_IIR) & IT87_II;
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	switch (iflags) {
559*4882a593Smuzhiyun 	case IT87_II_RXDS:
560*4882a593Smuzhiyun 		ret = ITE_IRQ_RX_FIFO;
561*4882a593Smuzhiyun 		break;
562*4882a593Smuzhiyun 	case IT87_II_RXFO:
563*4882a593Smuzhiyun 		ret = ITE_IRQ_RX_FIFO_OVERRUN;
564*4882a593Smuzhiyun 		break;
565*4882a593Smuzhiyun 	case IT87_II_TXLDL:
566*4882a593Smuzhiyun 		ret = ITE_IRQ_TX_FIFO;
567*4882a593Smuzhiyun 		break;
568*4882a593Smuzhiyun 	}
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun 	return ret;
571*4882a593Smuzhiyun }
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun /* set the carrier parameters; to be called with the spinlock held */
it87_set_carrier_params(struct ite_dev * dev,bool high_freq,bool use_demodulator,u8 carrier_freq_bits,u8 allowance_bits,u8 pulse_width_bits)574*4882a593Smuzhiyun static void it87_set_carrier_params(struct ite_dev *dev, bool high_freq,
575*4882a593Smuzhiyun 				    bool use_demodulator,
576*4882a593Smuzhiyun 				    u8 carrier_freq_bits, u8 allowance_bits,
577*4882a593Smuzhiyun 				    u8 pulse_width_bits)
578*4882a593Smuzhiyun {
579*4882a593Smuzhiyun 	u8 val;
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
582*4882a593Smuzhiyun 
583*4882a593Smuzhiyun 	/* program the RCR register */
584*4882a593Smuzhiyun 	val = inb(dev->cir_addr + IT87_RCR)
585*4882a593Smuzhiyun 		& ~(IT87_HCFS | IT87_RXEND | IT87_RXDCR);
586*4882a593Smuzhiyun 
587*4882a593Smuzhiyun 	if (high_freq)
588*4882a593Smuzhiyun 		val |= IT87_HCFS;
589*4882a593Smuzhiyun 
590*4882a593Smuzhiyun 	if (use_demodulator)
591*4882a593Smuzhiyun 		val |= IT87_RXEND;
592*4882a593Smuzhiyun 
593*4882a593Smuzhiyun 	val |= allowance_bits;
594*4882a593Smuzhiyun 
595*4882a593Smuzhiyun 	outb(val, dev->cir_addr + IT87_RCR);
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun 	/* program the TCR2 register */
598*4882a593Smuzhiyun 	outb((carrier_freq_bits << IT87_CFQ_SHIFT) | pulse_width_bits,
599*4882a593Smuzhiyun 		dev->cir_addr + IT87_TCR2);
600*4882a593Smuzhiyun }
601*4882a593Smuzhiyun 
602*4882a593Smuzhiyun /* read up to buf_size bytes from the RX FIFO; to be called with the spinlock
603*4882a593Smuzhiyun  * held */
it87_get_rx_bytes(struct ite_dev * dev,u8 * buf,int buf_size)604*4882a593Smuzhiyun static int it87_get_rx_bytes(struct ite_dev *dev, u8 * buf, int buf_size)
605*4882a593Smuzhiyun {
606*4882a593Smuzhiyun 	int fifo, read = 0;
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun 	/* read how many bytes are still in the FIFO */
611*4882a593Smuzhiyun 	fifo = inb(dev->cir_addr + IT87_RSR) & IT87_RXFBC;
612*4882a593Smuzhiyun 
613*4882a593Smuzhiyun 	while (fifo > 0 && buf_size > 0) {
614*4882a593Smuzhiyun 		*(buf++) = inb(dev->cir_addr + IT87_DR);
615*4882a593Smuzhiyun 		fifo--;
616*4882a593Smuzhiyun 		read++;
617*4882a593Smuzhiyun 		buf_size--;
618*4882a593Smuzhiyun 	}
619*4882a593Smuzhiyun 
620*4882a593Smuzhiyun 	return read;
621*4882a593Smuzhiyun }
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun /* return how many bytes are still in the FIFO; this will be called
624*4882a593Smuzhiyun  * with the device spinlock NOT HELD while waiting for the TX FIFO to get
625*4882a593Smuzhiyun  * empty; let's expect this won't be a problem */
it87_get_tx_used_slots(struct ite_dev * dev)626*4882a593Smuzhiyun static int it87_get_tx_used_slots(struct ite_dev *dev)
627*4882a593Smuzhiyun {
628*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun 	return inb(dev->cir_addr + IT87_TSR) & IT87_TXFBC;
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun 
633*4882a593Smuzhiyun /* put a byte to the TX fifo; this should be called with the spinlock held */
it87_put_tx_byte(struct ite_dev * dev,u8 value)634*4882a593Smuzhiyun static void it87_put_tx_byte(struct ite_dev *dev, u8 value)
635*4882a593Smuzhiyun {
636*4882a593Smuzhiyun 	outb(value, dev->cir_addr + IT87_DR);
637*4882a593Smuzhiyun }
638*4882a593Smuzhiyun 
639*4882a593Smuzhiyun /* idle the receiver so that we won't receive samples until another
640*4882a593Smuzhiyun   pulse is detected; this must be called with the device spinlock held */
it87_idle_rx(struct ite_dev * dev)641*4882a593Smuzhiyun static void it87_idle_rx(struct ite_dev *dev)
642*4882a593Smuzhiyun {
643*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	/* disable streaming by clearing RXACT writing it as 1 */
646*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT87_RCR) | IT87_RXACT,
647*4882a593Smuzhiyun 		dev->cir_addr + IT87_RCR);
648*4882a593Smuzhiyun 
649*4882a593Smuzhiyun 	/* clear the FIFO */
650*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT87_TCR1) | IT87_FIFOCLR,
651*4882a593Smuzhiyun 		dev->cir_addr + IT87_TCR1);
652*4882a593Smuzhiyun }
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun /* disable the receiver; this must be called with the device spinlock held */
it87_disable_rx(struct ite_dev * dev)655*4882a593Smuzhiyun static void it87_disable_rx(struct ite_dev *dev)
656*4882a593Smuzhiyun {
657*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
658*4882a593Smuzhiyun 
659*4882a593Smuzhiyun 	/* disable the receiver interrupts */
660*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT87_IER) & ~(IT87_RDAIE | IT87_RFOIE),
661*4882a593Smuzhiyun 		dev->cir_addr + IT87_IER);
662*4882a593Smuzhiyun 
663*4882a593Smuzhiyun 	/* disable the receiver */
664*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT87_RCR) & ~IT87_RXEN,
665*4882a593Smuzhiyun 		dev->cir_addr + IT87_RCR);
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun 	/* clear the FIFO and RXACT (actually RXACT should have been cleared
668*4882a593Smuzhiyun 	* in the previous outb() call) */
669*4882a593Smuzhiyun 	it87_idle_rx(dev);
670*4882a593Smuzhiyun }
671*4882a593Smuzhiyun 
672*4882a593Smuzhiyun /* enable the receiver; this must be called with the device spinlock held */
it87_enable_rx(struct ite_dev * dev)673*4882a593Smuzhiyun static void it87_enable_rx(struct ite_dev *dev)
674*4882a593Smuzhiyun {
675*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
676*4882a593Smuzhiyun 
677*4882a593Smuzhiyun 	/* enable the receiver by setting RXEN */
678*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT87_RCR) | IT87_RXEN,
679*4882a593Smuzhiyun 		dev->cir_addr + IT87_RCR);
680*4882a593Smuzhiyun 
681*4882a593Smuzhiyun 	/* just prepare it to idle for the next reception */
682*4882a593Smuzhiyun 	it87_idle_rx(dev);
683*4882a593Smuzhiyun 
684*4882a593Smuzhiyun 	/* enable the receiver interrupts and master enable flag */
685*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT87_IER) | IT87_RDAIE | IT87_RFOIE | IT87_IEC,
686*4882a593Smuzhiyun 		dev->cir_addr + IT87_IER);
687*4882a593Smuzhiyun }
688*4882a593Smuzhiyun 
689*4882a593Smuzhiyun /* disable the transmitter interrupt; this must be called with the device
690*4882a593Smuzhiyun  * spinlock held */
it87_disable_tx_interrupt(struct ite_dev * dev)691*4882a593Smuzhiyun static void it87_disable_tx_interrupt(struct ite_dev *dev)
692*4882a593Smuzhiyun {
693*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
694*4882a593Smuzhiyun 
695*4882a593Smuzhiyun 	/* disable the transmitter interrupts */
696*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT87_IER) & ~IT87_TLDLIE,
697*4882a593Smuzhiyun 		dev->cir_addr + IT87_IER);
698*4882a593Smuzhiyun }
699*4882a593Smuzhiyun 
700*4882a593Smuzhiyun /* enable the transmitter interrupt; this must be called with the device
701*4882a593Smuzhiyun  * spinlock held */
it87_enable_tx_interrupt(struct ite_dev * dev)702*4882a593Smuzhiyun static void it87_enable_tx_interrupt(struct ite_dev *dev)
703*4882a593Smuzhiyun {
704*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
705*4882a593Smuzhiyun 
706*4882a593Smuzhiyun 	/* enable the transmitter interrupts and master enable flag */
707*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT87_IER) | IT87_TLDLIE | IT87_IEC,
708*4882a593Smuzhiyun 		dev->cir_addr + IT87_IER);
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun 
711*4882a593Smuzhiyun /* disable the device; this must be called with the device spinlock held */
it87_disable(struct ite_dev * dev)712*4882a593Smuzhiyun static void it87_disable(struct ite_dev *dev)
713*4882a593Smuzhiyun {
714*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
715*4882a593Smuzhiyun 
716*4882a593Smuzhiyun 	/* clear out all interrupt enable flags */
717*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT87_IER) &
718*4882a593Smuzhiyun 		~(IT87_IEC | IT87_RFOIE | IT87_RDAIE | IT87_TLDLIE),
719*4882a593Smuzhiyun 		dev->cir_addr + IT87_IER);
720*4882a593Smuzhiyun 
721*4882a593Smuzhiyun 	/* disable the receiver */
722*4882a593Smuzhiyun 	it87_disable_rx(dev);
723*4882a593Smuzhiyun 
724*4882a593Smuzhiyun 	/* erase the FIFO */
725*4882a593Smuzhiyun 	outb(IT87_FIFOCLR | inb(dev->cir_addr + IT87_TCR1),
726*4882a593Smuzhiyun 		dev->cir_addr + IT87_TCR1);
727*4882a593Smuzhiyun }
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun /* initialize the hardware */
it87_init_hardware(struct ite_dev * dev)730*4882a593Smuzhiyun static void it87_init_hardware(struct ite_dev *dev)
731*4882a593Smuzhiyun {
732*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
733*4882a593Smuzhiyun 
734*4882a593Smuzhiyun 	/* enable just the baud rate divisor register,
735*4882a593Smuzhiyun 	disabling all the interrupts at the same time */
736*4882a593Smuzhiyun 	outb((inb(dev->cir_addr + IT87_IER) &
737*4882a593Smuzhiyun 		~(IT87_IEC | IT87_RFOIE | IT87_RDAIE | IT87_TLDLIE)) | IT87_BR,
738*4882a593Smuzhiyun 		dev->cir_addr + IT87_IER);
739*4882a593Smuzhiyun 
740*4882a593Smuzhiyun 	/* write out the baud rate divisor */
741*4882a593Smuzhiyun 	outb(ITE_BAUDRATE_DIVISOR & 0xff, dev->cir_addr + IT87_BDLR);
742*4882a593Smuzhiyun 	outb((ITE_BAUDRATE_DIVISOR >> 8) & 0xff, dev->cir_addr + IT87_BDHR);
743*4882a593Smuzhiyun 
744*4882a593Smuzhiyun 	/* disable the baud rate divisor register again */
745*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT87_IER) & ~IT87_BR,
746*4882a593Smuzhiyun 		dev->cir_addr + IT87_IER);
747*4882a593Smuzhiyun 
748*4882a593Smuzhiyun 	/* program the RCR register defaults */
749*4882a593Smuzhiyun 	outb(ITE_RXDCR_DEFAULT, dev->cir_addr + IT87_RCR);
750*4882a593Smuzhiyun 
751*4882a593Smuzhiyun 	/* program the TCR1 register */
752*4882a593Smuzhiyun 	outb(IT87_TXMPM_DEFAULT | IT87_TXENDF | IT87_TXRLE
753*4882a593Smuzhiyun 		| IT87_FIFOTL_DEFAULT | IT87_FIFOCLR,
754*4882a593Smuzhiyun 		dev->cir_addr + IT87_TCR1);
755*4882a593Smuzhiyun 
756*4882a593Smuzhiyun 	/* program the carrier parameters */
757*4882a593Smuzhiyun 	ite_set_carrier_params(dev);
758*4882a593Smuzhiyun }
759*4882a593Smuzhiyun 
760*4882a593Smuzhiyun /* IT8512F on ITE8708 HW-specific functions */
761*4882a593Smuzhiyun 
762*4882a593Smuzhiyun /* retrieve a bitmask of the current causes for a pending interrupt; this may
763*4882a593Smuzhiyun  * be composed of ITE_IRQ_TX_FIFO, ITE_IRQ_RX_FIFO and ITE_IRQ_RX_FIFO_OVERRUN
764*4882a593Smuzhiyun  * */
it8708_get_irq_causes(struct ite_dev * dev)765*4882a593Smuzhiyun static int it8708_get_irq_causes(struct ite_dev *dev)
766*4882a593Smuzhiyun {
767*4882a593Smuzhiyun 	u8 iflags;
768*4882a593Smuzhiyun 	int ret = 0;
769*4882a593Smuzhiyun 
770*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
771*4882a593Smuzhiyun 
772*4882a593Smuzhiyun 	/* read the interrupt flags */
773*4882a593Smuzhiyun 	iflags = inb(dev->cir_addr + IT8708_C0IIR);
774*4882a593Smuzhiyun 
775*4882a593Smuzhiyun 	if (iflags & IT85_TLDLI)
776*4882a593Smuzhiyun 		ret |= ITE_IRQ_TX_FIFO;
777*4882a593Smuzhiyun 	if (iflags & IT85_RDAI)
778*4882a593Smuzhiyun 		ret |= ITE_IRQ_RX_FIFO;
779*4882a593Smuzhiyun 	if (iflags & IT85_RFOI)
780*4882a593Smuzhiyun 		ret |= ITE_IRQ_RX_FIFO_OVERRUN;
781*4882a593Smuzhiyun 
782*4882a593Smuzhiyun 	return ret;
783*4882a593Smuzhiyun }
784*4882a593Smuzhiyun 
785*4882a593Smuzhiyun /* set the carrier parameters; to be called with the spinlock held */
it8708_set_carrier_params(struct ite_dev * dev,bool high_freq,bool use_demodulator,u8 carrier_freq_bits,u8 allowance_bits,u8 pulse_width_bits)786*4882a593Smuzhiyun static void it8708_set_carrier_params(struct ite_dev *dev, bool high_freq,
787*4882a593Smuzhiyun 				      bool use_demodulator,
788*4882a593Smuzhiyun 				      u8 carrier_freq_bits, u8 allowance_bits,
789*4882a593Smuzhiyun 				      u8 pulse_width_bits)
790*4882a593Smuzhiyun {
791*4882a593Smuzhiyun 	u8 val;
792*4882a593Smuzhiyun 
793*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
794*4882a593Smuzhiyun 
795*4882a593Smuzhiyun 	/* program the C0CFR register, with HRAE=1 */
796*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT8708_BANKSEL) | IT8708_HRAE,
797*4882a593Smuzhiyun 		dev->cir_addr + IT8708_BANKSEL);
798*4882a593Smuzhiyun 
799*4882a593Smuzhiyun 	val = (inb(dev->cir_addr + IT8708_C0CFR)
800*4882a593Smuzhiyun 		& ~(IT85_HCFS | IT85_CFQ)) | carrier_freq_bits;
801*4882a593Smuzhiyun 
802*4882a593Smuzhiyun 	if (high_freq)
803*4882a593Smuzhiyun 		val |= IT85_HCFS;
804*4882a593Smuzhiyun 
805*4882a593Smuzhiyun 	outb(val, dev->cir_addr + IT8708_C0CFR);
806*4882a593Smuzhiyun 
807*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT8708_BANKSEL) & ~IT8708_HRAE,
808*4882a593Smuzhiyun 		   dev->cir_addr + IT8708_BANKSEL);
809*4882a593Smuzhiyun 
810*4882a593Smuzhiyun 	/* program the C0RCR register */
811*4882a593Smuzhiyun 	val = inb(dev->cir_addr + IT8708_C0RCR)
812*4882a593Smuzhiyun 		& ~(IT85_RXEND | IT85_RXDCR);
813*4882a593Smuzhiyun 
814*4882a593Smuzhiyun 	if (use_demodulator)
815*4882a593Smuzhiyun 		val |= IT85_RXEND;
816*4882a593Smuzhiyun 
817*4882a593Smuzhiyun 	val |= allowance_bits;
818*4882a593Smuzhiyun 
819*4882a593Smuzhiyun 	outb(val, dev->cir_addr + IT8708_C0RCR);
820*4882a593Smuzhiyun 
821*4882a593Smuzhiyun 	/* program the C0TCR register */
822*4882a593Smuzhiyun 	val = inb(dev->cir_addr + IT8708_C0TCR) & ~IT85_TXMPW;
823*4882a593Smuzhiyun 	val |= pulse_width_bits;
824*4882a593Smuzhiyun 	outb(val, dev->cir_addr + IT8708_C0TCR);
825*4882a593Smuzhiyun }
826*4882a593Smuzhiyun 
827*4882a593Smuzhiyun /* read up to buf_size bytes from the RX FIFO; to be called with the spinlock
828*4882a593Smuzhiyun  * held */
it8708_get_rx_bytes(struct ite_dev * dev,u8 * buf,int buf_size)829*4882a593Smuzhiyun static int it8708_get_rx_bytes(struct ite_dev *dev, u8 * buf, int buf_size)
830*4882a593Smuzhiyun {
831*4882a593Smuzhiyun 	int fifo, read = 0;
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
834*4882a593Smuzhiyun 
835*4882a593Smuzhiyun 	/* read how many bytes are still in the FIFO */
836*4882a593Smuzhiyun 	fifo = inb(dev->cir_addr + IT8708_C0RFSR) & IT85_RXFBC;
837*4882a593Smuzhiyun 
838*4882a593Smuzhiyun 	while (fifo > 0 && buf_size > 0) {
839*4882a593Smuzhiyun 		*(buf++) = inb(dev->cir_addr + IT8708_C0DR);
840*4882a593Smuzhiyun 		fifo--;
841*4882a593Smuzhiyun 		read++;
842*4882a593Smuzhiyun 		buf_size--;
843*4882a593Smuzhiyun 	}
844*4882a593Smuzhiyun 
845*4882a593Smuzhiyun 	return read;
846*4882a593Smuzhiyun }
847*4882a593Smuzhiyun 
848*4882a593Smuzhiyun /* return how many bytes are still in the FIFO; this will be called
849*4882a593Smuzhiyun  * with the device spinlock NOT HELD while waiting for the TX FIFO to get
850*4882a593Smuzhiyun  * empty; let's expect this won't be a problem */
it8708_get_tx_used_slots(struct ite_dev * dev)851*4882a593Smuzhiyun static int it8708_get_tx_used_slots(struct ite_dev *dev)
852*4882a593Smuzhiyun {
853*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
854*4882a593Smuzhiyun 
855*4882a593Smuzhiyun 	return inb(dev->cir_addr + IT8708_C0TFSR) & IT85_TXFBC;
856*4882a593Smuzhiyun }
857*4882a593Smuzhiyun 
858*4882a593Smuzhiyun /* put a byte to the TX fifo; this should be called with the spinlock held */
it8708_put_tx_byte(struct ite_dev * dev,u8 value)859*4882a593Smuzhiyun static void it8708_put_tx_byte(struct ite_dev *dev, u8 value)
860*4882a593Smuzhiyun {
861*4882a593Smuzhiyun 	outb(value, dev->cir_addr + IT8708_C0DR);
862*4882a593Smuzhiyun }
863*4882a593Smuzhiyun 
864*4882a593Smuzhiyun /* idle the receiver so that we won't receive samples until another
865*4882a593Smuzhiyun   pulse is detected; this must be called with the device spinlock held */
it8708_idle_rx(struct ite_dev * dev)866*4882a593Smuzhiyun static void it8708_idle_rx(struct ite_dev *dev)
867*4882a593Smuzhiyun {
868*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
869*4882a593Smuzhiyun 
870*4882a593Smuzhiyun 	/* disable streaming by clearing RXACT writing it as 1 */
871*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT8708_C0RCR) | IT85_RXACT,
872*4882a593Smuzhiyun 		dev->cir_addr + IT8708_C0RCR);
873*4882a593Smuzhiyun 
874*4882a593Smuzhiyun 	/* clear the FIFO */
875*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT8708_C0MSTCR) | IT85_FIFOCLR,
876*4882a593Smuzhiyun 		dev->cir_addr + IT8708_C0MSTCR);
877*4882a593Smuzhiyun }
878*4882a593Smuzhiyun 
879*4882a593Smuzhiyun /* disable the receiver; this must be called with the device spinlock held */
it8708_disable_rx(struct ite_dev * dev)880*4882a593Smuzhiyun static void it8708_disable_rx(struct ite_dev *dev)
881*4882a593Smuzhiyun {
882*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
883*4882a593Smuzhiyun 
884*4882a593Smuzhiyun 	/* disable the receiver interrupts */
885*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT8708_C0IER) &
886*4882a593Smuzhiyun 		~(IT85_RDAIE | IT85_RFOIE),
887*4882a593Smuzhiyun 		dev->cir_addr + IT8708_C0IER);
888*4882a593Smuzhiyun 
889*4882a593Smuzhiyun 	/* disable the receiver */
890*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT8708_C0RCR) & ~IT85_RXEN,
891*4882a593Smuzhiyun 		dev->cir_addr + IT8708_C0RCR);
892*4882a593Smuzhiyun 
893*4882a593Smuzhiyun 	/* clear the FIFO and RXACT (actually RXACT should have been cleared
894*4882a593Smuzhiyun 	 * in the previous outb() call) */
895*4882a593Smuzhiyun 	it8708_idle_rx(dev);
896*4882a593Smuzhiyun }
897*4882a593Smuzhiyun 
898*4882a593Smuzhiyun /* enable the receiver; this must be called with the device spinlock held */
it8708_enable_rx(struct ite_dev * dev)899*4882a593Smuzhiyun static void it8708_enable_rx(struct ite_dev *dev)
900*4882a593Smuzhiyun {
901*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
902*4882a593Smuzhiyun 
903*4882a593Smuzhiyun 	/* enable the receiver by setting RXEN */
904*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT8708_C0RCR) | IT85_RXEN,
905*4882a593Smuzhiyun 		dev->cir_addr + IT8708_C0RCR);
906*4882a593Smuzhiyun 
907*4882a593Smuzhiyun 	/* just prepare it to idle for the next reception */
908*4882a593Smuzhiyun 	it8708_idle_rx(dev);
909*4882a593Smuzhiyun 
910*4882a593Smuzhiyun 	/* enable the receiver interrupts and master enable flag */
911*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT8708_C0IER)
912*4882a593Smuzhiyun 		|IT85_RDAIE | IT85_RFOIE | IT85_IEC,
913*4882a593Smuzhiyun 		dev->cir_addr + IT8708_C0IER);
914*4882a593Smuzhiyun }
915*4882a593Smuzhiyun 
916*4882a593Smuzhiyun /* disable the transmitter interrupt; this must be called with the device
917*4882a593Smuzhiyun  * spinlock held */
it8708_disable_tx_interrupt(struct ite_dev * dev)918*4882a593Smuzhiyun static void it8708_disable_tx_interrupt(struct ite_dev *dev)
919*4882a593Smuzhiyun {
920*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
921*4882a593Smuzhiyun 
922*4882a593Smuzhiyun 	/* disable the transmitter interrupts */
923*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT8708_C0IER) & ~IT85_TLDLIE,
924*4882a593Smuzhiyun 		dev->cir_addr + IT8708_C0IER);
925*4882a593Smuzhiyun }
926*4882a593Smuzhiyun 
927*4882a593Smuzhiyun /* enable the transmitter interrupt; this must be called with the device
928*4882a593Smuzhiyun  * spinlock held */
it8708_enable_tx_interrupt(struct ite_dev * dev)929*4882a593Smuzhiyun static void it8708_enable_tx_interrupt(struct ite_dev *dev)
930*4882a593Smuzhiyun {
931*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
932*4882a593Smuzhiyun 
933*4882a593Smuzhiyun 	/* enable the transmitter interrupts and master enable flag */
934*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT8708_C0IER)
935*4882a593Smuzhiyun 		|IT85_TLDLIE | IT85_IEC,
936*4882a593Smuzhiyun 		dev->cir_addr + IT8708_C0IER);
937*4882a593Smuzhiyun }
938*4882a593Smuzhiyun 
939*4882a593Smuzhiyun /* disable the device; this must be called with the device spinlock held */
it8708_disable(struct ite_dev * dev)940*4882a593Smuzhiyun static void it8708_disable(struct ite_dev *dev)
941*4882a593Smuzhiyun {
942*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
943*4882a593Smuzhiyun 
944*4882a593Smuzhiyun 	/* clear out all interrupt enable flags */
945*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT8708_C0IER) &
946*4882a593Smuzhiyun 		~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
947*4882a593Smuzhiyun 		dev->cir_addr + IT8708_C0IER);
948*4882a593Smuzhiyun 
949*4882a593Smuzhiyun 	/* disable the receiver */
950*4882a593Smuzhiyun 	it8708_disable_rx(dev);
951*4882a593Smuzhiyun 
952*4882a593Smuzhiyun 	/* erase the FIFO */
953*4882a593Smuzhiyun 	outb(IT85_FIFOCLR | inb(dev->cir_addr + IT8708_C0MSTCR),
954*4882a593Smuzhiyun 		dev->cir_addr + IT8708_C0MSTCR);
955*4882a593Smuzhiyun }
956*4882a593Smuzhiyun 
957*4882a593Smuzhiyun /* initialize the hardware */
it8708_init_hardware(struct ite_dev * dev)958*4882a593Smuzhiyun static void it8708_init_hardware(struct ite_dev *dev)
959*4882a593Smuzhiyun {
960*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
961*4882a593Smuzhiyun 
962*4882a593Smuzhiyun 	/* disable all the interrupts */
963*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT8708_C0IER) &
964*4882a593Smuzhiyun 		~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
965*4882a593Smuzhiyun 		dev->cir_addr + IT8708_C0IER);
966*4882a593Smuzhiyun 
967*4882a593Smuzhiyun 	/* program the baud rate divisor */
968*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT8708_BANKSEL) | IT8708_HRAE,
969*4882a593Smuzhiyun 		dev->cir_addr + IT8708_BANKSEL);
970*4882a593Smuzhiyun 
971*4882a593Smuzhiyun 	outb(ITE_BAUDRATE_DIVISOR & 0xff, dev->cir_addr + IT8708_C0BDLR);
972*4882a593Smuzhiyun 	outb((ITE_BAUDRATE_DIVISOR >> 8) & 0xff,
973*4882a593Smuzhiyun 		   dev->cir_addr + IT8708_C0BDHR);
974*4882a593Smuzhiyun 
975*4882a593Smuzhiyun 	outb(inb(dev->cir_addr + IT8708_BANKSEL) & ~IT8708_HRAE,
976*4882a593Smuzhiyun 		   dev->cir_addr + IT8708_BANKSEL);
977*4882a593Smuzhiyun 
978*4882a593Smuzhiyun 	/* program the C0MSTCR register defaults */
979*4882a593Smuzhiyun 	outb((inb(dev->cir_addr + IT8708_C0MSTCR) &
980*4882a593Smuzhiyun 			~(IT85_ILSEL | IT85_ILE | IT85_FIFOTL |
981*4882a593Smuzhiyun 			  IT85_FIFOCLR | IT85_RESET)) |
982*4882a593Smuzhiyun 		       IT85_FIFOTL_DEFAULT,
983*4882a593Smuzhiyun 		       dev->cir_addr + IT8708_C0MSTCR);
984*4882a593Smuzhiyun 
985*4882a593Smuzhiyun 	/* program the C0RCR register defaults */
986*4882a593Smuzhiyun 	outb((inb(dev->cir_addr + IT8708_C0RCR) &
987*4882a593Smuzhiyun 			~(IT85_RXEN | IT85_RDWOS | IT85_RXEND |
988*4882a593Smuzhiyun 			  IT85_RXACT | IT85_RXDCR)) |
989*4882a593Smuzhiyun 		       ITE_RXDCR_DEFAULT,
990*4882a593Smuzhiyun 		       dev->cir_addr + IT8708_C0RCR);
991*4882a593Smuzhiyun 
992*4882a593Smuzhiyun 	/* program the C0TCR register defaults */
993*4882a593Smuzhiyun 	outb((inb(dev->cir_addr + IT8708_C0TCR) &
994*4882a593Smuzhiyun 			~(IT85_TXMPM | IT85_TXMPW))
995*4882a593Smuzhiyun 		       |IT85_TXRLE | IT85_TXENDF |
996*4882a593Smuzhiyun 		       IT85_TXMPM_DEFAULT | IT85_TXMPW_DEFAULT,
997*4882a593Smuzhiyun 		       dev->cir_addr + IT8708_C0TCR);
998*4882a593Smuzhiyun 
999*4882a593Smuzhiyun 	/* program the carrier parameters */
1000*4882a593Smuzhiyun 	ite_set_carrier_params(dev);
1001*4882a593Smuzhiyun }
1002*4882a593Smuzhiyun 
1003*4882a593Smuzhiyun /* IT8512F on ITE8709 HW-specific functions */
1004*4882a593Smuzhiyun 
1005*4882a593Smuzhiyun /* read a byte from the SRAM module */
it8709_rm(struct ite_dev * dev,int index)1006*4882a593Smuzhiyun static inline u8 it8709_rm(struct ite_dev *dev, int index)
1007*4882a593Smuzhiyun {
1008*4882a593Smuzhiyun 	outb(index, dev->cir_addr + IT8709_RAM_IDX);
1009*4882a593Smuzhiyun 	return inb(dev->cir_addr + IT8709_RAM_VAL);
1010*4882a593Smuzhiyun }
1011*4882a593Smuzhiyun 
1012*4882a593Smuzhiyun /* write a byte to the SRAM module */
it8709_wm(struct ite_dev * dev,u8 val,int index)1013*4882a593Smuzhiyun static inline void it8709_wm(struct ite_dev *dev, u8 val, int index)
1014*4882a593Smuzhiyun {
1015*4882a593Smuzhiyun 	outb(index, dev->cir_addr + IT8709_RAM_IDX);
1016*4882a593Smuzhiyun 	outb(val, dev->cir_addr + IT8709_RAM_VAL);
1017*4882a593Smuzhiyun }
1018*4882a593Smuzhiyun 
it8709_wait(struct ite_dev * dev)1019*4882a593Smuzhiyun static void it8709_wait(struct ite_dev *dev)
1020*4882a593Smuzhiyun {
1021*4882a593Smuzhiyun 	int i = 0;
1022*4882a593Smuzhiyun 	/*
1023*4882a593Smuzhiyun 	 * loop until device tells it's ready to continue
1024*4882a593Smuzhiyun 	 * iterations count is usually ~750 but can sometimes achieve 13000
1025*4882a593Smuzhiyun 	 */
1026*4882a593Smuzhiyun 	for (i = 0; i < 15000; i++) {
1027*4882a593Smuzhiyun 		udelay(2);
1028*4882a593Smuzhiyun 		if (it8709_rm(dev, IT8709_MODE) == IT8709_IDLE)
1029*4882a593Smuzhiyun 			break;
1030*4882a593Smuzhiyun 	}
1031*4882a593Smuzhiyun }
1032*4882a593Smuzhiyun 
1033*4882a593Smuzhiyun /* read the value of a CIR register */
it8709_rr(struct ite_dev * dev,int index)1034*4882a593Smuzhiyun static u8 it8709_rr(struct ite_dev *dev, int index)
1035*4882a593Smuzhiyun {
1036*4882a593Smuzhiyun 	/* just wait in case the previous access was a write */
1037*4882a593Smuzhiyun 	it8709_wait(dev);
1038*4882a593Smuzhiyun 	it8709_wm(dev, index, IT8709_REG_IDX);
1039*4882a593Smuzhiyun 	it8709_wm(dev, IT8709_READ, IT8709_MODE);
1040*4882a593Smuzhiyun 
1041*4882a593Smuzhiyun 	/* wait for the read data to be available */
1042*4882a593Smuzhiyun 	it8709_wait(dev);
1043*4882a593Smuzhiyun 
1044*4882a593Smuzhiyun 	/* return the read value */
1045*4882a593Smuzhiyun 	return it8709_rm(dev, IT8709_REG_VAL);
1046*4882a593Smuzhiyun }
1047*4882a593Smuzhiyun 
1048*4882a593Smuzhiyun /* write the value of a CIR register */
it8709_wr(struct ite_dev * dev,u8 val,int index)1049*4882a593Smuzhiyun static void it8709_wr(struct ite_dev *dev, u8 val, int index)
1050*4882a593Smuzhiyun {
1051*4882a593Smuzhiyun 	/* we wait before writing, and not afterwards, since this allows us to
1052*4882a593Smuzhiyun 	 * pipeline the host CPU with the microcontroller */
1053*4882a593Smuzhiyun 	it8709_wait(dev);
1054*4882a593Smuzhiyun 	it8709_wm(dev, val, IT8709_REG_VAL);
1055*4882a593Smuzhiyun 	it8709_wm(dev, index, IT8709_REG_IDX);
1056*4882a593Smuzhiyun 	it8709_wm(dev, IT8709_WRITE, IT8709_MODE);
1057*4882a593Smuzhiyun }
1058*4882a593Smuzhiyun 
1059*4882a593Smuzhiyun /* retrieve a bitmask of the current causes for a pending interrupt; this may
1060*4882a593Smuzhiyun  * be composed of ITE_IRQ_TX_FIFO, ITE_IRQ_RX_FIFO and ITE_IRQ_RX_FIFO_OVERRUN
1061*4882a593Smuzhiyun  * */
it8709_get_irq_causes(struct ite_dev * dev)1062*4882a593Smuzhiyun static int it8709_get_irq_causes(struct ite_dev *dev)
1063*4882a593Smuzhiyun {
1064*4882a593Smuzhiyun 	u8 iflags;
1065*4882a593Smuzhiyun 	int ret = 0;
1066*4882a593Smuzhiyun 
1067*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
1068*4882a593Smuzhiyun 
1069*4882a593Smuzhiyun 	/* read the interrupt flags */
1070*4882a593Smuzhiyun 	iflags = it8709_rm(dev, IT8709_IIR);
1071*4882a593Smuzhiyun 
1072*4882a593Smuzhiyun 	if (iflags & IT85_TLDLI)
1073*4882a593Smuzhiyun 		ret |= ITE_IRQ_TX_FIFO;
1074*4882a593Smuzhiyun 	if (iflags & IT85_RDAI)
1075*4882a593Smuzhiyun 		ret |= ITE_IRQ_RX_FIFO;
1076*4882a593Smuzhiyun 	if (iflags & IT85_RFOI)
1077*4882a593Smuzhiyun 		ret |= ITE_IRQ_RX_FIFO_OVERRUN;
1078*4882a593Smuzhiyun 
1079*4882a593Smuzhiyun 	return ret;
1080*4882a593Smuzhiyun }
1081*4882a593Smuzhiyun 
1082*4882a593Smuzhiyun /* set the carrier parameters; to be called with the spinlock held */
it8709_set_carrier_params(struct ite_dev * dev,bool high_freq,bool use_demodulator,u8 carrier_freq_bits,u8 allowance_bits,u8 pulse_width_bits)1083*4882a593Smuzhiyun static void it8709_set_carrier_params(struct ite_dev *dev, bool high_freq,
1084*4882a593Smuzhiyun 				      bool use_demodulator,
1085*4882a593Smuzhiyun 				      u8 carrier_freq_bits, u8 allowance_bits,
1086*4882a593Smuzhiyun 				      u8 pulse_width_bits)
1087*4882a593Smuzhiyun {
1088*4882a593Smuzhiyun 	u8 val;
1089*4882a593Smuzhiyun 
1090*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
1091*4882a593Smuzhiyun 
1092*4882a593Smuzhiyun 	val = (it8709_rr(dev, IT85_C0CFR)
1093*4882a593Smuzhiyun 		     &~(IT85_HCFS | IT85_CFQ)) |
1094*4882a593Smuzhiyun 	    carrier_freq_bits;
1095*4882a593Smuzhiyun 
1096*4882a593Smuzhiyun 	if (high_freq)
1097*4882a593Smuzhiyun 		val |= IT85_HCFS;
1098*4882a593Smuzhiyun 
1099*4882a593Smuzhiyun 	it8709_wr(dev, val, IT85_C0CFR);
1100*4882a593Smuzhiyun 
1101*4882a593Smuzhiyun 	/* program the C0RCR register */
1102*4882a593Smuzhiyun 	val = it8709_rr(dev, IT85_C0RCR)
1103*4882a593Smuzhiyun 		& ~(IT85_RXEND | IT85_RXDCR);
1104*4882a593Smuzhiyun 
1105*4882a593Smuzhiyun 	if (use_demodulator)
1106*4882a593Smuzhiyun 		val |= IT85_RXEND;
1107*4882a593Smuzhiyun 
1108*4882a593Smuzhiyun 	val |= allowance_bits;
1109*4882a593Smuzhiyun 
1110*4882a593Smuzhiyun 	it8709_wr(dev, val, IT85_C0RCR);
1111*4882a593Smuzhiyun 
1112*4882a593Smuzhiyun 	/* program the C0TCR register */
1113*4882a593Smuzhiyun 	val = it8709_rr(dev, IT85_C0TCR) & ~IT85_TXMPW;
1114*4882a593Smuzhiyun 	val |= pulse_width_bits;
1115*4882a593Smuzhiyun 	it8709_wr(dev, val, IT85_C0TCR);
1116*4882a593Smuzhiyun }
1117*4882a593Smuzhiyun 
1118*4882a593Smuzhiyun /* read up to buf_size bytes from the RX FIFO; to be called with the spinlock
1119*4882a593Smuzhiyun  * held */
it8709_get_rx_bytes(struct ite_dev * dev,u8 * buf,int buf_size)1120*4882a593Smuzhiyun static int it8709_get_rx_bytes(struct ite_dev *dev, u8 * buf, int buf_size)
1121*4882a593Smuzhiyun {
1122*4882a593Smuzhiyun 	int fifo, read = 0;
1123*4882a593Smuzhiyun 
1124*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
1125*4882a593Smuzhiyun 
1126*4882a593Smuzhiyun 	/* read how many bytes are still in the FIFO */
1127*4882a593Smuzhiyun 	fifo = it8709_rm(dev, IT8709_RFSR) & IT85_RXFBC;
1128*4882a593Smuzhiyun 
1129*4882a593Smuzhiyun 	while (fifo > 0 && buf_size > 0) {
1130*4882a593Smuzhiyun 		*(buf++) = it8709_rm(dev, IT8709_FIFO + read);
1131*4882a593Smuzhiyun 		fifo--;
1132*4882a593Smuzhiyun 		read++;
1133*4882a593Smuzhiyun 		buf_size--;
1134*4882a593Smuzhiyun 	}
1135*4882a593Smuzhiyun 
1136*4882a593Smuzhiyun 	/* 'clear' the FIFO by setting the writing index to 0; this is
1137*4882a593Smuzhiyun 	 * completely bound to be racy, but we can't help it, since it's a
1138*4882a593Smuzhiyun 	 * limitation of the protocol */
1139*4882a593Smuzhiyun 	it8709_wm(dev, 0, IT8709_RFSR);
1140*4882a593Smuzhiyun 
1141*4882a593Smuzhiyun 	return read;
1142*4882a593Smuzhiyun }
1143*4882a593Smuzhiyun 
1144*4882a593Smuzhiyun /* return how many bytes are still in the FIFO; this will be called
1145*4882a593Smuzhiyun  * with the device spinlock NOT HELD while waiting for the TX FIFO to get
1146*4882a593Smuzhiyun  * empty; let's expect this won't be a problem */
it8709_get_tx_used_slots(struct ite_dev * dev)1147*4882a593Smuzhiyun static int it8709_get_tx_used_slots(struct ite_dev *dev)
1148*4882a593Smuzhiyun {
1149*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
1150*4882a593Smuzhiyun 
1151*4882a593Smuzhiyun 	return it8709_rr(dev, IT85_C0TFSR) & IT85_TXFBC;
1152*4882a593Smuzhiyun }
1153*4882a593Smuzhiyun 
1154*4882a593Smuzhiyun /* put a byte to the TX fifo; this should be called with the spinlock held */
it8709_put_tx_byte(struct ite_dev * dev,u8 value)1155*4882a593Smuzhiyun static void it8709_put_tx_byte(struct ite_dev *dev, u8 value)
1156*4882a593Smuzhiyun {
1157*4882a593Smuzhiyun 	it8709_wr(dev, value, IT85_C0DR);
1158*4882a593Smuzhiyun }
1159*4882a593Smuzhiyun 
1160*4882a593Smuzhiyun /* idle the receiver so that we won't receive samples until another
1161*4882a593Smuzhiyun   pulse is detected; this must be called with the device spinlock held */
it8709_idle_rx(struct ite_dev * dev)1162*4882a593Smuzhiyun static void it8709_idle_rx(struct ite_dev *dev)
1163*4882a593Smuzhiyun {
1164*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
1165*4882a593Smuzhiyun 
1166*4882a593Smuzhiyun 	/* disable streaming by clearing RXACT writing it as 1 */
1167*4882a593Smuzhiyun 	it8709_wr(dev, it8709_rr(dev, IT85_C0RCR) | IT85_RXACT,
1168*4882a593Smuzhiyun 			    IT85_C0RCR);
1169*4882a593Smuzhiyun 
1170*4882a593Smuzhiyun 	/* clear the FIFO */
1171*4882a593Smuzhiyun 	it8709_wr(dev, it8709_rr(dev, IT85_C0MSTCR) | IT85_FIFOCLR,
1172*4882a593Smuzhiyun 			    IT85_C0MSTCR);
1173*4882a593Smuzhiyun }
1174*4882a593Smuzhiyun 
1175*4882a593Smuzhiyun /* disable the receiver; this must be called with the device spinlock held */
it8709_disable_rx(struct ite_dev * dev)1176*4882a593Smuzhiyun static void it8709_disable_rx(struct ite_dev *dev)
1177*4882a593Smuzhiyun {
1178*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
1179*4882a593Smuzhiyun 
1180*4882a593Smuzhiyun 	/* disable the receiver interrupts */
1181*4882a593Smuzhiyun 	it8709_wr(dev, it8709_rr(dev, IT85_C0IER) &
1182*4882a593Smuzhiyun 			    ~(IT85_RDAIE | IT85_RFOIE),
1183*4882a593Smuzhiyun 			    IT85_C0IER);
1184*4882a593Smuzhiyun 
1185*4882a593Smuzhiyun 	/* disable the receiver */
1186*4882a593Smuzhiyun 	it8709_wr(dev, it8709_rr(dev, IT85_C0RCR) & ~IT85_RXEN,
1187*4882a593Smuzhiyun 			    IT85_C0RCR);
1188*4882a593Smuzhiyun 
1189*4882a593Smuzhiyun 	/* clear the FIFO and RXACT (actually RXACT should have been cleared
1190*4882a593Smuzhiyun 	 * in the previous it8709_wr(dev, ) call) */
1191*4882a593Smuzhiyun 	it8709_idle_rx(dev);
1192*4882a593Smuzhiyun }
1193*4882a593Smuzhiyun 
1194*4882a593Smuzhiyun /* enable the receiver; this must be called with the device spinlock held */
it8709_enable_rx(struct ite_dev * dev)1195*4882a593Smuzhiyun static void it8709_enable_rx(struct ite_dev *dev)
1196*4882a593Smuzhiyun {
1197*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
1198*4882a593Smuzhiyun 
1199*4882a593Smuzhiyun 	/* enable the receiver by setting RXEN */
1200*4882a593Smuzhiyun 	it8709_wr(dev, it8709_rr(dev, IT85_C0RCR) | IT85_RXEN,
1201*4882a593Smuzhiyun 			    IT85_C0RCR);
1202*4882a593Smuzhiyun 
1203*4882a593Smuzhiyun 	/* just prepare it to idle for the next reception */
1204*4882a593Smuzhiyun 	it8709_idle_rx(dev);
1205*4882a593Smuzhiyun 
1206*4882a593Smuzhiyun 	/* enable the receiver interrupts and master enable flag */
1207*4882a593Smuzhiyun 	it8709_wr(dev, it8709_rr(dev, IT85_C0IER)
1208*4882a593Smuzhiyun 			    |IT85_RDAIE | IT85_RFOIE | IT85_IEC,
1209*4882a593Smuzhiyun 			    IT85_C0IER);
1210*4882a593Smuzhiyun }
1211*4882a593Smuzhiyun 
1212*4882a593Smuzhiyun /* disable the transmitter interrupt; this must be called with the device
1213*4882a593Smuzhiyun  * spinlock held */
it8709_disable_tx_interrupt(struct ite_dev * dev)1214*4882a593Smuzhiyun static void it8709_disable_tx_interrupt(struct ite_dev *dev)
1215*4882a593Smuzhiyun {
1216*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
1217*4882a593Smuzhiyun 
1218*4882a593Smuzhiyun 	/* disable the transmitter interrupts */
1219*4882a593Smuzhiyun 	it8709_wr(dev, it8709_rr(dev, IT85_C0IER) & ~IT85_TLDLIE,
1220*4882a593Smuzhiyun 			    IT85_C0IER);
1221*4882a593Smuzhiyun }
1222*4882a593Smuzhiyun 
1223*4882a593Smuzhiyun /* enable the transmitter interrupt; this must be called with the device
1224*4882a593Smuzhiyun  * spinlock held */
it8709_enable_tx_interrupt(struct ite_dev * dev)1225*4882a593Smuzhiyun static void it8709_enable_tx_interrupt(struct ite_dev *dev)
1226*4882a593Smuzhiyun {
1227*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
1228*4882a593Smuzhiyun 
1229*4882a593Smuzhiyun 	/* enable the transmitter interrupts and master enable flag */
1230*4882a593Smuzhiyun 	it8709_wr(dev, it8709_rr(dev, IT85_C0IER)
1231*4882a593Smuzhiyun 			    |IT85_TLDLIE | IT85_IEC,
1232*4882a593Smuzhiyun 			    IT85_C0IER);
1233*4882a593Smuzhiyun }
1234*4882a593Smuzhiyun 
1235*4882a593Smuzhiyun /* disable the device; this must be called with the device spinlock held */
it8709_disable(struct ite_dev * dev)1236*4882a593Smuzhiyun static void it8709_disable(struct ite_dev *dev)
1237*4882a593Smuzhiyun {
1238*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
1239*4882a593Smuzhiyun 
1240*4882a593Smuzhiyun 	/* clear out all interrupt enable flags */
1241*4882a593Smuzhiyun 	it8709_wr(dev, it8709_rr(dev, IT85_C0IER) &
1242*4882a593Smuzhiyun 			~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
1243*4882a593Smuzhiyun 		  IT85_C0IER);
1244*4882a593Smuzhiyun 
1245*4882a593Smuzhiyun 	/* disable the receiver */
1246*4882a593Smuzhiyun 	it8709_disable_rx(dev);
1247*4882a593Smuzhiyun 
1248*4882a593Smuzhiyun 	/* erase the FIFO */
1249*4882a593Smuzhiyun 	it8709_wr(dev, IT85_FIFOCLR | it8709_rr(dev, IT85_C0MSTCR),
1250*4882a593Smuzhiyun 			    IT85_C0MSTCR);
1251*4882a593Smuzhiyun }
1252*4882a593Smuzhiyun 
1253*4882a593Smuzhiyun /* initialize the hardware */
it8709_init_hardware(struct ite_dev * dev)1254*4882a593Smuzhiyun static void it8709_init_hardware(struct ite_dev *dev)
1255*4882a593Smuzhiyun {
1256*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
1257*4882a593Smuzhiyun 
1258*4882a593Smuzhiyun 	/* disable all the interrupts */
1259*4882a593Smuzhiyun 	it8709_wr(dev, it8709_rr(dev, IT85_C0IER) &
1260*4882a593Smuzhiyun 			~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
1261*4882a593Smuzhiyun 		  IT85_C0IER);
1262*4882a593Smuzhiyun 
1263*4882a593Smuzhiyun 	/* program the baud rate divisor */
1264*4882a593Smuzhiyun 	it8709_wr(dev, ITE_BAUDRATE_DIVISOR & 0xff, IT85_C0BDLR);
1265*4882a593Smuzhiyun 	it8709_wr(dev, (ITE_BAUDRATE_DIVISOR >> 8) & 0xff,
1266*4882a593Smuzhiyun 			IT85_C0BDHR);
1267*4882a593Smuzhiyun 
1268*4882a593Smuzhiyun 	/* program the C0MSTCR register defaults */
1269*4882a593Smuzhiyun 	it8709_wr(dev, (it8709_rr(dev, IT85_C0MSTCR) &
1270*4882a593Smuzhiyun 			~(IT85_ILSEL | IT85_ILE | IT85_FIFOTL
1271*4882a593Smuzhiyun 			  | IT85_FIFOCLR | IT85_RESET)) | IT85_FIFOTL_DEFAULT,
1272*4882a593Smuzhiyun 		  IT85_C0MSTCR);
1273*4882a593Smuzhiyun 
1274*4882a593Smuzhiyun 	/* program the C0RCR register defaults */
1275*4882a593Smuzhiyun 	it8709_wr(dev, (it8709_rr(dev, IT85_C0RCR) &
1276*4882a593Smuzhiyun 			~(IT85_RXEN | IT85_RDWOS | IT85_RXEND | IT85_RXACT
1277*4882a593Smuzhiyun 			  | IT85_RXDCR)) | ITE_RXDCR_DEFAULT,
1278*4882a593Smuzhiyun 		  IT85_C0RCR);
1279*4882a593Smuzhiyun 
1280*4882a593Smuzhiyun 	/* program the C0TCR register defaults */
1281*4882a593Smuzhiyun 	it8709_wr(dev, (it8709_rr(dev, IT85_C0TCR) & ~(IT85_TXMPM | IT85_TXMPW))
1282*4882a593Smuzhiyun 			| IT85_TXRLE | IT85_TXENDF | IT85_TXMPM_DEFAULT
1283*4882a593Smuzhiyun 			| IT85_TXMPW_DEFAULT,
1284*4882a593Smuzhiyun 		  IT85_C0TCR);
1285*4882a593Smuzhiyun 
1286*4882a593Smuzhiyun 	/* program the carrier parameters */
1287*4882a593Smuzhiyun 	ite_set_carrier_params(dev);
1288*4882a593Smuzhiyun }
1289*4882a593Smuzhiyun 
1290*4882a593Smuzhiyun 
1291*4882a593Smuzhiyun /* generic hardware setup/teardown code */
1292*4882a593Smuzhiyun 
1293*4882a593Smuzhiyun /* activate the device for use */
ite_open(struct rc_dev * rcdev)1294*4882a593Smuzhiyun static int ite_open(struct rc_dev *rcdev)
1295*4882a593Smuzhiyun {
1296*4882a593Smuzhiyun 	struct ite_dev *dev = rcdev->priv;
1297*4882a593Smuzhiyun 	unsigned long flags;
1298*4882a593Smuzhiyun 
1299*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
1300*4882a593Smuzhiyun 
1301*4882a593Smuzhiyun 	spin_lock_irqsave(&dev->lock, flags);
1302*4882a593Smuzhiyun 	dev->in_use = true;
1303*4882a593Smuzhiyun 
1304*4882a593Smuzhiyun 	/* enable the receiver */
1305*4882a593Smuzhiyun 	dev->params.enable_rx(dev);
1306*4882a593Smuzhiyun 
1307*4882a593Smuzhiyun 	spin_unlock_irqrestore(&dev->lock, flags);
1308*4882a593Smuzhiyun 
1309*4882a593Smuzhiyun 	return 0;
1310*4882a593Smuzhiyun }
1311*4882a593Smuzhiyun 
1312*4882a593Smuzhiyun /* deactivate the device for use */
ite_close(struct rc_dev * rcdev)1313*4882a593Smuzhiyun static void ite_close(struct rc_dev *rcdev)
1314*4882a593Smuzhiyun {
1315*4882a593Smuzhiyun 	struct ite_dev *dev = rcdev->priv;
1316*4882a593Smuzhiyun 	unsigned long flags;
1317*4882a593Smuzhiyun 
1318*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
1319*4882a593Smuzhiyun 
1320*4882a593Smuzhiyun 	spin_lock_irqsave(&dev->lock, flags);
1321*4882a593Smuzhiyun 	dev->in_use = false;
1322*4882a593Smuzhiyun 
1323*4882a593Smuzhiyun 	/* wait for any transmission to end */
1324*4882a593Smuzhiyun 	spin_unlock_irqrestore(&dev->lock, flags);
1325*4882a593Smuzhiyun 	wait_event_interruptible(dev->tx_ended, !dev->transmitting);
1326*4882a593Smuzhiyun 	spin_lock_irqsave(&dev->lock, flags);
1327*4882a593Smuzhiyun 
1328*4882a593Smuzhiyun 	dev->params.disable(dev);
1329*4882a593Smuzhiyun 
1330*4882a593Smuzhiyun 	spin_unlock_irqrestore(&dev->lock, flags);
1331*4882a593Smuzhiyun }
1332*4882a593Smuzhiyun 
1333*4882a593Smuzhiyun /* supported models and their parameters */
1334*4882a593Smuzhiyun static const struct ite_dev_params ite_dev_descs[] = {
1335*4882a593Smuzhiyun 	{	/* 0: ITE8704 */
1336*4882a593Smuzhiyun 	       .model = "ITE8704 CIR transceiver",
1337*4882a593Smuzhiyun 	       .io_region_size = IT87_IOREG_LENGTH,
1338*4882a593Smuzhiyun 	       .io_rsrc_no = 0,
1339*4882a593Smuzhiyun 	       .hw_tx_capable = true,
1340*4882a593Smuzhiyun 	       .sample_period = (u32) (1000000000ULL / 115200),
1341*4882a593Smuzhiyun 	       .tx_carrier_freq = 38000,
1342*4882a593Smuzhiyun 	       .tx_duty_cycle = 33,
1343*4882a593Smuzhiyun 	       .rx_low_carrier_freq = 0,
1344*4882a593Smuzhiyun 	       .rx_high_carrier_freq = 0,
1345*4882a593Smuzhiyun 
1346*4882a593Smuzhiyun 		/* operations */
1347*4882a593Smuzhiyun 	       .get_irq_causes = it87_get_irq_causes,
1348*4882a593Smuzhiyun 	       .enable_rx = it87_enable_rx,
1349*4882a593Smuzhiyun 	       .idle_rx = it87_idle_rx,
1350*4882a593Smuzhiyun 	       .disable_rx = it87_idle_rx,
1351*4882a593Smuzhiyun 	       .get_rx_bytes = it87_get_rx_bytes,
1352*4882a593Smuzhiyun 	       .enable_tx_interrupt = it87_enable_tx_interrupt,
1353*4882a593Smuzhiyun 	       .disable_tx_interrupt = it87_disable_tx_interrupt,
1354*4882a593Smuzhiyun 	       .get_tx_used_slots = it87_get_tx_used_slots,
1355*4882a593Smuzhiyun 	       .put_tx_byte = it87_put_tx_byte,
1356*4882a593Smuzhiyun 	       .disable = it87_disable,
1357*4882a593Smuzhiyun 	       .init_hardware = it87_init_hardware,
1358*4882a593Smuzhiyun 	       .set_carrier_params = it87_set_carrier_params,
1359*4882a593Smuzhiyun 	       },
1360*4882a593Smuzhiyun 	{	/* 1: ITE8713 */
1361*4882a593Smuzhiyun 	       .model = "ITE8713 CIR transceiver",
1362*4882a593Smuzhiyun 	       .io_region_size = IT87_IOREG_LENGTH,
1363*4882a593Smuzhiyun 	       .io_rsrc_no = 0,
1364*4882a593Smuzhiyun 	       .hw_tx_capable = true,
1365*4882a593Smuzhiyun 	       .sample_period = (u32) (1000000000ULL / 115200),
1366*4882a593Smuzhiyun 	       .tx_carrier_freq = 38000,
1367*4882a593Smuzhiyun 	       .tx_duty_cycle = 33,
1368*4882a593Smuzhiyun 	       .rx_low_carrier_freq = 0,
1369*4882a593Smuzhiyun 	       .rx_high_carrier_freq = 0,
1370*4882a593Smuzhiyun 
1371*4882a593Smuzhiyun 		/* operations */
1372*4882a593Smuzhiyun 	       .get_irq_causes = it87_get_irq_causes,
1373*4882a593Smuzhiyun 	       .enable_rx = it87_enable_rx,
1374*4882a593Smuzhiyun 	       .idle_rx = it87_idle_rx,
1375*4882a593Smuzhiyun 	       .disable_rx = it87_idle_rx,
1376*4882a593Smuzhiyun 	       .get_rx_bytes = it87_get_rx_bytes,
1377*4882a593Smuzhiyun 	       .enable_tx_interrupt = it87_enable_tx_interrupt,
1378*4882a593Smuzhiyun 	       .disable_tx_interrupt = it87_disable_tx_interrupt,
1379*4882a593Smuzhiyun 	       .get_tx_used_slots = it87_get_tx_used_slots,
1380*4882a593Smuzhiyun 	       .put_tx_byte = it87_put_tx_byte,
1381*4882a593Smuzhiyun 	       .disable = it87_disable,
1382*4882a593Smuzhiyun 	       .init_hardware = it87_init_hardware,
1383*4882a593Smuzhiyun 	       .set_carrier_params = it87_set_carrier_params,
1384*4882a593Smuzhiyun 	       },
1385*4882a593Smuzhiyun 	{	/* 2: ITE8708 */
1386*4882a593Smuzhiyun 	       .model = "ITE8708 CIR transceiver",
1387*4882a593Smuzhiyun 	       .io_region_size = IT8708_IOREG_LENGTH,
1388*4882a593Smuzhiyun 	       .io_rsrc_no = 0,
1389*4882a593Smuzhiyun 	       .hw_tx_capable = true,
1390*4882a593Smuzhiyun 	       .sample_period = (u32) (1000000000ULL / 115200),
1391*4882a593Smuzhiyun 	       .tx_carrier_freq = 38000,
1392*4882a593Smuzhiyun 	       .tx_duty_cycle = 33,
1393*4882a593Smuzhiyun 	       .rx_low_carrier_freq = 0,
1394*4882a593Smuzhiyun 	       .rx_high_carrier_freq = 0,
1395*4882a593Smuzhiyun 
1396*4882a593Smuzhiyun 		/* operations */
1397*4882a593Smuzhiyun 	       .get_irq_causes = it8708_get_irq_causes,
1398*4882a593Smuzhiyun 	       .enable_rx = it8708_enable_rx,
1399*4882a593Smuzhiyun 	       .idle_rx = it8708_idle_rx,
1400*4882a593Smuzhiyun 	       .disable_rx = it8708_idle_rx,
1401*4882a593Smuzhiyun 	       .get_rx_bytes = it8708_get_rx_bytes,
1402*4882a593Smuzhiyun 	       .enable_tx_interrupt = it8708_enable_tx_interrupt,
1403*4882a593Smuzhiyun 	       .disable_tx_interrupt =
1404*4882a593Smuzhiyun 	       it8708_disable_tx_interrupt,
1405*4882a593Smuzhiyun 	       .get_tx_used_slots = it8708_get_tx_used_slots,
1406*4882a593Smuzhiyun 	       .put_tx_byte = it8708_put_tx_byte,
1407*4882a593Smuzhiyun 	       .disable = it8708_disable,
1408*4882a593Smuzhiyun 	       .init_hardware = it8708_init_hardware,
1409*4882a593Smuzhiyun 	       .set_carrier_params = it8708_set_carrier_params,
1410*4882a593Smuzhiyun 	       },
1411*4882a593Smuzhiyun 	{	/* 3: ITE8709 */
1412*4882a593Smuzhiyun 	       .model = "ITE8709 CIR transceiver",
1413*4882a593Smuzhiyun 	       .io_region_size = IT8709_IOREG_LENGTH,
1414*4882a593Smuzhiyun 	       .io_rsrc_no = 2,
1415*4882a593Smuzhiyun 	       .hw_tx_capable = true,
1416*4882a593Smuzhiyun 	       .sample_period = (u32) (1000000000ULL / 115200),
1417*4882a593Smuzhiyun 	       .tx_carrier_freq = 38000,
1418*4882a593Smuzhiyun 	       .tx_duty_cycle = 33,
1419*4882a593Smuzhiyun 	       .rx_low_carrier_freq = 0,
1420*4882a593Smuzhiyun 	       .rx_high_carrier_freq = 0,
1421*4882a593Smuzhiyun 
1422*4882a593Smuzhiyun 		/* operations */
1423*4882a593Smuzhiyun 	       .get_irq_causes = it8709_get_irq_causes,
1424*4882a593Smuzhiyun 	       .enable_rx = it8709_enable_rx,
1425*4882a593Smuzhiyun 	       .idle_rx = it8709_idle_rx,
1426*4882a593Smuzhiyun 	       .disable_rx = it8709_idle_rx,
1427*4882a593Smuzhiyun 	       .get_rx_bytes = it8709_get_rx_bytes,
1428*4882a593Smuzhiyun 	       .enable_tx_interrupt = it8709_enable_tx_interrupt,
1429*4882a593Smuzhiyun 	       .disable_tx_interrupt =
1430*4882a593Smuzhiyun 	       it8709_disable_tx_interrupt,
1431*4882a593Smuzhiyun 	       .get_tx_used_slots = it8709_get_tx_used_slots,
1432*4882a593Smuzhiyun 	       .put_tx_byte = it8709_put_tx_byte,
1433*4882a593Smuzhiyun 	       .disable = it8709_disable,
1434*4882a593Smuzhiyun 	       .init_hardware = it8709_init_hardware,
1435*4882a593Smuzhiyun 	       .set_carrier_params = it8709_set_carrier_params,
1436*4882a593Smuzhiyun 	       },
1437*4882a593Smuzhiyun };
1438*4882a593Smuzhiyun 
1439*4882a593Smuzhiyun static const struct pnp_device_id ite_ids[] = {
1440*4882a593Smuzhiyun 	{"ITE8704", 0},		/* Default model */
1441*4882a593Smuzhiyun 	{"ITE8713", 1},		/* CIR found in EEEBox 1501U */
1442*4882a593Smuzhiyun 	{"ITE8708", 2},		/* Bridged IT8512 */
1443*4882a593Smuzhiyun 	{"ITE8709", 3},		/* SRAM-Bridged IT8512 */
1444*4882a593Smuzhiyun 	{"", 0},
1445*4882a593Smuzhiyun };
1446*4882a593Smuzhiyun 
1447*4882a593Smuzhiyun /* allocate memory, probe hardware, and initialize everything */
ite_probe(struct pnp_dev * pdev,const struct pnp_device_id * dev_id)1448*4882a593Smuzhiyun static int ite_probe(struct pnp_dev *pdev, const struct pnp_device_id
1449*4882a593Smuzhiyun 		     *dev_id)
1450*4882a593Smuzhiyun {
1451*4882a593Smuzhiyun 	const struct ite_dev_params *dev_desc = NULL;
1452*4882a593Smuzhiyun 	struct ite_dev *itdev = NULL;
1453*4882a593Smuzhiyun 	struct rc_dev *rdev = NULL;
1454*4882a593Smuzhiyun 	int ret = -ENOMEM;
1455*4882a593Smuzhiyun 	int model_no;
1456*4882a593Smuzhiyun 	int io_rsrc_no;
1457*4882a593Smuzhiyun 
1458*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
1459*4882a593Smuzhiyun 
1460*4882a593Smuzhiyun 	itdev = kzalloc(sizeof(struct ite_dev), GFP_KERNEL);
1461*4882a593Smuzhiyun 	if (!itdev)
1462*4882a593Smuzhiyun 		return ret;
1463*4882a593Smuzhiyun 
1464*4882a593Smuzhiyun 	/* input device for IR remote (and tx) */
1465*4882a593Smuzhiyun 	rdev = rc_allocate_device(RC_DRIVER_IR_RAW);
1466*4882a593Smuzhiyun 	if (!rdev)
1467*4882a593Smuzhiyun 		goto exit_free_dev_rdev;
1468*4882a593Smuzhiyun 	itdev->rdev = rdev;
1469*4882a593Smuzhiyun 
1470*4882a593Smuzhiyun 	ret = -ENODEV;
1471*4882a593Smuzhiyun 
1472*4882a593Smuzhiyun 	/* get the model number */
1473*4882a593Smuzhiyun 	model_no = (int)dev_id->driver_data;
1474*4882a593Smuzhiyun 	ite_pr(KERN_NOTICE, "Auto-detected model: %s\n",
1475*4882a593Smuzhiyun 		ite_dev_descs[model_no].model);
1476*4882a593Smuzhiyun 
1477*4882a593Smuzhiyun 	if (model_number >= 0 && model_number < ARRAY_SIZE(ite_dev_descs)) {
1478*4882a593Smuzhiyun 		model_no = model_number;
1479*4882a593Smuzhiyun 		ite_pr(KERN_NOTICE, "The model has been fixed by a module parameter.");
1480*4882a593Smuzhiyun 	}
1481*4882a593Smuzhiyun 
1482*4882a593Smuzhiyun 	ite_pr(KERN_NOTICE, "Using model: %s\n", ite_dev_descs[model_no].model);
1483*4882a593Smuzhiyun 
1484*4882a593Smuzhiyun 	/* get the description for the device */
1485*4882a593Smuzhiyun 	dev_desc = &ite_dev_descs[model_no];
1486*4882a593Smuzhiyun 	io_rsrc_no = dev_desc->io_rsrc_no;
1487*4882a593Smuzhiyun 
1488*4882a593Smuzhiyun 	/* validate pnp resources */
1489*4882a593Smuzhiyun 	if (!pnp_port_valid(pdev, io_rsrc_no) ||
1490*4882a593Smuzhiyun 	    pnp_port_len(pdev, io_rsrc_no) != dev_desc->io_region_size) {
1491*4882a593Smuzhiyun 		dev_err(&pdev->dev, "IR PNP Port not valid!\n");
1492*4882a593Smuzhiyun 		goto exit_free_dev_rdev;
1493*4882a593Smuzhiyun 	}
1494*4882a593Smuzhiyun 
1495*4882a593Smuzhiyun 	if (!pnp_irq_valid(pdev, 0)) {
1496*4882a593Smuzhiyun 		dev_err(&pdev->dev, "PNP IRQ not valid!\n");
1497*4882a593Smuzhiyun 		goto exit_free_dev_rdev;
1498*4882a593Smuzhiyun 	}
1499*4882a593Smuzhiyun 
1500*4882a593Smuzhiyun 	/* store resource values */
1501*4882a593Smuzhiyun 	itdev->cir_addr = pnp_port_start(pdev, io_rsrc_no);
1502*4882a593Smuzhiyun 	itdev->cir_irq = pnp_irq(pdev, 0);
1503*4882a593Smuzhiyun 
1504*4882a593Smuzhiyun 	/* initialize spinlocks */
1505*4882a593Smuzhiyun 	spin_lock_init(&itdev->lock);
1506*4882a593Smuzhiyun 
1507*4882a593Smuzhiyun 	/* set driver data into the pnp device */
1508*4882a593Smuzhiyun 	pnp_set_drvdata(pdev, itdev);
1509*4882a593Smuzhiyun 	itdev->pdev = pdev;
1510*4882a593Smuzhiyun 
1511*4882a593Smuzhiyun 	/* initialize waitqueues for transmission */
1512*4882a593Smuzhiyun 	init_waitqueue_head(&itdev->tx_queue);
1513*4882a593Smuzhiyun 	init_waitqueue_head(&itdev->tx_ended);
1514*4882a593Smuzhiyun 
1515*4882a593Smuzhiyun 	/* copy model-specific parameters */
1516*4882a593Smuzhiyun 	itdev->params = *dev_desc;
1517*4882a593Smuzhiyun 
1518*4882a593Smuzhiyun 	/* apply any overrides */
1519*4882a593Smuzhiyun 	if (sample_period > 0)
1520*4882a593Smuzhiyun 		itdev->params.sample_period = sample_period;
1521*4882a593Smuzhiyun 
1522*4882a593Smuzhiyun 	if (tx_carrier_freq > 0)
1523*4882a593Smuzhiyun 		itdev->params.tx_carrier_freq = tx_carrier_freq;
1524*4882a593Smuzhiyun 
1525*4882a593Smuzhiyun 	if (tx_duty_cycle > 0 && tx_duty_cycle <= 100)
1526*4882a593Smuzhiyun 		itdev->params.tx_duty_cycle = tx_duty_cycle;
1527*4882a593Smuzhiyun 
1528*4882a593Smuzhiyun 	if (rx_low_carrier_freq > 0)
1529*4882a593Smuzhiyun 		itdev->params.rx_low_carrier_freq = rx_low_carrier_freq;
1530*4882a593Smuzhiyun 
1531*4882a593Smuzhiyun 	if (rx_high_carrier_freq > 0)
1532*4882a593Smuzhiyun 		itdev->params.rx_high_carrier_freq = rx_high_carrier_freq;
1533*4882a593Smuzhiyun 
1534*4882a593Smuzhiyun 	/* print out parameters */
1535*4882a593Smuzhiyun 	ite_pr(KERN_NOTICE, "TX-capable: %d\n", (int)
1536*4882a593Smuzhiyun 			 itdev->params.hw_tx_capable);
1537*4882a593Smuzhiyun 	ite_pr(KERN_NOTICE, "Sample period (ns): %ld\n", (long)
1538*4882a593Smuzhiyun 		     itdev->params.sample_period);
1539*4882a593Smuzhiyun 	ite_pr(KERN_NOTICE, "TX carrier frequency (Hz): %d\n", (int)
1540*4882a593Smuzhiyun 		     itdev->params.tx_carrier_freq);
1541*4882a593Smuzhiyun 	ite_pr(KERN_NOTICE, "TX duty cycle (%%): %d\n", (int)
1542*4882a593Smuzhiyun 		     itdev->params.tx_duty_cycle);
1543*4882a593Smuzhiyun 	ite_pr(KERN_NOTICE, "RX low carrier frequency (Hz): %d\n", (int)
1544*4882a593Smuzhiyun 		     itdev->params.rx_low_carrier_freq);
1545*4882a593Smuzhiyun 	ite_pr(KERN_NOTICE, "RX high carrier frequency (Hz): %d\n", (int)
1546*4882a593Smuzhiyun 		     itdev->params.rx_high_carrier_freq);
1547*4882a593Smuzhiyun 
1548*4882a593Smuzhiyun 	/* set up hardware initial state */
1549*4882a593Smuzhiyun 	itdev->params.init_hardware(itdev);
1550*4882a593Smuzhiyun 
1551*4882a593Smuzhiyun 	/* set up ir-core props */
1552*4882a593Smuzhiyun 	rdev->priv = itdev;
1553*4882a593Smuzhiyun 	rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
1554*4882a593Smuzhiyun 	rdev->open = ite_open;
1555*4882a593Smuzhiyun 	rdev->close = ite_close;
1556*4882a593Smuzhiyun 	rdev->s_idle = ite_s_idle;
1557*4882a593Smuzhiyun 	rdev->s_rx_carrier_range = ite_set_rx_carrier_range;
1558*4882a593Smuzhiyun 	/* FIFO threshold is 17 bytes, so 17 * 8 samples minimum */
1559*4882a593Smuzhiyun 	rdev->min_timeout = 17 * 8 * ITE_BAUDRATE_DIVISOR *
1560*4882a593Smuzhiyun 			    itdev->params.sample_period / 1000;
1561*4882a593Smuzhiyun 	rdev->timeout = IR_DEFAULT_TIMEOUT;
1562*4882a593Smuzhiyun 	rdev->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
1563*4882a593Smuzhiyun 	rdev->rx_resolution = ITE_BAUDRATE_DIVISOR *
1564*4882a593Smuzhiyun 				itdev->params.sample_period / 1000;
1565*4882a593Smuzhiyun 	rdev->tx_resolution = ITE_BAUDRATE_DIVISOR *
1566*4882a593Smuzhiyun 				itdev->params.sample_period / 1000;
1567*4882a593Smuzhiyun 
1568*4882a593Smuzhiyun 	/* set up transmitter related values if needed */
1569*4882a593Smuzhiyun 	if (itdev->params.hw_tx_capable) {
1570*4882a593Smuzhiyun 		rdev->tx_ir = ite_tx_ir;
1571*4882a593Smuzhiyun 		rdev->s_tx_carrier = ite_set_tx_carrier;
1572*4882a593Smuzhiyun 		rdev->s_tx_duty_cycle = ite_set_tx_duty_cycle;
1573*4882a593Smuzhiyun 	}
1574*4882a593Smuzhiyun 
1575*4882a593Smuzhiyun 	rdev->device_name = dev_desc->model;
1576*4882a593Smuzhiyun 	rdev->input_id.bustype = BUS_HOST;
1577*4882a593Smuzhiyun 	rdev->input_id.vendor = PCI_VENDOR_ID_ITE;
1578*4882a593Smuzhiyun 	rdev->input_id.product = 0;
1579*4882a593Smuzhiyun 	rdev->input_id.version = 0;
1580*4882a593Smuzhiyun 	rdev->driver_name = ITE_DRIVER_NAME;
1581*4882a593Smuzhiyun 	rdev->map_name = RC_MAP_RC6_MCE;
1582*4882a593Smuzhiyun 
1583*4882a593Smuzhiyun 	ret = rc_register_device(rdev);
1584*4882a593Smuzhiyun 	if (ret)
1585*4882a593Smuzhiyun 		goto exit_free_dev_rdev;
1586*4882a593Smuzhiyun 
1587*4882a593Smuzhiyun 	ret = -EBUSY;
1588*4882a593Smuzhiyun 	/* now claim resources */
1589*4882a593Smuzhiyun 	if (!request_region(itdev->cir_addr,
1590*4882a593Smuzhiyun 				dev_desc->io_region_size, ITE_DRIVER_NAME))
1591*4882a593Smuzhiyun 		goto exit_unregister_device;
1592*4882a593Smuzhiyun 
1593*4882a593Smuzhiyun 	if (request_irq(itdev->cir_irq, ite_cir_isr, IRQF_SHARED,
1594*4882a593Smuzhiyun 			ITE_DRIVER_NAME, (void *)itdev))
1595*4882a593Smuzhiyun 		goto exit_release_cir_addr;
1596*4882a593Smuzhiyun 
1597*4882a593Smuzhiyun 	ite_pr(KERN_NOTICE, "driver has been successfully loaded\n");
1598*4882a593Smuzhiyun 
1599*4882a593Smuzhiyun 	return 0;
1600*4882a593Smuzhiyun 
1601*4882a593Smuzhiyun exit_release_cir_addr:
1602*4882a593Smuzhiyun 	release_region(itdev->cir_addr, itdev->params.io_region_size);
1603*4882a593Smuzhiyun exit_unregister_device:
1604*4882a593Smuzhiyun 	rc_unregister_device(rdev);
1605*4882a593Smuzhiyun 	rdev = NULL;
1606*4882a593Smuzhiyun exit_free_dev_rdev:
1607*4882a593Smuzhiyun 	rc_free_device(rdev);
1608*4882a593Smuzhiyun 	kfree(itdev);
1609*4882a593Smuzhiyun 
1610*4882a593Smuzhiyun 	return ret;
1611*4882a593Smuzhiyun }
1612*4882a593Smuzhiyun 
ite_remove(struct pnp_dev * pdev)1613*4882a593Smuzhiyun static void ite_remove(struct pnp_dev *pdev)
1614*4882a593Smuzhiyun {
1615*4882a593Smuzhiyun 	struct ite_dev *dev = pnp_get_drvdata(pdev);
1616*4882a593Smuzhiyun 	unsigned long flags;
1617*4882a593Smuzhiyun 
1618*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
1619*4882a593Smuzhiyun 
1620*4882a593Smuzhiyun 	spin_lock_irqsave(&dev->lock, flags);
1621*4882a593Smuzhiyun 
1622*4882a593Smuzhiyun 	/* disable hardware */
1623*4882a593Smuzhiyun 	dev->params.disable(dev);
1624*4882a593Smuzhiyun 
1625*4882a593Smuzhiyun 	spin_unlock_irqrestore(&dev->lock, flags);
1626*4882a593Smuzhiyun 
1627*4882a593Smuzhiyun 	/* free resources */
1628*4882a593Smuzhiyun 	free_irq(dev->cir_irq, dev);
1629*4882a593Smuzhiyun 	release_region(dev->cir_addr, dev->params.io_region_size);
1630*4882a593Smuzhiyun 
1631*4882a593Smuzhiyun 	rc_unregister_device(dev->rdev);
1632*4882a593Smuzhiyun 
1633*4882a593Smuzhiyun 	kfree(dev);
1634*4882a593Smuzhiyun }
1635*4882a593Smuzhiyun 
ite_suspend(struct pnp_dev * pdev,pm_message_t state)1636*4882a593Smuzhiyun static int ite_suspend(struct pnp_dev *pdev, pm_message_t state)
1637*4882a593Smuzhiyun {
1638*4882a593Smuzhiyun 	struct ite_dev *dev = pnp_get_drvdata(pdev);
1639*4882a593Smuzhiyun 	unsigned long flags;
1640*4882a593Smuzhiyun 
1641*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
1642*4882a593Smuzhiyun 
1643*4882a593Smuzhiyun 	/* wait for any transmission to end */
1644*4882a593Smuzhiyun 	wait_event_interruptible(dev->tx_ended, !dev->transmitting);
1645*4882a593Smuzhiyun 
1646*4882a593Smuzhiyun 	spin_lock_irqsave(&dev->lock, flags);
1647*4882a593Smuzhiyun 
1648*4882a593Smuzhiyun 	/* disable all interrupts */
1649*4882a593Smuzhiyun 	dev->params.disable(dev);
1650*4882a593Smuzhiyun 
1651*4882a593Smuzhiyun 	spin_unlock_irqrestore(&dev->lock, flags);
1652*4882a593Smuzhiyun 
1653*4882a593Smuzhiyun 	return 0;
1654*4882a593Smuzhiyun }
1655*4882a593Smuzhiyun 
ite_resume(struct pnp_dev * pdev)1656*4882a593Smuzhiyun static int ite_resume(struct pnp_dev *pdev)
1657*4882a593Smuzhiyun {
1658*4882a593Smuzhiyun 	struct ite_dev *dev = pnp_get_drvdata(pdev);
1659*4882a593Smuzhiyun 	unsigned long flags;
1660*4882a593Smuzhiyun 
1661*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
1662*4882a593Smuzhiyun 
1663*4882a593Smuzhiyun 	spin_lock_irqsave(&dev->lock, flags);
1664*4882a593Smuzhiyun 
1665*4882a593Smuzhiyun 	/* reinitialize hardware config registers */
1666*4882a593Smuzhiyun 	dev->params.init_hardware(dev);
1667*4882a593Smuzhiyun 	/* enable the receiver */
1668*4882a593Smuzhiyun 	dev->params.enable_rx(dev);
1669*4882a593Smuzhiyun 
1670*4882a593Smuzhiyun 	spin_unlock_irqrestore(&dev->lock, flags);
1671*4882a593Smuzhiyun 
1672*4882a593Smuzhiyun 	return 0;
1673*4882a593Smuzhiyun }
1674*4882a593Smuzhiyun 
ite_shutdown(struct pnp_dev * pdev)1675*4882a593Smuzhiyun static void ite_shutdown(struct pnp_dev *pdev)
1676*4882a593Smuzhiyun {
1677*4882a593Smuzhiyun 	struct ite_dev *dev = pnp_get_drvdata(pdev);
1678*4882a593Smuzhiyun 	unsigned long flags;
1679*4882a593Smuzhiyun 
1680*4882a593Smuzhiyun 	ite_dbg("%s called", __func__);
1681*4882a593Smuzhiyun 
1682*4882a593Smuzhiyun 	spin_lock_irqsave(&dev->lock, flags);
1683*4882a593Smuzhiyun 
1684*4882a593Smuzhiyun 	/* disable all interrupts */
1685*4882a593Smuzhiyun 	dev->params.disable(dev);
1686*4882a593Smuzhiyun 
1687*4882a593Smuzhiyun 	spin_unlock_irqrestore(&dev->lock, flags);
1688*4882a593Smuzhiyun }
1689*4882a593Smuzhiyun 
1690*4882a593Smuzhiyun static struct pnp_driver ite_driver = {
1691*4882a593Smuzhiyun 	.name		= ITE_DRIVER_NAME,
1692*4882a593Smuzhiyun 	.id_table	= ite_ids,
1693*4882a593Smuzhiyun 	.probe		= ite_probe,
1694*4882a593Smuzhiyun 	.remove		= ite_remove,
1695*4882a593Smuzhiyun 	.suspend	= ite_suspend,
1696*4882a593Smuzhiyun 	.resume		= ite_resume,
1697*4882a593Smuzhiyun 	.shutdown	= ite_shutdown,
1698*4882a593Smuzhiyun };
1699*4882a593Smuzhiyun 
1700*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pnp, ite_ids);
1701*4882a593Smuzhiyun MODULE_DESCRIPTION("ITE Tech Inc. IT8712F/ITE8512F CIR driver");
1702*4882a593Smuzhiyun 
1703*4882a593Smuzhiyun MODULE_AUTHOR("Juan J. Garcia de Soria <skandalfo@gmail.com>");
1704*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1705*4882a593Smuzhiyun 
1706*4882a593Smuzhiyun module_pnp_driver(ite_driver);
1707