1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun // ir-imon-decoder.c - handle iMon protocol
3*4882a593Smuzhiyun //
4*4882a593Smuzhiyun // Copyright (C) 2018 by Sean Young <sean@mess.org>
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include "rc-core-priv.h"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define IMON_UNIT 416 /* us */
12*4882a593Smuzhiyun #define IMON_BITS 30
13*4882a593Smuzhiyun #define IMON_CHKBITS (BIT(30) | BIT(25) | BIT(24) | BIT(22) | \
14*4882a593Smuzhiyun BIT(21) | BIT(20) | BIT(19) | BIT(18) | \
15*4882a593Smuzhiyun BIT(17) | BIT(16) | BIT(14) | BIT(13) | \
16*4882a593Smuzhiyun BIT(12) | BIT(11) | BIT(10) | BIT(9))
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /*
19*4882a593Smuzhiyun * This protocol has 30 bits. The format is one IMON_UNIT header pulse,
20*4882a593Smuzhiyun * followed by 30 bits. Each bit is one IMON_UNIT check field, and then
21*4882a593Smuzhiyun * one IMON_UNIT field with the actual bit (1=space, 0=pulse).
22*4882a593Smuzhiyun * The check field is always space for some bits, for others it is pulse if
23*4882a593Smuzhiyun * both the preceding and current bit are zero, else space. IMON_CHKBITS
24*4882a593Smuzhiyun * defines which bits are of type check.
25*4882a593Smuzhiyun *
26*4882a593Smuzhiyun * There is no way to distinguish an incomplete message from one where
27*4882a593Smuzhiyun * the lower bits are all set, iow. the last pulse is for the lowest
28*4882a593Smuzhiyun * bit which is 0.
29*4882a593Smuzhiyun */
30*4882a593Smuzhiyun enum imon_state {
31*4882a593Smuzhiyun STATE_INACTIVE,
32*4882a593Smuzhiyun STATE_BIT_CHK,
33*4882a593Smuzhiyun STATE_BIT_START,
34*4882a593Smuzhiyun STATE_FINISHED,
35*4882a593Smuzhiyun STATE_ERROR,
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
ir_imon_decode_scancode(struct rc_dev * dev)38*4882a593Smuzhiyun static void ir_imon_decode_scancode(struct rc_dev *dev)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun struct imon_dec *imon = &dev->raw->imon;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* Keyboard/Mouse toggle */
43*4882a593Smuzhiyun if (imon->bits == 0x299115b7)
44*4882a593Smuzhiyun imon->stick_keyboard = !imon->stick_keyboard;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun if ((imon->bits & 0xfc0000ff) == 0x680000b7) {
47*4882a593Smuzhiyun int rel_x, rel_y;
48*4882a593Smuzhiyun u8 buf;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun buf = imon->bits >> 16;
51*4882a593Smuzhiyun rel_x = (buf & 0x08) | (buf & 0x10) >> 2 |
52*4882a593Smuzhiyun (buf & 0x20) >> 4 | (buf & 0x40) >> 6;
53*4882a593Smuzhiyun if (imon->bits & 0x02000000)
54*4882a593Smuzhiyun rel_x |= ~0x0f;
55*4882a593Smuzhiyun buf = imon->bits >> 8;
56*4882a593Smuzhiyun rel_y = (buf & 0x08) | (buf & 0x10) >> 2 |
57*4882a593Smuzhiyun (buf & 0x20) >> 4 | (buf & 0x40) >> 6;
58*4882a593Smuzhiyun if (imon->bits & 0x01000000)
59*4882a593Smuzhiyun rel_y |= ~0x0f;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun if (rel_x && rel_y && imon->stick_keyboard) {
62*4882a593Smuzhiyun if (abs(rel_y) > abs(rel_x))
63*4882a593Smuzhiyun imon->bits = rel_y > 0 ?
64*4882a593Smuzhiyun 0x289515b7 : /* KEY_DOWN */
65*4882a593Smuzhiyun 0x2aa515b7; /* KEY_UP */
66*4882a593Smuzhiyun else
67*4882a593Smuzhiyun imon->bits = rel_x > 0 ?
68*4882a593Smuzhiyun 0x2ba515b7 : /* KEY_RIGHT */
69*4882a593Smuzhiyun 0x29a515b7; /* KEY_LEFT */
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun if (!imon->stick_keyboard) {
73*4882a593Smuzhiyun input_report_rel(dev->input_dev, REL_X, rel_x);
74*4882a593Smuzhiyun input_report_rel(dev->input_dev, REL_Y, rel_y);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun input_report_key(dev->input_dev, BTN_LEFT,
77*4882a593Smuzhiyun (imon->bits & 0x00010000) != 0);
78*4882a593Smuzhiyun input_report_key(dev->input_dev, BTN_RIGHT,
79*4882a593Smuzhiyun (imon->bits & 0x00040000) != 0);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun rc_keydown(dev, RC_PROTO_IMON, imon->bits, 0);
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /**
87*4882a593Smuzhiyun * ir_imon_decode() - Decode one iMON pulse or space
88*4882a593Smuzhiyun * @dev: the struct rc_dev descriptor of the device
89*4882a593Smuzhiyun * @ev: the struct ir_raw_event descriptor of the pulse/space
90*4882a593Smuzhiyun *
91*4882a593Smuzhiyun * This function returns -EINVAL if the pulse violates the state machine
92*4882a593Smuzhiyun */
ir_imon_decode(struct rc_dev * dev,struct ir_raw_event ev)93*4882a593Smuzhiyun static int ir_imon_decode(struct rc_dev *dev, struct ir_raw_event ev)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun struct imon_dec *data = &dev->raw->imon;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (!is_timing_event(ev)) {
98*4882a593Smuzhiyun if (ev.reset)
99*4882a593Smuzhiyun data->state = STATE_INACTIVE;
100*4882a593Smuzhiyun return 0;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun dev_dbg(&dev->dev,
104*4882a593Smuzhiyun "iMON decode started at state %d bitno %d (%uus %s)\n",
105*4882a593Smuzhiyun data->state, data->count, ev.duration, TO_STR(ev.pulse));
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /*
108*4882a593Smuzhiyun * Since iMON protocol is a series of bits, if at any point
109*4882a593Smuzhiyun * we encounter an error, make sure that any remaining bits
110*4882a593Smuzhiyun * aren't parsed as a scancode made up of less bits.
111*4882a593Smuzhiyun *
112*4882a593Smuzhiyun * Note that if the stick is held, then the remote repeats
113*4882a593Smuzhiyun * the scancode with about 12ms between them. So, make sure
114*4882a593Smuzhiyun * we have at least 10ms of space after an error. That way,
115*4882a593Smuzhiyun * we're at a new scancode.
116*4882a593Smuzhiyun */
117*4882a593Smuzhiyun if (data->state == STATE_ERROR) {
118*4882a593Smuzhiyun if (!ev.pulse && ev.duration > MS_TO_US(10))
119*4882a593Smuzhiyun data->state = STATE_INACTIVE;
120*4882a593Smuzhiyun return 0;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun for (;;) {
124*4882a593Smuzhiyun if (!geq_margin(ev.duration, IMON_UNIT, IMON_UNIT / 2))
125*4882a593Smuzhiyun return 0;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun decrease_duration(&ev, IMON_UNIT);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun switch (data->state) {
130*4882a593Smuzhiyun case STATE_INACTIVE:
131*4882a593Smuzhiyun if (ev.pulse) {
132*4882a593Smuzhiyun data->state = STATE_BIT_CHK;
133*4882a593Smuzhiyun data->bits = 0;
134*4882a593Smuzhiyun data->count = IMON_BITS;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun break;
137*4882a593Smuzhiyun case STATE_BIT_CHK:
138*4882a593Smuzhiyun if (IMON_CHKBITS & BIT(data->count))
139*4882a593Smuzhiyun data->last_chk = ev.pulse;
140*4882a593Smuzhiyun else if (ev.pulse)
141*4882a593Smuzhiyun goto err_out;
142*4882a593Smuzhiyun data->state = STATE_BIT_START;
143*4882a593Smuzhiyun break;
144*4882a593Smuzhiyun case STATE_BIT_START:
145*4882a593Smuzhiyun data->bits <<= 1;
146*4882a593Smuzhiyun if (!ev.pulse)
147*4882a593Smuzhiyun data->bits |= 1;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun if (IMON_CHKBITS & BIT(data->count)) {
150*4882a593Smuzhiyun if (data->last_chk != !(data->bits & 3))
151*4882a593Smuzhiyun goto err_out;
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun if (!data->count--)
155*4882a593Smuzhiyun data->state = STATE_FINISHED;
156*4882a593Smuzhiyun else
157*4882a593Smuzhiyun data->state = STATE_BIT_CHK;
158*4882a593Smuzhiyun break;
159*4882a593Smuzhiyun case STATE_FINISHED:
160*4882a593Smuzhiyun if (ev.pulse)
161*4882a593Smuzhiyun goto err_out;
162*4882a593Smuzhiyun ir_imon_decode_scancode(dev);
163*4882a593Smuzhiyun data->state = STATE_INACTIVE;
164*4882a593Smuzhiyun break;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun err_out:
169*4882a593Smuzhiyun dev_dbg(&dev->dev,
170*4882a593Smuzhiyun "iMON decode failed at state %d bitno %d (%uus %s)\n",
171*4882a593Smuzhiyun data->state, data->count, ev.duration, TO_STR(ev.pulse));
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun data->state = STATE_ERROR;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun return -EINVAL;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun /**
179*4882a593Smuzhiyun * ir_imon_encode() - Encode a scancode as a stream of raw events
180*4882a593Smuzhiyun *
181*4882a593Smuzhiyun * @protocol: protocol to encode
182*4882a593Smuzhiyun * @scancode: scancode to encode
183*4882a593Smuzhiyun * @events: array of raw ir events to write into
184*4882a593Smuzhiyun * @max: maximum size of @events
185*4882a593Smuzhiyun *
186*4882a593Smuzhiyun * Returns: The number of events written.
187*4882a593Smuzhiyun * -ENOBUFS if there isn't enough space in the array to fit the
188*4882a593Smuzhiyun * encoding. In this case all @max events will have been written.
189*4882a593Smuzhiyun */
ir_imon_encode(enum rc_proto protocol,u32 scancode,struct ir_raw_event * events,unsigned int max)190*4882a593Smuzhiyun static int ir_imon_encode(enum rc_proto protocol, u32 scancode,
191*4882a593Smuzhiyun struct ir_raw_event *events, unsigned int max)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun struct ir_raw_event *e = events;
194*4882a593Smuzhiyun int i, pulse;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun if (!max--)
197*4882a593Smuzhiyun return -ENOBUFS;
198*4882a593Smuzhiyun init_ir_raw_event_duration(e, 1, IMON_UNIT);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun for (i = IMON_BITS; i >= 0; i--) {
201*4882a593Smuzhiyun if (BIT(i) & IMON_CHKBITS)
202*4882a593Smuzhiyun pulse = !(scancode & (BIT(i) | BIT(i + 1)));
203*4882a593Smuzhiyun else
204*4882a593Smuzhiyun pulse = 0;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun if (pulse == e->pulse) {
207*4882a593Smuzhiyun e->duration += IMON_UNIT;
208*4882a593Smuzhiyun } else {
209*4882a593Smuzhiyun if (!max--)
210*4882a593Smuzhiyun return -ENOBUFS;
211*4882a593Smuzhiyun init_ir_raw_event_duration(++e, pulse, IMON_UNIT);
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun pulse = !(scancode & BIT(i));
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun if (pulse == e->pulse) {
217*4882a593Smuzhiyun e->duration += IMON_UNIT;
218*4882a593Smuzhiyun } else {
219*4882a593Smuzhiyun if (!max--)
220*4882a593Smuzhiyun return -ENOBUFS;
221*4882a593Smuzhiyun init_ir_raw_event_duration(++e, pulse, IMON_UNIT);
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun if (e->pulse)
226*4882a593Smuzhiyun e++;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun return e - events;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
ir_imon_register(struct rc_dev * dev)231*4882a593Smuzhiyun static int ir_imon_register(struct rc_dev *dev)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun struct imon_dec *imon = &dev->raw->imon;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun imon->stick_keyboard = false;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun return 0;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun static struct ir_raw_handler imon_handler = {
241*4882a593Smuzhiyun .protocols = RC_PROTO_BIT_IMON,
242*4882a593Smuzhiyun .decode = ir_imon_decode,
243*4882a593Smuzhiyun .encode = ir_imon_encode,
244*4882a593Smuzhiyun .carrier = 38000,
245*4882a593Smuzhiyun .raw_register = ir_imon_register,
246*4882a593Smuzhiyun .min_timeout = IMON_UNIT * IMON_BITS * 2,
247*4882a593Smuzhiyun };
248*4882a593Smuzhiyun
ir_imon_decode_init(void)249*4882a593Smuzhiyun static int __init ir_imon_decode_init(void)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun ir_raw_handler_register(&imon_handler);
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun pr_info("IR iMON protocol handler initialized\n");
254*4882a593Smuzhiyun return 0;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
ir_imon_decode_exit(void)257*4882a593Smuzhiyun static void __exit ir_imon_decode_exit(void)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun ir_raw_handler_unregister(&imon_handler);
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun module_init(ir_imon_decode_init);
263*4882a593Smuzhiyun module_exit(ir_imon_decode_exit);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun MODULE_LICENSE("GPL");
266*4882a593Smuzhiyun MODULE_AUTHOR("Sean Young <sean@mess.org>");
267*4882a593Smuzhiyun MODULE_DESCRIPTION("iMON IR protocol decoder");
268