1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * driver for ENE KB3926 B/C/D/E/F CIR (pnp id: ENE0XXX)
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Special thanks to:
8*4882a593Smuzhiyun * Sami R. <maesesami@gmail.com> for lot of help in debugging and therefore
9*4882a593Smuzhiyun * bringing to life support for transmission & learning mode.
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Charlie Andrews <charliethepilot@googlemail.com> for lots of help in
12*4882a593Smuzhiyun * bringing up the support of new firmware buffer that is popular
13*4882a593Smuzhiyun * on latest notebooks
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * ENE for partial device documentation
16*4882a593Smuzhiyun */
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <linux/kernel.h>
21*4882a593Smuzhiyun #include <linux/module.h>
22*4882a593Smuzhiyun #include <linux/pnp.h>
23*4882a593Smuzhiyun #include <linux/io.h>
24*4882a593Smuzhiyun #include <linux/interrupt.h>
25*4882a593Smuzhiyun #include <linux/sched.h>
26*4882a593Smuzhiyun #include <linux/slab.h>
27*4882a593Smuzhiyun #include <media/rc-core.h>
28*4882a593Smuzhiyun #include "ene_ir.h"
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun static int sample_period;
31*4882a593Smuzhiyun static bool learning_mode_force;
32*4882a593Smuzhiyun static int debug;
33*4882a593Smuzhiyun static bool txsim;
34*4882a593Smuzhiyun
ene_set_reg_addr(struct ene_device * dev,u16 reg)35*4882a593Smuzhiyun static void ene_set_reg_addr(struct ene_device *dev, u16 reg)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun outb(reg >> 8, dev->hw_io + ENE_ADDR_HI);
38*4882a593Smuzhiyun outb(reg & 0xFF, dev->hw_io + ENE_ADDR_LO);
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* read a hardware register */
ene_read_reg(struct ene_device * dev,u16 reg)42*4882a593Smuzhiyun static u8 ene_read_reg(struct ene_device *dev, u16 reg)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun u8 retval;
45*4882a593Smuzhiyun ene_set_reg_addr(dev, reg);
46*4882a593Smuzhiyun retval = inb(dev->hw_io + ENE_IO);
47*4882a593Smuzhiyun dbg_regs("reg %04x == %02x", reg, retval);
48*4882a593Smuzhiyun return retval;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* write a hardware register */
ene_write_reg(struct ene_device * dev,u16 reg,u8 value)52*4882a593Smuzhiyun static void ene_write_reg(struct ene_device *dev, u16 reg, u8 value)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun dbg_regs("reg %04x <- %02x", reg, value);
55*4882a593Smuzhiyun ene_set_reg_addr(dev, reg);
56*4882a593Smuzhiyun outb(value, dev->hw_io + ENE_IO);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* Set bits in hardware register */
ene_set_reg_mask(struct ene_device * dev,u16 reg,u8 mask)60*4882a593Smuzhiyun static void ene_set_reg_mask(struct ene_device *dev, u16 reg, u8 mask)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun dbg_regs("reg %04x |= %02x", reg, mask);
63*4882a593Smuzhiyun ene_set_reg_addr(dev, reg);
64*4882a593Smuzhiyun outb(inb(dev->hw_io + ENE_IO) | mask, dev->hw_io + ENE_IO);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* Clear bits in hardware register */
ene_clear_reg_mask(struct ene_device * dev,u16 reg,u8 mask)68*4882a593Smuzhiyun static void ene_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun dbg_regs("reg %04x &= ~%02x ", reg, mask);
71*4882a593Smuzhiyun ene_set_reg_addr(dev, reg);
72*4882a593Smuzhiyun outb(inb(dev->hw_io + ENE_IO) & ~mask, dev->hw_io + ENE_IO);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* A helper to set/clear a bit in register according to boolean variable */
ene_set_clear_reg_mask(struct ene_device * dev,u16 reg,u8 mask,bool set)76*4882a593Smuzhiyun static void ene_set_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask,
77*4882a593Smuzhiyun bool set)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun if (set)
80*4882a593Smuzhiyun ene_set_reg_mask(dev, reg, mask);
81*4882a593Smuzhiyun else
82*4882a593Smuzhiyun ene_clear_reg_mask(dev, reg, mask);
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* detect hardware features */
ene_hw_detect(struct ene_device * dev)86*4882a593Smuzhiyun static int ene_hw_detect(struct ene_device *dev)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun u8 chip_major, chip_minor;
89*4882a593Smuzhiyun u8 hw_revision, old_ver;
90*4882a593Smuzhiyun u8 fw_reg2, fw_reg1;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun ene_clear_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD);
93*4882a593Smuzhiyun chip_major = ene_read_reg(dev, ENE_ECVER_MAJOR);
94*4882a593Smuzhiyun chip_minor = ene_read_reg(dev, ENE_ECVER_MINOR);
95*4882a593Smuzhiyun ene_set_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun hw_revision = ene_read_reg(dev, ENE_ECHV);
98*4882a593Smuzhiyun old_ver = ene_read_reg(dev, ENE_HW_VER_OLD);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun dev->pll_freq = (ene_read_reg(dev, ENE_PLLFRH) << 4) +
101*4882a593Smuzhiyun (ene_read_reg(dev, ENE_PLLFRL) >> 4);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun if (sample_period != ENE_DEFAULT_SAMPLE_PERIOD)
104*4882a593Smuzhiyun dev->rx_period_adjust =
105*4882a593Smuzhiyun dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 2 : 4;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun if (hw_revision == 0xFF) {
108*4882a593Smuzhiyun pr_warn("device seems to be disabled\n");
109*4882a593Smuzhiyun pr_warn("send a mail to lirc-list@lists.sourceforge.net\n");
110*4882a593Smuzhiyun pr_warn("please attach output of acpidump and dmidecode\n");
111*4882a593Smuzhiyun return -ENODEV;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun pr_notice("chip is 0x%02x%02x - kbver = 0x%02x, rev = 0x%02x\n",
115*4882a593Smuzhiyun chip_major, chip_minor, old_ver, hw_revision);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun pr_notice("PLL freq = %d\n", dev->pll_freq);
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun if (chip_major == 0x33) {
120*4882a593Smuzhiyun pr_warn("chips 0x33xx aren't supported\n");
121*4882a593Smuzhiyun return -ENODEV;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun if (chip_major == 0x39 && chip_minor == 0x26 && hw_revision == 0xC0) {
125*4882a593Smuzhiyun dev->hw_revision = ENE_HW_C;
126*4882a593Smuzhiyun pr_notice("KB3926C detected\n");
127*4882a593Smuzhiyun } else if (old_ver == 0x24 && hw_revision == 0xC0) {
128*4882a593Smuzhiyun dev->hw_revision = ENE_HW_B;
129*4882a593Smuzhiyun pr_notice("KB3926B detected\n");
130*4882a593Smuzhiyun } else {
131*4882a593Smuzhiyun dev->hw_revision = ENE_HW_D;
132*4882a593Smuzhiyun pr_notice("KB3926D or higher detected\n");
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun /* detect features hardware supports */
136*4882a593Smuzhiyun if (dev->hw_revision < ENE_HW_C)
137*4882a593Smuzhiyun return 0;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun fw_reg1 = ene_read_reg(dev, ENE_FW1);
140*4882a593Smuzhiyun fw_reg2 = ene_read_reg(dev, ENE_FW2);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun pr_notice("Firmware regs: %02x %02x\n", fw_reg1, fw_reg2);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun dev->hw_use_gpio_0a = !!(fw_reg2 & ENE_FW2_GP0A);
145*4882a593Smuzhiyun dev->hw_learning_and_tx_capable = !!(fw_reg2 & ENE_FW2_LEARNING);
146*4882a593Smuzhiyun dev->hw_extra_buffer = !!(fw_reg1 & ENE_FW1_HAS_EXTRA_BUF);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun if (dev->hw_learning_and_tx_capable)
149*4882a593Smuzhiyun dev->hw_fan_input = !!(fw_reg2 & ENE_FW2_FAN_INPUT);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun pr_notice("Hardware features:\n");
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun if (dev->hw_learning_and_tx_capable) {
154*4882a593Smuzhiyun pr_notice("* Supports transmitting & learning mode\n");
155*4882a593Smuzhiyun pr_notice(" This feature is rare and therefore,\n");
156*4882a593Smuzhiyun pr_notice(" you are welcome to test it,\n");
157*4882a593Smuzhiyun pr_notice(" and/or contact the author via:\n");
158*4882a593Smuzhiyun pr_notice(" lirc-list@lists.sourceforge.net\n");
159*4882a593Smuzhiyun pr_notice(" or maximlevitsky@gmail.com\n");
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun pr_notice("* Uses GPIO %s for IR raw input\n",
162*4882a593Smuzhiyun dev->hw_use_gpio_0a ? "40" : "0A");
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun if (dev->hw_fan_input)
165*4882a593Smuzhiyun pr_notice("* Uses unused fan feedback input as source of demodulated IR data\n");
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun if (!dev->hw_fan_input)
169*4882a593Smuzhiyun pr_notice("* Uses GPIO %s for IR demodulated input\n",
170*4882a593Smuzhiyun dev->hw_use_gpio_0a ? "0A" : "40");
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun if (dev->hw_extra_buffer)
173*4882a593Smuzhiyun pr_notice("* Uses new style input buffer\n");
174*4882a593Smuzhiyun return 0;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun /* Read properties of hw sample buffer */
ene_rx_setup_hw_buffer(struct ene_device * dev)178*4882a593Smuzhiyun static void ene_rx_setup_hw_buffer(struct ene_device *dev)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun u16 tmp;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun ene_rx_read_hw_pointer(dev);
183*4882a593Smuzhiyun dev->r_pointer = dev->w_pointer;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun if (!dev->hw_extra_buffer) {
186*4882a593Smuzhiyun dev->buffer_len = ENE_FW_PACKET_SIZE * 2;
187*4882a593Smuzhiyun return;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER);
191*4882a593Smuzhiyun tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER+1) << 8;
192*4882a593Smuzhiyun dev->extra_buf1_address = tmp;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun dev->extra_buf1_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 2);
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 3);
197*4882a593Smuzhiyun tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 4) << 8;
198*4882a593Smuzhiyun dev->extra_buf2_address = tmp;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun dev->extra_buf2_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 5);
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun dev->buffer_len = dev->extra_buf1_len + dev->extra_buf2_len + 8;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun pr_notice("Hardware uses 2 extended buffers:\n");
205*4882a593Smuzhiyun pr_notice(" 0x%04x - len : %d\n",
206*4882a593Smuzhiyun dev->extra_buf1_address, dev->extra_buf1_len);
207*4882a593Smuzhiyun pr_notice(" 0x%04x - len : %d\n",
208*4882a593Smuzhiyun dev->extra_buf2_address, dev->extra_buf2_len);
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun pr_notice("Total buffer len = %d\n", dev->buffer_len);
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun if (dev->buffer_len > 64 || dev->buffer_len < 16)
213*4882a593Smuzhiyun goto error;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun if (dev->extra_buf1_address > 0xFBFC ||
216*4882a593Smuzhiyun dev->extra_buf1_address < 0xEC00)
217*4882a593Smuzhiyun goto error;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun if (dev->extra_buf2_address > 0xFBFC ||
220*4882a593Smuzhiyun dev->extra_buf2_address < 0xEC00)
221*4882a593Smuzhiyun goto error;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun if (dev->r_pointer > dev->buffer_len)
224*4882a593Smuzhiyun goto error;
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
227*4882a593Smuzhiyun return;
228*4882a593Smuzhiyun error:
229*4882a593Smuzhiyun pr_warn("Error validating extra buffers, device probably won't work\n");
230*4882a593Smuzhiyun dev->hw_extra_buffer = false;
231*4882a593Smuzhiyun ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun /* Restore the pointers to extra buffers - to make module reload work*/
ene_rx_restore_hw_buffer(struct ene_device * dev)236*4882a593Smuzhiyun static void ene_rx_restore_hw_buffer(struct ene_device *dev)
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun if (!dev->hw_extra_buffer)
239*4882a593Smuzhiyun return;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 0,
242*4882a593Smuzhiyun dev->extra_buf1_address & 0xFF);
243*4882a593Smuzhiyun ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 1,
244*4882a593Smuzhiyun dev->extra_buf1_address >> 8);
245*4882a593Smuzhiyun ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 2, dev->extra_buf1_len);
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 3,
248*4882a593Smuzhiyun dev->extra_buf2_address & 0xFF);
249*4882a593Smuzhiyun ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 4,
250*4882a593Smuzhiyun dev->extra_buf2_address >> 8);
251*4882a593Smuzhiyun ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 5,
252*4882a593Smuzhiyun dev->extra_buf2_len);
253*4882a593Smuzhiyun ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun /* Read hardware write pointer */
ene_rx_read_hw_pointer(struct ene_device * dev)257*4882a593Smuzhiyun static void ene_rx_read_hw_pointer(struct ene_device *dev)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun if (dev->hw_extra_buffer)
260*4882a593Smuzhiyun dev->w_pointer = ene_read_reg(dev, ENE_FW_RX_POINTER);
261*4882a593Smuzhiyun else
262*4882a593Smuzhiyun dev->w_pointer = ene_read_reg(dev, ENE_FW2)
263*4882a593Smuzhiyun & ENE_FW2_BUF_WPTR ? 0 : ENE_FW_PACKET_SIZE;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun dbg_verbose("RB: HW write pointer: %02x, driver read pointer: %02x",
266*4882a593Smuzhiyun dev->w_pointer, dev->r_pointer);
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun /* Gets address of next sample from HW ring buffer */
ene_rx_get_sample_reg(struct ene_device * dev)270*4882a593Smuzhiyun static int ene_rx_get_sample_reg(struct ene_device *dev)
271*4882a593Smuzhiyun {
272*4882a593Smuzhiyun int r_pointer;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun if (dev->r_pointer == dev->w_pointer) {
275*4882a593Smuzhiyun dbg_verbose("RB: hit end, try update w_pointer");
276*4882a593Smuzhiyun ene_rx_read_hw_pointer(dev);
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun if (dev->r_pointer == dev->w_pointer) {
280*4882a593Smuzhiyun dbg_verbose("RB: end of data at %d", dev->r_pointer);
281*4882a593Smuzhiyun return 0;
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun dbg_verbose("RB: reading at offset %d", dev->r_pointer);
285*4882a593Smuzhiyun r_pointer = dev->r_pointer;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun dev->r_pointer++;
288*4882a593Smuzhiyun if (dev->r_pointer == dev->buffer_len)
289*4882a593Smuzhiyun dev->r_pointer = 0;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun dbg_verbose("RB: next read will be from offset %d", dev->r_pointer);
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun if (r_pointer < 8) {
294*4882a593Smuzhiyun dbg_verbose("RB: read at main buffer at %d", r_pointer);
295*4882a593Smuzhiyun return ENE_FW_SAMPLE_BUFFER + r_pointer;
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun r_pointer -= 8;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun if (r_pointer < dev->extra_buf1_len) {
301*4882a593Smuzhiyun dbg_verbose("RB: read at 1st extra buffer at %d", r_pointer);
302*4882a593Smuzhiyun return dev->extra_buf1_address + r_pointer;
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun r_pointer -= dev->extra_buf1_len;
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun if (r_pointer < dev->extra_buf2_len) {
308*4882a593Smuzhiyun dbg_verbose("RB: read at 2nd extra buffer at %d", r_pointer);
309*4882a593Smuzhiyun return dev->extra_buf2_address + r_pointer;
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun dbg("attempt to read beyond ring buffer end");
313*4882a593Smuzhiyun return 0;
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun /* Sense current received carrier */
ene_rx_sense_carrier(struct ene_device * dev)317*4882a593Smuzhiyun static void ene_rx_sense_carrier(struct ene_device *dev)
318*4882a593Smuzhiyun {
319*4882a593Smuzhiyun int carrier, duty_cycle;
320*4882a593Smuzhiyun int period = ene_read_reg(dev, ENE_CIRCAR_PRD);
321*4882a593Smuzhiyun int hperiod = ene_read_reg(dev, ENE_CIRCAR_HPRD);
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun if (!(period & ENE_CIRCAR_PRD_VALID))
324*4882a593Smuzhiyun return;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun period &= ~ENE_CIRCAR_PRD_VALID;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun if (!period)
329*4882a593Smuzhiyun return;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun dbg("RX: hardware carrier period = %02x", period);
332*4882a593Smuzhiyun dbg("RX: hardware carrier pulse period = %02x", hperiod);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun carrier = 2000000 / period;
335*4882a593Smuzhiyun duty_cycle = (hperiod * 100) / period;
336*4882a593Smuzhiyun dbg("RX: sensed carrier = %d Hz, duty cycle %d%%",
337*4882a593Smuzhiyun carrier, duty_cycle);
338*4882a593Smuzhiyun if (dev->carrier_detect_enabled) {
339*4882a593Smuzhiyun struct ir_raw_event ev = {
340*4882a593Smuzhiyun .carrier_report = true,
341*4882a593Smuzhiyun .carrier = carrier,
342*4882a593Smuzhiyun .duty_cycle = duty_cycle
343*4882a593Smuzhiyun };
344*4882a593Smuzhiyun ir_raw_event_store(dev->rdev, &ev);
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun /* this enables/disables the CIR RX engine */
ene_rx_enable_cir_engine(struct ene_device * dev,bool enable)349*4882a593Smuzhiyun static void ene_rx_enable_cir_engine(struct ene_device *dev, bool enable)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun ene_set_clear_reg_mask(dev, ENE_CIRCFG,
352*4882a593Smuzhiyun ENE_CIRCFG_RX_EN | ENE_CIRCFG_RX_IRQ, enable);
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun /* this selects input for CIR engine. Ether GPIO 0A or GPIO40*/
ene_rx_select_input(struct ene_device * dev,bool gpio_0a)356*4882a593Smuzhiyun static void ene_rx_select_input(struct ene_device *dev, bool gpio_0a)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_GPIO0A, gpio_0a);
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun /*
362*4882a593Smuzhiyun * this enables alternative input via fan tachometer sensor and bypasses
363*4882a593Smuzhiyun * the hw CIR engine
364*4882a593Smuzhiyun */
ene_rx_enable_fan_input(struct ene_device * dev,bool enable)365*4882a593Smuzhiyun static void ene_rx_enable_fan_input(struct ene_device *dev, bool enable)
366*4882a593Smuzhiyun {
367*4882a593Smuzhiyun if (!dev->hw_fan_input)
368*4882a593Smuzhiyun return;
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun if (!enable)
371*4882a593Smuzhiyun ene_write_reg(dev, ENE_FAN_AS_IN1, 0);
372*4882a593Smuzhiyun else {
373*4882a593Smuzhiyun ene_write_reg(dev, ENE_FAN_AS_IN1, ENE_FAN_AS_IN1_EN);
374*4882a593Smuzhiyun ene_write_reg(dev, ENE_FAN_AS_IN2, ENE_FAN_AS_IN2_EN);
375*4882a593Smuzhiyun }
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun /* setup the receiver for RX*/
ene_rx_setup(struct ene_device * dev)379*4882a593Smuzhiyun static void ene_rx_setup(struct ene_device *dev)
380*4882a593Smuzhiyun {
381*4882a593Smuzhiyun bool learning_mode = dev->learning_mode_enabled ||
382*4882a593Smuzhiyun dev->carrier_detect_enabled;
383*4882a593Smuzhiyun int sample_period_adjust = 0;
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun dbg("RX: setup receiver, learning mode = %d", learning_mode);
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun /* This selects RLC input and clears CFG2 settings */
389*4882a593Smuzhiyun ene_write_reg(dev, ENE_CIRCFG2, 0x00);
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun /* set sample period*/
392*4882a593Smuzhiyun if (sample_period == ENE_DEFAULT_SAMPLE_PERIOD)
393*4882a593Smuzhiyun sample_period_adjust =
394*4882a593Smuzhiyun dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 1 : 2;
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun ene_write_reg(dev, ENE_CIRRLC_CFG,
397*4882a593Smuzhiyun (sample_period + sample_period_adjust) |
398*4882a593Smuzhiyun ENE_CIRRLC_CFG_OVERFLOW);
399*4882a593Smuzhiyun /* revB doesn't support inputs */
400*4882a593Smuzhiyun if (dev->hw_revision < ENE_HW_C)
401*4882a593Smuzhiyun goto select_timeout;
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun if (learning_mode) {
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun WARN_ON(!dev->hw_learning_and_tx_capable);
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun /* Enable the opposite of the normal input
408*4882a593Smuzhiyun That means that if GPIO40 is normally used, use GPIO0A
409*4882a593Smuzhiyun and vice versa.
410*4882a593Smuzhiyun This input will carry non demodulated
411*4882a593Smuzhiyun signal, and we will tell the hw to demodulate it itself */
412*4882a593Smuzhiyun ene_rx_select_input(dev, !dev->hw_use_gpio_0a);
413*4882a593Smuzhiyun dev->rx_fan_input_inuse = false;
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun /* Enable carrier demodulation */
416*4882a593Smuzhiyun ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD);
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun /* Enable carrier detection */
419*4882a593Smuzhiyun ene_write_reg(dev, ENE_CIRCAR_PULS, 0x63);
420*4882a593Smuzhiyun ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT,
421*4882a593Smuzhiyun dev->carrier_detect_enabled || debug);
422*4882a593Smuzhiyun } else {
423*4882a593Smuzhiyun if (dev->hw_fan_input)
424*4882a593Smuzhiyun dev->rx_fan_input_inuse = true;
425*4882a593Smuzhiyun else
426*4882a593Smuzhiyun ene_rx_select_input(dev, dev->hw_use_gpio_0a);
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun /* Disable carrier detection & demodulation */
429*4882a593Smuzhiyun ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD);
430*4882a593Smuzhiyun ene_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT);
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun select_timeout:
434*4882a593Smuzhiyun if (dev->rx_fan_input_inuse) {
435*4882a593Smuzhiyun dev->rdev->rx_resolution = ENE_FW_SAMPLE_PERIOD_FAN;
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun /* Fan input doesn't support timeouts, it just ends the
438*4882a593Smuzhiyun input with a maximum sample */
439*4882a593Smuzhiyun dev->rdev->min_timeout = dev->rdev->max_timeout =
440*4882a593Smuzhiyun ENE_FW_SMPL_BUF_FAN_MSK *
441*4882a593Smuzhiyun ENE_FW_SAMPLE_PERIOD_FAN;
442*4882a593Smuzhiyun } else {
443*4882a593Smuzhiyun dev->rdev->rx_resolution = sample_period;
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun /* Theoreticly timeout is unlimited, but we cap it
446*4882a593Smuzhiyun * because it was seen that on one device, it
447*4882a593Smuzhiyun * would stop sending spaces after around 250 msec.
448*4882a593Smuzhiyun * Besides, this is close to 2^32 anyway and timeout is u32.
449*4882a593Smuzhiyun */
450*4882a593Smuzhiyun dev->rdev->min_timeout = 127 * sample_period;
451*4882a593Smuzhiyun dev->rdev->max_timeout = 200000;
452*4882a593Smuzhiyun }
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun if (dev->hw_learning_and_tx_capable)
455*4882a593Smuzhiyun dev->rdev->tx_resolution = sample_period;
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun if (dev->rdev->timeout > dev->rdev->max_timeout)
458*4882a593Smuzhiyun dev->rdev->timeout = dev->rdev->max_timeout;
459*4882a593Smuzhiyun if (dev->rdev->timeout < dev->rdev->min_timeout)
460*4882a593Smuzhiyun dev->rdev->timeout = dev->rdev->min_timeout;
461*4882a593Smuzhiyun }
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun /* Enable the device for receive */
ene_rx_enable_hw(struct ene_device * dev)464*4882a593Smuzhiyun static void ene_rx_enable_hw(struct ene_device *dev)
465*4882a593Smuzhiyun {
466*4882a593Smuzhiyun u8 reg_value;
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun /* Enable system interrupt */
469*4882a593Smuzhiyun if (dev->hw_revision < ENE_HW_C) {
470*4882a593Smuzhiyun ene_write_reg(dev, ENEB_IRQ, dev->irq << 1);
471*4882a593Smuzhiyun ene_write_reg(dev, ENEB_IRQ_UNK1, 0x01);
472*4882a593Smuzhiyun } else {
473*4882a593Smuzhiyun reg_value = ene_read_reg(dev, ENE_IRQ) & 0xF0;
474*4882a593Smuzhiyun reg_value |= ENE_IRQ_UNK_EN;
475*4882a593Smuzhiyun reg_value &= ~ENE_IRQ_STATUS;
476*4882a593Smuzhiyun reg_value |= (dev->irq & ENE_IRQ_MASK);
477*4882a593Smuzhiyun ene_write_reg(dev, ENE_IRQ, reg_value);
478*4882a593Smuzhiyun }
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun /* Enable inputs */
481*4882a593Smuzhiyun ene_rx_enable_fan_input(dev, dev->rx_fan_input_inuse);
482*4882a593Smuzhiyun ene_rx_enable_cir_engine(dev, !dev->rx_fan_input_inuse);
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun /* ack any pending irqs - just in case */
485*4882a593Smuzhiyun ene_irq_status(dev);
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun /* enable firmware bits */
488*4882a593Smuzhiyun ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ);
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun /* enter idle mode */
491*4882a593Smuzhiyun ir_raw_event_set_idle(dev->rdev, true);
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun /* Enable the device for receive - wrapper to track the state*/
ene_rx_enable(struct ene_device * dev)495*4882a593Smuzhiyun static void ene_rx_enable(struct ene_device *dev)
496*4882a593Smuzhiyun {
497*4882a593Smuzhiyun ene_rx_enable_hw(dev);
498*4882a593Smuzhiyun dev->rx_enabled = true;
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun /* Disable the device receiver */
ene_rx_disable_hw(struct ene_device * dev)502*4882a593Smuzhiyun static void ene_rx_disable_hw(struct ene_device *dev)
503*4882a593Smuzhiyun {
504*4882a593Smuzhiyun /* disable inputs */
505*4882a593Smuzhiyun ene_rx_enable_cir_engine(dev, false);
506*4882a593Smuzhiyun ene_rx_enable_fan_input(dev, false);
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun /* disable hardware IRQ and firmware flag */
509*4882a593Smuzhiyun ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ);
510*4882a593Smuzhiyun ir_raw_event_set_idle(dev->rdev, true);
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun /* Disable the device receiver - wrapper to track the state */
ene_rx_disable(struct ene_device * dev)514*4882a593Smuzhiyun static void ene_rx_disable(struct ene_device *dev)
515*4882a593Smuzhiyun {
516*4882a593Smuzhiyun ene_rx_disable_hw(dev);
517*4882a593Smuzhiyun dev->rx_enabled = false;
518*4882a593Smuzhiyun }
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun /* This resets the receiver. Useful to stop stream of spaces at end of
521*4882a593Smuzhiyun * transmission
522*4882a593Smuzhiyun */
ene_rx_reset(struct ene_device * dev)523*4882a593Smuzhiyun static void ene_rx_reset(struct ene_device *dev)
524*4882a593Smuzhiyun {
525*4882a593Smuzhiyun ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN);
526*4882a593Smuzhiyun ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN);
527*4882a593Smuzhiyun }
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun /* Set up the TX carrier frequency and duty cycle */
ene_tx_set_carrier(struct ene_device * dev)530*4882a593Smuzhiyun static void ene_tx_set_carrier(struct ene_device *dev)
531*4882a593Smuzhiyun {
532*4882a593Smuzhiyun u8 tx_puls_width;
533*4882a593Smuzhiyun unsigned long flags;
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun spin_lock_irqsave(&dev->hw_lock, flags);
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun ene_set_clear_reg_mask(dev, ENE_CIRCFG,
538*4882a593Smuzhiyun ENE_CIRCFG_TX_CARR, dev->tx_period > 0);
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun if (!dev->tx_period)
541*4882a593Smuzhiyun goto unlock;
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun BUG_ON(dev->tx_duty_cycle >= 100 || dev->tx_duty_cycle <= 0);
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun tx_puls_width = dev->tx_period / (100 / dev->tx_duty_cycle);
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun if (!tx_puls_width)
548*4882a593Smuzhiyun tx_puls_width = 1;
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun dbg("TX: pulse distance = %d * 500 ns", dev->tx_period);
551*4882a593Smuzhiyun dbg("TX: pulse width = %d * 500 ns", tx_puls_width);
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun ene_write_reg(dev, ENE_CIRMOD_PRD, dev->tx_period | ENE_CIRMOD_PRD_POL);
554*4882a593Smuzhiyun ene_write_reg(dev, ENE_CIRMOD_HPRD, tx_puls_width);
555*4882a593Smuzhiyun unlock:
556*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->hw_lock, flags);
557*4882a593Smuzhiyun }
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun /* Enable/disable transmitters */
ene_tx_set_transmitters(struct ene_device * dev)560*4882a593Smuzhiyun static void ene_tx_set_transmitters(struct ene_device *dev)
561*4882a593Smuzhiyun {
562*4882a593Smuzhiyun unsigned long flags;
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun spin_lock_irqsave(&dev->hw_lock, flags);
565*4882a593Smuzhiyun ene_set_clear_reg_mask(dev, ENE_GPIOFS8, ENE_GPIOFS8_GPIO41,
566*4882a593Smuzhiyun !!(dev->transmitter_mask & 0x01));
567*4882a593Smuzhiyun ene_set_clear_reg_mask(dev, ENE_GPIOFS1, ENE_GPIOFS1_GPIO0D,
568*4882a593Smuzhiyun !!(dev->transmitter_mask & 0x02));
569*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->hw_lock, flags);
570*4882a593Smuzhiyun }
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun /* prepare transmission */
ene_tx_enable(struct ene_device * dev)573*4882a593Smuzhiyun static void ene_tx_enable(struct ene_device *dev)
574*4882a593Smuzhiyun {
575*4882a593Smuzhiyun u8 conf1 = ene_read_reg(dev, ENE_CIRCFG);
576*4882a593Smuzhiyun u8 fwreg2 = ene_read_reg(dev, ENE_FW2);
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun dev->saved_conf1 = conf1;
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun /* Show information about currently connected transmitter jacks */
581*4882a593Smuzhiyun if (fwreg2 & ENE_FW2_EMMITER1_CONN)
582*4882a593Smuzhiyun dbg("TX: Transmitter #1 is connected");
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun if (fwreg2 & ENE_FW2_EMMITER2_CONN)
585*4882a593Smuzhiyun dbg("TX: Transmitter #2 is connected");
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun if (!(fwreg2 & (ENE_FW2_EMMITER1_CONN | ENE_FW2_EMMITER2_CONN)))
588*4882a593Smuzhiyun pr_warn("TX: transmitter cable isn't connected!\n");
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun /* disable receive on revc */
591*4882a593Smuzhiyun if (dev->hw_revision == ENE_HW_C)
592*4882a593Smuzhiyun conf1 &= ~ENE_CIRCFG_RX_EN;
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun /* Enable TX engine */
595*4882a593Smuzhiyun conf1 |= ENE_CIRCFG_TX_EN | ENE_CIRCFG_TX_IRQ;
596*4882a593Smuzhiyun ene_write_reg(dev, ENE_CIRCFG, conf1);
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun /* end transmission */
ene_tx_disable(struct ene_device * dev)600*4882a593Smuzhiyun static void ene_tx_disable(struct ene_device *dev)
601*4882a593Smuzhiyun {
602*4882a593Smuzhiyun ene_write_reg(dev, ENE_CIRCFG, dev->saved_conf1);
603*4882a593Smuzhiyun dev->tx_buffer = NULL;
604*4882a593Smuzhiyun }
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun /* TX one sample - must be called with dev->hw_lock*/
ene_tx_sample(struct ene_device * dev)608*4882a593Smuzhiyun static void ene_tx_sample(struct ene_device *dev)
609*4882a593Smuzhiyun {
610*4882a593Smuzhiyun u8 raw_tx;
611*4882a593Smuzhiyun u32 sample;
612*4882a593Smuzhiyun bool pulse = dev->tx_sample_pulse;
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun if (!dev->tx_buffer) {
615*4882a593Smuzhiyun pr_warn("TX: BUG: attempt to transmit NULL buffer\n");
616*4882a593Smuzhiyun return;
617*4882a593Smuzhiyun }
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun /* Grab next TX sample */
620*4882a593Smuzhiyun if (!dev->tx_sample) {
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun if (dev->tx_pos == dev->tx_len) {
623*4882a593Smuzhiyun if (!dev->tx_done) {
624*4882a593Smuzhiyun dbg("TX: no more data to send");
625*4882a593Smuzhiyun dev->tx_done = true;
626*4882a593Smuzhiyun goto exit;
627*4882a593Smuzhiyun } else {
628*4882a593Smuzhiyun dbg("TX: last sample sent by hardware");
629*4882a593Smuzhiyun ene_tx_disable(dev);
630*4882a593Smuzhiyun complete(&dev->tx_complete);
631*4882a593Smuzhiyun return;
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun }
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun sample = dev->tx_buffer[dev->tx_pos++];
636*4882a593Smuzhiyun dev->tx_sample_pulse = !dev->tx_sample_pulse;
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun dev->tx_sample = DIV_ROUND_CLOSEST(sample, sample_period);
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun if (!dev->tx_sample)
641*4882a593Smuzhiyun dev->tx_sample = 1;
642*4882a593Smuzhiyun }
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun raw_tx = min(dev->tx_sample , (unsigned int)ENE_CIRRLC_OUT_MASK);
645*4882a593Smuzhiyun dev->tx_sample -= raw_tx;
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun dbg("TX: sample %8d (%s)", raw_tx * sample_period,
648*4882a593Smuzhiyun pulse ? "pulse" : "space");
649*4882a593Smuzhiyun if (pulse)
650*4882a593Smuzhiyun raw_tx |= ENE_CIRRLC_OUT_PULSE;
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun ene_write_reg(dev,
653*4882a593Smuzhiyun dev->tx_reg ? ENE_CIRRLC_OUT1 : ENE_CIRRLC_OUT0, raw_tx);
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun dev->tx_reg = !dev->tx_reg;
656*4882a593Smuzhiyun exit:
657*4882a593Smuzhiyun /* simulate TX done interrupt */
658*4882a593Smuzhiyun if (txsim)
659*4882a593Smuzhiyun mod_timer(&dev->tx_sim_timer, jiffies + HZ / 500);
660*4882a593Smuzhiyun }
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun /* timer to simulate tx done interrupt */
ene_tx_irqsim(struct timer_list * t)663*4882a593Smuzhiyun static void ene_tx_irqsim(struct timer_list *t)
664*4882a593Smuzhiyun {
665*4882a593Smuzhiyun struct ene_device *dev = from_timer(dev, t, tx_sim_timer);
666*4882a593Smuzhiyun unsigned long flags;
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun spin_lock_irqsave(&dev->hw_lock, flags);
669*4882a593Smuzhiyun ene_tx_sample(dev);
670*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->hw_lock, flags);
671*4882a593Smuzhiyun }
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun /* read irq status and ack it */
ene_irq_status(struct ene_device * dev)675*4882a593Smuzhiyun static int ene_irq_status(struct ene_device *dev)
676*4882a593Smuzhiyun {
677*4882a593Smuzhiyun u8 irq_status;
678*4882a593Smuzhiyun u8 fw_flags1, fw_flags2;
679*4882a593Smuzhiyun int retval = 0;
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun fw_flags2 = ene_read_reg(dev, ENE_FW2);
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun if (dev->hw_revision < ENE_HW_C) {
684*4882a593Smuzhiyun irq_status = ene_read_reg(dev, ENEB_IRQ_STATUS);
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun if (!(irq_status & ENEB_IRQ_STATUS_IR))
687*4882a593Smuzhiyun return 0;
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun ene_clear_reg_mask(dev, ENEB_IRQ_STATUS, ENEB_IRQ_STATUS_IR);
690*4882a593Smuzhiyun return ENE_IRQ_RX;
691*4882a593Smuzhiyun }
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun irq_status = ene_read_reg(dev, ENE_IRQ);
694*4882a593Smuzhiyun if (!(irq_status & ENE_IRQ_STATUS))
695*4882a593Smuzhiyun return 0;
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun /* original driver does that twice - a workaround ? */
698*4882a593Smuzhiyun ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);
699*4882a593Smuzhiyun ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun /* check RX interrupt */
702*4882a593Smuzhiyun if (fw_flags2 & ENE_FW2_RXIRQ) {
703*4882a593Smuzhiyun retval |= ENE_IRQ_RX;
704*4882a593Smuzhiyun ene_write_reg(dev, ENE_FW2, fw_flags2 & ~ENE_FW2_RXIRQ);
705*4882a593Smuzhiyun }
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun /* check TX interrupt */
708*4882a593Smuzhiyun fw_flags1 = ene_read_reg(dev, ENE_FW1);
709*4882a593Smuzhiyun if (fw_flags1 & ENE_FW1_TXIRQ) {
710*4882a593Smuzhiyun ene_write_reg(dev, ENE_FW1, fw_flags1 & ~ENE_FW1_TXIRQ);
711*4882a593Smuzhiyun retval |= ENE_IRQ_TX;
712*4882a593Smuzhiyun }
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun return retval;
715*4882a593Smuzhiyun }
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun /* interrupt handler */
ene_isr(int irq,void * data)718*4882a593Smuzhiyun static irqreturn_t ene_isr(int irq, void *data)
719*4882a593Smuzhiyun {
720*4882a593Smuzhiyun u16 hw_value, reg;
721*4882a593Smuzhiyun int hw_sample, irq_status;
722*4882a593Smuzhiyun bool pulse;
723*4882a593Smuzhiyun unsigned long flags;
724*4882a593Smuzhiyun irqreturn_t retval = IRQ_NONE;
725*4882a593Smuzhiyun struct ene_device *dev = (struct ene_device *)data;
726*4882a593Smuzhiyun struct ir_raw_event ev = {};
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun spin_lock_irqsave(&dev->hw_lock, flags);
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun dbg_verbose("ISR called");
731*4882a593Smuzhiyun ene_rx_read_hw_pointer(dev);
732*4882a593Smuzhiyun irq_status = ene_irq_status(dev);
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun if (!irq_status)
735*4882a593Smuzhiyun goto unlock;
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun retval = IRQ_HANDLED;
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun if (irq_status & ENE_IRQ_TX) {
740*4882a593Smuzhiyun dbg_verbose("TX interrupt");
741*4882a593Smuzhiyun if (!dev->hw_learning_and_tx_capable) {
742*4882a593Smuzhiyun dbg("TX interrupt on unsupported device!");
743*4882a593Smuzhiyun goto unlock;
744*4882a593Smuzhiyun }
745*4882a593Smuzhiyun ene_tx_sample(dev);
746*4882a593Smuzhiyun }
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun if (!(irq_status & ENE_IRQ_RX))
749*4882a593Smuzhiyun goto unlock;
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun dbg_verbose("RX interrupt");
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun if (dev->hw_learning_and_tx_capable)
754*4882a593Smuzhiyun ene_rx_sense_carrier(dev);
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun /* On hardware that don't support extra buffer we need to trust
757*4882a593Smuzhiyun the interrupt and not track the read pointer */
758*4882a593Smuzhiyun if (!dev->hw_extra_buffer)
759*4882a593Smuzhiyun dev->r_pointer = dev->w_pointer == 0 ? ENE_FW_PACKET_SIZE : 0;
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun while (1) {
762*4882a593Smuzhiyun
763*4882a593Smuzhiyun reg = ene_rx_get_sample_reg(dev);
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun dbg_verbose("next sample to read at: %04x", reg);
766*4882a593Smuzhiyun if (!reg)
767*4882a593Smuzhiyun break;
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun hw_value = ene_read_reg(dev, reg);
770*4882a593Smuzhiyun
771*4882a593Smuzhiyun if (dev->rx_fan_input_inuse) {
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun int offset = ENE_FW_SMPL_BUF_FAN - ENE_FW_SAMPLE_BUFFER;
774*4882a593Smuzhiyun
775*4882a593Smuzhiyun /* read high part of the sample */
776*4882a593Smuzhiyun hw_value |= ene_read_reg(dev, reg + offset) << 8;
777*4882a593Smuzhiyun pulse = hw_value & ENE_FW_SMPL_BUF_FAN_PLS;
778*4882a593Smuzhiyun
779*4882a593Smuzhiyun /* clear space bit, and other unused bits */
780*4882a593Smuzhiyun hw_value &= ENE_FW_SMPL_BUF_FAN_MSK;
781*4882a593Smuzhiyun hw_sample = hw_value * ENE_FW_SAMPLE_PERIOD_FAN;
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun } else {
784*4882a593Smuzhiyun pulse = !(hw_value & ENE_FW_SAMPLE_SPACE);
785*4882a593Smuzhiyun hw_value &= ~ENE_FW_SAMPLE_SPACE;
786*4882a593Smuzhiyun hw_sample = hw_value * sample_period;
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun if (dev->rx_period_adjust) {
789*4882a593Smuzhiyun hw_sample *= 100;
790*4882a593Smuzhiyun hw_sample /= (100 + dev->rx_period_adjust);
791*4882a593Smuzhiyun }
792*4882a593Smuzhiyun }
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun if (!dev->hw_extra_buffer && !hw_sample) {
795*4882a593Smuzhiyun dev->r_pointer = dev->w_pointer;
796*4882a593Smuzhiyun continue;
797*4882a593Smuzhiyun }
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun dbg("RX: %d (%s)", hw_sample, pulse ? "pulse" : "space");
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun ev.duration = hw_sample;
802*4882a593Smuzhiyun ev.pulse = pulse;
803*4882a593Smuzhiyun ir_raw_event_store_with_filter(dev->rdev, &ev);
804*4882a593Smuzhiyun }
805*4882a593Smuzhiyun
806*4882a593Smuzhiyun ir_raw_event_handle(dev->rdev);
807*4882a593Smuzhiyun unlock:
808*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->hw_lock, flags);
809*4882a593Smuzhiyun return retval;
810*4882a593Smuzhiyun }
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun /* Initialize default settings */
ene_setup_default_settings(struct ene_device * dev)813*4882a593Smuzhiyun static void ene_setup_default_settings(struct ene_device *dev)
814*4882a593Smuzhiyun {
815*4882a593Smuzhiyun dev->tx_period = 32;
816*4882a593Smuzhiyun dev->tx_duty_cycle = 50; /*%*/
817*4882a593Smuzhiyun dev->transmitter_mask = 0x03;
818*4882a593Smuzhiyun dev->learning_mode_enabled = learning_mode_force;
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun /* Set reasonable default timeout */
821*4882a593Smuzhiyun dev->rdev->timeout = MS_TO_US(150);
822*4882a593Smuzhiyun }
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun /* Upload all hardware settings at once. Used at load and resume time */
ene_setup_hw_settings(struct ene_device * dev)825*4882a593Smuzhiyun static void ene_setup_hw_settings(struct ene_device *dev)
826*4882a593Smuzhiyun {
827*4882a593Smuzhiyun if (dev->hw_learning_and_tx_capable) {
828*4882a593Smuzhiyun ene_tx_set_carrier(dev);
829*4882a593Smuzhiyun ene_tx_set_transmitters(dev);
830*4882a593Smuzhiyun }
831*4882a593Smuzhiyun
832*4882a593Smuzhiyun ene_rx_setup(dev);
833*4882a593Smuzhiyun }
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun /* outside interface: called on first open*/
ene_open(struct rc_dev * rdev)836*4882a593Smuzhiyun static int ene_open(struct rc_dev *rdev)
837*4882a593Smuzhiyun {
838*4882a593Smuzhiyun struct ene_device *dev = rdev->priv;
839*4882a593Smuzhiyun unsigned long flags;
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun spin_lock_irqsave(&dev->hw_lock, flags);
842*4882a593Smuzhiyun ene_rx_enable(dev);
843*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->hw_lock, flags);
844*4882a593Smuzhiyun return 0;
845*4882a593Smuzhiyun }
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun /* outside interface: called on device close*/
ene_close(struct rc_dev * rdev)848*4882a593Smuzhiyun static void ene_close(struct rc_dev *rdev)
849*4882a593Smuzhiyun {
850*4882a593Smuzhiyun struct ene_device *dev = rdev->priv;
851*4882a593Smuzhiyun unsigned long flags;
852*4882a593Smuzhiyun spin_lock_irqsave(&dev->hw_lock, flags);
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun ene_rx_disable(dev);
855*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->hw_lock, flags);
856*4882a593Smuzhiyun }
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun /* outside interface: set transmitter mask */
ene_set_tx_mask(struct rc_dev * rdev,u32 tx_mask)859*4882a593Smuzhiyun static int ene_set_tx_mask(struct rc_dev *rdev, u32 tx_mask)
860*4882a593Smuzhiyun {
861*4882a593Smuzhiyun struct ene_device *dev = rdev->priv;
862*4882a593Smuzhiyun dbg("TX: attempt to set transmitter mask %02x", tx_mask);
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun /* invalid txmask */
865*4882a593Smuzhiyun if (!tx_mask || tx_mask & ~0x03) {
866*4882a593Smuzhiyun dbg("TX: invalid mask");
867*4882a593Smuzhiyun /* return count of transmitters */
868*4882a593Smuzhiyun return 2;
869*4882a593Smuzhiyun }
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun dev->transmitter_mask = tx_mask;
872*4882a593Smuzhiyun ene_tx_set_transmitters(dev);
873*4882a593Smuzhiyun return 0;
874*4882a593Smuzhiyun }
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun /* outside interface : set tx carrier */
ene_set_tx_carrier(struct rc_dev * rdev,u32 carrier)877*4882a593Smuzhiyun static int ene_set_tx_carrier(struct rc_dev *rdev, u32 carrier)
878*4882a593Smuzhiyun {
879*4882a593Smuzhiyun struct ene_device *dev = rdev->priv;
880*4882a593Smuzhiyun u32 period;
881*4882a593Smuzhiyun
882*4882a593Smuzhiyun dbg("TX: attempt to set tx carrier to %d kHz", carrier);
883*4882a593Smuzhiyun if (carrier == 0)
884*4882a593Smuzhiyun return -EINVAL;
885*4882a593Smuzhiyun
886*4882a593Smuzhiyun period = 2000000 / carrier;
887*4882a593Smuzhiyun if (period && (period > ENE_CIRMOD_PRD_MAX ||
888*4882a593Smuzhiyun period < ENE_CIRMOD_PRD_MIN)) {
889*4882a593Smuzhiyun
890*4882a593Smuzhiyun dbg("TX: out of range %d-%d kHz carrier",
891*4882a593Smuzhiyun 2000 / ENE_CIRMOD_PRD_MIN, 2000 / ENE_CIRMOD_PRD_MAX);
892*4882a593Smuzhiyun return -EINVAL;
893*4882a593Smuzhiyun }
894*4882a593Smuzhiyun
895*4882a593Smuzhiyun dev->tx_period = period;
896*4882a593Smuzhiyun ene_tx_set_carrier(dev);
897*4882a593Smuzhiyun return 0;
898*4882a593Smuzhiyun }
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun /*outside interface : set tx duty cycle */
ene_set_tx_duty_cycle(struct rc_dev * rdev,u32 duty_cycle)901*4882a593Smuzhiyun static int ene_set_tx_duty_cycle(struct rc_dev *rdev, u32 duty_cycle)
902*4882a593Smuzhiyun {
903*4882a593Smuzhiyun struct ene_device *dev = rdev->priv;
904*4882a593Smuzhiyun dbg("TX: setting duty cycle to %d%%", duty_cycle);
905*4882a593Smuzhiyun dev->tx_duty_cycle = duty_cycle;
906*4882a593Smuzhiyun ene_tx_set_carrier(dev);
907*4882a593Smuzhiyun return 0;
908*4882a593Smuzhiyun }
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun /* outside interface: enable learning mode */
ene_set_learning_mode(struct rc_dev * rdev,int enable)911*4882a593Smuzhiyun static int ene_set_learning_mode(struct rc_dev *rdev, int enable)
912*4882a593Smuzhiyun {
913*4882a593Smuzhiyun struct ene_device *dev = rdev->priv;
914*4882a593Smuzhiyun unsigned long flags;
915*4882a593Smuzhiyun if (enable == dev->learning_mode_enabled)
916*4882a593Smuzhiyun return 0;
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun spin_lock_irqsave(&dev->hw_lock, flags);
919*4882a593Smuzhiyun dev->learning_mode_enabled = enable;
920*4882a593Smuzhiyun ene_rx_disable(dev);
921*4882a593Smuzhiyun ene_rx_setup(dev);
922*4882a593Smuzhiyun ene_rx_enable(dev);
923*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->hw_lock, flags);
924*4882a593Smuzhiyun return 0;
925*4882a593Smuzhiyun }
926*4882a593Smuzhiyun
ene_set_carrier_report(struct rc_dev * rdev,int enable)927*4882a593Smuzhiyun static int ene_set_carrier_report(struct rc_dev *rdev, int enable)
928*4882a593Smuzhiyun {
929*4882a593Smuzhiyun struct ene_device *dev = rdev->priv;
930*4882a593Smuzhiyun unsigned long flags;
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun if (enable == dev->carrier_detect_enabled)
933*4882a593Smuzhiyun return 0;
934*4882a593Smuzhiyun
935*4882a593Smuzhiyun spin_lock_irqsave(&dev->hw_lock, flags);
936*4882a593Smuzhiyun dev->carrier_detect_enabled = enable;
937*4882a593Smuzhiyun ene_rx_disable(dev);
938*4882a593Smuzhiyun ene_rx_setup(dev);
939*4882a593Smuzhiyun ene_rx_enable(dev);
940*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->hw_lock, flags);
941*4882a593Smuzhiyun return 0;
942*4882a593Smuzhiyun }
943*4882a593Smuzhiyun
944*4882a593Smuzhiyun /* outside interface: enable or disable idle mode */
ene_set_idle(struct rc_dev * rdev,bool idle)945*4882a593Smuzhiyun static void ene_set_idle(struct rc_dev *rdev, bool idle)
946*4882a593Smuzhiyun {
947*4882a593Smuzhiyun struct ene_device *dev = rdev->priv;
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun if (idle) {
950*4882a593Smuzhiyun ene_rx_reset(dev);
951*4882a593Smuzhiyun dbg("RX: end of data");
952*4882a593Smuzhiyun }
953*4882a593Smuzhiyun }
954*4882a593Smuzhiyun
955*4882a593Smuzhiyun /* outside interface: transmit */
ene_transmit(struct rc_dev * rdev,unsigned * buf,unsigned n)956*4882a593Smuzhiyun static int ene_transmit(struct rc_dev *rdev, unsigned *buf, unsigned n)
957*4882a593Smuzhiyun {
958*4882a593Smuzhiyun struct ene_device *dev = rdev->priv;
959*4882a593Smuzhiyun unsigned long flags;
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun dev->tx_buffer = buf;
962*4882a593Smuzhiyun dev->tx_len = n;
963*4882a593Smuzhiyun dev->tx_pos = 0;
964*4882a593Smuzhiyun dev->tx_reg = 0;
965*4882a593Smuzhiyun dev->tx_done = 0;
966*4882a593Smuzhiyun dev->tx_sample = 0;
967*4882a593Smuzhiyun dev->tx_sample_pulse = false;
968*4882a593Smuzhiyun
969*4882a593Smuzhiyun dbg("TX: %d samples", dev->tx_len);
970*4882a593Smuzhiyun
971*4882a593Smuzhiyun spin_lock_irqsave(&dev->hw_lock, flags);
972*4882a593Smuzhiyun
973*4882a593Smuzhiyun ene_tx_enable(dev);
974*4882a593Smuzhiyun
975*4882a593Smuzhiyun /* Transmit first two samples */
976*4882a593Smuzhiyun ene_tx_sample(dev);
977*4882a593Smuzhiyun ene_tx_sample(dev);
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->hw_lock, flags);
980*4882a593Smuzhiyun
981*4882a593Smuzhiyun if (wait_for_completion_timeout(&dev->tx_complete, 2 * HZ) == 0) {
982*4882a593Smuzhiyun dbg("TX: timeout");
983*4882a593Smuzhiyun spin_lock_irqsave(&dev->hw_lock, flags);
984*4882a593Smuzhiyun ene_tx_disable(dev);
985*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->hw_lock, flags);
986*4882a593Smuzhiyun } else
987*4882a593Smuzhiyun dbg("TX: done");
988*4882a593Smuzhiyun return n;
989*4882a593Smuzhiyun }
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun /* probe entry */
ene_probe(struct pnp_dev * pnp_dev,const struct pnp_device_id * id)992*4882a593Smuzhiyun static int ene_probe(struct pnp_dev *pnp_dev, const struct pnp_device_id *id)
993*4882a593Smuzhiyun {
994*4882a593Smuzhiyun int error = -ENOMEM;
995*4882a593Smuzhiyun struct rc_dev *rdev;
996*4882a593Smuzhiyun struct ene_device *dev;
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun /* allocate memory */
999*4882a593Smuzhiyun dev = kzalloc(sizeof(struct ene_device), GFP_KERNEL);
1000*4882a593Smuzhiyun rdev = rc_allocate_device(RC_DRIVER_IR_RAW);
1001*4882a593Smuzhiyun if (!dev || !rdev)
1002*4882a593Smuzhiyun goto exit_free_dev_rdev;
1003*4882a593Smuzhiyun
1004*4882a593Smuzhiyun /* validate resources */
1005*4882a593Smuzhiyun error = -ENODEV;
1006*4882a593Smuzhiyun
1007*4882a593Smuzhiyun /* init these to -1, as 0 is valid for both */
1008*4882a593Smuzhiyun dev->hw_io = -1;
1009*4882a593Smuzhiyun dev->irq = -1;
1010*4882a593Smuzhiyun
1011*4882a593Smuzhiyun if (!pnp_port_valid(pnp_dev, 0) ||
1012*4882a593Smuzhiyun pnp_port_len(pnp_dev, 0) < ENE_IO_SIZE)
1013*4882a593Smuzhiyun goto exit_free_dev_rdev;
1014*4882a593Smuzhiyun
1015*4882a593Smuzhiyun if (!pnp_irq_valid(pnp_dev, 0))
1016*4882a593Smuzhiyun goto exit_free_dev_rdev;
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun spin_lock_init(&dev->hw_lock);
1019*4882a593Smuzhiyun
1020*4882a593Smuzhiyun dev->hw_io = pnp_port_start(pnp_dev, 0);
1021*4882a593Smuzhiyun dev->irq = pnp_irq(pnp_dev, 0);
1022*4882a593Smuzhiyun
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun pnp_set_drvdata(pnp_dev, dev);
1025*4882a593Smuzhiyun dev->pnp_dev = pnp_dev;
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun /* don't allow too short/long sample periods */
1028*4882a593Smuzhiyun if (sample_period < 5 || sample_period > 0x7F)
1029*4882a593Smuzhiyun sample_period = ENE_DEFAULT_SAMPLE_PERIOD;
1030*4882a593Smuzhiyun
1031*4882a593Smuzhiyun /* detect hardware version and features */
1032*4882a593Smuzhiyun error = ene_hw_detect(dev);
1033*4882a593Smuzhiyun if (error)
1034*4882a593Smuzhiyun goto exit_free_dev_rdev;
1035*4882a593Smuzhiyun
1036*4882a593Smuzhiyun if (!dev->hw_learning_and_tx_capable && txsim) {
1037*4882a593Smuzhiyun dev->hw_learning_and_tx_capable = true;
1038*4882a593Smuzhiyun timer_setup(&dev->tx_sim_timer, ene_tx_irqsim, 0);
1039*4882a593Smuzhiyun pr_warn("Simulation of TX activated\n");
1040*4882a593Smuzhiyun }
1041*4882a593Smuzhiyun
1042*4882a593Smuzhiyun if (!dev->hw_learning_and_tx_capable)
1043*4882a593Smuzhiyun learning_mode_force = false;
1044*4882a593Smuzhiyun
1045*4882a593Smuzhiyun rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
1046*4882a593Smuzhiyun rdev->priv = dev;
1047*4882a593Smuzhiyun rdev->open = ene_open;
1048*4882a593Smuzhiyun rdev->close = ene_close;
1049*4882a593Smuzhiyun rdev->s_idle = ene_set_idle;
1050*4882a593Smuzhiyun rdev->driver_name = ENE_DRIVER_NAME;
1051*4882a593Smuzhiyun rdev->map_name = RC_MAP_RC6_MCE;
1052*4882a593Smuzhiyun rdev->device_name = "ENE eHome Infrared Remote Receiver";
1053*4882a593Smuzhiyun
1054*4882a593Smuzhiyun if (dev->hw_learning_and_tx_capable) {
1055*4882a593Smuzhiyun rdev->s_learning_mode = ene_set_learning_mode;
1056*4882a593Smuzhiyun init_completion(&dev->tx_complete);
1057*4882a593Smuzhiyun rdev->tx_ir = ene_transmit;
1058*4882a593Smuzhiyun rdev->s_tx_mask = ene_set_tx_mask;
1059*4882a593Smuzhiyun rdev->s_tx_carrier = ene_set_tx_carrier;
1060*4882a593Smuzhiyun rdev->s_tx_duty_cycle = ene_set_tx_duty_cycle;
1061*4882a593Smuzhiyun rdev->s_carrier_report = ene_set_carrier_report;
1062*4882a593Smuzhiyun rdev->device_name = "ENE eHome Infrared Remote Transceiver";
1063*4882a593Smuzhiyun }
1064*4882a593Smuzhiyun
1065*4882a593Smuzhiyun dev->rdev = rdev;
1066*4882a593Smuzhiyun
1067*4882a593Smuzhiyun ene_rx_setup_hw_buffer(dev);
1068*4882a593Smuzhiyun ene_setup_default_settings(dev);
1069*4882a593Smuzhiyun ene_setup_hw_settings(dev);
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun device_set_wakeup_capable(&pnp_dev->dev, true);
1072*4882a593Smuzhiyun device_set_wakeup_enable(&pnp_dev->dev, true);
1073*4882a593Smuzhiyun
1074*4882a593Smuzhiyun error = rc_register_device(rdev);
1075*4882a593Smuzhiyun if (error < 0)
1076*4882a593Smuzhiyun goto exit_free_dev_rdev;
1077*4882a593Smuzhiyun
1078*4882a593Smuzhiyun /* claim the resources */
1079*4882a593Smuzhiyun error = -EBUSY;
1080*4882a593Smuzhiyun if (!request_region(dev->hw_io, ENE_IO_SIZE, ENE_DRIVER_NAME)) {
1081*4882a593Smuzhiyun goto exit_unregister_device;
1082*4882a593Smuzhiyun }
1083*4882a593Smuzhiyun
1084*4882a593Smuzhiyun if (request_irq(dev->irq, ene_isr,
1085*4882a593Smuzhiyun IRQF_SHARED, ENE_DRIVER_NAME, (void *)dev)) {
1086*4882a593Smuzhiyun goto exit_release_hw_io;
1087*4882a593Smuzhiyun }
1088*4882a593Smuzhiyun
1089*4882a593Smuzhiyun pr_notice("driver has been successfully loaded\n");
1090*4882a593Smuzhiyun return 0;
1091*4882a593Smuzhiyun
1092*4882a593Smuzhiyun exit_release_hw_io:
1093*4882a593Smuzhiyun release_region(dev->hw_io, ENE_IO_SIZE);
1094*4882a593Smuzhiyun exit_unregister_device:
1095*4882a593Smuzhiyun rc_unregister_device(rdev);
1096*4882a593Smuzhiyun rdev = NULL;
1097*4882a593Smuzhiyun exit_free_dev_rdev:
1098*4882a593Smuzhiyun rc_free_device(rdev);
1099*4882a593Smuzhiyun kfree(dev);
1100*4882a593Smuzhiyun return error;
1101*4882a593Smuzhiyun }
1102*4882a593Smuzhiyun
1103*4882a593Smuzhiyun /* main unload function */
ene_remove(struct pnp_dev * pnp_dev)1104*4882a593Smuzhiyun static void ene_remove(struct pnp_dev *pnp_dev)
1105*4882a593Smuzhiyun {
1106*4882a593Smuzhiyun struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1107*4882a593Smuzhiyun unsigned long flags;
1108*4882a593Smuzhiyun
1109*4882a593Smuzhiyun spin_lock_irqsave(&dev->hw_lock, flags);
1110*4882a593Smuzhiyun ene_rx_disable(dev);
1111*4882a593Smuzhiyun ene_rx_restore_hw_buffer(dev);
1112*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->hw_lock, flags);
1113*4882a593Smuzhiyun
1114*4882a593Smuzhiyun free_irq(dev->irq, dev);
1115*4882a593Smuzhiyun release_region(dev->hw_io, ENE_IO_SIZE);
1116*4882a593Smuzhiyun rc_unregister_device(dev->rdev);
1117*4882a593Smuzhiyun kfree(dev);
1118*4882a593Smuzhiyun }
1119*4882a593Smuzhiyun
1120*4882a593Smuzhiyun /* enable wake on IR (wakes on specific button on original remote) */
ene_enable_wake(struct ene_device * dev,bool enable)1121*4882a593Smuzhiyun static void ene_enable_wake(struct ene_device *dev, bool enable)
1122*4882a593Smuzhiyun {
1123*4882a593Smuzhiyun dbg("wake on IR %s", enable ? "enabled" : "disabled");
1124*4882a593Smuzhiyun ene_set_clear_reg_mask(dev, ENE_FW1, ENE_FW1_WAKE, enable);
1125*4882a593Smuzhiyun }
1126*4882a593Smuzhiyun
1127*4882a593Smuzhiyun #ifdef CONFIG_PM
ene_suspend(struct pnp_dev * pnp_dev,pm_message_t state)1128*4882a593Smuzhiyun static int ene_suspend(struct pnp_dev *pnp_dev, pm_message_t state)
1129*4882a593Smuzhiyun {
1130*4882a593Smuzhiyun struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1131*4882a593Smuzhiyun bool wake = device_may_wakeup(&dev->pnp_dev->dev);
1132*4882a593Smuzhiyun
1133*4882a593Smuzhiyun if (!wake && dev->rx_enabled)
1134*4882a593Smuzhiyun ene_rx_disable_hw(dev);
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun ene_enable_wake(dev, wake);
1137*4882a593Smuzhiyun return 0;
1138*4882a593Smuzhiyun }
1139*4882a593Smuzhiyun
ene_resume(struct pnp_dev * pnp_dev)1140*4882a593Smuzhiyun static int ene_resume(struct pnp_dev *pnp_dev)
1141*4882a593Smuzhiyun {
1142*4882a593Smuzhiyun struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1143*4882a593Smuzhiyun ene_setup_hw_settings(dev);
1144*4882a593Smuzhiyun
1145*4882a593Smuzhiyun if (dev->rx_enabled)
1146*4882a593Smuzhiyun ene_rx_enable(dev);
1147*4882a593Smuzhiyun
1148*4882a593Smuzhiyun ene_enable_wake(dev, false);
1149*4882a593Smuzhiyun return 0;
1150*4882a593Smuzhiyun }
1151*4882a593Smuzhiyun #endif
1152*4882a593Smuzhiyun
ene_shutdown(struct pnp_dev * pnp_dev)1153*4882a593Smuzhiyun static void ene_shutdown(struct pnp_dev *pnp_dev)
1154*4882a593Smuzhiyun {
1155*4882a593Smuzhiyun struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1156*4882a593Smuzhiyun ene_enable_wake(dev, true);
1157*4882a593Smuzhiyun }
1158*4882a593Smuzhiyun
1159*4882a593Smuzhiyun static const struct pnp_device_id ene_ids[] = {
1160*4882a593Smuzhiyun {.id = "ENE0100",},
1161*4882a593Smuzhiyun {.id = "ENE0200",},
1162*4882a593Smuzhiyun {.id = "ENE0201",},
1163*4882a593Smuzhiyun {.id = "ENE0202",},
1164*4882a593Smuzhiyun {},
1165*4882a593Smuzhiyun };
1166*4882a593Smuzhiyun
1167*4882a593Smuzhiyun static struct pnp_driver ene_driver = {
1168*4882a593Smuzhiyun .name = ENE_DRIVER_NAME,
1169*4882a593Smuzhiyun .id_table = ene_ids,
1170*4882a593Smuzhiyun .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1171*4882a593Smuzhiyun
1172*4882a593Smuzhiyun .probe = ene_probe,
1173*4882a593Smuzhiyun .remove = ene_remove,
1174*4882a593Smuzhiyun #ifdef CONFIG_PM
1175*4882a593Smuzhiyun .suspend = ene_suspend,
1176*4882a593Smuzhiyun .resume = ene_resume,
1177*4882a593Smuzhiyun #endif
1178*4882a593Smuzhiyun .shutdown = ene_shutdown,
1179*4882a593Smuzhiyun };
1180*4882a593Smuzhiyun
1181*4882a593Smuzhiyun module_param(sample_period, int, S_IRUGO);
1182*4882a593Smuzhiyun MODULE_PARM_DESC(sample_period, "Hardware sample period (50 us default)");
1183*4882a593Smuzhiyun
1184*4882a593Smuzhiyun module_param(learning_mode_force, bool, S_IRUGO);
1185*4882a593Smuzhiyun MODULE_PARM_DESC(learning_mode_force, "Enable learning mode by default");
1186*4882a593Smuzhiyun
1187*4882a593Smuzhiyun module_param(debug, int, S_IRUGO | S_IWUSR);
1188*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Debug level");
1189*4882a593Smuzhiyun
1190*4882a593Smuzhiyun module_param(txsim, bool, S_IRUGO);
1191*4882a593Smuzhiyun MODULE_PARM_DESC(txsim,
1192*4882a593Smuzhiyun "Simulate TX features on unsupported hardware (dangerous)");
1193*4882a593Smuzhiyun
1194*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pnp, ene_ids);
1195*4882a593Smuzhiyun MODULE_DESCRIPTION
1196*4882a593Smuzhiyun ("Infrared input driver for KB3926B/C/D/E/F (aka ENE0100/ENE0200/ENE0201/ENE0202) CIR port");
1197*4882a593Smuzhiyun
1198*4882a593Smuzhiyun MODULE_AUTHOR("Maxim Levitsky");
1199*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1200*4882a593Smuzhiyun
1201*4882a593Smuzhiyun module_pnp_driver(ene_driver);
1202