1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * FM Driver for Connectivity chip of Texas Instruments. 4*4882a593Smuzhiyun * FM Common module header file 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2011 Texas Instruments 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _FMDRV_COMMON_H 10*4882a593Smuzhiyun #define _FMDRV_COMMON_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define FM_ST_REG_TIMEOUT msecs_to_jiffies(6000) /* 6 sec */ 13*4882a593Smuzhiyun #define FM_PKT_LOGICAL_CHAN_NUMBER 0x08 /* Logical channel 8 */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define REG_RD 0x1 16*4882a593Smuzhiyun #define REG_WR 0x0 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun struct fm_reg_table { 19*4882a593Smuzhiyun u8 opcode; 20*4882a593Smuzhiyun u8 type; 21*4882a593Smuzhiyun u8 *name; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define STEREO_GET 0 25*4882a593Smuzhiyun #define RSSI_LVL_GET 1 26*4882a593Smuzhiyun #define IF_COUNT_GET 2 27*4882a593Smuzhiyun #define FLAG_GET 3 28*4882a593Smuzhiyun #define RDS_SYNC_GET 4 29*4882a593Smuzhiyun #define RDS_DATA_GET 5 30*4882a593Smuzhiyun #define FREQ_SET 10 31*4882a593Smuzhiyun #define AF_FREQ_SET 11 32*4882a593Smuzhiyun #define MOST_MODE_SET 12 33*4882a593Smuzhiyun #define MOST_BLEND_SET 13 34*4882a593Smuzhiyun #define DEMPH_MODE_SET 14 35*4882a593Smuzhiyun #define SEARCH_LVL_SET 15 36*4882a593Smuzhiyun #define BAND_SET 16 37*4882a593Smuzhiyun #define MUTE_STATUS_SET 17 38*4882a593Smuzhiyun #define RDS_PAUSE_LVL_SET 18 39*4882a593Smuzhiyun #define RDS_PAUSE_DUR_SET 19 40*4882a593Smuzhiyun #define RDS_MEM_SET 20 41*4882a593Smuzhiyun #define RDS_BLK_B_SET 21 42*4882a593Smuzhiyun #define RDS_MSK_B_SET 22 43*4882a593Smuzhiyun #define RDS_PI_MASK_SET 23 44*4882a593Smuzhiyun #define RDS_PI_SET 24 45*4882a593Smuzhiyun #define RDS_SYSTEM_SET 25 46*4882a593Smuzhiyun #define INT_MASK_SET 26 47*4882a593Smuzhiyun #define SEARCH_DIR_SET 27 48*4882a593Smuzhiyun #define VOLUME_SET 28 49*4882a593Smuzhiyun #define AUDIO_ENABLE_SET 29 50*4882a593Smuzhiyun #define PCM_MODE_SET 30 51*4882a593Smuzhiyun #define I2S_MODE_CONFIG_SET 31 52*4882a593Smuzhiyun #define POWER_SET 32 53*4882a593Smuzhiyun #define INTX_CONFIG_SET 33 54*4882a593Smuzhiyun #define PULL_EN_SET 34 55*4882a593Smuzhiyun #define HILO_SET 35 56*4882a593Smuzhiyun #define SWITCH2FREF 36 57*4882a593Smuzhiyun #define FREQ_DRIFT_REPORT 37 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define PCE_GET 40 60*4882a593Smuzhiyun #define FIRM_VER_GET 41 61*4882a593Smuzhiyun #define ASIC_VER_GET 42 62*4882a593Smuzhiyun #define ASIC_ID_GET 43 63*4882a593Smuzhiyun #define MAN_ID_GET 44 64*4882a593Smuzhiyun #define TUNER_MODE_SET 45 65*4882a593Smuzhiyun #define STOP_SEARCH 46 66*4882a593Smuzhiyun #define RDS_CNTRL_SET 47 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define WRITE_HARDWARE_REG 100 69*4882a593Smuzhiyun #define CODE_DOWNLOAD 101 70*4882a593Smuzhiyun #define RESET 102 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define FM_POWER_MODE 254 73*4882a593Smuzhiyun #define FM_INTERRUPT 255 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* Transmitter API */ 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define CHANL_SET 55 78*4882a593Smuzhiyun #define CHANL_BW_SET 56 79*4882a593Smuzhiyun #define REF_SET 57 80*4882a593Smuzhiyun #define POWER_ENB_SET 90 81*4882a593Smuzhiyun #define POWER_ATT_SET 58 82*4882a593Smuzhiyun #define POWER_LEV_SET 59 83*4882a593Smuzhiyun #define AUDIO_DEV_SET 60 84*4882a593Smuzhiyun #define PILOT_DEV_SET 61 85*4882a593Smuzhiyun #define RDS_DEV_SET 62 86*4882a593Smuzhiyun #define TX_BAND_SET 65 87*4882a593Smuzhiyun #define PUPD_SET 91 88*4882a593Smuzhiyun #define AUDIO_IO_SET 63 89*4882a593Smuzhiyun #define PREMPH_SET 64 90*4882a593Smuzhiyun #define MONO_SET 66 91*4882a593Smuzhiyun #define MUTE 92 92*4882a593Smuzhiyun #define MPX_LMT_ENABLE 67 93*4882a593Smuzhiyun #define PI_SET 93 94*4882a593Smuzhiyun #define ECC_SET 69 95*4882a593Smuzhiyun #define PTY 70 96*4882a593Smuzhiyun #define AF 71 97*4882a593Smuzhiyun #define DISPLAY_MODE 74 98*4882a593Smuzhiyun #define RDS_REP_SET 77 99*4882a593Smuzhiyun #define RDS_CONFIG_DATA_SET 98 100*4882a593Smuzhiyun #define RDS_DATA_SET 99 101*4882a593Smuzhiyun #define RDS_DATA_ENB 94 102*4882a593Smuzhiyun #define TA_SET 78 103*4882a593Smuzhiyun #define TP_SET 79 104*4882a593Smuzhiyun #define DI_SET 80 105*4882a593Smuzhiyun #define MS_SET 81 106*4882a593Smuzhiyun #define PS_SCROLL_SPEED 82 107*4882a593Smuzhiyun #define TX_AUDIO_LEVEL_TEST 96 108*4882a593Smuzhiyun #define TX_AUDIO_LEVEL_TEST_THRESHOLD 73 109*4882a593Smuzhiyun #define TX_AUDIO_INPUT_LEVEL_RANGE_SET 54 110*4882a593Smuzhiyun #define RX_ANTENNA_SELECT 87 111*4882a593Smuzhiyun #define I2C_DEV_ADDR_SET 86 112*4882a593Smuzhiyun #define REF_ERR_CALIB_PARAM_SET 88 113*4882a593Smuzhiyun #define REF_ERR_CALIB_PERIODICITY_SET 89 114*4882a593Smuzhiyun #define SOC_INT_TRIGGER 52 115*4882a593Smuzhiyun #define SOC_AUDIO_PATH_SET 83 116*4882a593Smuzhiyun #define SOC_PCMI_OVERRIDE 84 117*4882a593Smuzhiyun #define SOC_I2S_OVERRIDE 85 118*4882a593Smuzhiyun #define RSSI_BLOCK_SCAN_FREQ_SET 95 119*4882a593Smuzhiyun #define RSSI_BLOCK_SCAN_START 97 120*4882a593Smuzhiyun #define RSSI_BLOCK_SCAN_DATA_GET 5 121*4882a593Smuzhiyun #define READ_FMANT_TUNE_VALUE 104 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* SKB helpers */ 124*4882a593Smuzhiyun struct fm_skb_cb { 125*4882a593Smuzhiyun __u8 fm_op; 126*4882a593Smuzhiyun struct completion *completion; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define fm_cb(skb) ((struct fm_skb_cb *)(skb->cb)) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* FM Channel-8 command message format */ 132*4882a593Smuzhiyun struct fm_cmd_msg_hdr { 133*4882a593Smuzhiyun __u8 hdr; /* Logical Channel-8 */ 134*4882a593Smuzhiyun __u8 len; /* Number of bytes follows */ 135*4882a593Smuzhiyun __u8 op; /* FM Opcode */ 136*4882a593Smuzhiyun __u8 rd_wr; /* Read/Write command */ 137*4882a593Smuzhiyun __u8 dlen; /* Length of payload */ 138*4882a593Smuzhiyun } __attribute__ ((packed)); 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #define FM_CMD_MSG_HDR_SIZE 5 /* sizeof(struct fm_cmd_msg_hdr) */ 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* FM Channel-8 event messgage format */ 143*4882a593Smuzhiyun struct fm_event_msg_hdr { 144*4882a593Smuzhiyun __u8 header; /* Logical Channel-8 */ 145*4882a593Smuzhiyun __u8 len; /* Number of bytes follows */ 146*4882a593Smuzhiyun __u8 status; /* Event status */ 147*4882a593Smuzhiyun __u8 num_fm_hci_cmds; /* Number of pkts the host allowed to send */ 148*4882a593Smuzhiyun __u8 op; /* FM Opcode */ 149*4882a593Smuzhiyun __u8 rd_wr; /* Read/Write command */ 150*4882a593Smuzhiyun __u8 dlen; /* Length of payload */ 151*4882a593Smuzhiyun } __attribute__ ((packed)); 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun #define FM_EVT_MSG_HDR_SIZE 7 /* sizeof(struct fm_event_msg_hdr) */ 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun /* TI's magic number in firmware file */ 156*4882a593Smuzhiyun #define FM_FW_FILE_HEADER_MAGIC 0x42535442 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun #define FM_ENABLE 1 159*4882a593Smuzhiyun #define FM_DISABLE 0 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* FLAG_GET register bits */ 162*4882a593Smuzhiyun #define FM_FR_EVENT BIT(0) 163*4882a593Smuzhiyun #define FM_BL_EVENT BIT(1) 164*4882a593Smuzhiyun #define FM_RDS_EVENT BIT(2) 165*4882a593Smuzhiyun #define FM_BBLK_EVENT BIT(3) 166*4882a593Smuzhiyun #define FM_LSYNC_EVENT BIT(4) 167*4882a593Smuzhiyun #define FM_LEV_EVENT BIT(5) 168*4882a593Smuzhiyun #define FM_IFFR_EVENT BIT(6) 169*4882a593Smuzhiyun #define FM_PI_EVENT BIT(7) 170*4882a593Smuzhiyun #define FM_PD_EVENT BIT(8) 171*4882a593Smuzhiyun #define FM_STIC_EVENT BIT(9) 172*4882a593Smuzhiyun #define FM_MAL_EVENT BIT(10) 173*4882a593Smuzhiyun #define FM_POW_ENB_EVENT BIT(11) 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* 176*4882a593Smuzhiyun * Firmware files of FM. ASIC ID and ASIC version will be appened to this, 177*4882a593Smuzhiyun * later. 178*4882a593Smuzhiyun */ 179*4882a593Smuzhiyun #define FM_FMC_FW_FILE_START ("fmc_ch8") 180*4882a593Smuzhiyun #define FM_RX_FW_FILE_START ("fm_rx_ch8") 181*4882a593Smuzhiyun #define FM_TX_FW_FILE_START ("fm_tx_ch8") 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun #define FM_UNDEFINED_FREQ 0xFFFFFFFF 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun /* Band types */ 186*4882a593Smuzhiyun #define FM_BAND_EUROPE_US 0 187*4882a593Smuzhiyun #define FM_BAND_JAPAN 1 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun /* Seek directions */ 190*4882a593Smuzhiyun #define FM_SEARCH_DIRECTION_DOWN 0 191*4882a593Smuzhiyun #define FM_SEARCH_DIRECTION_UP 1 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun /* Tunner modes */ 194*4882a593Smuzhiyun #define FM_TUNER_STOP_SEARCH_MODE 0 195*4882a593Smuzhiyun #define FM_TUNER_PRESET_MODE 1 196*4882a593Smuzhiyun #define FM_TUNER_AUTONOMOUS_SEARCH_MODE 2 197*4882a593Smuzhiyun #define FM_TUNER_AF_JUMP_MODE 3 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun /* Min and Max volume */ 200*4882a593Smuzhiyun #define FM_RX_VOLUME_MIN 0 201*4882a593Smuzhiyun #define FM_RX_VOLUME_MAX 70 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun /* Volume gain step */ 204*4882a593Smuzhiyun #define FM_RX_VOLUME_GAIN_STEP 0x370 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun /* Mute modes */ 207*4882a593Smuzhiyun #define FM_MUTE_ON 0 208*4882a593Smuzhiyun #define FM_MUTE_OFF 1 209*4882a593Smuzhiyun #define FM_MUTE_ATTENUATE 2 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun #define FM_RX_UNMUTE_MODE 0x00 212*4882a593Smuzhiyun #define FM_RX_RF_DEP_MODE 0x01 213*4882a593Smuzhiyun #define FM_RX_AC_MUTE_MODE 0x02 214*4882a593Smuzhiyun #define FM_RX_HARD_MUTE_LEFT_MODE 0x04 215*4882a593Smuzhiyun #define FM_RX_HARD_MUTE_RIGHT_MODE 0x08 216*4882a593Smuzhiyun #define FM_RX_SOFT_MUTE_FORCE_MODE 0x10 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun /* RF dependent mute mode */ 219*4882a593Smuzhiyun #define FM_RX_RF_DEPENDENT_MUTE_ON 1 220*4882a593Smuzhiyun #define FM_RX_RF_DEPENDENT_MUTE_OFF 0 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun /* RSSI threshold min and max */ 223*4882a593Smuzhiyun #define FM_RX_RSSI_THRESHOLD_MIN -128 224*4882a593Smuzhiyun #define FM_RX_RSSI_THRESHOLD_MAX 127 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun /* Stereo/Mono mode */ 227*4882a593Smuzhiyun #define FM_STEREO_MODE 0 228*4882a593Smuzhiyun #define FM_MONO_MODE 1 229*4882a593Smuzhiyun #define FM_STEREO_SOFT_BLEND 1 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /* FM RX De-emphasis filter modes */ 232*4882a593Smuzhiyun #define FM_RX_EMPHASIS_FILTER_50_USEC 0 233*4882a593Smuzhiyun #define FM_RX_EMPHASIS_FILTER_75_USEC 1 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun /* FM RDS modes */ 236*4882a593Smuzhiyun #define FM_RDS_DISABLE 0 237*4882a593Smuzhiyun #define FM_RDS_ENABLE 1 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun #define FM_NO_PI_CODE 0 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun /* FM and RX RDS block enable/disable */ 242*4882a593Smuzhiyun #define FM_RX_PWR_SET_FM_ON_RDS_OFF 0x1 243*4882a593Smuzhiyun #define FM_RX_PWR_SET_FM_AND_RDS_BLK_ON 0x3 244*4882a593Smuzhiyun #define FM_RX_PWR_SET_FM_AND_RDS_BLK_OFF 0x0 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun /* RX RDS */ 247*4882a593Smuzhiyun #define FM_RX_RDS_FLUSH_FIFO 0x1 248*4882a593Smuzhiyun #define FM_RX_RDS_FIFO_THRESHOLD 64 /* tuples */ 249*4882a593Smuzhiyun #define FM_RDS_BLK_SIZE 3 /* 3 bytes */ 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun /* RDS block types */ 252*4882a593Smuzhiyun #define FM_RDS_BLOCK_A 0 253*4882a593Smuzhiyun #define FM_RDS_BLOCK_B 1 254*4882a593Smuzhiyun #define FM_RDS_BLOCK_C 2 255*4882a593Smuzhiyun #define FM_RDS_BLOCK_Ctag 3 256*4882a593Smuzhiyun #define FM_RDS_BLOCK_D 4 257*4882a593Smuzhiyun #define FM_RDS_BLOCK_E 5 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun #define FM_RDS_BLK_IDX_A 0 260*4882a593Smuzhiyun #define FM_RDS_BLK_IDX_B 1 261*4882a593Smuzhiyun #define FM_RDS_BLK_IDX_C 2 262*4882a593Smuzhiyun #define FM_RDS_BLK_IDX_D 3 263*4882a593Smuzhiyun #define FM_RDS_BLK_IDX_UNKNOWN 0xF0 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun #define FM_RDS_STATUS_ERR_MASK 0x18 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun /* 268*4882a593Smuzhiyun * Represents an RDS group type & version. 269*4882a593Smuzhiyun * There are 15 groups, each group has 2 versions: A and B. 270*4882a593Smuzhiyun */ 271*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_0A BIT(0) 272*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_0B BIT(1) 273*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_1A BIT(2) 274*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_1B BIT(3) 275*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_2A BIT(4) 276*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_2B BIT(5) 277*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_3A BIT(6) 278*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_3B BIT(7) 279*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_4A BIT(8) 280*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_4B BIT(9) 281*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_5A BIT(10) 282*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_5B BIT(11) 283*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_6A BIT(12) 284*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_6B BIT(13) 285*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_7A BIT(14) 286*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_7B BIT(15) 287*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_8A BIT(16) 288*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_8B BIT(17) 289*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_9A BIT(18) 290*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_9B BIT(19) 291*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_10A BIT(20) 292*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_10B BIT(21) 293*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_11A BIT(22) 294*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_11B BIT(23) 295*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_12A BIT(24) 296*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_12B BIT(25) 297*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_13A BIT(26) 298*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_13B BIT(27) 299*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_14A BIT(28) 300*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_14B BIT(29) 301*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_15A BIT(30) 302*4882a593Smuzhiyun #define FM_RDS_GROUP_TYPE_MASK_15B BIT(31) 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun /* RX Alternate Frequency info */ 305*4882a593Smuzhiyun #define FM_RDS_MIN_AF 1 306*4882a593Smuzhiyun #define FM_RDS_MAX_AF 204 307*4882a593Smuzhiyun #define FM_RDS_MAX_AF_JAPAN 140 308*4882a593Smuzhiyun #define FM_RDS_1_AF_FOLLOWS 225 309*4882a593Smuzhiyun #define FM_RDS_25_AF_FOLLOWS 249 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun /* RDS system type (RDS/RBDS) */ 312*4882a593Smuzhiyun #define FM_RDS_SYSTEM_RDS 0 313*4882a593Smuzhiyun #define FM_RDS_SYSTEM_RBDS 1 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun /* AF on/off */ 316*4882a593Smuzhiyun #define FM_RX_RDS_AF_SWITCH_MODE_ON 1 317*4882a593Smuzhiyun #define FM_RX_RDS_AF_SWITCH_MODE_OFF 0 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun /* Retry count when interrupt process goes wrong */ 320*4882a593Smuzhiyun #define FM_IRQ_TIMEOUT_RETRY_MAX 5 /* 5 times */ 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun /* Audio IO set values */ 323*4882a593Smuzhiyun #define FM_RX_AUDIO_ENABLE_I2S 0x01 324*4882a593Smuzhiyun #define FM_RX_AUDIO_ENABLE_ANALOG 0x02 325*4882a593Smuzhiyun #define FM_RX_AUDIO_ENABLE_I2S_AND_ANALOG 0x03 326*4882a593Smuzhiyun #define FM_RX_AUDIO_ENABLE_DISABLE 0x00 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun /* HI/LO set values */ 329*4882a593Smuzhiyun #define FM_RX_IFFREQ_TO_HI_SIDE 0x0 330*4882a593Smuzhiyun #define FM_RX_IFFREQ_TO_LO_SIDE 0x1 331*4882a593Smuzhiyun #define FM_RX_IFFREQ_HILO_AUTOMATIC 0x2 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun /* 334*4882a593Smuzhiyun * Default RX mode configuration. Chip will be configured 335*4882a593Smuzhiyun * with this default values after loading RX firmware. 336*4882a593Smuzhiyun */ 337*4882a593Smuzhiyun #define FM_DEFAULT_RX_VOLUME 10 338*4882a593Smuzhiyun #define FM_DEFAULT_RSSI_THRESHOLD 3 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun /* Range for TX power level in units for dB/uV */ 341*4882a593Smuzhiyun #define FM_PWR_LVL_LOW 91 342*4882a593Smuzhiyun #define FM_PWR_LVL_HIGH 122 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun /* Chip specific default TX power level value */ 345*4882a593Smuzhiyun #define FM_PWR_LVL_DEF 4 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun /* FM TX Pre-emphasis filter values */ 348*4882a593Smuzhiyun #define FM_TX_PREEMPH_OFF 1 349*4882a593Smuzhiyun #define FM_TX_PREEMPH_50US 0 350*4882a593Smuzhiyun #define FM_TX_PREEMPH_75US 2 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun /* FM TX antenna impedance values */ 353*4882a593Smuzhiyun #define FM_TX_ANT_IMP_50 0 354*4882a593Smuzhiyun #define FM_TX_ANT_IMP_200 1 355*4882a593Smuzhiyun #define FM_TX_ANT_IMP_500 2 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun /* Functions exported by FM common sub-module */ 358*4882a593Smuzhiyun int fmc_prepare(struct fmdev *); 359*4882a593Smuzhiyun int fmc_release(struct fmdev *); 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun void fmc_update_region_info(struct fmdev *, u8); 362*4882a593Smuzhiyun int fmc_send_cmd(struct fmdev *, u8, u16, 363*4882a593Smuzhiyun void *, unsigned int, void *, int *); 364*4882a593Smuzhiyun int fmc_is_rds_data_available(struct fmdev *, struct file *, 365*4882a593Smuzhiyun struct poll_table_struct *); 366*4882a593Smuzhiyun int fmc_transfer_rds_from_internal_buff(struct fmdev *, struct file *, 367*4882a593Smuzhiyun u8 __user *, size_t); 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun int fmc_set_freq(struct fmdev *, u32); 370*4882a593Smuzhiyun int fmc_set_mode(struct fmdev *, u8); 371*4882a593Smuzhiyun int fmc_set_region(struct fmdev *, u8); 372*4882a593Smuzhiyun int fmc_set_mute_mode(struct fmdev *, u8); 373*4882a593Smuzhiyun int fmc_set_stereo_mono(struct fmdev *, u16); 374*4882a593Smuzhiyun int fmc_set_rds_mode(struct fmdev *, u8); 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun int fmc_get_freq(struct fmdev *, u32 *); 377*4882a593Smuzhiyun int fmc_get_region(struct fmdev *, u8 *); 378*4882a593Smuzhiyun int fmc_get_mode(struct fmdev *, u8 *); 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun /* 381*4882a593Smuzhiyun * channel spacing 382*4882a593Smuzhiyun */ 383*4882a593Smuzhiyun #define FM_CHANNEL_SPACING_50KHZ 1 384*4882a593Smuzhiyun #define FM_CHANNEL_SPACING_100KHZ 2 385*4882a593Smuzhiyun #define FM_CHANNEL_SPACING_200KHZ 4 386*4882a593Smuzhiyun #define FM_FREQ_MUL 50 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun #endif 389*4882a593Smuzhiyun 390