xref: /OK3568_Linux_fs/kernel/drivers/media/radio/si4713/si4713.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * drivers/media/radio/si4713-i2c.h
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Property and commands definitions for Si4713 radio transmitter chip.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright (c) 2008 Instituto Nokia de Tecnologia - INdT
7*4882a593Smuzhiyun  * Contact: Eduardo Valentin <eduardo.valentin@nokia.com>
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This file is licensed under the terms of the GNU General Public License
10*4882a593Smuzhiyun  * version 2. This program is licensed "as is" without any warranty of any
11*4882a593Smuzhiyun  * kind, whether express or implied.
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  */
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #ifndef SI4713_I2C_H
16*4882a593Smuzhiyun #define SI4713_I2C_H
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <linux/platform_device.h>
19*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
20*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
21*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
22*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
23*4882a593Smuzhiyun #include <linux/platform_data/media/si4713.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #define SI4713_PRODUCT_NUMBER		0x0D
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /* Command Timeouts */
28*4882a593Smuzhiyun #define DEFAULT_TIMEOUT			500
29*4882a593Smuzhiyun #define TIMEOUT_SET_PROPERTY		20
30*4882a593Smuzhiyun #define TIMEOUT_TX_TUNE_POWER		30000
31*4882a593Smuzhiyun #define TIMEOUT_TX_TUNE			110000
32*4882a593Smuzhiyun #define TIMEOUT_POWER_UP		200000
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun /*
35*4882a593Smuzhiyun  * Command and its arguments definitions
36*4882a593Smuzhiyun  */
37*4882a593Smuzhiyun #define SI4713_PWUP_CTSIEN		(1<<7)
38*4882a593Smuzhiyun #define SI4713_PWUP_GPO2OEN		(1<<6)
39*4882a593Smuzhiyun #define SI4713_PWUP_PATCH		(1<<5)
40*4882a593Smuzhiyun #define SI4713_PWUP_XOSCEN		(1<<4)
41*4882a593Smuzhiyun #define SI4713_PWUP_FUNC_TX		0x02
42*4882a593Smuzhiyun #define SI4713_PWUP_FUNC_PATCH		0x0F
43*4882a593Smuzhiyun #define SI4713_PWUP_OPMOD_ANALOG	0x50
44*4882a593Smuzhiyun #define SI4713_PWUP_OPMOD_DIGITAL	0x0F
45*4882a593Smuzhiyun #define SI4713_PWUP_NARGS		2
46*4882a593Smuzhiyun #define SI4713_PWUP_NRESP		1
47*4882a593Smuzhiyun #define SI4713_CMD_POWER_UP		0x01
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun #define SI4713_GETREV_NRESP		9
50*4882a593Smuzhiyun #define SI4713_CMD_GET_REV		0x10
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define SI4713_PWDN_NRESP		1
53*4882a593Smuzhiyun #define SI4713_CMD_POWER_DOWN		0x11
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun #define SI4713_SET_PROP_NARGS		5
56*4882a593Smuzhiyun #define SI4713_SET_PROP_NRESP		1
57*4882a593Smuzhiyun #define SI4713_CMD_SET_PROPERTY		0x12
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun #define SI4713_GET_PROP_NARGS		3
60*4882a593Smuzhiyun #define SI4713_GET_PROP_NRESP		4
61*4882a593Smuzhiyun #define SI4713_CMD_GET_PROPERTY		0x13
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun #define SI4713_GET_STATUS_NRESP		1
64*4882a593Smuzhiyun #define SI4713_CMD_GET_INT_STATUS	0x14
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun #define SI4713_CMD_PATCH_ARGS		0x15
67*4882a593Smuzhiyun #define SI4713_CMD_PATCH_DATA		0x16
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define SI4713_MAX_FREQ			10800
70*4882a593Smuzhiyun #define SI4713_MIN_FREQ			7600
71*4882a593Smuzhiyun #define SI4713_TXFREQ_NARGS		3
72*4882a593Smuzhiyun #define SI4713_TXFREQ_NRESP		1
73*4882a593Smuzhiyun #define SI4713_CMD_TX_TUNE_FREQ		0x30
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun #define SI4713_MAX_POWER		120
76*4882a593Smuzhiyun #define SI4713_MIN_POWER		88
77*4882a593Smuzhiyun #define SI4713_MAX_ANTCAP		191
78*4882a593Smuzhiyun #define SI4713_MIN_ANTCAP		0
79*4882a593Smuzhiyun #define SI4713_TXPWR_NARGS		4
80*4882a593Smuzhiyun #define SI4713_TXPWR_NRESP		1
81*4882a593Smuzhiyun #define SI4713_CMD_TX_TUNE_POWER	0x31
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun #define SI4713_TXMEA_NARGS		4
84*4882a593Smuzhiyun #define SI4713_TXMEA_NRESP		1
85*4882a593Smuzhiyun #define SI4713_CMD_TX_TUNE_MEASURE	0x32
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun #define SI4713_INTACK_MASK		0x01
88*4882a593Smuzhiyun #define SI4713_TXSTATUS_NARGS		1
89*4882a593Smuzhiyun #define SI4713_TXSTATUS_NRESP		8
90*4882a593Smuzhiyun #define SI4713_CMD_TX_TUNE_STATUS	0x33
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun #define SI4713_OVERMOD_BIT		(1 << 2)
93*4882a593Smuzhiyun #define SI4713_IALH_BIT			(1 << 1)
94*4882a593Smuzhiyun #define SI4713_IALL_BIT			(1 << 0)
95*4882a593Smuzhiyun #define SI4713_ASQSTATUS_NARGS		1
96*4882a593Smuzhiyun #define SI4713_ASQSTATUS_NRESP		5
97*4882a593Smuzhiyun #define SI4713_CMD_TX_ASQ_STATUS	0x34
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun #define SI4713_RDSBUFF_MODE_MASK	0x87
100*4882a593Smuzhiyun #define SI4713_RDSBUFF_NARGS		7
101*4882a593Smuzhiyun #define SI4713_RDSBUFF_NRESP		6
102*4882a593Smuzhiyun #define SI4713_CMD_TX_RDS_BUFF		0x35
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun #define SI4713_RDSPS_PSID_MASK		0x1F
105*4882a593Smuzhiyun #define SI4713_RDSPS_NARGS		5
106*4882a593Smuzhiyun #define SI4713_RDSPS_NRESP		1
107*4882a593Smuzhiyun #define SI4713_CMD_TX_RDS_PS		0x36
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun #define SI4713_CMD_GPO_CTL		0x80
110*4882a593Smuzhiyun #define SI4713_CMD_GPO_SET		0x81
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun /*
113*4882a593Smuzhiyun  * Bits from status response
114*4882a593Smuzhiyun  */
115*4882a593Smuzhiyun #define SI4713_CTS			(1<<7)
116*4882a593Smuzhiyun #define SI4713_ERR			(1<<6)
117*4882a593Smuzhiyun #define SI4713_RDS_INT			(1<<2)
118*4882a593Smuzhiyun #define SI4713_ASQ_INT			(1<<1)
119*4882a593Smuzhiyun #define SI4713_STC_INT			(1<<0)
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun /*
122*4882a593Smuzhiyun  * Property definitions
123*4882a593Smuzhiyun  */
124*4882a593Smuzhiyun #define SI4713_GPO_IEN			0x0001
125*4882a593Smuzhiyun #define SI4713_DIG_INPUT_FORMAT		0x0101
126*4882a593Smuzhiyun #define SI4713_DIG_INPUT_SAMPLE_RATE	0x0103
127*4882a593Smuzhiyun #define SI4713_REFCLK_FREQ		0x0201
128*4882a593Smuzhiyun #define SI4713_REFCLK_PRESCALE		0x0202
129*4882a593Smuzhiyun #define SI4713_TX_COMPONENT_ENABLE	0x2100
130*4882a593Smuzhiyun #define SI4713_TX_AUDIO_DEVIATION	0x2101
131*4882a593Smuzhiyun #define SI4713_TX_PILOT_DEVIATION	0x2102
132*4882a593Smuzhiyun #define SI4713_TX_RDS_DEVIATION		0x2103
133*4882a593Smuzhiyun #define SI4713_TX_LINE_INPUT_LEVEL	0x2104
134*4882a593Smuzhiyun #define SI4713_TX_LINE_INPUT_MUTE	0x2105
135*4882a593Smuzhiyun #define SI4713_TX_PREEMPHASIS		0x2106
136*4882a593Smuzhiyun #define SI4713_TX_PILOT_FREQUENCY	0x2107
137*4882a593Smuzhiyun #define SI4713_TX_ACOMP_ENABLE		0x2200
138*4882a593Smuzhiyun #define SI4713_TX_ACOMP_THRESHOLD	0x2201
139*4882a593Smuzhiyun #define SI4713_TX_ACOMP_ATTACK_TIME	0x2202
140*4882a593Smuzhiyun #define SI4713_TX_ACOMP_RELEASE_TIME	0x2203
141*4882a593Smuzhiyun #define SI4713_TX_ACOMP_GAIN		0x2204
142*4882a593Smuzhiyun #define SI4713_TX_LIMITER_RELEASE_TIME	0x2205
143*4882a593Smuzhiyun #define SI4713_TX_ASQ_INTERRUPT_SOURCE	0x2300
144*4882a593Smuzhiyun #define SI4713_TX_ASQ_LEVEL_LOW		0x2301
145*4882a593Smuzhiyun #define SI4713_TX_ASQ_DURATION_LOW	0x2302
146*4882a593Smuzhiyun #define SI4713_TX_ASQ_LEVEL_HIGH	0x2303
147*4882a593Smuzhiyun #define SI4713_TX_ASQ_DURATION_HIGH	0x2304
148*4882a593Smuzhiyun #define SI4713_TX_RDS_INTERRUPT_SOURCE	0x2C00
149*4882a593Smuzhiyun #define SI4713_TX_RDS_PI		0x2C01
150*4882a593Smuzhiyun #define SI4713_TX_RDS_PS_MIX		0x2C02
151*4882a593Smuzhiyun #define SI4713_TX_RDS_PS_MISC		0x2C03
152*4882a593Smuzhiyun #define SI4713_TX_RDS_PS_REPEAT_COUNT	0x2C04
153*4882a593Smuzhiyun #define SI4713_TX_RDS_PS_MESSAGE_COUNT	0x2C05
154*4882a593Smuzhiyun #define SI4713_TX_RDS_PS_AF		0x2C06
155*4882a593Smuzhiyun #define SI4713_TX_RDS_FIFO_SIZE		0x2C07
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun #define PREEMPHASIS_USA			75
158*4882a593Smuzhiyun #define PREEMPHASIS_EU			50
159*4882a593Smuzhiyun #define PREEMPHASIS_DISABLED		0
160*4882a593Smuzhiyun #define FMPE_USA			0x00
161*4882a593Smuzhiyun #define FMPE_EU				0x01
162*4882a593Smuzhiyun #define FMPE_DISABLED			0x02
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun #define POWER_UP			0x01
165*4882a593Smuzhiyun #define POWER_DOWN			0x00
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun #define MAX_RDS_PTY			31
168*4882a593Smuzhiyun #define MAX_RDS_DEVIATION		90000
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun /*
171*4882a593Smuzhiyun  * PSNAME is known to be defined as 8 character sized (RDS Spec).
172*4882a593Smuzhiyun  * However, there is receivers which scroll PSNAME 8xN sized.
173*4882a593Smuzhiyun  */
174*4882a593Smuzhiyun #define MAX_RDS_PS_NAME			96
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun /*
177*4882a593Smuzhiyun  * MAX_RDS_RADIO_TEXT is known to be defined as 32 (2A group) or 64 (2B group)
178*4882a593Smuzhiyun  * character sized (RDS Spec).
179*4882a593Smuzhiyun  * However, there is receivers which scroll them as well.
180*4882a593Smuzhiyun  */
181*4882a593Smuzhiyun #define MAX_RDS_RADIO_TEXT		384
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun #define MAX_LIMITER_RELEASE_TIME	102390
184*4882a593Smuzhiyun #define MAX_LIMITER_DEVIATION		90000
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun #define MAX_PILOT_DEVIATION		90000
187*4882a593Smuzhiyun #define MAX_PILOT_FREQUENCY		19000
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun #define MAX_ACOMP_RELEASE_TIME		1000000
190*4882a593Smuzhiyun #define MAX_ACOMP_ATTACK_TIME		5000
191*4882a593Smuzhiyun #define MAX_ACOMP_THRESHOLD		0
192*4882a593Smuzhiyun #define MIN_ACOMP_THRESHOLD		(-40)
193*4882a593Smuzhiyun #define MAX_ACOMP_GAIN			20
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun /*
196*4882a593Smuzhiyun  * si4713_device - private data
197*4882a593Smuzhiyun  */
198*4882a593Smuzhiyun struct si4713_device {
199*4882a593Smuzhiyun 	/* v4l2_subdev and i2c reference (v4l2_subdev priv data) */
200*4882a593Smuzhiyun 	struct v4l2_subdev sd;
201*4882a593Smuzhiyun 	struct v4l2_ctrl_handler ctrl_handler;
202*4882a593Smuzhiyun 	/* private data structures */
203*4882a593Smuzhiyun 	struct { /* si4713 control cluster */
204*4882a593Smuzhiyun 		/* This is one big cluster since the mute control
205*4882a593Smuzhiyun 		 * powers off the device and after unmuting again all
206*4882a593Smuzhiyun 		 * controls need to be set at once. The only way of doing
207*4882a593Smuzhiyun 		 * that is by making it one big cluster. */
208*4882a593Smuzhiyun 		struct v4l2_ctrl *mute;
209*4882a593Smuzhiyun 		struct v4l2_ctrl *rds_ps_name;
210*4882a593Smuzhiyun 		struct v4l2_ctrl *rds_radio_text;
211*4882a593Smuzhiyun 		struct v4l2_ctrl *rds_pi;
212*4882a593Smuzhiyun 		struct v4l2_ctrl *rds_deviation;
213*4882a593Smuzhiyun 		struct v4l2_ctrl *rds_pty;
214*4882a593Smuzhiyun 		struct v4l2_ctrl *rds_compressed;
215*4882a593Smuzhiyun 		struct v4l2_ctrl *rds_art_head;
216*4882a593Smuzhiyun 		struct v4l2_ctrl *rds_stereo;
217*4882a593Smuzhiyun 		struct v4l2_ctrl *rds_ta;
218*4882a593Smuzhiyun 		struct v4l2_ctrl *rds_tp;
219*4882a593Smuzhiyun 		struct v4l2_ctrl *rds_ms;
220*4882a593Smuzhiyun 		struct v4l2_ctrl *rds_dyn_pty;
221*4882a593Smuzhiyun 		struct v4l2_ctrl *rds_alt_freqs_enable;
222*4882a593Smuzhiyun 		struct v4l2_ctrl *rds_alt_freqs;
223*4882a593Smuzhiyun 		struct v4l2_ctrl *compression_enabled;
224*4882a593Smuzhiyun 		struct v4l2_ctrl *compression_threshold;
225*4882a593Smuzhiyun 		struct v4l2_ctrl *compression_gain;
226*4882a593Smuzhiyun 		struct v4l2_ctrl *compression_attack_time;
227*4882a593Smuzhiyun 		struct v4l2_ctrl *compression_release_time;
228*4882a593Smuzhiyun 		struct v4l2_ctrl *pilot_tone_enabled;
229*4882a593Smuzhiyun 		struct v4l2_ctrl *pilot_tone_freq;
230*4882a593Smuzhiyun 		struct v4l2_ctrl *pilot_tone_deviation;
231*4882a593Smuzhiyun 		struct v4l2_ctrl *limiter_enabled;
232*4882a593Smuzhiyun 		struct v4l2_ctrl *limiter_deviation;
233*4882a593Smuzhiyun 		struct v4l2_ctrl *limiter_release_time;
234*4882a593Smuzhiyun 		struct v4l2_ctrl *tune_preemphasis;
235*4882a593Smuzhiyun 		struct v4l2_ctrl *tune_pwr_level;
236*4882a593Smuzhiyun 		struct v4l2_ctrl *tune_ant_cap;
237*4882a593Smuzhiyun 	};
238*4882a593Smuzhiyun 	struct completion work;
239*4882a593Smuzhiyun 	struct regulator *vdd;
240*4882a593Smuzhiyun 	struct regulator *vio;
241*4882a593Smuzhiyun 	struct gpio_desc *gpio_reset;
242*4882a593Smuzhiyun 	struct platform_device *pd;
243*4882a593Smuzhiyun 	u32 power_state;
244*4882a593Smuzhiyun 	u32 rds_enabled;
245*4882a593Smuzhiyun 	u32 frequency;
246*4882a593Smuzhiyun 	u32 preemphasis;
247*4882a593Smuzhiyun 	u32 stereo;
248*4882a593Smuzhiyun 	u32 tune_rnl;
249*4882a593Smuzhiyun };
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun struct radio_si4713_platform_data {
252*4882a593Smuzhiyun 	struct i2c_client *subdev;
253*4882a593Smuzhiyun };
254*4882a593Smuzhiyun #endif /* ifndef SI4713_I2C_H */
255