1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Xilinx Video Timing Controller 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013-2015 Ideas on Board 6*4882a593Smuzhiyun * Copyright (C) 2013-2015 Xilinx, Inc. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> 9*4882a593Smuzhiyun * Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __XILINX_VTC_H__ 13*4882a593Smuzhiyun #define __XILINX_VTC_H__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct device_node; 16*4882a593Smuzhiyun struct xvtc_device; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define XVTC_MAX_HSIZE 8191 19*4882a593Smuzhiyun #define XVTC_MAX_VSIZE 8191 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun struct xvtc_config { 22*4882a593Smuzhiyun unsigned int hblank_start; 23*4882a593Smuzhiyun unsigned int hsync_start; 24*4882a593Smuzhiyun unsigned int hsync_end; 25*4882a593Smuzhiyun unsigned int hsize; 26*4882a593Smuzhiyun unsigned int vblank_start; 27*4882a593Smuzhiyun unsigned int vsync_start; 28*4882a593Smuzhiyun unsigned int vsync_end; 29*4882a593Smuzhiyun unsigned int vsize; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun struct xvtc_device *xvtc_of_get(struct device_node *np); 33*4882a593Smuzhiyun void xvtc_put(struct xvtc_device *xvtc); 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun int xvtc_generator_start(struct xvtc_device *xvtc, 36*4882a593Smuzhiyun const struct xvtc_config *config); 37*4882a593Smuzhiyun int xvtc_generator_stop(struct xvtc_device *xvtc); 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #endif /* __XILINX_VTC_H__ */ 40