1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Xilinx Video IP Composite Device 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013-2015 Ideas on Board 6*4882a593Smuzhiyun * Copyright (C) 2013-2015 Xilinx, Inc. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> 9*4882a593Smuzhiyun * Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __XILINX_VIPP_H__ 13*4882a593Smuzhiyun #define __XILINX_VIPP_H__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <linux/list.h> 16*4882a593Smuzhiyun #include <linux/mutex.h> 17*4882a593Smuzhiyun #include <media/media-device.h> 18*4882a593Smuzhiyun #include <media/v4l2-async.h> 19*4882a593Smuzhiyun #include <media/v4l2-ctrls.h> 20*4882a593Smuzhiyun #include <media/v4l2-device.h> 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /** 23*4882a593Smuzhiyun * struct xvip_composite_device - Xilinx Video IP device structure 24*4882a593Smuzhiyun * @v4l2_dev: V4L2 device 25*4882a593Smuzhiyun * @media_dev: media device 26*4882a593Smuzhiyun * @dev: (OF) device 27*4882a593Smuzhiyun * @notifier: V4L2 asynchronous subdevs notifier 28*4882a593Smuzhiyun * @dmas: list of DMA channels at the pipeline output and input 29*4882a593Smuzhiyun * @v4l2_caps: V4L2 capabilities of the whole device (see VIDIOC_QUERYCAP) 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun struct xvip_composite_device { 32*4882a593Smuzhiyun struct v4l2_device v4l2_dev; 33*4882a593Smuzhiyun struct media_device media_dev; 34*4882a593Smuzhiyun struct device *dev; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun struct v4l2_async_notifier notifier; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun struct list_head dmas; 39*4882a593Smuzhiyun u32 v4l2_caps; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #endif /* __XILINX_VIPP_H__ */ 43