1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Xilinx Test Pattern Generator
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013-2015 Ideas on Board
6*4882a593Smuzhiyun * Copyright (C) 2013-2015 Xilinx, Inc.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Contacts: Hyun Kwon <hyun.kwon@xilinx.com>
9*4882a593Smuzhiyun * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/of.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/xilinx-v4l2-controls.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <media/v4l2-async.h>
20*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
21*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include "xilinx-vip.h"
24*4882a593Smuzhiyun #include "xilinx-vtc.h"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define XTPG_CTRL_STATUS_SLAVE_ERROR (1 << 16)
27*4882a593Smuzhiyun #define XTPG_CTRL_IRQ_SLAVE_ERROR (1 << 16)
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define XTPG_PATTERN_CONTROL 0x0100
30*4882a593Smuzhiyun #define XTPG_PATTERN_MASK (0xf << 0)
31*4882a593Smuzhiyun #define XTPG_PATTERN_CONTROL_CROSS_HAIRS (1 << 4)
32*4882a593Smuzhiyun #define XTPG_PATTERN_CONTROL_MOVING_BOX (1 << 5)
33*4882a593Smuzhiyun #define XTPG_PATTERN_CONTROL_COLOR_MASK_SHIFT 6
34*4882a593Smuzhiyun #define XTPG_PATTERN_CONTROL_COLOR_MASK_MASK (0xf << 6)
35*4882a593Smuzhiyun #define XTPG_PATTERN_CONTROL_STUCK_PIXEL (1 << 9)
36*4882a593Smuzhiyun #define XTPG_PATTERN_CONTROL_NOISE (1 << 10)
37*4882a593Smuzhiyun #define XTPG_PATTERN_CONTROL_MOTION (1 << 12)
38*4882a593Smuzhiyun #define XTPG_MOTION_SPEED 0x0104
39*4882a593Smuzhiyun #define XTPG_CROSS_HAIRS 0x0108
40*4882a593Smuzhiyun #define XTPG_CROSS_HAIRS_ROW_SHIFT 0
41*4882a593Smuzhiyun #define XTPG_CROSS_HAIRS_ROW_MASK (0xfff << 0)
42*4882a593Smuzhiyun #define XTPG_CROSS_HAIRS_COLUMN_SHIFT 16
43*4882a593Smuzhiyun #define XTPG_CROSS_HAIRS_COLUMN_MASK (0xfff << 16)
44*4882a593Smuzhiyun #define XTPG_ZPLATE_HOR_CONTROL 0x010c
45*4882a593Smuzhiyun #define XTPG_ZPLATE_VER_CONTROL 0x0110
46*4882a593Smuzhiyun #define XTPG_ZPLATE_START_SHIFT 0
47*4882a593Smuzhiyun #define XTPG_ZPLATE_START_MASK (0xffff << 0)
48*4882a593Smuzhiyun #define XTPG_ZPLATE_SPEED_SHIFT 16
49*4882a593Smuzhiyun #define XTPG_ZPLATE_SPEED_MASK (0xffff << 16)
50*4882a593Smuzhiyun #define XTPG_BOX_SIZE 0x0114
51*4882a593Smuzhiyun #define XTPG_BOX_COLOR 0x0118
52*4882a593Smuzhiyun #define XTPG_STUCK_PIXEL_THRESH 0x011c
53*4882a593Smuzhiyun #define XTPG_NOISE_GAIN 0x0120
54*4882a593Smuzhiyun #define XTPG_BAYER_PHASE 0x0124
55*4882a593Smuzhiyun #define XTPG_BAYER_PHASE_RGGB 0
56*4882a593Smuzhiyun #define XTPG_BAYER_PHASE_GRBG 1
57*4882a593Smuzhiyun #define XTPG_BAYER_PHASE_GBRG 2
58*4882a593Smuzhiyun #define XTPG_BAYER_PHASE_BGGR 3
59*4882a593Smuzhiyun #define XTPG_BAYER_PHASE_OFF 4
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /*
62*4882a593Smuzhiyun * The minimum blanking value is one clock cycle for the front porch, one clock
63*4882a593Smuzhiyun * cycle for the sync pulse and one clock cycle for the back porch.
64*4882a593Smuzhiyun */
65*4882a593Smuzhiyun #define XTPG_MIN_HBLANK 3
66*4882a593Smuzhiyun #define XTPG_MAX_HBLANK (XVTC_MAX_HSIZE - XVIP_MIN_WIDTH)
67*4882a593Smuzhiyun #define XTPG_MIN_VBLANK 3
68*4882a593Smuzhiyun #define XTPG_MAX_VBLANK (XVTC_MAX_VSIZE - XVIP_MIN_HEIGHT)
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /**
71*4882a593Smuzhiyun * struct xtpg_device - Xilinx Test Pattern Generator device structure
72*4882a593Smuzhiyun * @xvip: Xilinx Video IP device
73*4882a593Smuzhiyun * @pads: media pads
74*4882a593Smuzhiyun * @npads: number of pads (1 or 2)
75*4882a593Smuzhiyun * @has_input: whether an input is connected to the sink pad
76*4882a593Smuzhiyun * @formats: active V4L2 media bus format for each pad
77*4882a593Smuzhiyun * @default_format: default V4L2 media bus format
78*4882a593Smuzhiyun * @vip_format: format information corresponding to the active format
79*4882a593Smuzhiyun * @bayer: boolean flag if TPG is set to any bayer format
80*4882a593Smuzhiyun * @ctrl_handler: control handler
81*4882a593Smuzhiyun * @hblank: horizontal blanking control
82*4882a593Smuzhiyun * @vblank: vertical blanking control
83*4882a593Smuzhiyun * @pattern: test pattern control
84*4882a593Smuzhiyun * @streaming: is the video stream active
85*4882a593Smuzhiyun * @vtc: video timing controller
86*4882a593Smuzhiyun * @vtmux_gpio: video timing mux GPIO
87*4882a593Smuzhiyun */
88*4882a593Smuzhiyun struct xtpg_device {
89*4882a593Smuzhiyun struct xvip_device xvip;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun struct media_pad pads[2];
92*4882a593Smuzhiyun unsigned int npads;
93*4882a593Smuzhiyun bool has_input;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun struct v4l2_mbus_framefmt formats[2];
96*4882a593Smuzhiyun struct v4l2_mbus_framefmt default_format;
97*4882a593Smuzhiyun const struct xvip_video_format *vip_format;
98*4882a593Smuzhiyun bool bayer;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun struct v4l2_ctrl_handler ctrl_handler;
101*4882a593Smuzhiyun struct v4l2_ctrl *hblank;
102*4882a593Smuzhiyun struct v4l2_ctrl *vblank;
103*4882a593Smuzhiyun struct v4l2_ctrl *pattern;
104*4882a593Smuzhiyun bool streaming;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun struct xvtc_device *vtc;
107*4882a593Smuzhiyun struct gpio_desc *vtmux_gpio;
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun
to_tpg(struct v4l2_subdev * subdev)110*4882a593Smuzhiyun static inline struct xtpg_device *to_tpg(struct v4l2_subdev *subdev)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun return container_of(subdev, struct xtpg_device, xvip.subdev);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
xtpg_get_bayer_phase(unsigned int code)115*4882a593Smuzhiyun static u32 xtpg_get_bayer_phase(unsigned int code)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun switch (code) {
118*4882a593Smuzhiyun case MEDIA_BUS_FMT_SRGGB8_1X8:
119*4882a593Smuzhiyun return XTPG_BAYER_PHASE_RGGB;
120*4882a593Smuzhiyun case MEDIA_BUS_FMT_SGRBG8_1X8:
121*4882a593Smuzhiyun return XTPG_BAYER_PHASE_GRBG;
122*4882a593Smuzhiyun case MEDIA_BUS_FMT_SGBRG8_1X8:
123*4882a593Smuzhiyun return XTPG_BAYER_PHASE_GBRG;
124*4882a593Smuzhiyun case MEDIA_BUS_FMT_SBGGR8_1X8:
125*4882a593Smuzhiyun return XTPG_BAYER_PHASE_BGGR;
126*4882a593Smuzhiyun default:
127*4882a593Smuzhiyun return XTPG_BAYER_PHASE_OFF;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
__xtpg_update_pattern_control(struct xtpg_device * xtpg,bool passthrough,bool pattern)131*4882a593Smuzhiyun static void __xtpg_update_pattern_control(struct xtpg_device *xtpg,
132*4882a593Smuzhiyun bool passthrough, bool pattern)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun u32 pattern_mask = (1 << (xtpg->pattern->maximum + 1)) - 1;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun /*
137*4882a593Smuzhiyun * If the TPG has no sink pad or no input connected to its sink pad
138*4882a593Smuzhiyun * passthrough mode can't be enabled.
139*4882a593Smuzhiyun */
140*4882a593Smuzhiyun if (xtpg->npads == 1 || !xtpg->has_input)
141*4882a593Smuzhiyun passthrough = false;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* If passthrough mode is allowed unmask bit 0. */
144*4882a593Smuzhiyun if (passthrough)
145*4882a593Smuzhiyun pattern_mask &= ~1;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun /* If test pattern mode is allowed unmask all other bits. */
148*4882a593Smuzhiyun if (pattern)
149*4882a593Smuzhiyun pattern_mask &= 1;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun __v4l2_ctrl_modify_range(xtpg->pattern, 0, xtpg->pattern->maximum,
152*4882a593Smuzhiyun pattern_mask, pattern ? 9 : 0);
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
xtpg_update_pattern_control(struct xtpg_device * xtpg,bool passthrough,bool pattern)155*4882a593Smuzhiyun static void xtpg_update_pattern_control(struct xtpg_device *xtpg,
156*4882a593Smuzhiyun bool passthrough, bool pattern)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun mutex_lock(xtpg->ctrl_handler.lock);
159*4882a593Smuzhiyun __xtpg_update_pattern_control(xtpg, passthrough, pattern);
160*4882a593Smuzhiyun mutex_unlock(xtpg->ctrl_handler.lock);
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
164*4882a593Smuzhiyun * V4L2 Subdevice Video Operations
165*4882a593Smuzhiyun */
166*4882a593Smuzhiyun
xtpg_s_stream(struct v4l2_subdev * subdev,int enable)167*4882a593Smuzhiyun static int xtpg_s_stream(struct v4l2_subdev *subdev, int enable)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun struct xtpg_device *xtpg = to_tpg(subdev);
170*4882a593Smuzhiyun unsigned int width = xtpg->formats[0].width;
171*4882a593Smuzhiyun unsigned int height = xtpg->formats[0].height;
172*4882a593Smuzhiyun bool passthrough;
173*4882a593Smuzhiyun u32 bayer_phase;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun if (!enable) {
176*4882a593Smuzhiyun xvip_stop(&xtpg->xvip);
177*4882a593Smuzhiyun if (xtpg->vtc)
178*4882a593Smuzhiyun xvtc_generator_stop(xtpg->vtc);
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun xtpg_update_pattern_control(xtpg, true, true);
181*4882a593Smuzhiyun xtpg->streaming = false;
182*4882a593Smuzhiyun return 0;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun xvip_set_frame_size(&xtpg->xvip, &xtpg->formats[0]);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun if (xtpg->vtc) {
188*4882a593Smuzhiyun struct xvtc_config config = {
189*4882a593Smuzhiyun .hblank_start = width,
190*4882a593Smuzhiyun .hsync_start = width + 1,
191*4882a593Smuzhiyun .vblank_start = height,
192*4882a593Smuzhiyun .vsync_start = height + 1,
193*4882a593Smuzhiyun };
194*4882a593Smuzhiyun unsigned int htotal;
195*4882a593Smuzhiyun unsigned int vtotal;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun htotal = min_t(unsigned int, XVTC_MAX_HSIZE,
198*4882a593Smuzhiyun v4l2_ctrl_g_ctrl(xtpg->hblank) + width);
199*4882a593Smuzhiyun vtotal = min_t(unsigned int, XVTC_MAX_VSIZE,
200*4882a593Smuzhiyun v4l2_ctrl_g_ctrl(xtpg->vblank) + height);
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun config.hsync_end = htotal - 1;
203*4882a593Smuzhiyun config.hsize = htotal;
204*4882a593Smuzhiyun config.vsync_end = vtotal - 1;
205*4882a593Smuzhiyun config.vsize = vtotal;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun xvtc_generator_start(xtpg->vtc, &config);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun /*
211*4882a593Smuzhiyun * Configure the bayer phase and video timing mux based on the
212*4882a593Smuzhiyun * operation mode (passthrough or test pattern generation). The test
213*4882a593Smuzhiyun * pattern can be modified by the control set handler, we thus need to
214*4882a593Smuzhiyun * take the control lock here to avoid races.
215*4882a593Smuzhiyun */
216*4882a593Smuzhiyun mutex_lock(xtpg->ctrl_handler.lock);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun xvip_clr_and_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
219*4882a593Smuzhiyun XTPG_PATTERN_MASK, xtpg->pattern->cur.val);
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun /*
222*4882a593Smuzhiyun * Switching between passthrough and test pattern generation modes isn't
223*4882a593Smuzhiyun * allowed during streaming, update the control range accordingly.
224*4882a593Smuzhiyun */
225*4882a593Smuzhiyun passthrough = xtpg->pattern->cur.val == 0;
226*4882a593Smuzhiyun __xtpg_update_pattern_control(xtpg, passthrough, !passthrough);
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun xtpg->streaming = true;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun mutex_unlock(xtpg->ctrl_handler.lock);
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun /*
233*4882a593Smuzhiyun * For TPG v5.0, the bayer phase needs to be off for the pass through
234*4882a593Smuzhiyun * mode, otherwise the external input would be subsampled.
235*4882a593Smuzhiyun */
236*4882a593Smuzhiyun bayer_phase = passthrough ? XTPG_BAYER_PHASE_OFF
237*4882a593Smuzhiyun : xtpg_get_bayer_phase(xtpg->formats[0].code);
238*4882a593Smuzhiyun xvip_write(&xtpg->xvip, XTPG_BAYER_PHASE, bayer_phase);
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun if (xtpg->vtmux_gpio)
241*4882a593Smuzhiyun gpiod_set_value_cansleep(xtpg->vtmux_gpio, !passthrough);
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun xvip_start(&xtpg->xvip);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun return 0;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
249*4882a593Smuzhiyun * V4L2 Subdevice Pad Operations
250*4882a593Smuzhiyun */
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun static struct v4l2_mbus_framefmt *
__xtpg_get_pad_format(struct xtpg_device * xtpg,struct v4l2_subdev_pad_config * cfg,unsigned int pad,u32 which)253*4882a593Smuzhiyun __xtpg_get_pad_format(struct xtpg_device *xtpg,
254*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
255*4882a593Smuzhiyun unsigned int pad, u32 which)
256*4882a593Smuzhiyun {
257*4882a593Smuzhiyun switch (which) {
258*4882a593Smuzhiyun case V4L2_SUBDEV_FORMAT_TRY:
259*4882a593Smuzhiyun return v4l2_subdev_get_try_format(&xtpg->xvip.subdev, cfg, pad);
260*4882a593Smuzhiyun case V4L2_SUBDEV_FORMAT_ACTIVE:
261*4882a593Smuzhiyun return &xtpg->formats[pad];
262*4882a593Smuzhiyun default:
263*4882a593Smuzhiyun return NULL;
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
xtpg_get_format(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)267*4882a593Smuzhiyun static int xtpg_get_format(struct v4l2_subdev *subdev,
268*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
269*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun struct xtpg_device *xtpg = to_tpg(subdev);
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun fmt->format = *__xtpg_get_pad_format(xtpg, cfg, fmt->pad, fmt->which);
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun return 0;
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun
xtpg_set_format(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)278*4882a593Smuzhiyun static int xtpg_set_format(struct v4l2_subdev *subdev,
279*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
280*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
281*4882a593Smuzhiyun {
282*4882a593Smuzhiyun struct xtpg_device *xtpg = to_tpg(subdev);
283*4882a593Smuzhiyun struct v4l2_mbus_framefmt *__format;
284*4882a593Smuzhiyun u32 bayer_phase;
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun __format = __xtpg_get_pad_format(xtpg, cfg, fmt->pad, fmt->which);
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun /* In two pads mode the source pad format is always identical to the
289*4882a593Smuzhiyun * sink pad format.
290*4882a593Smuzhiyun */
291*4882a593Smuzhiyun if (xtpg->npads == 2 && fmt->pad == 1) {
292*4882a593Smuzhiyun fmt->format = *__format;
293*4882a593Smuzhiyun return 0;
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun /* Bayer phase is configurable at runtime */
297*4882a593Smuzhiyun if (xtpg->bayer) {
298*4882a593Smuzhiyun bayer_phase = xtpg_get_bayer_phase(fmt->format.code);
299*4882a593Smuzhiyun if (bayer_phase != XTPG_BAYER_PHASE_OFF)
300*4882a593Smuzhiyun __format->code = fmt->format.code;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun xvip_set_format_size(__format, fmt);
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun fmt->format = *__format;
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun /* Propagate the format to the source pad. */
308*4882a593Smuzhiyun if (xtpg->npads == 2) {
309*4882a593Smuzhiyun __format = __xtpg_get_pad_format(xtpg, cfg, 1, fmt->which);
310*4882a593Smuzhiyun *__format = fmt->format;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun return 0;
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
317*4882a593Smuzhiyun * V4L2 Subdevice Operations
318*4882a593Smuzhiyun */
319*4882a593Smuzhiyun
xtpg_enum_frame_size(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)320*4882a593Smuzhiyun static int xtpg_enum_frame_size(struct v4l2_subdev *subdev,
321*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
322*4882a593Smuzhiyun struct v4l2_subdev_frame_size_enum *fse)
323*4882a593Smuzhiyun {
324*4882a593Smuzhiyun struct v4l2_mbus_framefmt *format;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun format = v4l2_subdev_get_try_format(subdev, cfg, fse->pad);
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun if (fse->index || fse->code != format->code)
329*4882a593Smuzhiyun return -EINVAL;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun /* Min / max values for pad 0 is always fixed in both one and two pads
332*4882a593Smuzhiyun * modes. In two pads mode, the source pad(= 1) size is identical to
333*4882a593Smuzhiyun * the sink pad size */
334*4882a593Smuzhiyun if (fse->pad == 0) {
335*4882a593Smuzhiyun fse->min_width = XVIP_MIN_WIDTH;
336*4882a593Smuzhiyun fse->max_width = XVIP_MAX_WIDTH;
337*4882a593Smuzhiyun fse->min_height = XVIP_MIN_HEIGHT;
338*4882a593Smuzhiyun fse->max_height = XVIP_MAX_HEIGHT;
339*4882a593Smuzhiyun } else {
340*4882a593Smuzhiyun fse->min_width = format->width;
341*4882a593Smuzhiyun fse->max_width = format->width;
342*4882a593Smuzhiyun fse->min_height = format->height;
343*4882a593Smuzhiyun fse->max_height = format->height;
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun return 0;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun
xtpg_open(struct v4l2_subdev * subdev,struct v4l2_subdev_fh * fh)349*4882a593Smuzhiyun static int xtpg_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun struct xtpg_device *xtpg = to_tpg(subdev);
352*4882a593Smuzhiyun struct v4l2_mbus_framefmt *format;
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun format = v4l2_subdev_get_try_format(subdev, fh->pad, 0);
355*4882a593Smuzhiyun *format = xtpg->default_format;
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun if (xtpg->npads == 2) {
358*4882a593Smuzhiyun format = v4l2_subdev_get_try_format(subdev, fh->pad, 1);
359*4882a593Smuzhiyun *format = xtpg->default_format;
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun return 0;
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun
xtpg_close(struct v4l2_subdev * subdev,struct v4l2_subdev_fh * fh)365*4882a593Smuzhiyun static int xtpg_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
366*4882a593Smuzhiyun {
367*4882a593Smuzhiyun return 0;
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun
xtpg_s_ctrl(struct v4l2_ctrl * ctrl)370*4882a593Smuzhiyun static int xtpg_s_ctrl(struct v4l2_ctrl *ctrl)
371*4882a593Smuzhiyun {
372*4882a593Smuzhiyun struct xtpg_device *xtpg = container_of(ctrl->handler,
373*4882a593Smuzhiyun struct xtpg_device,
374*4882a593Smuzhiyun ctrl_handler);
375*4882a593Smuzhiyun switch (ctrl->id) {
376*4882a593Smuzhiyun case V4L2_CID_TEST_PATTERN:
377*4882a593Smuzhiyun xvip_clr_and_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
378*4882a593Smuzhiyun XTPG_PATTERN_MASK, ctrl->val);
379*4882a593Smuzhiyun return 0;
380*4882a593Smuzhiyun case V4L2_CID_XILINX_TPG_CROSS_HAIRS:
381*4882a593Smuzhiyun xvip_clr_or_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
382*4882a593Smuzhiyun XTPG_PATTERN_CONTROL_CROSS_HAIRS, ctrl->val);
383*4882a593Smuzhiyun return 0;
384*4882a593Smuzhiyun case V4L2_CID_XILINX_TPG_MOVING_BOX:
385*4882a593Smuzhiyun xvip_clr_or_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
386*4882a593Smuzhiyun XTPG_PATTERN_CONTROL_MOVING_BOX, ctrl->val);
387*4882a593Smuzhiyun return 0;
388*4882a593Smuzhiyun case V4L2_CID_XILINX_TPG_COLOR_MASK:
389*4882a593Smuzhiyun xvip_clr_and_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
390*4882a593Smuzhiyun XTPG_PATTERN_CONTROL_COLOR_MASK_MASK,
391*4882a593Smuzhiyun ctrl->val <<
392*4882a593Smuzhiyun XTPG_PATTERN_CONTROL_COLOR_MASK_SHIFT);
393*4882a593Smuzhiyun return 0;
394*4882a593Smuzhiyun case V4L2_CID_XILINX_TPG_STUCK_PIXEL:
395*4882a593Smuzhiyun xvip_clr_or_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
396*4882a593Smuzhiyun XTPG_PATTERN_CONTROL_STUCK_PIXEL, ctrl->val);
397*4882a593Smuzhiyun return 0;
398*4882a593Smuzhiyun case V4L2_CID_XILINX_TPG_NOISE:
399*4882a593Smuzhiyun xvip_clr_or_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
400*4882a593Smuzhiyun XTPG_PATTERN_CONTROL_NOISE, ctrl->val);
401*4882a593Smuzhiyun return 0;
402*4882a593Smuzhiyun case V4L2_CID_XILINX_TPG_MOTION:
403*4882a593Smuzhiyun xvip_clr_or_set(&xtpg->xvip, XTPG_PATTERN_CONTROL,
404*4882a593Smuzhiyun XTPG_PATTERN_CONTROL_MOTION, ctrl->val);
405*4882a593Smuzhiyun return 0;
406*4882a593Smuzhiyun case V4L2_CID_XILINX_TPG_MOTION_SPEED:
407*4882a593Smuzhiyun xvip_write(&xtpg->xvip, XTPG_MOTION_SPEED, ctrl->val);
408*4882a593Smuzhiyun return 0;
409*4882a593Smuzhiyun case V4L2_CID_XILINX_TPG_CROSS_HAIR_ROW:
410*4882a593Smuzhiyun xvip_clr_and_set(&xtpg->xvip, XTPG_CROSS_HAIRS,
411*4882a593Smuzhiyun XTPG_CROSS_HAIRS_ROW_MASK,
412*4882a593Smuzhiyun ctrl->val << XTPG_CROSS_HAIRS_ROW_SHIFT);
413*4882a593Smuzhiyun return 0;
414*4882a593Smuzhiyun case V4L2_CID_XILINX_TPG_CROSS_HAIR_COLUMN:
415*4882a593Smuzhiyun xvip_clr_and_set(&xtpg->xvip, XTPG_CROSS_HAIRS,
416*4882a593Smuzhiyun XTPG_CROSS_HAIRS_COLUMN_MASK,
417*4882a593Smuzhiyun ctrl->val << XTPG_CROSS_HAIRS_COLUMN_SHIFT);
418*4882a593Smuzhiyun return 0;
419*4882a593Smuzhiyun case V4L2_CID_XILINX_TPG_ZPLATE_HOR_START:
420*4882a593Smuzhiyun xvip_clr_and_set(&xtpg->xvip, XTPG_ZPLATE_HOR_CONTROL,
421*4882a593Smuzhiyun XTPG_ZPLATE_START_MASK,
422*4882a593Smuzhiyun ctrl->val << XTPG_ZPLATE_START_SHIFT);
423*4882a593Smuzhiyun return 0;
424*4882a593Smuzhiyun case V4L2_CID_XILINX_TPG_ZPLATE_HOR_SPEED:
425*4882a593Smuzhiyun xvip_clr_and_set(&xtpg->xvip, XTPG_ZPLATE_HOR_CONTROL,
426*4882a593Smuzhiyun XTPG_ZPLATE_SPEED_MASK,
427*4882a593Smuzhiyun ctrl->val << XTPG_ZPLATE_SPEED_SHIFT);
428*4882a593Smuzhiyun return 0;
429*4882a593Smuzhiyun case V4L2_CID_XILINX_TPG_ZPLATE_VER_START:
430*4882a593Smuzhiyun xvip_clr_and_set(&xtpg->xvip, XTPG_ZPLATE_VER_CONTROL,
431*4882a593Smuzhiyun XTPG_ZPLATE_START_MASK,
432*4882a593Smuzhiyun ctrl->val << XTPG_ZPLATE_START_SHIFT);
433*4882a593Smuzhiyun return 0;
434*4882a593Smuzhiyun case V4L2_CID_XILINX_TPG_ZPLATE_VER_SPEED:
435*4882a593Smuzhiyun xvip_clr_and_set(&xtpg->xvip, XTPG_ZPLATE_VER_CONTROL,
436*4882a593Smuzhiyun XTPG_ZPLATE_SPEED_MASK,
437*4882a593Smuzhiyun ctrl->val << XTPG_ZPLATE_SPEED_SHIFT);
438*4882a593Smuzhiyun return 0;
439*4882a593Smuzhiyun case V4L2_CID_XILINX_TPG_BOX_SIZE:
440*4882a593Smuzhiyun xvip_write(&xtpg->xvip, XTPG_BOX_SIZE, ctrl->val);
441*4882a593Smuzhiyun return 0;
442*4882a593Smuzhiyun case V4L2_CID_XILINX_TPG_BOX_COLOR:
443*4882a593Smuzhiyun xvip_write(&xtpg->xvip, XTPG_BOX_COLOR, ctrl->val);
444*4882a593Smuzhiyun return 0;
445*4882a593Smuzhiyun case V4L2_CID_XILINX_TPG_STUCK_PIXEL_THRESH:
446*4882a593Smuzhiyun xvip_write(&xtpg->xvip, XTPG_STUCK_PIXEL_THRESH, ctrl->val);
447*4882a593Smuzhiyun return 0;
448*4882a593Smuzhiyun case V4L2_CID_XILINX_TPG_NOISE_GAIN:
449*4882a593Smuzhiyun xvip_write(&xtpg->xvip, XTPG_NOISE_GAIN, ctrl->val);
450*4882a593Smuzhiyun return 0;
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun return 0;
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun static const struct v4l2_ctrl_ops xtpg_ctrl_ops = {
457*4882a593Smuzhiyun .s_ctrl = xtpg_s_ctrl,
458*4882a593Smuzhiyun };
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops xtpg_core_ops = {
461*4882a593Smuzhiyun };
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops xtpg_video_ops = {
464*4882a593Smuzhiyun .s_stream = xtpg_s_stream,
465*4882a593Smuzhiyun };
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops xtpg_pad_ops = {
468*4882a593Smuzhiyun .enum_mbus_code = xvip_enum_mbus_code,
469*4882a593Smuzhiyun .enum_frame_size = xtpg_enum_frame_size,
470*4882a593Smuzhiyun .get_fmt = xtpg_get_format,
471*4882a593Smuzhiyun .set_fmt = xtpg_set_format,
472*4882a593Smuzhiyun };
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun static const struct v4l2_subdev_ops xtpg_ops = {
475*4882a593Smuzhiyun .core = &xtpg_core_ops,
476*4882a593Smuzhiyun .video = &xtpg_video_ops,
477*4882a593Smuzhiyun .pad = &xtpg_pad_ops,
478*4882a593Smuzhiyun };
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops xtpg_internal_ops = {
481*4882a593Smuzhiyun .open = xtpg_open,
482*4882a593Smuzhiyun .close = xtpg_close,
483*4882a593Smuzhiyun };
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun /*
486*4882a593Smuzhiyun * Control Config
487*4882a593Smuzhiyun */
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun static const char *const xtpg_pattern_strings[] = {
490*4882a593Smuzhiyun "Passthrough",
491*4882a593Smuzhiyun "Horizontal Ramp",
492*4882a593Smuzhiyun "Vertical Ramp",
493*4882a593Smuzhiyun "Temporal Ramp",
494*4882a593Smuzhiyun "Solid Red",
495*4882a593Smuzhiyun "Solid Green",
496*4882a593Smuzhiyun "Solid Blue",
497*4882a593Smuzhiyun "Solid Black",
498*4882a593Smuzhiyun "Solid White",
499*4882a593Smuzhiyun "Color Bars",
500*4882a593Smuzhiyun "Zone Plate",
501*4882a593Smuzhiyun "Tartan Color Bars",
502*4882a593Smuzhiyun "Cross Hatch",
503*4882a593Smuzhiyun "None",
504*4882a593Smuzhiyun "Vertical/Horizontal Ramps",
505*4882a593Smuzhiyun "Black/White Checker Board",
506*4882a593Smuzhiyun };
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun static struct v4l2_ctrl_config xtpg_ctrls[] = {
509*4882a593Smuzhiyun {
510*4882a593Smuzhiyun .ops = &xtpg_ctrl_ops,
511*4882a593Smuzhiyun .id = V4L2_CID_XILINX_TPG_CROSS_HAIRS,
512*4882a593Smuzhiyun .name = "Test Pattern: Cross Hairs",
513*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_BOOLEAN,
514*4882a593Smuzhiyun .min = false,
515*4882a593Smuzhiyun .max = true,
516*4882a593Smuzhiyun .step = 1,
517*4882a593Smuzhiyun .def = 0,
518*4882a593Smuzhiyun }, {
519*4882a593Smuzhiyun .ops = &xtpg_ctrl_ops,
520*4882a593Smuzhiyun .id = V4L2_CID_XILINX_TPG_MOVING_BOX,
521*4882a593Smuzhiyun .name = "Test Pattern: Moving Box",
522*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_BOOLEAN,
523*4882a593Smuzhiyun .min = false,
524*4882a593Smuzhiyun .max = true,
525*4882a593Smuzhiyun .step = 1,
526*4882a593Smuzhiyun .def = 0,
527*4882a593Smuzhiyun }, {
528*4882a593Smuzhiyun .ops = &xtpg_ctrl_ops,
529*4882a593Smuzhiyun .id = V4L2_CID_XILINX_TPG_COLOR_MASK,
530*4882a593Smuzhiyun .name = "Test Pattern: Color Mask",
531*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_BITMASK,
532*4882a593Smuzhiyun .min = 0,
533*4882a593Smuzhiyun .max = 0xf,
534*4882a593Smuzhiyun .def = 0,
535*4882a593Smuzhiyun }, {
536*4882a593Smuzhiyun .ops = &xtpg_ctrl_ops,
537*4882a593Smuzhiyun .id = V4L2_CID_XILINX_TPG_STUCK_PIXEL,
538*4882a593Smuzhiyun .name = "Test Pattern: Stuck Pixel",
539*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_BOOLEAN,
540*4882a593Smuzhiyun .min = false,
541*4882a593Smuzhiyun .max = true,
542*4882a593Smuzhiyun .step = 1,
543*4882a593Smuzhiyun .def = 0,
544*4882a593Smuzhiyun }, {
545*4882a593Smuzhiyun .ops = &xtpg_ctrl_ops,
546*4882a593Smuzhiyun .id = V4L2_CID_XILINX_TPG_NOISE,
547*4882a593Smuzhiyun .name = "Test Pattern: Noise",
548*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_BOOLEAN,
549*4882a593Smuzhiyun .min = false,
550*4882a593Smuzhiyun .max = true,
551*4882a593Smuzhiyun .step = 1,
552*4882a593Smuzhiyun .def = 0,
553*4882a593Smuzhiyun }, {
554*4882a593Smuzhiyun .ops = &xtpg_ctrl_ops,
555*4882a593Smuzhiyun .id = V4L2_CID_XILINX_TPG_MOTION,
556*4882a593Smuzhiyun .name = "Test Pattern: Motion",
557*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_BOOLEAN,
558*4882a593Smuzhiyun .min = false,
559*4882a593Smuzhiyun .max = true,
560*4882a593Smuzhiyun .step = 1,
561*4882a593Smuzhiyun .def = 0,
562*4882a593Smuzhiyun }, {
563*4882a593Smuzhiyun .ops = &xtpg_ctrl_ops,
564*4882a593Smuzhiyun .id = V4L2_CID_XILINX_TPG_MOTION_SPEED,
565*4882a593Smuzhiyun .name = "Test Pattern: Motion Speed",
566*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_INTEGER,
567*4882a593Smuzhiyun .min = 0,
568*4882a593Smuzhiyun .max = (1 << 8) - 1,
569*4882a593Smuzhiyun .step = 1,
570*4882a593Smuzhiyun .def = 4,
571*4882a593Smuzhiyun .flags = V4L2_CTRL_FLAG_SLIDER,
572*4882a593Smuzhiyun }, {
573*4882a593Smuzhiyun .ops = &xtpg_ctrl_ops,
574*4882a593Smuzhiyun .id = V4L2_CID_XILINX_TPG_CROSS_HAIR_ROW,
575*4882a593Smuzhiyun .name = "Test Pattern: Cross Hairs Row",
576*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_INTEGER,
577*4882a593Smuzhiyun .min = 0,
578*4882a593Smuzhiyun .max = (1 << 12) - 1,
579*4882a593Smuzhiyun .step = 1,
580*4882a593Smuzhiyun .def = 0x64,
581*4882a593Smuzhiyun .flags = V4L2_CTRL_FLAG_SLIDER,
582*4882a593Smuzhiyun }, {
583*4882a593Smuzhiyun .ops = &xtpg_ctrl_ops,
584*4882a593Smuzhiyun .id = V4L2_CID_XILINX_TPG_CROSS_HAIR_COLUMN,
585*4882a593Smuzhiyun .name = "Test Pattern: Cross Hairs Column",
586*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_INTEGER,
587*4882a593Smuzhiyun .min = 0,
588*4882a593Smuzhiyun .max = (1 << 12) - 1,
589*4882a593Smuzhiyun .step = 1,
590*4882a593Smuzhiyun .def = 0x64,
591*4882a593Smuzhiyun .flags = V4L2_CTRL_FLAG_SLIDER,
592*4882a593Smuzhiyun }, {
593*4882a593Smuzhiyun .ops = &xtpg_ctrl_ops,
594*4882a593Smuzhiyun .id = V4L2_CID_XILINX_TPG_ZPLATE_HOR_START,
595*4882a593Smuzhiyun .name = "Test Pattern: Zplate Horizontal Start Pos",
596*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_INTEGER,
597*4882a593Smuzhiyun .min = 0,
598*4882a593Smuzhiyun .max = (1 << 16) - 1,
599*4882a593Smuzhiyun .step = 1,
600*4882a593Smuzhiyun .def = 0x1e,
601*4882a593Smuzhiyun .flags = V4L2_CTRL_FLAG_SLIDER,
602*4882a593Smuzhiyun }, {
603*4882a593Smuzhiyun .ops = &xtpg_ctrl_ops,
604*4882a593Smuzhiyun .id = V4L2_CID_XILINX_TPG_ZPLATE_HOR_SPEED,
605*4882a593Smuzhiyun .name = "Test Pattern: Zplate Horizontal Speed",
606*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_INTEGER,
607*4882a593Smuzhiyun .min = 0,
608*4882a593Smuzhiyun .max = (1 << 16) - 1,
609*4882a593Smuzhiyun .step = 1,
610*4882a593Smuzhiyun .def = 0,
611*4882a593Smuzhiyun .flags = V4L2_CTRL_FLAG_SLIDER,
612*4882a593Smuzhiyun }, {
613*4882a593Smuzhiyun .ops = &xtpg_ctrl_ops,
614*4882a593Smuzhiyun .id = V4L2_CID_XILINX_TPG_ZPLATE_VER_START,
615*4882a593Smuzhiyun .name = "Test Pattern: Zplate Vertical Start Pos",
616*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_INTEGER,
617*4882a593Smuzhiyun .min = 0,
618*4882a593Smuzhiyun .max = (1 << 16) - 1,
619*4882a593Smuzhiyun .step = 1,
620*4882a593Smuzhiyun .def = 1,
621*4882a593Smuzhiyun .flags = V4L2_CTRL_FLAG_SLIDER,
622*4882a593Smuzhiyun }, {
623*4882a593Smuzhiyun .ops = &xtpg_ctrl_ops,
624*4882a593Smuzhiyun .id = V4L2_CID_XILINX_TPG_ZPLATE_VER_SPEED,
625*4882a593Smuzhiyun .name = "Test Pattern: Zplate Vertical Speed",
626*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_INTEGER,
627*4882a593Smuzhiyun .min = 0,
628*4882a593Smuzhiyun .max = (1 << 16) - 1,
629*4882a593Smuzhiyun .step = 1,
630*4882a593Smuzhiyun .def = 0,
631*4882a593Smuzhiyun .flags = V4L2_CTRL_FLAG_SLIDER,
632*4882a593Smuzhiyun }, {
633*4882a593Smuzhiyun .ops = &xtpg_ctrl_ops,
634*4882a593Smuzhiyun .id = V4L2_CID_XILINX_TPG_BOX_SIZE,
635*4882a593Smuzhiyun .name = "Test Pattern: Box Size",
636*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_INTEGER,
637*4882a593Smuzhiyun .min = 0,
638*4882a593Smuzhiyun .max = (1 << 12) - 1,
639*4882a593Smuzhiyun .step = 1,
640*4882a593Smuzhiyun .def = 0x32,
641*4882a593Smuzhiyun .flags = V4L2_CTRL_FLAG_SLIDER,
642*4882a593Smuzhiyun }, {
643*4882a593Smuzhiyun .ops = &xtpg_ctrl_ops,
644*4882a593Smuzhiyun .id = V4L2_CID_XILINX_TPG_BOX_COLOR,
645*4882a593Smuzhiyun .name = "Test Pattern: Box Color(RGB)",
646*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_INTEGER,
647*4882a593Smuzhiyun .min = 0,
648*4882a593Smuzhiyun .max = (1 << 24) - 1,
649*4882a593Smuzhiyun .step = 1,
650*4882a593Smuzhiyun .def = 0,
651*4882a593Smuzhiyun }, {
652*4882a593Smuzhiyun .ops = &xtpg_ctrl_ops,
653*4882a593Smuzhiyun .id = V4L2_CID_XILINX_TPG_STUCK_PIXEL_THRESH,
654*4882a593Smuzhiyun .name = "Test Pattern: Stuck Pixel threshold",
655*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_INTEGER,
656*4882a593Smuzhiyun .min = 0,
657*4882a593Smuzhiyun .max = (1 << 16) - 1,
658*4882a593Smuzhiyun .step = 1,
659*4882a593Smuzhiyun .def = 0,
660*4882a593Smuzhiyun .flags = V4L2_CTRL_FLAG_SLIDER,
661*4882a593Smuzhiyun }, {
662*4882a593Smuzhiyun .ops = &xtpg_ctrl_ops,
663*4882a593Smuzhiyun .id = V4L2_CID_XILINX_TPG_NOISE_GAIN,
664*4882a593Smuzhiyun .name = "Test Pattern: Noise Gain",
665*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_INTEGER,
666*4882a593Smuzhiyun .min = 0,
667*4882a593Smuzhiyun .max = (1 << 8) - 1,
668*4882a593Smuzhiyun .step = 1,
669*4882a593Smuzhiyun .def = 0,
670*4882a593Smuzhiyun .flags = V4L2_CTRL_FLAG_SLIDER,
671*4882a593Smuzhiyun },
672*4882a593Smuzhiyun };
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
675*4882a593Smuzhiyun * Media Operations
676*4882a593Smuzhiyun */
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun static const struct media_entity_operations xtpg_media_ops = {
679*4882a593Smuzhiyun .link_validate = v4l2_subdev_link_validate,
680*4882a593Smuzhiyun };
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
683*4882a593Smuzhiyun * Power Management
684*4882a593Smuzhiyun */
685*4882a593Smuzhiyun
xtpg_pm_suspend(struct device * dev)686*4882a593Smuzhiyun static int __maybe_unused xtpg_pm_suspend(struct device *dev)
687*4882a593Smuzhiyun {
688*4882a593Smuzhiyun struct xtpg_device *xtpg = dev_get_drvdata(dev);
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun xvip_suspend(&xtpg->xvip);
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun return 0;
693*4882a593Smuzhiyun }
694*4882a593Smuzhiyun
xtpg_pm_resume(struct device * dev)695*4882a593Smuzhiyun static int __maybe_unused xtpg_pm_resume(struct device *dev)
696*4882a593Smuzhiyun {
697*4882a593Smuzhiyun struct xtpg_device *xtpg = dev_get_drvdata(dev);
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun xvip_resume(&xtpg->xvip);
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun return 0;
702*4882a593Smuzhiyun }
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
705*4882a593Smuzhiyun * Platform Device Driver
706*4882a593Smuzhiyun */
707*4882a593Smuzhiyun
xtpg_parse_of(struct xtpg_device * xtpg)708*4882a593Smuzhiyun static int xtpg_parse_of(struct xtpg_device *xtpg)
709*4882a593Smuzhiyun {
710*4882a593Smuzhiyun struct device *dev = xtpg->xvip.dev;
711*4882a593Smuzhiyun struct device_node *node = xtpg->xvip.dev->of_node;
712*4882a593Smuzhiyun struct device_node *ports;
713*4882a593Smuzhiyun struct device_node *port;
714*4882a593Smuzhiyun unsigned int nports = 0;
715*4882a593Smuzhiyun bool has_endpoint = false;
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun ports = of_get_child_by_name(node, "ports");
718*4882a593Smuzhiyun if (ports == NULL)
719*4882a593Smuzhiyun ports = node;
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun for_each_child_of_node(ports, port) {
722*4882a593Smuzhiyun const struct xvip_video_format *format;
723*4882a593Smuzhiyun struct device_node *endpoint;
724*4882a593Smuzhiyun
725*4882a593Smuzhiyun if (!of_node_name_eq(port, "port"))
726*4882a593Smuzhiyun continue;
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun format = xvip_of_get_format(port);
729*4882a593Smuzhiyun if (IS_ERR(format)) {
730*4882a593Smuzhiyun dev_err(dev, "invalid format in DT");
731*4882a593Smuzhiyun of_node_put(port);
732*4882a593Smuzhiyun return PTR_ERR(format);
733*4882a593Smuzhiyun }
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun /* Get and check the format description */
736*4882a593Smuzhiyun if (!xtpg->vip_format) {
737*4882a593Smuzhiyun xtpg->vip_format = format;
738*4882a593Smuzhiyun } else if (xtpg->vip_format != format) {
739*4882a593Smuzhiyun dev_err(dev, "in/out format mismatch in DT");
740*4882a593Smuzhiyun of_node_put(port);
741*4882a593Smuzhiyun return -EINVAL;
742*4882a593Smuzhiyun }
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun if (nports == 0) {
745*4882a593Smuzhiyun endpoint = of_get_next_child(port, NULL);
746*4882a593Smuzhiyun if (endpoint)
747*4882a593Smuzhiyun has_endpoint = true;
748*4882a593Smuzhiyun of_node_put(endpoint);
749*4882a593Smuzhiyun }
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun /* Count the number of ports. */
752*4882a593Smuzhiyun nports++;
753*4882a593Smuzhiyun }
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun if (nports != 1 && nports != 2) {
756*4882a593Smuzhiyun dev_err(dev, "invalid number of ports %u\n", nports);
757*4882a593Smuzhiyun return -EINVAL;
758*4882a593Smuzhiyun }
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun xtpg->npads = nports;
761*4882a593Smuzhiyun if (nports == 2 && has_endpoint)
762*4882a593Smuzhiyun xtpg->has_input = true;
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun return 0;
765*4882a593Smuzhiyun }
766*4882a593Smuzhiyun
xtpg_probe(struct platform_device * pdev)767*4882a593Smuzhiyun static int xtpg_probe(struct platform_device *pdev)
768*4882a593Smuzhiyun {
769*4882a593Smuzhiyun struct v4l2_subdev *subdev;
770*4882a593Smuzhiyun struct xtpg_device *xtpg;
771*4882a593Smuzhiyun u32 i, bayer_phase;
772*4882a593Smuzhiyun int ret;
773*4882a593Smuzhiyun
774*4882a593Smuzhiyun xtpg = devm_kzalloc(&pdev->dev, sizeof(*xtpg), GFP_KERNEL);
775*4882a593Smuzhiyun if (!xtpg)
776*4882a593Smuzhiyun return -ENOMEM;
777*4882a593Smuzhiyun
778*4882a593Smuzhiyun xtpg->xvip.dev = &pdev->dev;
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun ret = xtpg_parse_of(xtpg);
781*4882a593Smuzhiyun if (ret < 0)
782*4882a593Smuzhiyun return ret;
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun ret = xvip_init_resources(&xtpg->xvip);
785*4882a593Smuzhiyun if (ret < 0)
786*4882a593Smuzhiyun return ret;
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun xtpg->vtmux_gpio = devm_gpiod_get_optional(&pdev->dev, "timing",
789*4882a593Smuzhiyun GPIOD_OUT_HIGH);
790*4882a593Smuzhiyun if (IS_ERR(xtpg->vtmux_gpio)) {
791*4882a593Smuzhiyun ret = PTR_ERR(xtpg->vtmux_gpio);
792*4882a593Smuzhiyun goto error_resource;
793*4882a593Smuzhiyun }
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun xtpg->vtc = xvtc_of_get(pdev->dev.of_node);
796*4882a593Smuzhiyun if (IS_ERR(xtpg->vtc)) {
797*4882a593Smuzhiyun ret = PTR_ERR(xtpg->vtc);
798*4882a593Smuzhiyun goto error_resource;
799*4882a593Smuzhiyun }
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun /* Reset and initialize the core */
802*4882a593Smuzhiyun xvip_reset(&xtpg->xvip);
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun /* Initialize V4L2 subdevice and media entity. Pad numbers depend on the
805*4882a593Smuzhiyun * number of pads.
806*4882a593Smuzhiyun */
807*4882a593Smuzhiyun if (xtpg->npads == 2) {
808*4882a593Smuzhiyun xtpg->pads[0].flags = MEDIA_PAD_FL_SINK;
809*4882a593Smuzhiyun xtpg->pads[1].flags = MEDIA_PAD_FL_SOURCE;
810*4882a593Smuzhiyun } else {
811*4882a593Smuzhiyun xtpg->pads[0].flags = MEDIA_PAD_FL_SOURCE;
812*4882a593Smuzhiyun }
813*4882a593Smuzhiyun
814*4882a593Smuzhiyun /* Initialize the default format */
815*4882a593Smuzhiyun xtpg->default_format.code = xtpg->vip_format->code;
816*4882a593Smuzhiyun xtpg->default_format.field = V4L2_FIELD_NONE;
817*4882a593Smuzhiyun xtpg->default_format.colorspace = V4L2_COLORSPACE_SRGB;
818*4882a593Smuzhiyun xvip_get_frame_size(&xtpg->xvip, &xtpg->default_format);
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun bayer_phase = xtpg_get_bayer_phase(xtpg->vip_format->code);
821*4882a593Smuzhiyun if (bayer_phase != XTPG_BAYER_PHASE_OFF)
822*4882a593Smuzhiyun xtpg->bayer = true;
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun xtpg->formats[0] = xtpg->default_format;
825*4882a593Smuzhiyun if (xtpg->npads == 2)
826*4882a593Smuzhiyun xtpg->formats[1] = xtpg->default_format;
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun /* Initialize V4L2 subdevice and media entity */
829*4882a593Smuzhiyun subdev = &xtpg->xvip.subdev;
830*4882a593Smuzhiyun v4l2_subdev_init(subdev, &xtpg_ops);
831*4882a593Smuzhiyun subdev->dev = &pdev->dev;
832*4882a593Smuzhiyun subdev->internal_ops = &xtpg_internal_ops;
833*4882a593Smuzhiyun strscpy(subdev->name, dev_name(&pdev->dev), sizeof(subdev->name));
834*4882a593Smuzhiyun v4l2_set_subdevdata(subdev, xtpg);
835*4882a593Smuzhiyun subdev->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
836*4882a593Smuzhiyun subdev->entity.ops = &xtpg_media_ops;
837*4882a593Smuzhiyun
838*4882a593Smuzhiyun ret = media_entity_pads_init(&subdev->entity, xtpg->npads, xtpg->pads);
839*4882a593Smuzhiyun if (ret < 0)
840*4882a593Smuzhiyun goto error;
841*4882a593Smuzhiyun
842*4882a593Smuzhiyun v4l2_ctrl_handler_init(&xtpg->ctrl_handler, 3 + ARRAY_SIZE(xtpg_ctrls));
843*4882a593Smuzhiyun
844*4882a593Smuzhiyun xtpg->vblank = v4l2_ctrl_new_std(&xtpg->ctrl_handler, &xtpg_ctrl_ops,
845*4882a593Smuzhiyun V4L2_CID_VBLANK, XTPG_MIN_VBLANK,
846*4882a593Smuzhiyun XTPG_MAX_VBLANK, 1, 100);
847*4882a593Smuzhiyun xtpg->hblank = v4l2_ctrl_new_std(&xtpg->ctrl_handler, &xtpg_ctrl_ops,
848*4882a593Smuzhiyun V4L2_CID_HBLANK, XTPG_MIN_HBLANK,
849*4882a593Smuzhiyun XTPG_MAX_HBLANK, 1, 100);
850*4882a593Smuzhiyun xtpg->pattern = v4l2_ctrl_new_std_menu_items(&xtpg->ctrl_handler,
851*4882a593Smuzhiyun &xtpg_ctrl_ops, V4L2_CID_TEST_PATTERN,
852*4882a593Smuzhiyun ARRAY_SIZE(xtpg_pattern_strings) - 1,
853*4882a593Smuzhiyun 1, 9, xtpg_pattern_strings);
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(xtpg_ctrls); i++)
856*4882a593Smuzhiyun v4l2_ctrl_new_custom(&xtpg->ctrl_handler, &xtpg_ctrls[i], NULL);
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun if (xtpg->ctrl_handler.error) {
859*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to add controls\n");
860*4882a593Smuzhiyun ret = xtpg->ctrl_handler.error;
861*4882a593Smuzhiyun goto error;
862*4882a593Smuzhiyun }
863*4882a593Smuzhiyun subdev->ctrl_handler = &xtpg->ctrl_handler;
864*4882a593Smuzhiyun
865*4882a593Smuzhiyun xtpg_update_pattern_control(xtpg, true, true);
866*4882a593Smuzhiyun
867*4882a593Smuzhiyun ret = v4l2_ctrl_handler_setup(&xtpg->ctrl_handler);
868*4882a593Smuzhiyun if (ret < 0) {
869*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to set controls\n");
870*4882a593Smuzhiyun goto error;
871*4882a593Smuzhiyun }
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun platform_set_drvdata(pdev, xtpg);
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun xvip_print_version(&xtpg->xvip);
876*4882a593Smuzhiyun
877*4882a593Smuzhiyun ret = v4l2_async_register_subdev(subdev);
878*4882a593Smuzhiyun if (ret < 0) {
879*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to register subdev\n");
880*4882a593Smuzhiyun goto error;
881*4882a593Smuzhiyun }
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun return 0;
884*4882a593Smuzhiyun
885*4882a593Smuzhiyun error:
886*4882a593Smuzhiyun v4l2_ctrl_handler_free(&xtpg->ctrl_handler);
887*4882a593Smuzhiyun media_entity_cleanup(&subdev->entity);
888*4882a593Smuzhiyun xvtc_put(xtpg->vtc);
889*4882a593Smuzhiyun error_resource:
890*4882a593Smuzhiyun xvip_cleanup_resources(&xtpg->xvip);
891*4882a593Smuzhiyun return ret;
892*4882a593Smuzhiyun }
893*4882a593Smuzhiyun
xtpg_remove(struct platform_device * pdev)894*4882a593Smuzhiyun static int xtpg_remove(struct platform_device *pdev)
895*4882a593Smuzhiyun {
896*4882a593Smuzhiyun struct xtpg_device *xtpg = platform_get_drvdata(pdev);
897*4882a593Smuzhiyun struct v4l2_subdev *subdev = &xtpg->xvip.subdev;
898*4882a593Smuzhiyun
899*4882a593Smuzhiyun v4l2_async_unregister_subdev(subdev);
900*4882a593Smuzhiyun v4l2_ctrl_handler_free(&xtpg->ctrl_handler);
901*4882a593Smuzhiyun media_entity_cleanup(&subdev->entity);
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun xvip_cleanup_resources(&xtpg->xvip);
904*4882a593Smuzhiyun
905*4882a593Smuzhiyun return 0;
906*4882a593Smuzhiyun }
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(xtpg_pm_ops, xtpg_pm_suspend, xtpg_pm_resume);
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun static const struct of_device_id xtpg_of_id_table[] = {
911*4882a593Smuzhiyun { .compatible = "xlnx,v-tpg-5.0" },
912*4882a593Smuzhiyun { }
913*4882a593Smuzhiyun };
914*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, xtpg_of_id_table);
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun static struct platform_driver xtpg_driver = {
917*4882a593Smuzhiyun .driver = {
918*4882a593Smuzhiyun .name = "xilinx-tpg",
919*4882a593Smuzhiyun .pm = &xtpg_pm_ops,
920*4882a593Smuzhiyun .of_match_table = xtpg_of_id_table,
921*4882a593Smuzhiyun },
922*4882a593Smuzhiyun .probe = xtpg_probe,
923*4882a593Smuzhiyun .remove = xtpg_remove,
924*4882a593Smuzhiyun };
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun module_platform_driver(xtpg_driver);
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
929*4882a593Smuzhiyun MODULE_DESCRIPTION("Xilinx Test Pattern Generator Driver");
930*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
931