1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Xilinx Video DMA 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013-2015 Ideas on Board 6*4882a593Smuzhiyun * Copyright (C) 2013-2015 Xilinx, Inc. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> 9*4882a593Smuzhiyun * Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __XILINX_VIP_DMA_H__ 13*4882a593Smuzhiyun #define __XILINX_VIP_DMA_H__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <linux/dmaengine.h> 16*4882a593Smuzhiyun #include <linux/mutex.h> 17*4882a593Smuzhiyun #include <linux/spinlock.h> 18*4882a593Smuzhiyun #include <linux/videodev2.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include <media/media-entity.h> 21*4882a593Smuzhiyun #include <media/v4l2-dev.h> 22*4882a593Smuzhiyun #include <media/videobuf2-v4l2.h> 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct dma_chan; 25*4882a593Smuzhiyun struct xvip_composite_device; 26*4882a593Smuzhiyun struct xvip_video_format; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /** 29*4882a593Smuzhiyun * struct xvip_pipeline - Xilinx Video IP pipeline structure 30*4882a593Smuzhiyun * @pipe: media pipeline 31*4882a593Smuzhiyun * @lock: protects the pipeline @stream_count 32*4882a593Smuzhiyun * @use_count: number of DMA engines using the pipeline 33*4882a593Smuzhiyun * @stream_count: number of DMA engines currently streaming 34*4882a593Smuzhiyun * @num_dmas: number of DMA engines in the pipeline 35*4882a593Smuzhiyun * @output: DMA engine at the output of the pipeline 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun struct xvip_pipeline { 38*4882a593Smuzhiyun struct media_pipeline pipe; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun struct mutex lock; 41*4882a593Smuzhiyun unsigned int use_count; 42*4882a593Smuzhiyun unsigned int stream_count; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun unsigned int num_dmas; 45*4882a593Smuzhiyun struct xvip_dma *output; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun to_xvip_pipeline(struct media_entity * e)48*4882a593Smuzhiyunstatic inline struct xvip_pipeline *to_xvip_pipeline(struct media_entity *e) 49*4882a593Smuzhiyun { 50*4882a593Smuzhiyun return container_of(e->pipe, struct xvip_pipeline, pipe); 51*4882a593Smuzhiyun } 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /** 54*4882a593Smuzhiyun * struct xvip_dma - Video DMA channel 55*4882a593Smuzhiyun * @list: list entry in a composite device dmas list 56*4882a593Smuzhiyun * @video: V4L2 video device associated with the DMA channel 57*4882a593Smuzhiyun * @pad: media pad for the video device entity 58*4882a593Smuzhiyun * @xdev: composite device the DMA channel belongs to 59*4882a593Smuzhiyun * @pipe: pipeline belonging to the DMA channel 60*4882a593Smuzhiyun * @port: composite device DT node port number for the DMA channel 61*4882a593Smuzhiyun * @lock: protects the @format, @fmtinfo and @queue fields 62*4882a593Smuzhiyun * @format: active V4L2 pixel format 63*4882a593Smuzhiyun * @fmtinfo: format information corresponding to the active @format 64*4882a593Smuzhiyun * @queue: vb2 buffers queue 65*4882a593Smuzhiyun * @sequence: V4L2 buffers sequence number 66*4882a593Smuzhiyun * @queued_bufs: list of queued buffers 67*4882a593Smuzhiyun * @queued_lock: protects the buf_queued list 68*4882a593Smuzhiyun * @dma: DMA engine channel 69*4882a593Smuzhiyun * @align: transfer alignment required by the DMA channel (in bytes) 70*4882a593Smuzhiyun * @xt: dma interleaved template for dma configuration 71*4882a593Smuzhiyun * @sgl: data chunk structure for dma_interleaved_template 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun struct xvip_dma { 74*4882a593Smuzhiyun struct list_head list; 75*4882a593Smuzhiyun struct video_device video; 76*4882a593Smuzhiyun struct media_pad pad; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun struct xvip_composite_device *xdev; 79*4882a593Smuzhiyun struct xvip_pipeline pipe; 80*4882a593Smuzhiyun unsigned int port; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun struct mutex lock; 83*4882a593Smuzhiyun struct v4l2_pix_format format; 84*4882a593Smuzhiyun const struct xvip_video_format *fmtinfo; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun struct vb2_queue queue; 87*4882a593Smuzhiyun unsigned int sequence; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun struct list_head queued_bufs; 90*4882a593Smuzhiyun spinlock_t queued_lock; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun struct dma_chan *dma; 93*4882a593Smuzhiyun unsigned int align; 94*4882a593Smuzhiyun struct dma_interleaved_template xt; 95*4882a593Smuzhiyun struct data_chunk sgl[1]; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define to_xvip_dma(vdev) container_of(vdev, struct xvip_dma, video) 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun int xvip_dma_init(struct xvip_composite_device *xdev, struct xvip_dma *dma, 101*4882a593Smuzhiyun enum v4l2_buf_type type, unsigned int port); 102*4882a593Smuzhiyun void xvip_dma_cleanup(struct xvip_dma *dma); 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #endif /* __XILINX_VIP_DMA_H__ */ 105