1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Xilinx Video DMA
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013-2015 Ideas on Board
6*4882a593Smuzhiyun * Copyright (C) 2013-2015 Xilinx, Inc.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Contacts: Hyun Kwon <hyun.kwon@xilinx.com>
9*4882a593Smuzhiyun * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/dma/xilinx_dma.h>
13*4882a593Smuzhiyun #include <linux/lcm.h>
14*4882a593Smuzhiyun #include <linux/list.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/of.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <media/v4l2-dev.h>
20*4882a593Smuzhiyun #include <media/v4l2-fh.h>
21*4882a593Smuzhiyun #include <media/v4l2-ioctl.h>
22*4882a593Smuzhiyun #include <media/videobuf2-v4l2.h>
23*4882a593Smuzhiyun #include <media/videobuf2-dma-contig.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #include "xilinx-dma.h"
26*4882a593Smuzhiyun #include "xilinx-vip.h"
27*4882a593Smuzhiyun #include "xilinx-vipp.h"
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define XVIP_DMA_DEF_FORMAT V4L2_PIX_FMT_YUYV
30*4882a593Smuzhiyun #define XVIP_DMA_DEF_WIDTH 1920
31*4882a593Smuzhiyun #define XVIP_DMA_DEF_HEIGHT 1080
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* Minimum and maximum widths are expressed in bytes */
34*4882a593Smuzhiyun #define XVIP_DMA_MIN_WIDTH 1U
35*4882a593Smuzhiyun #define XVIP_DMA_MAX_WIDTH 65535U
36*4882a593Smuzhiyun #define XVIP_DMA_MIN_HEIGHT 1U
37*4882a593Smuzhiyun #define XVIP_DMA_MAX_HEIGHT 8191U
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
40*4882a593Smuzhiyun * Helper functions
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun static struct v4l2_subdev *
xvip_dma_remote_subdev(struct media_pad * local,u32 * pad)44*4882a593Smuzhiyun xvip_dma_remote_subdev(struct media_pad *local, u32 *pad)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun struct media_pad *remote;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun remote = media_entity_remote_pad(local);
49*4882a593Smuzhiyun if (!remote || !is_media_entity_v4l2_subdev(remote->entity))
50*4882a593Smuzhiyun return NULL;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun if (pad)
53*4882a593Smuzhiyun *pad = remote->index;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun return media_entity_to_v4l2_subdev(remote->entity);
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
xvip_dma_verify_format(struct xvip_dma * dma)58*4882a593Smuzhiyun static int xvip_dma_verify_format(struct xvip_dma *dma)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun struct v4l2_subdev_format fmt;
61*4882a593Smuzhiyun struct v4l2_subdev *subdev;
62*4882a593Smuzhiyun int ret;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun subdev = xvip_dma_remote_subdev(&dma->pad, &fmt.pad);
65*4882a593Smuzhiyun if (subdev == NULL)
66*4882a593Smuzhiyun return -EPIPE;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
69*4882a593Smuzhiyun ret = v4l2_subdev_call(subdev, pad, get_fmt, NULL, &fmt);
70*4882a593Smuzhiyun if (ret < 0)
71*4882a593Smuzhiyun return ret == -ENOIOCTLCMD ? -EINVAL : ret;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun if (dma->fmtinfo->code != fmt.format.code ||
74*4882a593Smuzhiyun dma->format.height != fmt.format.height ||
75*4882a593Smuzhiyun dma->format.width != fmt.format.width ||
76*4882a593Smuzhiyun dma->format.colorspace != fmt.format.colorspace)
77*4882a593Smuzhiyun return -EINVAL;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun return 0;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
83*4882a593Smuzhiyun * Pipeline Stream Management
84*4882a593Smuzhiyun */
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /**
87*4882a593Smuzhiyun * xvip_pipeline_start_stop - Start ot stop streaming on a pipeline
88*4882a593Smuzhiyun * @pipe: The pipeline
89*4882a593Smuzhiyun * @start: Start (when true) or stop (when false) the pipeline
90*4882a593Smuzhiyun *
91*4882a593Smuzhiyun * Walk the entities chain starting at the pipeline output video node and start
92*4882a593Smuzhiyun * or stop all of them.
93*4882a593Smuzhiyun *
94*4882a593Smuzhiyun * Return: 0 if successful, or the return value of the failed video::s_stream
95*4882a593Smuzhiyun * operation otherwise.
96*4882a593Smuzhiyun */
xvip_pipeline_start_stop(struct xvip_pipeline * pipe,bool start)97*4882a593Smuzhiyun static int xvip_pipeline_start_stop(struct xvip_pipeline *pipe, bool start)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun struct xvip_dma *dma = pipe->output;
100*4882a593Smuzhiyun struct media_entity *entity;
101*4882a593Smuzhiyun struct media_pad *pad;
102*4882a593Smuzhiyun struct v4l2_subdev *subdev;
103*4882a593Smuzhiyun int ret;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun entity = &dma->video.entity;
106*4882a593Smuzhiyun while (1) {
107*4882a593Smuzhiyun pad = &entity->pads[0];
108*4882a593Smuzhiyun if (!(pad->flags & MEDIA_PAD_FL_SINK))
109*4882a593Smuzhiyun break;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun pad = media_entity_remote_pad(pad);
112*4882a593Smuzhiyun if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
113*4882a593Smuzhiyun break;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun entity = pad->entity;
116*4882a593Smuzhiyun subdev = media_entity_to_v4l2_subdev(entity);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun ret = v4l2_subdev_call(subdev, video, s_stream, start);
119*4882a593Smuzhiyun if (start && ret < 0 && ret != -ENOIOCTLCMD)
120*4882a593Smuzhiyun return ret;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun return 0;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun /**
127*4882a593Smuzhiyun * xvip_pipeline_set_stream - Enable/disable streaming on a pipeline
128*4882a593Smuzhiyun * @pipe: The pipeline
129*4882a593Smuzhiyun * @on: Turn the stream on when true or off when false
130*4882a593Smuzhiyun *
131*4882a593Smuzhiyun * The pipeline is shared between all DMA engines connect at its input and
132*4882a593Smuzhiyun * output. While the stream state of DMA engines can be controlled
133*4882a593Smuzhiyun * independently, pipelines have a shared stream state that enable or disable
134*4882a593Smuzhiyun * all entities in the pipeline. For this reason the pipeline uses a streaming
135*4882a593Smuzhiyun * counter that tracks the number of DMA engines that have requested the stream
136*4882a593Smuzhiyun * to be enabled.
137*4882a593Smuzhiyun *
138*4882a593Smuzhiyun * When called with the @on argument set to true, this function will increment
139*4882a593Smuzhiyun * the pipeline streaming count. If the streaming count reaches the number of
140*4882a593Smuzhiyun * DMA engines in the pipeline it will enable all entities that belong to the
141*4882a593Smuzhiyun * pipeline.
142*4882a593Smuzhiyun *
143*4882a593Smuzhiyun * Similarly, when called with the @on argument set to false, this function will
144*4882a593Smuzhiyun * decrement the pipeline streaming count and disable all entities in the
145*4882a593Smuzhiyun * pipeline when the streaming count reaches zero.
146*4882a593Smuzhiyun *
147*4882a593Smuzhiyun * Return: 0 if successful, or the return value of the failed video::s_stream
148*4882a593Smuzhiyun * operation otherwise. Stopping the pipeline never fails. The pipeline state is
149*4882a593Smuzhiyun * not updated when the operation fails.
150*4882a593Smuzhiyun */
xvip_pipeline_set_stream(struct xvip_pipeline * pipe,bool on)151*4882a593Smuzhiyun static int xvip_pipeline_set_stream(struct xvip_pipeline *pipe, bool on)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun int ret = 0;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun mutex_lock(&pipe->lock);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun if (on) {
158*4882a593Smuzhiyun if (pipe->stream_count == pipe->num_dmas - 1) {
159*4882a593Smuzhiyun ret = xvip_pipeline_start_stop(pipe, true);
160*4882a593Smuzhiyun if (ret < 0)
161*4882a593Smuzhiyun goto done;
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun pipe->stream_count++;
164*4882a593Smuzhiyun } else {
165*4882a593Smuzhiyun if (--pipe->stream_count == 0)
166*4882a593Smuzhiyun xvip_pipeline_start_stop(pipe, false);
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun done:
170*4882a593Smuzhiyun mutex_unlock(&pipe->lock);
171*4882a593Smuzhiyun return ret;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
xvip_pipeline_validate(struct xvip_pipeline * pipe,struct xvip_dma * start)174*4882a593Smuzhiyun static int xvip_pipeline_validate(struct xvip_pipeline *pipe,
175*4882a593Smuzhiyun struct xvip_dma *start)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun struct media_graph graph;
178*4882a593Smuzhiyun struct media_entity *entity = &start->video.entity;
179*4882a593Smuzhiyun struct media_device *mdev = entity->graph_obj.mdev;
180*4882a593Smuzhiyun unsigned int num_inputs = 0;
181*4882a593Smuzhiyun unsigned int num_outputs = 0;
182*4882a593Smuzhiyun int ret;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun mutex_lock(&mdev->graph_mutex);
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun /* Walk the graph to locate the video nodes. */
187*4882a593Smuzhiyun ret = media_graph_walk_init(&graph, mdev);
188*4882a593Smuzhiyun if (ret) {
189*4882a593Smuzhiyun mutex_unlock(&mdev->graph_mutex);
190*4882a593Smuzhiyun return ret;
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun media_graph_walk_start(&graph, entity);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun while ((entity = media_graph_walk_next(&graph))) {
196*4882a593Smuzhiyun struct xvip_dma *dma;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun if (entity->function != MEDIA_ENT_F_IO_V4L)
199*4882a593Smuzhiyun continue;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun dma = to_xvip_dma(media_entity_to_video_device(entity));
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun if (dma->pad.flags & MEDIA_PAD_FL_SINK) {
204*4882a593Smuzhiyun pipe->output = dma;
205*4882a593Smuzhiyun num_outputs++;
206*4882a593Smuzhiyun } else {
207*4882a593Smuzhiyun num_inputs++;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun mutex_unlock(&mdev->graph_mutex);
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun media_graph_walk_cleanup(&graph);
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun /* We need exactly one output and zero or one input. */
216*4882a593Smuzhiyun if (num_outputs != 1 || num_inputs > 1)
217*4882a593Smuzhiyun return -EPIPE;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun pipe->num_dmas = num_inputs + num_outputs;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun return 0;
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun
__xvip_pipeline_cleanup(struct xvip_pipeline * pipe)224*4882a593Smuzhiyun static void __xvip_pipeline_cleanup(struct xvip_pipeline *pipe)
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun pipe->num_dmas = 0;
227*4882a593Smuzhiyun pipe->output = NULL;
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun /**
231*4882a593Smuzhiyun * xvip_pipeline_cleanup - Cleanup the pipeline after streaming
232*4882a593Smuzhiyun * @pipe: the pipeline
233*4882a593Smuzhiyun *
234*4882a593Smuzhiyun * Decrease the pipeline use count and clean it up if we were the last user.
235*4882a593Smuzhiyun */
xvip_pipeline_cleanup(struct xvip_pipeline * pipe)236*4882a593Smuzhiyun static void xvip_pipeline_cleanup(struct xvip_pipeline *pipe)
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun mutex_lock(&pipe->lock);
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun /* If we're the last user clean up the pipeline. */
241*4882a593Smuzhiyun if (--pipe->use_count == 0)
242*4882a593Smuzhiyun __xvip_pipeline_cleanup(pipe);
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun mutex_unlock(&pipe->lock);
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun /**
248*4882a593Smuzhiyun * xvip_pipeline_prepare - Prepare the pipeline for streaming
249*4882a593Smuzhiyun * @pipe: the pipeline
250*4882a593Smuzhiyun * @dma: DMA engine at one end of the pipeline
251*4882a593Smuzhiyun *
252*4882a593Smuzhiyun * Validate the pipeline if no user exists yet, otherwise just increase the use
253*4882a593Smuzhiyun * count.
254*4882a593Smuzhiyun *
255*4882a593Smuzhiyun * Return: 0 if successful or -EPIPE if the pipeline is not valid.
256*4882a593Smuzhiyun */
xvip_pipeline_prepare(struct xvip_pipeline * pipe,struct xvip_dma * dma)257*4882a593Smuzhiyun static int xvip_pipeline_prepare(struct xvip_pipeline *pipe,
258*4882a593Smuzhiyun struct xvip_dma *dma)
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun int ret;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun mutex_lock(&pipe->lock);
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun /* If we're the first user validate and initialize the pipeline. */
265*4882a593Smuzhiyun if (pipe->use_count == 0) {
266*4882a593Smuzhiyun ret = xvip_pipeline_validate(pipe, dma);
267*4882a593Smuzhiyun if (ret < 0) {
268*4882a593Smuzhiyun __xvip_pipeline_cleanup(pipe);
269*4882a593Smuzhiyun goto done;
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun pipe->use_count++;
274*4882a593Smuzhiyun ret = 0;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun done:
277*4882a593Smuzhiyun mutex_unlock(&pipe->lock);
278*4882a593Smuzhiyun return ret;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
282*4882a593Smuzhiyun * videobuf2 queue operations
283*4882a593Smuzhiyun */
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun /**
286*4882a593Smuzhiyun * struct xvip_dma_buffer - Video DMA buffer
287*4882a593Smuzhiyun * @buf: vb2 buffer base object
288*4882a593Smuzhiyun * @queue: buffer list entry in the DMA engine queued buffers list
289*4882a593Smuzhiyun * @dma: DMA channel that uses the buffer
290*4882a593Smuzhiyun */
291*4882a593Smuzhiyun struct xvip_dma_buffer {
292*4882a593Smuzhiyun struct vb2_v4l2_buffer buf;
293*4882a593Smuzhiyun struct list_head queue;
294*4882a593Smuzhiyun struct xvip_dma *dma;
295*4882a593Smuzhiyun };
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun #define to_xvip_dma_buffer(vb) container_of(vb, struct xvip_dma_buffer, buf)
298*4882a593Smuzhiyun
xvip_dma_complete(void * param)299*4882a593Smuzhiyun static void xvip_dma_complete(void *param)
300*4882a593Smuzhiyun {
301*4882a593Smuzhiyun struct xvip_dma_buffer *buf = param;
302*4882a593Smuzhiyun struct xvip_dma *dma = buf->dma;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun spin_lock(&dma->queued_lock);
305*4882a593Smuzhiyun list_del(&buf->queue);
306*4882a593Smuzhiyun spin_unlock(&dma->queued_lock);
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun buf->buf.field = V4L2_FIELD_NONE;
309*4882a593Smuzhiyun buf->buf.sequence = dma->sequence++;
310*4882a593Smuzhiyun buf->buf.vb2_buf.timestamp = ktime_get_ns();
311*4882a593Smuzhiyun vb2_set_plane_payload(&buf->buf.vb2_buf, 0, dma->format.sizeimage);
312*4882a593Smuzhiyun vb2_buffer_done(&buf->buf.vb2_buf, VB2_BUF_STATE_DONE);
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun static int
xvip_dma_queue_setup(struct vb2_queue * vq,unsigned int * nbuffers,unsigned int * nplanes,unsigned int sizes[],struct device * alloc_devs[])316*4882a593Smuzhiyun xvip_dma_queue_setup(struct vb2_queue *vq,
317*4882a593Smuzhiyun unsigned int *nbuffers, unsigned int *nplanes,
318*4882a593Smuzhiyun unsigned int sizes[], struct device *alloc_devs[])
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun struct xvip_dma *dma = vb2_get_drv_priv(vq);
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun /* Make sure the image size is large enough. */
323*4882a593Smuzhiyun if (*nplanes)
324*4882a593Smuzhiyun return sizes[0] < dma->format.sizeimage ? -EINVAL : 0;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun *nplanes = 1;
327*4882a593Smuzhiyun sizes[0] = dma->format.sizeimage;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun return 0;
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun
xvip_dma_buffer_prepare(struct vb2_buffer * vb)332*4882a593Smuzhiyun static int xvip_dma_buffer_prepare(struct vb2_buffer *vb)
333*4882a593Smuzhiyun {
334*4882a593Smuzhiyun struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
335*4882a593Smuzhiyun struct xvip_dma *dma = vb2_get_drv_priv(vb->vb2_queue);
336*4882a593Smuzhiyun struct xvip_dma_buffer *buf = to_xvip_dma_buffer(vbuf);
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun buf->dma = dma;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun return 0;
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun
xvip_dma_buffer_queue(struct vb2_buffer * vb)343*4882a593Smuzhiyun static void xvip_dma_buffer_queue(struct vb2_buffer *vb)
344*4882a593Smuzhiyun {
345*4882a593Smuzhiyun struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
346*4882a593Smuzhiyun struct xvip_dma *dma = vb2_get_drv_priv(vb->vb2_queue);
347*4882a593Smuzhiyun struct xvip_dma_buffer *buf = to_xvip_dma_buffer(vbuf);
348*4882a593Smuzhiyun struct dma_async_tx_descriptor *desc;
349*4882a593Smuzhiyun dma_addr_t addr = vb2_dma_contig_plane_dma_addr(vb, 0);
350*4882a593Smuzhiyun u32 flags;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun if (dma->queue.type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
353*4882a593Smuzhiyun flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
354*4882a593Smuzhiyun dma->xt.dir = DMA_DEV_TO_MEM;
355*4882a593Smuzhiyun dma->xt.src_sgl = false;
356*4882a593Smuzhiyun dma->xt.dst_sgl = true;
357*4882a593Smuzhiyun dma->xt.dst_start = addr;
358*4882a593Smuzhiyun } else {
359*4882a593Smuzhiyun flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
360*4882a593Smuzhiyun dma->xt.dir = DMA_MEM_TO_DEV;
361*4882a593Smuzhiyun dma->xt.src_sgl = true;
362*4882a593Smuzhiyun dma->xt.dst_sgl = false;
363*4882a593Smuzhiyun dma->xt.src_start = addr;
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun dma->xt.frame_size = 1;
367*4882a593Smuzhiyun dma->sgl[0].size = dma->format.width * dma->fmtinfo->bpp;
368*4882a593Smuzhiyun dma->sgl[0].icg = dma->format.bytesperline - dma->sgl[0].size;
369*4882a593Smuzhiyun dma->xt.numf = dma->format.height;
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun desc = dmaengine_prep_interleaved_dma(dma->dma, &dma->xt, flags);
372*4882a593Smuzhiyun if (!desc) {
373*4882a593Smuzhiyun dev_err(dma->xdev->dev, "Failed to prepare DMA transfer\n");
374*4882a593Smuzhiyun vb2_buffer_done(&buf->buf.vb2_buf, VB2_BUF_STATE_ERROR);
375*4882a593Smuzhiyun return;
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun desc->callback = xvip_dma_complete;
378*4882a593Smuzhiyun desc->callback_param = buf;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun spin_lock_irq(&dma->queued_lock);
381*4882a593Smuzhiyun list_add_tail(&buf->queue, &dma->queued_bufs);
382*4882a593Smuzhiyun spin_unlock_irq(&dma->queued_lock);
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun dmaengine_submit(desc);
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun if (vb2_is_streaming(&dma->queue))
387*4882a593Smuzhiyun dma_async_issue_pending(dma->dma);
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun
xvip_dma_start_streaming(struct vb2_queue * vq,unsigned int count)390*4882a593Smuzhiyun static int xvip_dma_start_streaming(struct vb2_queue *vq, unsigned int count)
391*4882a593Smuzhiyun {
392*4882a593Smuzhiyun struct xvip_dma *dma = vb2_get_drv_priv(vq);
393*4882a593Smuzhiyun struct xvip_dma_buffer *buf, *nbuf;
394*4882a593Smuzhiyun struct xvip_pipeline *pipe;
395*4882a593Smuzhiyun int ret;
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun dma->sequence = 0;
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun /*
400*4882a593Smuzhiyun * Start streaming on the pipeline. No link touching an entity in the
401*4882a593Smuzhiyun * pipeline can be activated or deactivated once streaming is started.
402*4882a593Smuzhiyun *
403*4882a593Smuzhiyun * Use the pipeline object embedded in the first DMA object that starts
404*4882a593Smuzhiyun * streaming.
405*4882a593Smuzhiyun */
406*4882a593Smuzhiyun pipe = dma->video.entity.pipe
407*4882a593Smuzhiyun ? to_xvip_pipeline(&dma->video.entity) : &dma->pipe;
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun ret = media_pipeline_start(&dma->video.entity, &pipe->pipe);
410*4882a593Smuzhiyun if (ret < 0)
411*4882a593Smuzhiyun goto error;
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun /* Verify that the configured format matches the output of the
414*4882a593Smuzhiyun * connected subdev.
415*4882a593Smuzhiyun */
416*4882a593Smuzhiyun ret = xvip_dma_verify_format(dma);
417*4882a593Smuzhiyun if (ret < 0)
418*4882a593Smuzhiyun goto error_stop;
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun ret = xvip_pipeline_prepare(pipe, dma);
421*4882a593Smuzhiyun if (ret < 0)
422*4882a593Smuzhiyun goto error_stop;
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun /* Start the DMA engine. This must be done before starting the blocks
425*4882a593Smuzhiyun * in the pipeline to avoid DMA synchronization issues.
426*4882a593Smuzhiyun */
427*4882a593Smuzhiyun dma_async_issue_pending(dma->dma);
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun /* Start the pipeline. */
430*4882a593Smuzhiyun xvip_pipeline_set_stream(pipe, true);
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun return 0;
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun error_stop:
435*4882a593Smuzhiyun media_pipeline_stop(&dma->video.entity);
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun error:
438*4882a593Smuzhiyun /* Give back all queued buffers to videobuf2. */
439*4882a593Smuzhiyun spin_lock_irq(&dma->queued_lock);
440*4882a593Smuzhiyun list_for_each_entry_safe(buf, nbuf, &dma->queued_bufs, queue) {
441*4882a593Smuzhiyun vb2_buffer_done(&buf->buf.vb2_buf, VB2_BUF_STATE_QUEUED);
442*4882a593Smuzhiyun list_del(&buf->queue);
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun spin_unlock_irq(&dma->queued_lock);
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun return ret;
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun
xvip_dma_stop_streaming(struct vb2_queue * vq)449*4882a593Smuzhiyun static void xvip_dma_stop_streaming(struct vb2_queue *vq)
450*4882a593Smuzhiyun {
451*4882a593Smuzhiyun struct xvip_dma *dma = vb2_get_drv_priv(vq);
452*4882a593Smuzhiyun struct xvip_pipeline *pipe = to_xvip_pipeline(&dma->video.entity);
453*4882a593Smuzhiyun struct xvip_dma_buffer *buf, *nbuf;
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun /* Stop the pipeline. */
456*4882a593Smuzhiyun xvip_pipeline_set_stream(pipe, false);
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun /* Stop and reset the DMA engine. */
459*4882a593Smuzhiyun dmaengine_terminate_all(dma->dma);
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun /* Cleanup the pipeline and mark it as being stopped. */
462*4882a593Smuzhiyun xvip_pipeline_cleanup(pipe);
463*4882a593Smuzhiyun media_pipeline_stop(&dma->video.entity);
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun /* Give back all queued buffers to videobuf2. */
466*4882a593Smuzhiyun spin_lock_irq(&dma->queued_lock);
467*4882a593Smuzhiyun list_for_each_entry_safe(buf, nbuf, &dma->queued_bufs, queue) {
468*4882a593Smuzhiyun vb2_buffer_done(&buf->buf.vb2_buf, VB2_BUF_STATE_ERROR);
469*4882a593Smuzhiyun list_del(&buf->queue);
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun spin_unlock_irq(&dma->queued_lock);
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun static const struct vb2_ops xvip_dma_queue_qops = {
475*4882a593Smuzhiyun .queue_setup = xvip_dma_queue_setup,
476*4882a593Smuzhiyun .buf_prepare = xvip_dma_buffer_prepare,
477*4882a593Smuzhiyun .buf_queue = xvip_dma_buffer_queue,
478*4882a593Smuzhiyun .wait_prepare = vb2_ops_wait_prepare,
479*4882a593Smuzhiyun .wait_finish = vb2_ops_wait_finish,
480*4882a593Smuzhiyun .start_streaming = xvip_dma_start_streaming,
481*4882a593Smuzhiyun .stop_streaming = xvip_dma_stop_streaming,
482*4882a593Smuzhiyun };
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
485*4882a593Smuzhiyun * V4L2 ioctls
486*4882a593Smuzhiyun */
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun static int
xvip_dma_querycap(struct file * file,void * fh,struct v4l2_capability * cap)489*4882a593Smuzhiyun xvip_dma_querycap(struct file *file, void *fh, struct v4l2_capability *cap)
490*4882a593Smuzhiyun {
491*4882a593Smuzhiyun struct v4l2_fh *vfh = file->private_data;
492*4882a593Smuzhiyun struct xvip_dma *dma = to_xvip_dma(vfh->vdev);
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun cap->capabilities = dma->xdev->v4l2_caps | V4L2_CAP_STREAMING |
495*4882a593Smuzhiyun V4L2_CAP_DEVICE_CAPS;
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun strscpy(cap->driver, "xilinx-vipp", sizeof(cap->driver));
498*4882a593Smuzhiyun strscpy(cap->card, dma->video.name, sizeof(cap->card));
499*4882a593Smuzhiyun snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%pOFn:%u",
500*4882a593Smuzhiyun dma->xdev->dev->of_node, dma->port);
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun return 0;
503*4882a593Smuzhiyun }
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun /* FIXME: without this callback function, some applications are not configured
506*4882a593Smuzhiyun * with correct formats, and it results in frames in wrong format. Whether this
507*4882a593Smuzhiyun * callback needs to be required is not clearly defined, so it should be
508*4882a593Smuzhiyun * clarified through the mailing list.
509*4882a593Smuzhiyun */
510*4882a593Smuzhiyun static int
xvip_dma_enum_format(struct file * file,void * fh,struct v4l2_fmtdesc * f)511*4882a593Smuzhiyun xvip_dma_enum_format(struct file *file, void *fh, struct v4l2_fmtdesc *f)
512*4882a593Smuzhiyun {
513*4882a593Smuzhiyun struct v4l2_fh *vfh = file->private_data;
514*4882a593Smuzhiyun struct xvip_dma *dma = to_xvip_dma(vfh->vdev);
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun if (f->index > 0)
517*4882a593Smuzhiyun return -EINVAL;
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun f->pixelformat = dma->format.pixelformat;
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun return 0;
522*4882a593Smuzhiyun }
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun static int
xvip_dma_get_format(struct file * file,void * fh,struct v4l2_format * format)525*4882a593Smuzhiyun xvip_dma_get_format(struct file *file, void *fh, struct v4l2_format *format)
526*4882a593Smuzhiyun {
527*4882a593Smuzhiyun struct v4l2_fh *vfh = file->private_data;
528*4882a593Smuzhiyun struct xvip_dma *dma = to_xvip_dma(vfh->vdev);
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun format->fmt.pix = dma->format;
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun return 0;
533*4882a593Smuzhiyun }
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun static void
__xvip_dma_try_format(struct xvip_dma * dma,struct v4l2_pix_format * pix,const struct xvip_video_format ** fmtinfo)536*4882a593Smuzhiyun __xvip_dma_try_format(struct xvip_dma *dma, struct v4l2_pix_format *pix,
537*4882a593Smuzhiyun const struct xvip_video_format **fmtinfo)
538*4882a593Smuzhiyun {
539*4882a593Smuzhiyun const struct xvip_video_format *info;
540*4882a593Smuzhiyun unsigned int min_width;
541*4882a593Smuzhiyun unsigned int max_width;
542*4882a593Smuzhiyun unsigned int min_bpl;
543*4882a593Smuzhiyun unsigned int max_bpl;
544*4882a593Smuzhiyun unsigned int width;
545*4882a593Smuzhiyun unsigned int align;
546*4882a593Smuzhiyun unsigned int bpl;
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun /* Retrieve format information and select the default format if the
549*4882a593Smuzhiyun * requested format isn't supported.
550*4882a593Smuzhiyun */
551*4882a593Smuzhiyun info = xvip_get_format_by_fourcc(pix->pixelformat);
552*4882a593Smuzhiyun if (IS_ERR(info))
553*4882a593Smuzhiyun info = xvip_get_format_by_fourcc(XVIP_DMA_DEF_FORMAT);
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun pix->pixelformat = info->fourcc;
556*4882a593Smuzhiyun pix->field = V4L2_FIELD_NONE;
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun /* The transfer alignment requirements are expressed in bytes. Compute
559*4882a593Smuzhiyun * the minimum and maximum values, clamp the requested width and convert
560*4882a593Smuzhiyun * it back to pixels.
561*4882a593Smuzhiyun */
562*4882a593Smuzhiyun align = lcm(dma->align, info->bpp);
563*4882a593Smuzhiyun min_width = roundup(XVIP_DMA_MIN_WIDTH, align);
564*4882a593Smuzhiyun max_width = rounddown(XVIP_DMA_MAX_WIDTH, align);
565*4882a593Smuzhiyun width = rounddown(pix->width * info->bpp, align);
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun pix->width = clamp(width, min_width, max_width) / info->bpp;
568*4882a593Smuzhiyun pix->height = clamp(pix->height, XVIP_DMA_MIN_HEIGHT,
569*4882a593Smuzhiyun XVIP_DMA_MAX_HEIGHT);
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun /* Clamp the requested bytes per line value. If the maximum bytes per
572*4882a593Smuzhiyun * line value is zero, the module doesn't support user configurable line
573*4882a593Smuzhiyun * sizes. Override the requested value with the minimum in that case.
574*4882a593Smuzhiyun */
575*4882a593Smuzhiyun min_bpl = pix->width * info->bpp;
576*4882a593Smuzhiyun max_bpl = rounddown(XVIP_DMA_MAX_WIDTH, dma->align);
577*4882a593Smuzhiyun bpl = rounddown(pix->bytesperline, dma->align);
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun pix->bytesperline = clamp(bpl, min_bpl, max_bpl);
580*4882a593Smuzhiyun pix->sizeimage = pix->bytesperline * pix->height;
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun if (fmtinfo)
583*4882a593Smuzhiyun *fmtinfo = info;
584*4882a593Smuzhiyun }
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun static int
xvip_dma_try_format(struct file * file,void * fh,struct v4l2_format * format)587*4882a593Smuzhiyun xvip_dma_try_format(struct file *file, void *fh, struct v4l2_format *format)
588*4882a593Smuzhiyun {
589*4882a593Smuzhiyun struct v4l2_fh *vfh = file->private_data;
590*4882a593Smuzhiyun struct xvip_dma *dma = to_xvip_dma(vfh->vdev);
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun __xvip_dma_try_format(dma, &format->fmt.pix, NULL);
593*4882a593Smuzhiyun return 0;
594*4882a593Smuzhiyun }
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun static int
xvip_dma_set_format(struct file * file,void * fh,struct v4l2_format * format)597*4882a593Smuzhiyun xvip_dma_set_format(struct file *file, void *fh, struct v4l2_format *format)
598*4882a593Smuzhiyun {
599*4882a593Smuzhiyun struct v4l2_fh *vfh = file->private_data;
600*4882a593Smuzhiyun struct xvip_dma *dma = to_xvip_dma(vfh->vdev);
601*4882a593Smuzhiyun const struct xvip_video_format *info;
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun __xvip_dma_try_format(dma, &format->fmt.pix, &info);
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun if (vb2_is_busy(&dma->queue))
606*4882a593Smuzhiyun return -EBUSY;
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun dma->format = format->fmt.pix;
609*4882a593Smuzhiyun dma->fmtinfo = info;
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun return 0;
612*4882a593Smuzhiyun }
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun static const struct v4l2_ioctl_ops xvip_dma_ioctl_ops = {
615*4882a593Smuzhiyun .vidioc_querycap = xvip_dma_querycap,
616*4882a593Smuzhiyun .vidioc_enum_fmt_vid_cap = xvip_dma_enum_format,
617*4882a593Smuzhiyun .vidioc_g_fmt_vid_cap = xvip_dma_get_format,
618*4882a593Smuzhiyun .vidioc_g_fmt_vid_out = xvip_dma_get_format,
619*4882a593Smuzhiyun .vidioc_s_fmt_vid_cap = xvip_dma_set_format,
620*4882a593Smuzhiyun .vidioc_s_fmt_vid_out = xvip_dma_set_format,
621*4882a593Smuzhiyun .vidioc_try_fmt_vid_cap = xvip_dma_try_format,
622*4882a593Smuzhiyun .vidioc_try_fmt_vid_out = xvip_dma_try_format,
623*4882a593Smuzhiyun .vidioc_reqbufs = vb2_ioctl_reqbufs,
624*4882a593Smuzhiyun .vidioc_querybuf = vb2_ioctl_querybuf,
625*4882a593Smuzhiyun .vidioc_qbuf = vb2_ioctl_qbuf,
626*4882a593Smuzhiyun .vidioc_dqbuf = vb2_ioctl_dqbuf,
627*4882a593Smuzhiyun .vidioc_create_bufs = vb2_ioctl_create_bufs,
628*4882a593Smuzhiyun .vidioc_expbuf = vb2_ioctl_expbuf,
629*4882a593Smuzhiyun .vidioc_streamon = vb2_ioctl_streamon,
630*4882a593Smuzhiyun .vidioc_streamoff = vb2_ioctl_streamoff,
631*4882a593Smuzhiyun };
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
634*4882a593Smuzhiyun * V4L2 file operations
635*4882a593Smuzhiyun */
636*4882a593Smuzhiyun
637*4882a593Smuzhiyun static const struct v4l2_file_operations xvip_dma_fops = {
638*4882a593Smuzhiyun .owner = THIS_MODULE,
639*4882a593Smuzhiyun .unlocked_ioctl = video_ioctl2,
640*4882a593Smuzhiyun .open = v4l2_fh_open,
641*4882a593Smuzhiyun .release = vb2_fop_release,
642*4882a593Smuzhiyun .poll = vb2_fop_poll,
643*4882a593Smuzhiyun .mmap = vb2_fop_mmap,
644*4882a593Smuzhiyun };
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
647*4882a593Smuzhiyun * Xilinx Video DMA Core
648*4882a593Smuzhiyun */
649*4882a593Smuzhiyun
xvip_dma_init(struct xvip_composite_device * xdev,struct xvip_dma * dma,enum v4l2_buf_type type,unsigned int port)650*4882a593Smuzhiyun int xvip_dma_init(struct xvip_composite_device *xdev, struct xvip_dma *dma,
651*4882a593Smuzhiyun enum v4l2_buf_type type, unsigned int port)
652*4882a593Smuzhiyun {
653*4882a593Smuzhiyun char name[16];
654*4882a593Smuzhiyun int ret;
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun dma->xdev = xdev;
657*4882a593Smuzhiyun dma->port = port;
658*4882a593Smuzhiyun mutex_init(&dma->lock);
659*4882a593Smuzhiyun mutex_init(&dma->pipe.lock);
660*4882a593Smuzhiyun INIT_LIST_HEAD(&dma->queued_bufs);
661*4882a593Smuzhiyun spin_lock_init(&dma->queued_lock);
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun dma->fmtinfo = xvip_get_format_by_fourcc(XVIP_DMA_DEF_FORMAT);
664*4882a593Smuzhiyun dma->format.pixelformat = dma->fmtinfo->fourcc;
665*4882a593Smuzhiyun dma->format.colorspace = V4L2_COLORSPACE_SRGB;
666*4882a593Smuzhiyun dma->format.field = V4L2_FIELD_NONE;
667*4882a593Smuzhiyun dma->format.width = XVIP_DMA_DEF_WIDTH;
668*4882a593Smuzhiyun dma->format.height = XVIP_DMA_DEF_HEIGHT;
669*4882a593Smuzhiyun dma->format.bytesperline = dma->format.width * dma->fmtinfo->bpp;
670*4882a593Smuzhiyun dma->format.sizeimage = dma->format.bytesperline * dma->format.height;
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun /* Initialize the media entity... */
673*4882a593Smuzhiyun dma->pad.flags = type == V4L2_BUF_TYPE_VIDEO_CAPTURE
674*4882a593Smuzhiyun ? MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE;
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun ret = media_entity_pads_init(&dma->video.entity, 1, &dma->pad);
677*4882a593Smuzhiyun if (ret < 0)
678*4882a593Smuzhiyun goto error;
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun /* ... and the video node... */
681*4882a593Smuzhiyun dma->video.fops = &xvip_dma_fops;
682*4882a593Smuzhiyun dma->video.v4l2_dev = &xdev->v4l2_dev;
683*4882a593Smuzhiyun dma->video.queue = &dma->queue;
684*4882a593Smuzhiyun snprintf(dma->video.name, sizeof(dma->video.name), "%pOFn %s %u",
685*4882a593Smuzhiyun xdev->dev->of_node,
686*4882a593Smuzhiyun type == V4L2_BUF_TYPE_VIDEO_CAPTURE ? "output" : "input",
687*4882a593Smuzhiyun port);
688*4882a593Smuzhiyun dma->video.vfl_type = VFL_TYPE_VIDEO;
689*4882a593Smuzhiyun dma->video.vfl_dir = type == V4L2_BUF_TYPE_VIDEO_CAPTURE
690*4882a593Smuzhiyun ? VFL_DIR_RX : VFL_DIR_TX;
691*4882a593Smuzhiyun dma->video.release = video_device_release_empty;
692*4882a593Smuzhiyun dma->video.ioctl_ops = &xvip_dma_ioctl_ops;
693*4882a593Smuzhiyun dma->video.lock = &dma->lock;
694*4882a593Smuzhiyun dma->video.device_caps = V4L2_CAP_STREAMING;
695*4882a593Smuzhiyun if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
696*4882a593Smuzhiyun dma->video.device_caps |= V4L2_CAP_VIDEO_CAPTURE;
697*4882a593Smuzhiyun else
698*4882a593Smuzhiyun dma->video.device_caps |= V4L2_CAP_VIDEO_OUTPUT;
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun video_set_drvdata(&dma->video, dma);
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun /* ... and the buffers queue... */
703*4882a593Smuzhiyun /* Don't enable VB2_READ and VB2_WRITE, as using the read() and write()
704*4882a593Smuzhiyun * V4L2 APIs would be inefficient. Testing on the command line with a
705*4882a593Smuzhiyun * 'cat /dev/video?' thus won't be possible, but given that the driver
706*4882a593Smuzhiyun * anyway requires a test tool to setup the pipeline before any video
707*4882a593Smuzhiyun * stream can be started, requiring a specific V4L2 test tool as well
708*4882a593Smuzhiyun * instead of 'cat' isn't really a drawback.
709*4882a593Smuzhiyun */
710*4882a593Smuzhiyun dma->queue.type = type;
711*4882a593Smuzhiyun dma->queue.io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
712*4882a593Smuzhiyun dma->queue.lock = &dma->lock;
713*4882a593Smuzhiyun dma->queue.drv_priv = dma;
714*4882a593Smuzhiyun dma->queue.buf_struct_size = sizeof(struct xvip_dma_buffer);
715*4882a593Smuzhiyun dma->queue.ops = &xvip_dma_queue_qops;
716*4882a593Smuzhiyun dma->queue.mem_ops = &vb2_dma_contig_memops;
717*4882a593Smuzhiyun dma->queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC
718*4882a593Smuzhiyun | V4L2_BUF_FLAG_TSTAMP_SRC_EOF;
719*4882a593Smuzhiyun dma->queue.dev = dma->xdev->dev;
720*4882a593Smuzhiyun ret = vb2_queue_init(&dma->queue);
721*4882a593Smuzhiyun if (ret < 0) {
722*4882a593Smuzhiyun dev_err(dma->xdev->dev, "failed to initialize VB2 queue\n");
723*4882a593Smuzhiyun goto error;
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun /* ... and the DMA channel. */
727*4882a593Smuzhiyun snprintf(name, sizeof(name), "port%u", port);
728*4882a593Smuzhiyun dma->dma = dma_request_chan(dma->xdev->dev, name);
729*4882a593Smuzhiyun if (IS_ERR(dma->dma)) {
730*4882a593Smuzhiyun ret = PTR_ERR(dma->dma);
731*4882a593Smuzhiyun if (ret != -EPROBE_DEFER)
732*4882a593Smuzhiyun dev_err(dma->xdev->dev, "no VDMA channel found\n");
733*4882a593Smuzhiyun goto error;
734*4882a593Smuzhiyun }
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun dma->align = 1 << dma->dma->device->copy_align;
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun ret = video_register_device(&dma->video, VFL_TYPE_VIDEO, -1);
739*4882a593Smuzhiyun if (ret < 0) {
740*4882a593Smuzhiyun dev_err(dma->xdev->dev, "failed to register video device\n");
741*4882a593Smuzhiyun goto error;
742*4882a593Smuzhiyun }
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun return 0;
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun error:
747*4882a593Smuzhiyun xvip_dma_cleanup(dma);
748*4882a593Smuzhiyun return ret;
749*4882a593Smuzhiyun }
750*4882a593Smuzhiyun
xvip_dma_cleanup(struct xvip_dma * dma)751*4882a593Smuzhiyun void xvip_dma_cleanup(struct xvip_dma *dma)
752*4882a593Smuzhiyun {
753*4882a593Smuzhiyun if (video_is_registered(&dma->video))
754*4882a593Smuzhiyun video_unregister_device(&dma->video);
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(dma->dma))
757*4882a593Smuzhiyun dma_release_channel(dma->dma);
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun media_entity_cleanup(&dma->video.entity);
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun mutex_destroy(&dma->lock);
762*4882a593Smuzhiyun mutex_destroy(&dma->pipe.lock);
763*4882a593Smuzhiyun }
764