1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * vsp1_sru.c -- R-Car VSP1 Super Resolution Unit
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013 Renesas Corporation
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/gfp.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "vsp1.h"
16*4882a593Smuzhiyun #include "vsp1_dl.h"
17*4882a593Smuzhiyun #include "vsp1_pipe.h"
18*4882a593Smuzhiyun #include "vsp1_sru.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define SRU_MIN_SIZE 4U
21*4882a593Smuzhiyun #define SRU_MAX_SIZE 8190U
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
24*4882a593Smuzhiyun * Device Access
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun
vsp1_sru_write(struct vsp1_sru * sru,struct vsp1_dl_body * dlb,u32 reg,u32 data)27*4882a593Smuzhiyun static inline void vsp1_sru_write(struct vsp1_sru *sru,
28*4882a593Smuzhiyun struct vsp1_dl_body *dlb, u32 reg, u32 data)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun vsp1_dl_body_write(dlb, reg, data);
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
34*4882a593Smuzhiyun * Controls
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define V4L2_CID_VSP1_SRU_INTENSITY (V4L2_CID_USER_BASE | 0x1001)
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun struct vsp1_sru_param {
40*4882a593Smuzhiyun u32 ctrl0;
41*4882a593Smuzhiyun u32 ctrl2;
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define VI6_SRU_CTRL0_PARAMS(p0, p1) \
45*4882a593Smuzhiyun (((p0) << VI6_SRU_CTRL0_PARAM0_SHIFT) | \
46*4882a593Smuzhiyun ((p1) << VI6_SRU_CTRL0_PARAM1_SHIFT))
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define VI6_SRU_CTRL2_PARAMS(p6, p7, p8) \
49*4882a593Smuzhiyun (((p6) << VI6_SRU_CTRL2_PARAM6_SHIFT) | \
50*4882a593Smuzhiyun ((p7) << VI6_SRU_CTRL2_PARAM7_SHIFT) | \
51*4882a593Smuzhiyun ((p8) << VI6_SRU_CTRL2_PARAM8_SHIFT))
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun static const struct vsp1_sru_param vsp1_sru_params[] = {
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun .ctrl0 = VI6_SRU_CTRL0_PARAMS(256, 4) | VI6_SRU_CTRL0_EN,
56*4882a593Smuzhiyun .ctrl2 = VI6_SRU_CTRL2_PARAMS(24, 40, 255),
57*4882a593Smuzhiyun }, {
58*4882a593Smuzhiyun .ctrl0 = VI6_SRU_CTRL0_PARAMS(256, 4) | VI6_SRU_CTRL0_EN,
59*4882a593Smuzhiyun .ctrl2 = VI6_SRU_CTRL2_PARAMS(8, 16, 255),
60*4882a593Smuzhiyun }, {
61*4882a593Smuzhiyun .ctrl0 = VI6_SRU_CTRL0_PARAMS(384, 5) | VI6_SRU_CTRL0_EN,
62*4882a593Smuzhiyun .ctrl2 = VI6_SRU_CTRL2_PARAMS(36, 60, 255),
63*4882a593Smuzhiyun }, {
64*4882a593Smuzhiyun .ctrl0 = VI6_SRU_CTRL0_PARAMS(384, 5) | VI6_SRU_CTRL0_EN,
65*4882a593Smuzhiyun .ctrl2 = VI6_SRU_CTRL2_PARAMS(12, 27, 255),
66*4882a593Smuzhiyun }, {
67*4882a593Smuzhiyun .ctrl0 = VI6_SRU_CTRL0_PARAMS(511, 6) | VI6_SRU_CTRL0_EN,
68*4882a593Smuzhiyun .ctrl2 = VI6_SRU_CTRL2_PARAMS(48, 80, 255),
69*4882a593Smuzhiyun }, {
70*4882a593Smuzhiyun .ctrl0 = VI6_SRU_CTRL0_PARAMS(511, 6) | VI6_SRU_CTRL0_EN,
71*4882a593Smuzhiyun .ctrl2 = VI6_SRU_CTRL2_PARAMS(16, 36, 255),
72*4882a593Smuzhiyun },
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun
sru_s_ctrl(struct v4l2_ctrl * ctrl)75*4882a593Smuzhiyun static int sru_s_ctrl(struct v4l2_ctrl *ctrl)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun struct vsp1_sru *sru =
78*4882a593Smuzhiyun container_of(ctrl->handler, struct vsp1_sru, ctrls);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun switch (ctrl->id) {
81*4882a593Smuzhiyun case V4L2_CID_VSP1_SRU_INTENSITY:
82*4882a593Smuzhiyun sru->intensity = ctrl->val;
83*4882a593Smuzhiyun break;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun return 0;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun static const struct v4l2_ctrl_ops sru_ctrl_ops = {
90*4882a593Smuzhiyun .s_ctrl = sru_s_ctrl,
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun static const struct v4l2_ctrl_config sru_intensity_control = {
94*4882a593Smuzhiyun .ops = &sru_ctrl_ops,
95*4882a593Smuzhiyun .id = V4L2_CID_VSP1_SRU_INTENSITY,
96*4882a593Smuzhiyun .name = "Intensity",
97*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_INTEGER,
98*4882a593Smuzhiyun .min = 1,
99*4882a593Smuzhiyun .max = 6,
100*4882a593Smuzhiyun .def = 1,
101*4882a593Smuzhiyun .step = 1,
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
105*4882a593Smuzhiyun * V4L2 Subdevice Operations
106*4882a593Smuzhiyun */
107*4882a593Smuzhiyun
sru_enum_mbus_code(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)108*4882a593Smuzhiyun static int sru_enum_mbus_code(struct v4l2_subdev *subdev,
109*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
110*4882a593Smuzhiyun struct v4l2_subdev_mbus_code_enum *code)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun static const unsigned int codes[] = {
113*4882a593Smuzhiyun MEDIA_BUS_FMT_ARGB8888_1X32,
114*4882a593Smuzhiyun MEDIA_BUS_FMT_AYUV8_1X32,
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun return vsp1_subdev_enum_mbus_code(subdev, cfg, code, codes,
118*4882a593Smuzhiyun ARRAY_SIZE(codes));
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
sru_enum_frame_size(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)121*4882a593Smuzhiyun static int sru_enum_frame_size(struct v4l2_subdev *subdev,
122*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
123*4882a593Smuzhiyun struct v4l2_subdev_frame_size_enum *fse)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun struct vsp1_sru *sru = to_sru(subdev);
126*4882a593Smuzhiyun struct v4l2_subdev_pad_config *config;
127*4882a593Smuzhiyun struct v4l2_mbus_framefmt *format;
128*4882a593Smuzhiyun int ret = 0;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun config = vsp1_entity_get_pad_config(&sru->entity, cfg, fse->which);
131*4882a593Smuzhiyun if (!config)
132*4882a593Smuzhiyun return -EINVAL;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun format = vsp1_entity_get_pad_format(&sru->entity, config, SRU_PAD_SINK);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun mutex_lock(&sru->entity.lock);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun if (fse->index || fse->code != format->code) {
139*4882a593Smuzhiyun ret = -EINVAL;
140*4882a593Smuzhiyun goto done;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun if (fse->pad == SRU_PAD_SINK) {
144*4882a593Smuzhiyun fse->min_width = SRU_MIN_SIZE;
145*4882a593Smuzhiyun fse->max_width = SRU_MAX_SIZE;
146*4882a593Smuzhiyun fse->min_height = SRU_MIN_SIZE;
147*4882a593Smuzhiyun fse->max_height = SRU_MAX_SIZE;
148*4882a593Smuzhiyun } else {
149*4882a593Smuzhiyun fse->min_width = format->width;
150*4882a593Smuzhiyun fse->min_height = format->height;
151*4882a593Smuzhiyun if (format->width <= SRU_MAX_SIZE / 2 &&
152*4882a593Smuzhiyun format->height <= SRU_MAX_SIZE / 2) {
153*4882a593Smuzhiyun fse->max_width = format->width * 2;
154*4882a593Smuzhiyun fse->max_height = format->height * 2;
155*4882a593Smuzhiyun } else {
156*4882a593Smuzhiyun fse->max_width = format->width;
157*4882a593Smuzhiyun fse->max_height = format->height;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun done:
162*4882a593Smuzhiyun mutex_unlock(&sru->entity.lock);
163*4882a593Smuzhiyun return ret;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun
sru_try_format(struct vsp1_sru * sru,struct v4l2_subdev_pad_config * config,unsigned int pad,struct v4l2_mbus_framefmt * fmt)166*4882a593Smuzhiyun static void sru_try_format(struct vsp1_sru *sru,
167*4882a593Smuzhiyun struct v4l2_subdev_pad_config *config,
168*4882a593Smuzhiyun unsigned int pad, struct v4l2_mbus_framefmt *fmt)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun struct v4l2_mbus_framefmt *format;
171*4882a593Smuzhiyun unsigned int input_area;
172*4882a593Smuzhiyun unsigned int output_area;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun switch (pad) {
175*4882a593Smuzhiyun case SRU_PAD_SINK:
176*4882a593Smuzhiyun /* Default to YUV if the requested format is not supported. */
177*4882a593Smuzhiyun if (fmt->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
178*4882a593Smuzhiyun fmt->code != MEDIA_BUS_FMT_AYUV8_1X32)
179*4882a593Smuzhiyun fmt->code = MEDIA_BUS_FMT_AYUV8_1X32;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun fmt->width = clamp(fmt->width, SRU_MIN_SIZE, SRU_MAX_SIZE);
182*4882a593Smuzhiyun fmt->height = clamp(fmt->height, SRU_MIN_SIZE, SRU_MAX_SIZE);
183*4882a593Smuzhiyun break;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun case SRU_PAD_SOURCE:
186*4882a593Smuzhiyun /* The SRU can't perform format conversion. */
187*4882a593Smuzhiyun format = vsp1_entity_get_pad_format(&sru->entity, config,
188*4882a593Smuzhiyun SRU_PAD_SINK);
189*4882a593Smuzhiyun fmt->code = format->code;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun /*
192*4882a593Smuzhiyun * We can upscale by 2 in both direction, but not independently.
193*4882a593Smuzhiyun * Compare the input and output rectangles areas (avoiding
194*4882a593Smuzhiyun * integer overflows on the output): if the requested output
195*4882a593Smuzhiyun * area is larger than 1.5^2 the input area upscale by two,
196*4882a593Smuzhiyun * otherwise don't scale.
197*4882a593Smuzhiyun */
198*4882a593Smuzhiyun input_area = format->width * format->height;
199*4882a593Smuzhiyun output_area = min(fmt->width, SRU_MAX_SIZE)
200*4882a593Smuzhiyun * min(fmt->height, SRU_MAX_SIZE);
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun if (fmt->width <= SRU_MAX_SIZE / 2 &&
203*4882a593Smuzhiyun fmt->height <= SRU_MAX_SIZE / 2 &&
204*4882a593Smuzhiyun output_area > input_area * 9 / 4) {
205*4882a593Smuzhiyun fmt->width = format->width * 2;
206*4882a593Smuzhiyun fmt->height = format->height * 2;
207*4882a593Smuzhiyun } else {
208*4882a593Smuzhiyun fmt->width = format->width;
209*4882a593Smuzhiyun fmt->height = format->height;
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun break;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun fmt->field = V4L2_FIELD_NONE;
215*4882a593Smuzhiyun fmt->colorspace = V4L2_COLORSPACE_SRGB;
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun
sru_set_format(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)218*4882a593Smuzhiyun static int sru_set_format(struct v4l2_subdev *subdev,
219*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
220*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun struct vsp1_sru *sru = to_sru(subdev);
223*4882a593Smuzhiyun struct v4l2_subdev_pad_config *config;
224*4882a593Smuzhiyun struct v4l2_mbus_framefmt *format;
225*4882a593Smuzhiyun int ret = 0;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun mutex_lock(&sru->entity.lock);
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun config = vsp1_entity_get_pad_config(&sru->entity, cfg, fmt->which);
230*4882a593Smuzhiyun if (!config) {
231*4882a593Smuzhiyun ret = -EINVAL;
232*4882a593Smuzhiyun goto done;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun sru_try_format(sru, config, fmt->pad, &fmt->format);
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun format = vsp1_entity_get_pad_format(&sru->entity, config, fmt->pad);
238*4882a593Smuzhiyun *format = fmt->format;
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun if (fmt->pad == SRU_PAD_SINK) {
241*4882a593Smuzhiyun /* Propagate the format to the source pad. */
242*4882a593Smuzhiyun format = vsp1_entity_get_pad_format(&sru->entity, config,
243*4882a593Smuzhiyun SRU_PAD_SOURCE);
244*4882a593Smuzhiyun *format = fmt->format;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun sru_try_format(sru, config, SRU_PAD_SOURCE, format);
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun done:
250*4882a593Smuzhiyun mutex_unlock(&sru->entity.lock);
251*4882a593Smuzhiyun return ret;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops sru_pad_ops = {
255*4882a593Smuzhiyun .init_cfg = vsp1_entity_init_cfg,
256*4882a593Smuzhiyun .enum_mbus_code = sru_enum_mbus_code,
257*4882a593Smuzhiyun .enum_frame_size = sru_enum_frame_size,
258*4882a593Smuzhiyun .get_fmt = vsp1_subdev_get_pad_format,
259*4882a593Smuzhiyun .set_fmt = sru_set_format,
260*4882a593Smuzhiyun };
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun static const struct v4l2_subdev_ops sru_ops = {
263*4882a593Smuzhiyun .pad = &sru_pad_ops,
264*4882a593Smuzhiyun };
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
267*4882a593Smuzhiyun * VSP1 Entity Operations
268*4882a593Smuzhiyun */
269*4882a593Smuzhiyun
sru_configure_stream(struct vsp1_entity * entity,struct vsp1_pipeline * pipe,struct vsp1_dl_list * dl,struct vsp1_dl_body * dlb)270*4882a593Smuzhiyun static void sru_configure_stream(struct vsp1_entity *entity,
271*4882a593Smuzhiyun struct vsp1_pipeline *pipe,
272*4882a593Smuzhiyun struct vsp1_dl_list *dl,
273*4882a593Smuzhiyun struct vsp1_dl_body *dlb)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun const struct vsp1_sru_param *param;
276*4882a593Smuzhiyun struct vsp1_sru *sru = to_sru(&entity->subdev);
277*4882a593Smuzhiyun struct v4l2_mbus_framefmt *input;
278*4882a593Smuzhiyun struct v4l2_mbus_framefmt *output;
279*4882a593Smuzhiyun u32 ctrl0;
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun input = vsp1_entity_get_pad_format(&sru->entity, sru->entity.config,
282*4882a593Smuzhiyun SRU_PAD_SINK);
283*4882a593Smuzhiyun output = vsp1_entity_get_pad_format(&sru->entity, sru->entity.config,
284*4882a593Smuzhiyun SRU_PAD_SOURCE);
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun if (input->code == MEDIA_BUS_FMT_ARGB8888_1X32)
287*4882a593Smuzhiyun ctrl0 = VI6_SRU_CTRL0_PARAM2 | VI6_SRU_CTRL0_PARAM3
288*4882a593Smuzhiyun | VI6_SRU_CTRL0_PARAM4;
289*4882a593Smuzhiyun else
290*4882a593Smuzhiyun ctrl0 = VI6_SRU_CTRL0_PARAM3;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun if (input->width != output->width)
293*4882a593Smuzhiyun ctrl0 |= VI6_SRU_CTRL0_MODE_UPSCALE;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun param = &vsp1_sru_params[sru->intensity - 1];
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun ctrl0 |= param->ctrl0;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun vsp1_sru_write(sru, dlb, VI6_SRU_CTRL0, ctrl0);
300*4882a593Smuzhiyun vsp1_sru_write(sru, dlb, VI6_SRU_CTRL1, VI6_SRU_CTRL1_PARAM5);
301*4882a593Smuzhiyun vsp1_sru_write(sru, dlb, VI6_SRU_CTRL2, param->ctrl2);
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun
sru_max_width(struct vsp1_entity * entity,struct vsp1_pipeline * pipe)304*4882a593Smuzhiyun static unsigned int sru_max_width(struct vsp1_entity *entity,
305*4882a593Smuzhiyun struct vsp1_pipeline *pipe)
306*4882a593Smuzhiyun {
307*4882a593Smuzhiyun struct vsp1_sru *sru = to_sru(&entity->subdev);
308*4882a593Smuzhiyun struct v4l2_mbus_framefmt *input;
309*4882a593Smuzhiyun struct v4l2_mbus_framefmt *output;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun input = vsp1_entity_get_pad_format(&sru->entity, sru->entity.config,
312*4882a593Smuzhiyun SRU_PAD_SINK);
313*4882a593Smuzhiyun output = vsp1_entity_get_pad_format(&sru->entity, sru->entity.config,
314*4882a593Smuzhiyun SRU_PAD_SOURCE);
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun /*
317*4882a593Smuzhiyun * The maximum input width of the SRU is 288 input pixels, but 32
318*4882a593Smuzhiyun * pixels are reserved to support overlapping partition windows when
319*4882a593Smuzhiyun * scaling.
320*4882a593Smuzhiyun */
321*4882a593Smuzhiyun if (input->width != output->width)
322*4882a593Smuzhiyun return 512;
323*4882a593Smuzhiyun else
324*4882a593Smuzhiyun return 256;
325*4882a593Smuzhiyun }
326*4882a593Smuzhiyun
sru_partition(struct vsp1_entity * entity,struct vsp1_pipeline * pipe,struct vsp1_partition * partition,unsigned int partition_idx,struct vsp1_partition_window * window)327*4882a593Smuzhiyun static void sru_partition(struct vsp1_entity *entity,
328*4882a593Smuzhiyun struct vsp1_pipeline *pipe,
329*4882a593Smuzhiyun struct vsp1_partition *partition,
330*4882a593Smuzhiyun unsigned int partition_idx,
331*4882a593Smuzhiyun struct vsp1_partition_window *window)
332*4882a593Smuzhiyun {
333*4882a593Smuzhiyun struct vsp1_sru *sru = to_sru(&entity->subdev);
334*4882a593Smuzhiyun struct v4l2_mbus_framefmt *input;
335*4882a593Smuzhiyun struct v4l2_mbus_framefmt *output;
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun input = vsp1_entity_get_pad_format(&sru->entity, sru->entity.config,
338*4882a593Smuzhiyun SRU_PAD_SINK);
339*4882a593Smuzhiyun output = vsp1_entity_get_pad_format(&sru->entity, sru->entity.config,
340*4882a593Smuzhiyun SRU_PAD_SOURCE);
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun /* Adapt if SRUx2 is enabled. */
343*4882a593Smuzhiyun if (input->width != output->width) {
344*4882a593Smuzhiyun window->width /= 2;
345*4882a593Smuzhiyun window->left /= 2;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun partition->sru = *window;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun static const struct vsp1_entity_operations sru_entity_ops = {
352*4882a593Smuzhiyun .configure_stream = sru_configure_stream,
353*4882a593Smuzhiyun .max_width = sru_max_width,
354*4882a593Smuzhiyun .partition = sru_partition,
355*4882a593Smuzhiyun };
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
358*4882a593Smuzhiyun * Initialization and Cleanup
359*4882a593Smuzhiyun */
360*4882a593Smuzhiyun
vsp1_sru_create(struct vsp1_device * vsp1)361*4882a593Smuzhiyun struct vsp1_sru *vsp1_sru_create(struct vsp1_device *vsp1)
362*4882a593Smuzhiyun {
363*4882a593Smuzhiyun struct vsp1_sru *sru;
364*4882a593Smuzhiyun int ret;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun sru = devm_kzalloc(vsp1->dev, sizeof(*sru), GFP_KERNEL);
367*4882a593Smuzhiyun if (sru == NULL)
368*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun sru->entity.ops = &sru_entity_ops;
371*4882a593Smuzhiyun sru->entity.type = VSP1_ENTITY_SRU;
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun ret = vsp1_entity_init(vsp1, &sru->entity, "sru", 2, &sru_ops,
374*4882a593Smuzhiyun MEDIA_ENT_F_PROC_VIDEO_SCALER);
375*4882a593Smuzhiyun if (ret < 0)
376*4882a593Smuzhiyun return ERR_PTR(ret);
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun /* Initialize the control handler. */
379*4882a593Smuzhiyun v4l2_ctrl_handler_init(&sru->ctrls, 1);
380*4882a593Smuzhiyun v4l2_ctrl_new_custom(&sru->ctrls, &sru_intensity_control, NULL);
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun sru->intensity = 1;
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun sru->entity.subdev.ctrl_handler = &sru->ctrls;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun if (sru->ctrls.error) {
387*4882a593Smuzhiyun dev_err(vsp1->dev, "sru: failed to initialize controls\n");
388*4882a593Smuzhiyun ret = sru->ctrls.error;
389*4882a593Smuzhiyun vsp1_entity_destroy(&sru->entity);
390*4882a593Smuzhiyun return ERR_PTR(ret);
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun return sru;
394*4882a593Smuzhiyun }
395