xref: /OK3568_Linux_fs/kernel/drivers/media/platform/vsp1/vsp1_pipe.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * vsp1_pipe.h  --  R-Car VSP1 Pipeline
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2013-2015 Renesas Electronics Corporation
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun #ifndef __VSP1_PIPE_H__
10*4882a593Smuzhiyun #define __VSP1_PIPE_H__
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/kref.h>
13*4882a593Smuzhiyun #include <linux/list.h>
14*4882a593Smuzhiyun #include <linux/spinlock.h>
15*4882a593Smuzhiyun #include <linux/wait.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <media/media-entity.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun struct vsp1_dl_list;
20*4882a593Smuzhiyun struct vsp1_rwpf;
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /*
23*4882a593Smuzhiyun  * struct vsp1_format_info - VSP1 video format description
24*4882a593Smuzhiyun  * @fourcc: V4L2 pixel format FCC identifier
25*4882a593Smuzhiyun  * @mbus: media bus format code
26*4882a593Smuzhiyun  * @hwfmt: VSP1 hardware format
27*4882a593Smuzhiyun  * @swap: swap register control
28*4882a593Smuzhiyun  * @planes: number of planes
29*4882a593Smuzhiyun  * @bpp: bits per pixel
30*4882a593Smuzhiyun  * @swap_yc: the Y and C components are swapped (Y comes before C)
31*4882a593Smuzhiyun  * @swap_uv: the U and V components are swapped (V comes before U)
32*4882a593Smuzhiyun  * @hsub: horizontal subsampling factor
33*4882a593Smuzhiyun  * @vsub: vertical subsampling factor
34*4882a593Smuzhiyun  * @alpha: has an alpha channel
35*4882a593Smuzhiyun  */
36*4882a593Smuzhiyun struct vsp1_format_info {
37*4882a593Smuzhiyun 	u32 fourcc;
38*4882a593Smuzhiyun 	unsigned int mbus;
39*4882a593Smuzhiyun 	unsigned int hwfmt;
40*4882a593Smuzhiyun 	unsigned int swap;
41*4882a593Smuzhiyun 	unsigned int planes;
42*4882a593Smuzhiyun 	unsigned int bpp[3];
43*4882a593Smuzhiyun 	bool swap_yc;
44*4882a593Smuzhiyun 	bool swap_uv;
45*4882a593Smuzhiyun 	unsigned int hsub;
46*4882a593Smuzhiyun 	unsigned int vsub;
47*4882a593Smuzhiyun 	bool alpha;
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun enum vsp1_pipeline_state {
51*4882a593Smuzhiyun 	VSP1_PIPELINE_STOPPED,
52*4882a593Smuzhiyun 	VSP1_PIPELINE_RUNNING,
53*4882a593Smuzhiyun 	VSP1_PIPELINE_STOPPING,
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun /*
57*4882a593Smuzhiyun  * struct vsp1_partition_window - Partition window coordinates
58*4882a593Smuzhiyun  * @left: horizontal coordinate of the partition start in pixels relative to the
59*4882a593Smuzhiyun  *	  left edge of the image
60*4882a593Smuzhiyun  * @width: partition width in pixels
61*4882a593Smuzhiyun  */
62*4882a593Smuzhiyun struct vsp1_partition_window {
63*4882a593Smuzhiyun 	unsigned int left;
64*4882a593Smuzhiyun 	unsigned int width;
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun /*
68*4882a593Smuzhiyun  * struct vsp1_partition - A description of a slice for the partition algorithm
69*4882a593Smuzhiyun  * @rpf: The RPF partition window configuration
70*4882a593Smuzhiyun  * @uds_sink: The UDS input partition window configuration
71*4882a593Smuzhiyun  * @uds_source: The UDS output partition window configuration
72*4882a593Smuzhiyun  * @sru: The SRU partition window configuration
73*4882a593Smuzhiyun  * @wpf: The WPF partition window configuration
74*4882a593Smuzhiyun  */
75*4882a593Smuzhiyun struct vsp1_partition {
76*4882a593Smuzhiyun 	struct vsp1_partition_window rpf;
77*4882a593Smuzhiyun 	struct vsp1_partition_window uds_sink;
78*4882a593Smuzhiyun 	struct vsp1_partition_window uds_source;
79*4882a593Smuzhiyun 	struct vsp1_partition_window sru;
80*4882a593Smuzhiyun 	struct vsp1_partition_window wpf;
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun /*
84*4882a593Smuzhiyun  * struct vsp1_pipeline - A VSP1 hardware pipeline
85*4882a593Smuzhiyun  * @pipe: the media pipeline
86*4882a593Smuzhiyun  * @irqlock: protects the pipeline state
87*4882a593Smuzhiyun  * @state: current state
88*4882a593Smuzhiyun  * @wq: wait queue to wait for state change completion
89*4882a593Smuzhiyun  * @frame_end: frame end interrupt handler
90*4882a593Smuzhiyun  * @lock: protects the pipeline use count and stream count
91*4882a593Smuzhiyun  * @kref: pipeline reference count
92*4882a593Smuzhiyun  * @stream_count: number of streaming video nodes
93*4882a593Smuzhiyun  * @buffers_ready: bitmask of RPFs and WPFs with at least one buffer available
94*4882a593Smuzhiyun  * @sequence: frame sequence number
95*4882a593Smuzhiyun  * @num_inputs: number of RPFs
96*4882a593Smuzhiyun  * @inputs: array of RPFs in the pipeline (indexed by RPF index)
97*4882a593Smuzhiyun  * @output: WPF at the output of the pipeline
98*4882a593Smuzhiyun  * @brx: BRx entity, if present
99*4882a593Smuzhiyun  * @hgo: HGO entity, if present
100*4882a593Smuzhiyun  * @hgt: HGT entity, if present
101*4882a593Smuzhiyun  * @lif: LIF entity, if present
102*4882a593Smuzhiyun  * @uds: UDS entity, if present
103*4882a593Smuzhiyun  * @uds_input: entity at the input of the UDS, if the UDS is present
104*4882a593Smuzhiyun  * @entities: list of entities in the pipeline
105*4882a593Smuzhiyun  * @stream_config: cached stream configuration for video pipelines
106*4882a593Smuzhiyun  * @configured: when false the @stream_config shall be written to the hardware
107*4882a593Smuzhiyun  * @interlaced: True when the pipeline is configured in interlaced mode
108*4882a593Smuzhiyun  * @partitions: The number of partitions used to process one frame
109*4882a593Smuzhiyun  * @partition: The current partition for configuration to process
110*4882a593Smuzhiyun  * @part_table: The pre-calculated partitions used by the pipeline
111*4882a593Smuzhiyun  */
112*4882a593Smuzhiyun struct vsp1_pipeline {
113*4882a593Smuzhiyun 	struct media_pipeline pipe;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	spinlock_t irqlock;
116*4882a593Smuzhiyun 	enum vsp1_pipeline_state state;
117*4882a593Smuzhiyun 	wait_queue_head_t wq;
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	void (*frame_end)(struct vsp1_pipeline *pipe, unsigned int completion);
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	struct mutex lock;
122*4882a593Smuzhiyun 	struct kref kref;
123*4882a593Smuzhiyun 	unsigned int stream_count;
124*4882a593Smuzhiyun 	unsigned int buffers_ready;
125*4882a593Smuzhiyun 	unsigned int sequence;
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	unsigned int num_inputs;
128*4882a593Smuzhiyun 	struct vsp1_rwpf *inputs[VSP1_MAX_RPF];
129*4882a593Smuzhiyun 	struct vsp1_rwpf *output;
130*4882a593Smuzhiyun 	struct vsp1_entity *brx;
131*4882a593Smuzhiyun 	struct vsp1_entity *hgo;
132*4882a593Smuzhiyun 	struct vsp1_entity *hgt;
133*4882a593Smuzhiyun 	struct vsp1_entity *lif;
134*4882a593Smuzhiyun 	struct vsp1_entity *uds;
135*4882a593Smuzhiyun 	struct vsp1_entity *uds_input;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	/*
138*4882a593Smuzhiyun 	 * The order of this list must be identical to the order of the entities
139*4882a593Smuzhiyun 	 * in the pipeline, as it is assumed by the partition algorithm that we
140*4882a593Smuzhiyun 	 * can walk this list in sequence.
141*4882a593Smuzhiyun 	 */
142*4882a593Smuzhiyun 	struct list_head entities;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	struct vsp1_dl_body *stream_config;
145*4882a593Smuzhiyun 	bool configured;
146*4882a593Smuzhiyun 	bool interlaced;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	unsigned int partitions;
149*4882a593Smuzhiyun 	struct vsp1_partition *partition;
150*4882a593Smuzhiyun 	struct vsp1_partition *part_table;
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun void vsp1_pipeline_reset(struct vsp1_pipeline *pipe);
154*4882a593Smuzhiyun void vsp1_pipeline_init(struct vsp1_pipeline *pipe);
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun void vsp1_pipeline_run(struct vsp1_pipeline *pipe);
157*4882a593Smuzhiyun bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe);
158*4882a593Smuzhiyun int vsp1_pipeline_stop(struct vsp1_pipeline *pipe);
159*4882a593Smuzhiyun bool vsp1_pipeline_ready(struct vsp1_pipeline *pipe);
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe);
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe,
164*4882a593Smuzhiyun 				   struct vsp1_dl_body *dlb,
165*4882a593Smuzhiyun 				   unsigned int alpha);
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun void vsp1_pipeline_propagate_partition(struct vsp1_pipeline *pipe,
168*4882a593Smuzhiyun 				       struct vsp1_partition *partition,
169*4882a593Smuzhiyun 				       unsigned int index,
170*4882a593Smuzhiyun 				       struct vsp1_partition_window *window);
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun const struct vsp1_format_info *vsp1_get_format_info(struct vsp1_device *vsp1,
173*4882a593Smuzhiyun 						    u32 fourcc);
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun #endif /* __VSP1_PIPE_H__ */
176