1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * vsp1_hgt.c -- R-Car VSP1 Histogram Generator 2D
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016 Renesas Electronics Corporation
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Contact: Niklas Söderlund (niklas.soderlund@ragnatech.se)
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/gfp.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
14*4882a593Smuzhiyun #include <media/videobuf2-vmalloc.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "vsp1.h"
17*4882a593Smuzhiyun #include "vsp1_dl.h"
18*4882a593Smuzhiyun #include "vsp1_hgt.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define HGT_DATA_SIZE ((2 + 6 * 32) * 4)
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
23*4882a593Smuzhiyun * Device Access
24*4882a593Smuzhiyun */
25*4882a593Smuzhiyun
vsp1_hgt_read(struct vsp1_hgt * hgt,u32 reg)26*4882a593Smuzhiyun static inline u32 vsp1_hgt_read(struct vsp1_hgt *hgt, u32 reg)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun return vsp1_read(hgt->histo.entity.vsp1, reg);
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
vsp1_hgt_write(struct vsp1_hgt * hgt,struct vsp1_dl_body * dlb,u32 reg,u32 data)31*4882a593Smuzhiyun static inline void vsp1_hgt_write(struct vsp1_hgt *hgt,
32*4882a593Smuzhiyun struct vsp1_dl_body *dlb, u32 reg, u32 data)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun vsp1_dl_body_write(dlb, reg, data);
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
38*4882a593Smuzhiyun * Frame End Handler
39*4882a593Smuzhiyun */
40*4882a593Smuzhiyun
vsp1_hgt_frame_end(struct vsp1_entity * entity)41*4882a593Smuzhiyun void vsp1_hgt_frame_end(struct vsp1_entity *entity)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun struct vsp1_hgt *hgt = to_hgt(&entity->subdev);
44*4882a593Smuzhiyun struct vsp1_histogram_buffer *buf;
45*4882a593Smuzhiyun unsigned int m;
46*4882a593Smuzhiyun unsigned int n;
47*4882a593Smuzhiyun u32 *data;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun buf = vsp1_histogram_buffer_get(&hgt->histo);
50*4882a593Smuzhiyun if (!buf)
51*4882a593Smuzhiyun return;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun data = buf->addr;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun *data++ = vsp1_hgt_read(hgt, VI6_HGT_MAXMIN);
56*4882a593Smuzhiyun *data++ = vsp1_hgt_read(hgt, VI6_HGT_SUM);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun for (m = 0; m < 6; ++m)
59*4882a593Smuzhiyun for (n = 0; n < 32; ++n)
60*4882a593Smuzhiyun *data++ = vsp1_hgt_read(hgt, VI6_HGT_HISTO(m, n));
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun vsp1_histogram_buffer_complete(&hgt->histo, buf, HGT_DATA_SIZE);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
66*4882a593Smuzhiyun * Controls
67*4882a593Smuzhiyun */
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun #define V4L2_CID_VSP1_HGT_HUE_AREAS (V4L2_CID_USER_BASE | 0x1001)
70*4882a593Smuzhiyun
hgt_hue_areas_try_ctrl(struct v4l2_ctrl * ctrl)71*4882a593Smuzhiyun static int hgt_hue_areas_try_ctrl(struct v4l2_ctrl *ctrl)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun const u8 *values = ctrl->p_new.p_u8;
74*4882a593Smuzhiyun unsigned int i;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /*
77*4882a593Smuzhiyun * The hardware has constraints on the hue area boundaries beyond the
78*4882a593Smuzhiyun * control min, max and step. The values must match one of the following
79*4882a593Smuzhiyun * expressions.
80*4882a593Smuzhiyun *
81*4882a593Smuzhiyun * 0L <= 0U <= 1L <= 1U <= 2L <= 2U <= 3L <= 3U <= 4L <= 4U <= 5L <= 5U
82*4882a593Smuzhiyun * 0U <= 1L <= 1U <= 2L <= 2U <= 3L <= 3U <= 4L <= 4U <= 5L <= 5U <= 0L
83*4882a593Smuzhiyun *
84*4882a593Smuzhiyun * Start by verifying the common part...
85*4882a593Smuzhiyun */
86*4882a593Smuzhiyun for (i = 1; i < (HGT_NUM_HUE_AREAS * 2) - 1; ++i) {
87*4882a593Smuzhiyun if (values[i] > values[i+1])
88*4882a593Smuzhiyun return -EINVAL;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /* ... and handle 0L separately. */
92*4882a593Smuzhiyun if (values[0] > values[1] && values[11] > values[0])
93*4882a593Smuzhiyun return -EINVAL;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return 0;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
hgt_hue_areas_s_ctrl(struct v4l2_ctrl * ctrl)98*4882a593Smuzhiyun static int hgt_hue_areas_s_ctrl(struct v4l2_ctrl *ctrl)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun struct vsp1_hgt *hgt = container_of(ctrl->handler, struct vsp1_hgt,
101*4882a593Smuzhiyun ctrls);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun memcpy(hgt->hue_areas, ctrl->p_new.p_u8, sizeof(hgt->hue_areas));
104*4882a593Smuzhiyun return 0;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun static const struct v4l2_ctrl_ops hgt_hue_areas_ctrl_ops = {
108*4882a593Smuzhiyun .try_ctrl = hgt_hue_areas_try_ctrl,
109*4882a593Smuzhiyun .s_ctrl = hgt_hue_areas_s_ctrl,
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun static const struct v4l2_ctrl_config hgt_hue_areas = {
113*4882a593Smuzhiyun .ops = &hgt_hue_areas_ctrl_ops,
114*4882a593Smuzhiyun .id = V4L2_CID_VSP1_HGT_HUE_AREAS,
115*4882a593Smuzhiyun .name = "Boundary Values for Hue Area",
116*4882a593Smuzhiyun .type = V4L2_CTRL_TYPE_U8,
117*4882a593Smuzhiyun .min = 0,
118*4882a593Smuzhiyun .max = 255,
119*4882a593Smuzhiyun .def = 0,
120*4882a593Smuzhiyun .step = 1,
121*4882a593Smuzhiyun .dims = { 12 },
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
125*4882a593Smuzhiyun * VSP1 Entity Operations
126*4882a593Smuzhiyun */
127*4882a593Smuzhiyun
hgt_configure_stream(struct vsp1_entity * entity,struct vsp1_pipeline * pipe,struct vsp1_dl_list * dl,struct vsp1_dl_body * dlb)128*4882a593Smuzhiyun static void hgt_configure_stream(struct vsp1_entity *entity,
129*4882a593Smuzhiyun struct vsp1_pipeline *pipe,
130*4882a593Smuzhiyun struct vsp1_dl_list *dl,
131*4882a593Smuzhiyun struct vsp1_dl_body *dlb)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun struct vsp1_hgt *hgt = to_hgt(&entity->subdev);
134*4882a593Smuzhiyun struct v4l2_rect *compose;
135*4882a593Smuzhiyun struct v4l2_rect *crop;
136*4882a593Smuzhiyun unsigned int hratio;
137*4882a593Smuzhiyun unsigned int vratio;
138*4882a593Smuzhiyun u8 lower;
139*4882a593Smuzhiyun u8 upper;
140*4882a593Smuzhiyun unsigned int i;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun crop = vsp1_entity_get_pad_selection(entity, entity->config,
143*4882a593Smuzhiyun HISTO_PAD_SINK, V4L2_SEL_TGT_CROP);
144*4882a593Smuzhiyun compose = vsp1_entity_get_pad_selection(entity, entity->config,
145*4882a593Smuzhiyun HISTO_PAD_SINK,
146*4882a593Smuzhiyun V4L2_SEL_TGT_COMPOSE);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun vsp1_hgt_write(hgt, dlb, VI6_HGT_REGRST, VI6_HGT_REGRST_RCLEA);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun vsp1_hgt_write(hgt, dlb, VI6_HGT_OFFSET,
151*4882a593Smuzhiyun (crop->left << VI6_HGT_OFFSET_HOFFSET_SHIFT) |
152*4882a593Smuzhiyun (crop->top << VI6_HGT_OFFSET_VOFFSET_SHIFT));
153*4882a593Smuzhiyun vsp1_hgt_write(hgt, dlb, VI6_HGT_SIZE,
154*4882a593Smuzhiyun (crop->width << VI6_HGT_SIZE_HSIZE_SHIFT) |
155*4882a593Smuzhiyun (crop->height << VI6_HGT_SIZE_VSIZE_SHIFT));
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun mutex_lock(hgt->ctrls.lock);
158*4882a593Smuzhiyun for (i = 0; i < HGT_NUM_HUE_AREAS; ++i) {
159*4882a593Smuzhiyun lower = hgt->hue_areas[i*2 + 0];
160*4882a593Smuzhiyun upper = hgt->hue_areas[i*2 + 1];
161*4882a593Smuzhiyun vsp1_hgt_write(hgt, dlb, VI6_HGT_HUE_AREA(i),
162*4882a593Smuzhiyun (lower << VI6_HGT_HUE_AREA_LOWER_SHIFT) |
163*4882a593Smuzhiyun (upper << VI6_HGT_HUE_AREA_UPPER_SHIFT));
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun mutex_unlock(hgt->ctrls.lock);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun hratio = crop->width * 2 / compose->width / 3;
168*4882a593Smuzhiyun vratio = crop->height * 2 / compose->height / 3;
169*4882a593Smuzhiyun vsp1_hgt_write(hgt, dlb, VI6_HGT_MODE,
170*4882a593Smuzhiyun (hratio << VI6_HGT_MODE_HRATIO_SHIFT) |
171*4882a593Smuzhiyun (vratio << VI6_HGT_MODE_VRATIO_SHIFT));
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun static const struct vsp1_entity_operations hgt_entity_ops = {
175*4882a593Smuzhiyun .configure_stream = hgt_configure_stream,
176*4882a593Smuzhiyun .destroy = vsp1_histogram_destroy,
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
180*4882a593Smuzhiyun * Initialization and Cleanup
181*4882a593Smuzhiyun */
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun static const unsigned int hgt_mbus_formats[] = {
184*4882a593Smuzhiyun MEDIA_BUS_FMT_AHSV8888_1X32,
185*4882a593Smuzhiyun };
186*4882a593Smuzhiyun
vsp1_hgt_create(struct vsp1_device * vsp1)187*4882a593Smuzhiyun struct vsp1_hgt *vsp1_hgt_create(struct vsp1_device *vsp1)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun struct vsp1_hgt *hgt;
190*4882a593Smuzhiyun int ret;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun hgt = devm_kzalloc(vsp1->dev, sizeof(*hgt), GFP_KERNEL);
193*4882a593Smuzhiyun if (hgt == NULL)
194*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun /* Initialize the control handler. */
197*4882a593Smuzhiyun v4l2_ctrl_handler_init(&hgt->ctrls, 1);
198*4882a593Smuzhiyun v4l2_ctrl_new_custom(&hgt->ctrls, &hgt_hue_areas, NULL);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun hgt->histo.entity.subdev.ctrl_handler = &hgt->ctrls;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun /* Initialize the video device and queue for statistics data. */
203*4882a593Smuzhiyun ret = vsp1_histogram_init(vsp1, &hgt->histo, VSP1_ENTITY_HGT, "hgt",
204*4882a593Smuzhiyun &hgt_entity_ops, hgt_mbus_formats,
205*4882a593Smuzhiyun ARRAY_SIZE(hgt_mbus_formats),
206*4882a593Smuzhiyun HGT_DATA_SIZE, V4L2_META_FMT_VSP1_HGT);
207*4882a593Smuzhiyun if (ret < 0) {
208*4882a593Smuzhiyun vsp1_entity_destroy(&hgt->histo.entity);
209*4882a593Smuzhiyun return ERR_PTR(ret);
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun v4l2_ctrl_handler_setup(&hgt->ctrls);
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun return hgt;
215*4882a593Smuzhiyun }
216