xref: /OK3568_Linux_fs/kernel/drivers/media/platform/vsp1/vsp1_hgo.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * vsp1_hgo.c  --  R-Car VSP1 Histogram Generator 1D
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2016 Renesas Electronics Corporation
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/gfp.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
14*4882a593Smuzhiyun #include <media/videobuf2-vmalloc.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include "vsp1.h"
17*4882a593Smuzhiyun #include "vsp1_dl.h"
18*4882a593Smuzhiyun #include "vsp1_hgo.h"
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define HGO_DATA_SIZE				((2 + 256) * 4)
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
23*4882a593Smuzhiyun  * Device Access
24*4882a593Smuzhiyun  */
25*4882a593Smuzhiyun 
vsp1_hgo_read(struct vsp1_hgo * hgo,u32 reg)26*4882a593Smuzhiyun static inline u32 vsp1_hgo_read(struct vsp1_hgo *hgo, u32 reg)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun 	return vsp1_read(hgo->histo.entity.vsp1, reg);
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun 
vsp1_hgo_write(struct vsp1_hgo * hgo,struct vsp1_dl_body * dlb,u32 reg,u32 data)31*4882a593Smuzhiyun static inline void vsp1_hgo_write(struct vsp1_hgo *hgo,
32*4882a593Smuzhiyun 				  struct vsp1_dl_body *dlb, u32 reg, u32 data)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun 	vsp1_dl_body_write(dlb, reg, data);
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
38*4882a593Smuzhiyun  * Frame End Handler
39*4882a593Smuzhiyun  */
40*4882a593Smuzhiyun 
vsp1_hgo_frame_end(struct vsp1_entity * entity)41*4882a593Smuzhiyun void vsp1_hgo_frame_end(struct vsp1_entity *entity)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun 	struct vsp1_hgo *hgo = to_hgo(&entity->subdev);
44*4882a593Smuzhiyun 	struct vsp1_histogram_buffer *buf;
45*4882a593Smuzhiyun 	unsigned int i;
46*4882a593Smuzhiyun 	size_t size;
47*4882a593Smuzhiyun 	u32 *data;
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	buf = vsp1_histogram_buffer_get(&hgo->histo);
50*4882a593Smuzhiyun 	if (!buf)
51*4882a593Smuzhiyun 		return;
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 	data = buf->addr;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	if (hgo->num_bins == 256) {
56*4882a593Smuzhiyun 		*data++ = vsp1_hgo_read(hgo, VI6_HGO_G_MAXMIN);
57*4882a593Smuzhiyun 		*data++ = vsp1_hgo_read(hgo, VI6_HGO_G_SUM);
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 		for (i = 0; i < 256; ++i) {
60*4882a593Smuzhiyun 			vsp1_write(hgo->histo.entity.vsp1,
61*4882a593Smuzhiyun 				   VI6_HGO_EXT_HIST_ADDR, i);
62*4882a593Smuzhiyun 			*data++ = vsp1_hgo_read(hgo, VI6_HGO_EXT_HIST_DATA);
63*4882a593Smuzhiyun 		}
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 		size = (2 + 256) * sizeof(u32);
66*4882a593Smuzhiyun 	} else if (hgo->max_rgb) {
67*4882a593Smuzhiyun 		*data++ = vsp1_hgo_read(hgo, VI6_HGO_G_MAXMIN);
68*4882a593Smuzhiyun 		*data++ = vsp1_hgo_read(hgo, VI6_HGO_G_SUM);
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 		for (i = 0; i < 64; ++i)
71*4882a593Smuzhiyun 			*data++ = vsp1_hgo_read(hgo, VI6_HGO_G_HISTO(i));
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 		size = (2 + 64) * sizeof(u32);
74*4882a593Smuzhiyun 	} else {
75*4882a593Smuzhiyun 		*data++ = vsp1_hgo_read(hgo, VI6_HGO_R_MAXMIN);
76*4882a593Smuzhiyun 		*data++ = vsp1_hgo_read(hgo, VI6_HGO_G_MAXMIN);
77*4882a593Smuzhiyun 		*data++ = vsp1_hgo_read(hgo, VI6_HGO_B_MAXMIN);
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 		*data++ = vsp1_hgo_read(hgo, VI6_HGO_R_SUM);
80*4882a593Smuzhiyun 		*data++ = vsp1_hgo_read(hgo, VI6_HGO_G_SUM);
81*4882a593Smuzhiyun 		*data++ = vsp1_hgo_read(hgo, VI6_HGO_B_SUM);
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 		for (i = 0; i < 64; ++i) {
84*4882a593Smuzhiyun 			data[i] = vsp1_hgo_read(hgo, VI6_HGO_R_HISTO(i));
85*4882a593Smuzhiyun 			data[i+64] = vsp1_hgo_read(hgo, VI6_HGO_G_HISTO(i));
86*4882a593Smuzhiyun 			data[i+128] = vsp1_hgo_read(hgo, VI6_HGO_B_HISTO(i));
87*4882a593Smuzhiyun 		}
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 		size = (6 + 64 * 3) * sizeof(u32);
90*4882a593Smuzhiyun 	}
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	vsp1_histogram_buffer_complete(&hgo->histo, buf, size);
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
96*4882a593Smuzhiyun  * Controls
97*4882a593Smuzhiyun  */
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun #define V4L2_CID_VSP1_HGO_MAX_RGB		(V4L2_CID_USER_BASE | 0x1001)
100*4882a593Smuzhiyun #define V4L2_CID_VSP1_HGO_NUM_BINS		(V4L2_CID_USER_BASE | 0x1002)
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun static const struct v4l2_ctrl_config hgo_max_rgb_control = {
103*4882a593Smuzhiyun 	.id = V4L2_CID_VSP1_HGO_MAX_RGB,
104*4882a593Smuzhiyun 	.name = "Maximum RGB Mode",
105*4882a593Smuzhiyun 	.type = V4L2_CTRL_TYPE_BOOLEAN,
106*4882a593Smuzhiyun 	.min = 0,
107*4882a593Smuzhiyun 	.max = 1,
108*4882a593Smuzhiyun 	.def = 0,
109*4882a593Smuzhiyun 	.step = 1,
110*4882a593Smuzhiyun 	.flags = V4L2_CTRL_FLAG_MODIFY_LAYOUT,
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun static const s64 hgo_num_bins[] = {
114*4882a593Smuzhiyun 	64, 256,
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun static const struct v4l2_ctrl_config hgo_num_bins_control = {
118*4882a593Smuzhiyun 	.id = V4L2_CID_VSP1_HGO_NUM_BINS,
119*4882a593Smuzhiyun 	.name = "Number of Bins",
120*4882a593Smuzhiyun 	.type = V4L2_CTRL_TYPE_INTEGER_MENU,
121*4882a593Smuzhiyun 	.min = 0,
122*4882a593Smuzhiyun 	.max = 1,
123*4882a593Smuzhiyun 	.def = 0,
124*4882a593Smuzhiyun 	.qmenu_int = hgo_num_bins,
125*4882a593Smuzhiyun 	.flags = V4L2_CTRL_FLAG_MODIFY_LAYOUT,
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
129*4882a593Smuzhiyun  * VSP1 Entity Operations
130*4882a593Smuzhiyun  */
131*4882a593Smuzhiyun 
hgo_configure_stream(struct vsp1_entity * entity,struct vsp1_pipeline * pipe,struct vsp1_dl_list * dl,struct vsp1_dl_body * dlb)132*4882a593Smuzhiyun static void hgo_configure_stream(struct vsp1_entity *entity,
133*4882a593Smuzhiyun 				 struct vsp1_pipeline *pipe,
134*4882a593Smuzhiyun 				 struct vsp1_dl_list *dl,
135*4882a593Smuzhiyun 				 struct vsp1_dl_body *dlb)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun 	struct vsp1_hgo *hgo = to_hgo(&entity->subdev);
138*4882a593Smuzhiyun 	struct v4l2_rect *compose;
139*4882a593Smuzhiyun 	struct v4l2_rect *crop;
140*4882a593Smuzhiyun 	unsigned int hratio;
141*4882a593Smuzhiyun 	unsigned int vratio;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	crop = vsp1_entity_get_pad_selection(entity, entity->config,
144*4882a593Smuzhiyun 					     HISTO_PAD_SINK, V4L2_SEL_TGT_CROP);
145*4882a593Smuzhiyun 	compose = vsp1_entity_get_pad_selection(entity, entity->config,
146*4882a593Smuzhiyun 						HISTO_PAD_SINK,
147*4882a593Smuzhiyun 						V4L2_SEL_TGT_COMPOSE);
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	vsp1_hgo_write(hgo, dlb, VI6_HGO_REGRST, VI6_HGO_REGRST_RCLEA);
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	vsp1_hgo_write(hgo, dlb, VI6_HGO_OFFSET,
152*4882a593Smuzhiyun 		       (crop->left << VI6_HGO_OFFSET_HOFFSET_SHIFT) |
153*4882a593Smuzhiyun 		       (crop->top << VI6_HGO_OFFSET_VOFFSET_SHIFT));
154*4882a593Smuzhiyun 	vsp1_hgo_write(hgo, dlb, VI6_HGO_SIZE,
155*4882a593Smuzhiyun 		       (crop->width << VI6_HGO_SIZE_HSIZE_SHIFT) |
156*4882a593Smuzhiyun 		       (crop->height << VI6_HGO_SIZE_VSIZE_SHIFT));
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	mutex_lock(hgo->ctrls.handler.lock);
159*4882a593Smuzhiyun 	hgo->max_rgb = hgo->ctrls.max_rgb->cur.val;
160*4882a593Smuzhiyun 	if (hgo->ctrls.num_bins)
161*4882a593Smuzhiyun 		hgo->num_bins = hgo_num_bins[hgo->ctrls.num_bins->cur.val];
162*4882a593Smuzhiyun 	mutex_unlock(hgo->ctrls.handler.lock);
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	hratio = crop->width * 2 / compose->width / 3;
165*4882a593Smuzhiyun 	vratio = crop->height * 2 / compose->height / 3;
166*4882a593Smuzhiyun 	vsp1_hgo_write(hgo, dlb, VI6_HGO_MODE,
167*4882a593Smuzhiyun 		       (hgo->num_bins == 256 ? VI6_HGO_MODE_STEP : 0) |
168*4882a593Smuzhiyun 		       (hgo->max_rgb ? VI6_HGO_MODE_MAXRGB : 0) |
169*4882a593Smuzhiyun 		       (hratio << VI6_HGO_MODE_HRATIO_SHIFT) |
170*4882a593Smuzhiyun 		       (vratio << VI6_HGO_MODE_VRATIO_SHIFT));
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun static const struct vsp1_entity_operations hgo_entity_ops = {
174*4882a593Smuzhiyun 	.configure_stream = hgo_configure_stream,
175*4882a593Smuzhiyun 	.destroy = vsp1_histogram_destroy,
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
179*4882a593Smuzhiyun  * Initialization and Cleanup
180*4882a593Smuzhiyun  */
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun static const unsigned int hgo_mbus_formats[] = {
183*4882a593Smuzhiyun 	MEDIA_BUS_FMT_AYUV8_1X32,
184*4882a593Smuzhiyun 	MEDIA_BUS_FMT_ARGB8888_1X32,
185*4882a593Smuzhiyun 	MEDIA_BUS_FMT_AHSV8888_1X32,
186*4882a593Smuzhiyun };
187*4882a593Smuzhiyun 
vsp1_hgo_create(struct vsp1_device * vsp1)188*4882a593Smuzhiyun struct vsp1_hgo *vsp1_hgo_create(struct vsp1_device *vsp1)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	struct vsp1_hgo *hgo;
191*4882a593Smuzhiyun 	int ret;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	hgo = devm_kzalloc(vsp1->dev, sizeof(*hgo), GFP_KERNEL);
194*4882a593Smuzhiyun 	if (hgo == NULL)
195*4882a593Smuzhiyun 		return ERR_PTR(-ENOMEM);
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	/* Initialize the control handler. */
198*4882a593Smuzhiyun 	v4l2_ctrl_handler_init(&hgo->ctrls.handler,
199*4882a593Smuzhiyun 			       vsp1->info->gen == 3 ? 2 : 1);
200*4882a593Smuzhiyun 	hgo->ctrls.max_rgb = v4l2_ctrl_new_custom(&hgo->ctrls.handler,
201*4882a593Smuzhiyun 						  &hgo_max_rgb_control, NULL);
202*4882a593Smuzhiyun 	if (vsp1->info->gen == 3)
203*4882a593Smuzhiyun 		hgo->ctrls.num_bins =
204*4882a593Smuzhiyun 			v4l2_ctrl_new_custom(&hgo->ctrls.handler,
205*4882a593Smuzhiyun 					     &hgo_num_bins_control, NULL);
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	hgo->max_rgb = false;
208*4882a593Smuzhiyun 	hgo->num_bins = 64;
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	hgo->histo.entity.subdev.ctrl_handler = &hgo->ctrls.handler;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	/* Initialize the video device and queue for statistics data. */
213*4882a593Smuzhiyun 	ret = vsp1_histogram_init(vsp1, &hgo->histo, VSP1_ENTITY_HGO, "hgo",
214*4882a593Smuzhiyun 				  &hgo_entity_ops, hgo_mbus_formats,
215*4882a593Smuzhiyun 				  ARRAY_SIZE(hgo_mbus_formats),
216*4882a593Smuzhiyun 				  HGO_DATA_SIZE, V4L2_META_FMT_VSP1_HGO);
217*4882a593Smuzhiyun 	if (ret < 0) {
218*4882a593Smuzhiyun 		vsp1_entity_destroy(&hgo->histo.entity);
219*4882a593Smuzhiyun 		return ERR_PTR(ret);
220*4882a593Smuzhiyun 	}
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	return hgo;
223*4882a593Smuzhiyun }
224