1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * vsp1_drm.h -- R-Car VSP1 DRM/KMS Interface 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2015 Renesas Electronics Corporation 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __VSP1_DRM_H__ 10*4882a593Smuzhiyun #define __VSP1_DRM_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/mutex.h> 13*4882a593Smuzhiyun #include <linux/videodev2.h> 14*4882a593Smuzhiyun #include <linux/wait.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include <media/vsp1.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include "vsp1_pipe.h" 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /** 21*4882a593Smuzhiyun * vsp1_drm_pipeline - State for the API exposed to the DRM driver 22*4882a593Smuzhiyun * @pipe: the VSP1 pipeline used for display 23*4882a593Smuzhiyun * @width: output display width 24*4882a593Smuzhiyun * @height: output display height 25*4882a593Smuzhiyun * @force_brx_release: when set, release the BRx during the next reconfiguration 26*4882a593Smuzhiyun * @wait_queue: wait queue to wait for BRx release completion 27*4882a593Smuzhiyun * @uif: UIF entity if available for the pipeline 28*4882a593Smuzhiyun * @crc: CRC computation configuration 29*4882a593Smuzhiyun * @du_complete: frame completion callback for the DU driver (optional) 30*4882a593Smuzhiyun * @du_private: data to be passed to the du_complete callback 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun struct vsp1_drm_pipeline { 33*4882a593Smuzhiyun struct vsp1_pipeline pipe; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun unsigned int width; 36*4882a593Smuzhiyun unsigned int height; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun bool force_brx_release; 39*4882a593Smuzhiyun wait_queue_head_t wait_queue; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct vsp1_entity *uif; 42*4882a593Smuzhiyun struct vsp1_du_crc_config crc; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Frame synchronisation */ 45*4882a593Smuzhiyun void (*du_complete)(void *data, unsigned int status, u32 crc); 46*4882a593Smuzhiyun void *du_private; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /** 50*4882a593Smuzhiyun * vsp1_drm - State for the API exposed to the DRM driver 51*4882a593Smuzhiyun * @pipe: the VSP1 DRM pipeline used for display 52*4882a593Smuzhiyun * @lock: protects the BRU and BRS allocation 53*4882a593Smuzhiyun * @inputs: source crop rectangle, destination compose rectangle and z-order 54*4882a593Smuzhiyun * position for every input (indexed by RPF index) 55*4882a593Smuzhiyun */ 56*4882a593Smuzhiyun struct vsp1_drm { 57*4882a593Smuzhiyun struct vsp1_drm_pipeline pipe[VSP1_MAX_LIF]; 58*4882a593Smuzhiyun struct mutex lock; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct { 61*4882a593Smuzhiyun struct v4l2_rect crop; 62*4882a593Smuzhiyun struct v4l2_rect compose; 63*4882a593Smuzhiyun unsigned int zpos; 64*4882a593Smuzhiyun } inputs[VSP1_MAX_RPF]; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun static inline struct vsp1_drm_pipeline * to_vsp1_drm_pipeline(struct vsp1_pipeline * pipe)68*4882a593Smuzhiyunto_vsp1_drm_pipeline(struct vsp1_pipeline *pipe) 69*4882a593Smuzhiyun { 70*4882a593Smuzhiyun return container_of(pipe, struct vsp1_drm_pipeline, pipe); 71*4882a593Smuzhiyun } 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun int vsp1_drm_init(struct vsp1_device *vsp1); 74*4882a593Smuzhiyun void vsp1_drm_cleanup(struct vsp1_device *vsp1); 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif /* __VSP1_DRM_H__ */ 77